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Dependents: STM32_F103-C8T6basecanblink_led
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Revision 157:ff67d9f36b67, committed 2017-02-02
- Comitter:
- <>
- Date:
- Thu Feb 02 17:01:33 2017 +0000
- Parent:
- 156:95d6b41a828b
- Child:
- 158:b23ee177fd68
- Commit message:
- This updates the lib to the mbed lib v135
Changed in this revision
--- a/mbed.h Mon Jan 16 15:03:32 2017 +0000 +++ b/mbed.h Thu Feb 02 17:01:33 2017 +0000 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 134 +#define MBED_LIBRARY_VERSION 135 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 3 -#define MBED_PATCH_VERSION 3 +#define MBED_PATCH_VERSION 4 #else // mbed 2
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/trng_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,82 @@
+/*
+ * Hardware entropy collector for the K22F, using Freescale's RNGA
+ *
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#if defined(DEVICE_TRNG)
+
+#include <stdlib.h>
+#include "cmsis.h"
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "trng_api.h"
+
+void trng_init(trng_t *obj)
+{
+ (void)obj;
+ CLOCK_EnableClock(kCLOCK_Rnga0);
+ CLOCK_DisableClock(kCLOCK_Rnga0);
+ CLOCK_EnableClock(kCLOCK_Rnga0);
+}
+
+void trng_free(trng_t *obj)
+{
+ (void)obj;
+ CLOCK_DisableClock(kCLOCK_Rnga0);
+}
+
+/*
+ * Get one byte of entropy from the RNG, assuming it is up and running.
+ * As recommended, get only one bit of each output.
+ */
+static void trng_get_byte(unsigned char *byte)
+{
+ size_t bit;
+
+ /* 34.5 Steps 3-4-5: poll SR and read from OR when ready */
+ for( bit = 0; bit < 8; bit++ )
+ {
+ while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 );
+ *byte |= (RNG->OR & 1) << bit;
+ }
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+ (void)obj;
+ size_t i;
+
+ /* Set "Interrupt Mask", "High Assurance" and "Go",
+ * unset "Clear interrupt" and "Sleep" */
+ RNG->CR = RNG_CR_INTM_MASK | RNG_CR_HA_MASK | RNG_CR_GO_MASK;
+
+ for (i = 0; i < length; i++) {
+ trng_get_byte(output + i);
+ }
+
+ /* Just be extra sure that we didn't do it wrong */
+ if ((RNG->SR & RNG_SR_SECV_MASK) != 0) {
+ return -1;
+ }
+
+ *output_length = length;
+
+ return 0;
+}
+
+#endif
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld Thu Feb 02 17:01:33 2017 +0000
@@ -93,9 +93,9 @@
/* The program code and other data goes into internal flash */
/* Note: The uVisor expects this section at a fixed location, as specified by
* the porting process configuration parameter: FLASH_OFFSET. */
- __UVISOR_TEXT_OFFSET = 0x410;
- __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;
- .text __UVISOR_TEXT_START :
+ __UVISOR_FLASH_OFFSET = 0x410;
+ __UVISOR_FLASH_START = ORIGIN(m_interrupts) + __UVISOR_FLASH_OFFSET;
+ .text __UVISOR_FLASH_START :
{
/* uVisor code and data */
. = ALIGN(4);
@@ -197,27 +197,26 @@
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
- /* Ensure that the uVisor BSS section is put first after the relocated
- * interrupt table in SRAM. */
- /* Note: The uVisor expects this section at a fixed location, as specified by
- * the porting process configuration parameter: SRAM_OFFSET. */
+ /* uVisor own memory and private box memories
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the VTOR relocation section. */
+ /* Note: The uVisor expects this section at a fixed location, as specified
+ by the porting process configuration parameter: SRAM_OFFSET. */
__UVISOR_SRAM_OFFSET = 0x400;
- __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
- ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,
- "The ISR relocation region overlaps with the uVisor BSS section.")
- .uvisor.bss __UVISOR_BSS_START (NOLOAD):
+ __UVISOR_SRAM_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
+ .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;
- /* protected uvisor main bss */
+ /* Protected uVisor own BSS section */
. = ALIGN(32);
__uvisor_bss_main_start = .;
KEEP(*(.keep.uvisor.bss.main))
. = ALIGN(32);
__uvisor_bss_main_end = .;
- /* protected uvisor secure boxes bss */
+ /* Protected uVisor boxes' static memories */
. = ALIGN(32);
__uvisor_bss_boxes_start = .;
KEEP(*(.keep.uvisor.bss.boxes))
@@ -228,7 +227,10 @@
__uvisor_bss_end = .;
} > m_data
- /* Heap space for the page allocator */
+ /* Heap space for the page allocator
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the uVisor BSS section. Otherwise, ensure it is the
+ * first one after the VTOR relocation section. */
.page_heap (NOLOAD) :
{
. = ALIGN(32);
@@ -305,6 +307,7 @@
} > m_data_2
USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;
+
/* Uninitialized data section */
.bss :
{
@@ -354,11 +357,13 @@
.ARM.attributes 0 : { *(.ARM.attributes) }
- ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
+ ASSERT(__StackLimit >= __HeapLimit, "Region m_data_2 overflowed with stack and heap")
/* Provide the physical memory boundaries for uVisor. */
__uvisor_flash_start = ORIGIN(m_interrupts);
__uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text);
__uvisor_sram_start = ORIGIN(m_data);
__uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2);
+ __uvisor_public_sram_start = __uvisor_sram_start;
+ __uvisor_public_sram_end = __uvisor_sram_end;
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,197 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "device.h"
+#include "PeripheralPins.h"
+#include "ioman_regs.h"
+#include "ioman.h"
+#include "adc.h"
+
+/*
+ * To select a peripheral function on Maxim microcontrollers, multiple
+ * configurations must be made. The mbed PinMap structure only includes one
+ * data member to hold this information. To extend the configuration storage,
+ * the "function" data member is used as a pointer to a pin_function_t
+ * structure. This structure is defined in objects.h. The definitions below
+ * include the creation of the pin_function_t structures and the assignment of
+ * the pointers to the "function" data members.
+ */
+
+#ifdef TOOLCHAIN_ARM_STD
+#pragma diag_suppress 1296
+#endif
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+ { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
+ { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P5_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { P7_1, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P6_7, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P7_3, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+ { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
+ { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P6_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { P7_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P7_0, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { P8_0, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM1_ACK_IO_SEL | MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK)}) },
+ { P7_4, I2C_2, (int)&((pin_function_t){&MXC_IOMAN->i2cm2_req, &MXC_IOMAN->i2cm2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ), (MXC_F_IOMAN_I2CM2_ACK_IO_SEL | MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK)}) },
+ { NC, NC, 0 }
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+ { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
+ { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
+ { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
+ { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
+ { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
+ { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
+ { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
+ { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_UART_RX[] = {
+ { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
+ { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
+ { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
+ { P5_3, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
+ { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
+ { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
+ { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
+ { P5_4, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_IO_REQ), (MXC_F_IOMAN_UART3_ACK_IO_MAP | MXC_F_IOMAN_UART3_ACK_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_UART_CTS[] = {
+ { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
+ { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
+ { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
+ { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
+ { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
+ { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
+ { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
+ { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_CTS_MAP | MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_UART_RTS[] = {
+ { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
+ { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
+ { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
+ { P5_6, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
+ { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
+ { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
+ { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
+ { P5_5, UART_3, (int)&((pin_function_t){&MXC_IOMAN->uart3_req, &MXC_IOMAN->uart3_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART3_ACK_RTS_MAP | MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+ { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
+ { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
+ { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P5_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P6_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+ { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
+ { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
+ { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P5_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P6_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+ { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
+ { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
+ { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P5_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { P6_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, ((uint32_t)IOMAN_MAP_C | MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ), (MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ | MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK)}) },
+ { NC, NC, 0 }
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+ { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) },
+ { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) },
+ { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
+ { P5_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
+ { P6_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
+ { NC, NC, 0 }
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+ { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 }, { P6_0, PWM_0, 1 }, { P8_0, PWM_0, 1 },
+ { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 }, { P6_1, PWM_1, 1 }, { P8_1, PWM_1, 1 },
+ { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 }, { P6_2, PWM_2, 1 },
+ { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 }, { P6_3, PWM_3, 1 },
+ { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 }, { P6_4, PWM_4, 1 },
+ { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 }, { P6_5, PWM_5, 1 },
+ { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 }, { P6_6, PWM_6, 1 },
+ { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 }, { P6_7, PWM_7, 1 },
+ { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 }, { P5_0, PWM_8, 1 }, { P7_0, PWM_8, 1 },
+ { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 }, { P5_1, PWM_9, 1 }, { P7_1, PWM_9, 1 },
+ { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 }, { P5_2, PWM_10, 1 }, { P7_2, PWM_10, 1 },
+ { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 }, { P5_3, PWM_11, 1 }, { P7_3, PWM_11, 1 },
+ { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 }, { P5_4, PWM_12, 1 }, { P7_4, PWM_12, 1 },
+ { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 }, { P5_5, PWM_13, 1 }, { P7_5, PWM_13, 1 },
+ { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 }, { P5_6, PWM_14, 1 }, { P7_6, PWM_14, 1 },
+ { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 }, { P5_7, PWM_15, 1 }, { P7_7, PWM_15, 1 },
+ { NC, NC, 0 }
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+ { AIN_0, ADC, ADC_CH_0 },
+ { AIN_1, ADC, ADC_CH_1 },
+ { AIN_2, ADC, ADC_CH_2 },
+ { AIN_3, ADC, ADC_CH_3 },
+ { AIN_4, ADC, ADC_CH_0_DIV_5 },
+ { AIN_5, ADC, ADC_CH_1_DIV_5 },
+ { AIN_6, ADC, ADC_CH_VDDB_DIV_4 },
+ { AIN_7, ADC, ADC_CH_VDD18 },
+ { AIN_8, ADC, ADC_CH_VDD12 },
+ { AIN_9, ADC, ADC_CH_VRTC_DIV_2 },
+ { NC, NC, 0 }
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/PeripheralPins.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" + +//************I2C*************** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//************UART*************** +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +//************SPI*************** +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +//************PWM*************** +extern const PinMap PinMap_PWM[]; + +//************ADC*************** +extern const PinMap PinMap_ADC[]; +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/PortNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,56 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1,
+ Port2,
+ Port3,
+ Port4,
+ Port5,
+ Port6,
+ Port7,
+ Port8,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PeripheralNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = MXC_BASE_UART0,
+ UART_1 = MXC_BASE_UART1,
+ UART_2 = MXC_BASE_UART2,
+ UART_3 = MXC_BASE_UART3,
+ STDIO_UART = UART_1
+} UARTName;
+
+typedef enum {
+ I2C_0 = MXC_BASE_I2CM0,
+ I2C_1 = MXC_BASE_I2CM1,
+ I2C_2 = MXC_BASE_I2CM2
+} I2CName;
+
+typedef enum {
+ SPI_0 = MXC_BASE_SPIM0,
+ SPI_1 = MXC_BASE_SPIM1,
+ SPI_2 = MXC_BASE_SPIM2
+} SPIName;
+
+typedef enum {
+ PWM_0 = MXC_BASE_PT0,
+ PWM_1 = MXC_BASE_PT1,
+ PWM_2 = MXC_BASE_PT2,
+ PWM_3 = MXC_BASE_PT3,
+ PWM_4 = MXC_BASE_PT4,
+ PWM_5 = MXC_BASE_PT5,
+ PWM_6 = MXC_BASE_PT6,
+ PWM_7 = MXC_BASE_PT7,
+ PWM_8 = MXC_BASE_PT8,
+ PWM_9 = MXC_BASE_PT9,
+ PWM_10 = MXC_BASE_PT10,
+ PWM_11 = MXC_BASE_PT11,
+ PWM_12 = MXC_BASE_PT12,
+ PWM_13 = MXC_BASE_PT13,
+ PWM_14 = MXC_BASE_PT14,
+ PWM_15 = MXC_BASE_PT15
+} PWMName;
+
+typedef enum {
+ ADC = MXC_BASE_ADC
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,180 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z,
+ PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL
+} PinDirection;
+
+#define PORT_SHIFT 12
+#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT)
+#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
+
+#define NOT_CONNECTED (int)0xFFFFFFFF
+
+typedef enum {
+ P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7,
+ P1_0 = (1 << PORT_SHIFT), P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7,
+ P2_0 = (2 << PORT_SHIFT), P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7,
+ P3_0 = (3 << PORT_SHIFT), P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7,
+ P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
+ P5_0 = (5 << PORT_SHIFT), P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7,
+ P6_0 = (6 << PORT_SHIFT), P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7,
+ P7_0 = (7 << PORT_SHIFT), P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7,
+ P8_0 = (8 << PORT_SHIFT), P8_1,
+
+ // Analog input pins
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
+
+ // LEDs
+ LED_RED = P2_4,
+ LED_GREEN = P2_5,
+ LED_BLUE = P2_6,
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+ LED4 = LED_RED,
+
+ // Push button
+ SW1 = P2_3,
+ SW2 = NOT_CONNECTED,
+ SW3 = NOT_CONNECTED,
+
+ // USB bridge connected UART pins
+ USBTX = P2_1,
+ USBRX = P2_0,
+ STDIO_UART_TX = USBTX,
+ STDIO_UART_RX = USBRX,
+
+ // I2C pins
+ I2C0_SCL = NOT_CONNECTED,
+ I2C0_SDA = NOT_CONNECTED,
+
+ I2C1_SCL = P3_5,
+ I2C1_SDA = P3_4,
+
+ I2C2_SCL = P6_0,
+ I2C2_SDA = P5_7,
+
+ // UART pins
+ UART0_RX = P0_0,
+ UART0_TX = P0_1,
+ UART0_CTS = P0_2,
+ UART0_RTS = P0_3,
+
+ UART1_RX = P2_0,
+ UART1_TX = P2_1,
+ UART1_CTS = NOT_CONNECTED,
+ UART1_RTS = NOT_CONNECTED,
+
+ UART2_RX = P3_0,
+ UART2_TX = P3_1,
+ UART2_CTS = P3_2,
+ UART2_RTS = P3_3,
+
+ UART3_RX = P5_3,
+ UART3_TX = P5_4,
+ UART3_CTS = P5_5,
+ UART3_RTS = P5_6,
+
+ // SPI pins
+ SPI0_SCK = P0_4,
+ SPI0_MOSI = P0_5,
+ SPI0_MISO = P0_6,
+ SPI0_SS = P0_7,
+
+ SPI1_SCK = P1_0,
+ SPI1_MOSI = P1_1,
+ SPI1_MISO = P1_2,
+ SPI1_SS = P1_3,
+ SPI1_DIO2 = P1_4,
+ SPI1_DIO3 = P1_5,
+
+ SPI2_SCK = P5_0,
+ SPI2_MOSI = P5_1,
+ SPI2_MISO = P5_2,
+ SPI2_SS = P5_3,
+ SPI2_SDIO2 = P5_4,
+ SPI2_SDIO3 = P5_5,
+ SPI2_SRN = P5_6,
+
+ // 1-Wire Master
+ OWM = P4_0,
+
+ // BTLE Module hardwired
+ BT_RST = P1_6,
+ BT_CLK = P1_7,
+
+ // MAX14690N hardwired
+ PMIC_INT = P3_7,
+ MPC = P2_7,
+ MON = AIN_0,
+
+ // BMI160 hardwired
+ IMU_INT = P3_6,
+
+ // microSD hardwired
+ DETECT = P2_2,
+
+ // Not connected
+ NC = NOT_CONNECTED
+} PinName;
+
+typedef enum {
+ PullUp,
+ PullDown,
+ OpenDrain,
+ PullNone,
+ PullDefault = PullUp
+} PinMode;
+
+typedef enum {
+ LED_ON = 0,
+ LED_OFF = 1
+} LedStates;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/TARGET_MAX32630FTHR/low_level_init.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "cmsis.h"
+#include "i2cm_regs.h"
+#include "ioman_regs.h"
+#include "clkman_regs.h"
+
+//******************************************************************************
+// This function will get called early in system initialization
+void low_level_init(void)
+{
+ /* The MAX32630FTHR board utilizes the MAX14690N PMIC which has the 3.3V
+ * LDO supplying the VDDB and VDDIOH disabled by default. USB cannot
+ * be initialized until this regulator is enabled. This code enables
+ * the regulator early in the process so that the system does not hang
+ * if USB is configured before the PMIC is configured in user code.
+ */
+ MXC_CLKMAN->sys_clk_ctrl_9_i2cm = 1; // source clock for I2C
+ MXC_CLKMAN->i2c_timer_ctrl = 1; // enable timer for timeouts
+ MXC_IOMAN->i2cm2_req = 0x10; // Request mode A
+ // Configure clock divider for 96MHz (worst case)
+ MXC_I2CM2->fs_clk_div =((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS));
+
+ // Reset module
+ MXC_I2CM2->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
+ MXC_I2CM2->ctrl = 0;
+
+ // Enable tx_fifo and rx_fifo
+ MXC_I2CM2->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
+
+ // Disable and clear the interrupts
+ MXC_I2CM2->inten = 0;
+ MXC_I2CM2->intfl = MXC_I2CM2->intfl;
+
+ // Write the address to the TXFIFO
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address
+
+ // Start the transaction
+ MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+ // Load write data into the FIFO
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x15); // ldo2vset register addresss
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x19); // 3.3V
+ // Send the stop condition
+ MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP;
+
+ // Wait for first write to complete
+ while (MXC_I2CM2->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS);
+
+ // Write the address to the TXFIFO
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_START | 0x50); // MAX14690 PMIC I2C Address
+
+ // Start the transaction
+ MXC_I2CM2->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+ // Load write data into the FIFO
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x14); // ldo2cfg register address
+ MXC_I2CM2_FIFO->tx = (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | 0x02); // ldo enabled
+ // Send the stop condition
+ MXC_I2CM2_FIFO->tx = MXC_S_I2CM_TRANS_TAG_STOP;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "adc.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+#define ADC_FULL_SCALE 0x3FFU
+#define INT_FULL_SCALE 0xFFFFU
+#define FLOAT_FULL_SCALE 1.0f
+
+static int initialized = 0;
+
+//******************************************************************************
+void analogin_init(analogin_t *obj, PinName pin)
+{
+ // Make sure pin is an analog pin we can use for ADC
+ MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC);
+
+ // Set the object pointer and channel encoding
+ obj->adc = MXC_ADC;
+ obj->channel = pinmap_find_function(pin, PinMap_ADC);
+
+ if (!initialized) {
+ MBED_ASSERT(ADC_Init() == E_NO_ERROR);
+ initialized = 1;
+ }
+}
+
+//******************************************************************************
+float analogin_read(analogin_t *obj)
+{
+ uint16_t tmp;
+ float result;
+
+ // Start conversion with no input scaling and no input buffer bypass
+ ADC_StartConvert(obj->channel, 1, 0);
+
+ if (ADC_GetData(&tmp) == E_OVERFLOW) {
+ result = FLOAT_FULL_SCALE;
+ } else {
+ result = (float)tmp * (FLOAT_FULL_SCALE / (float)ADC_FULL_SCALE);
+ }
+
+ return result;
+}
+
+//******************************************************************************
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+ uint16_t tmp;
+ uint16_t result;
+
+ // Start conversion with no input scaling and no input buffer bypass
+ ADC_StartConvert(obj->channel, 1, 0);
+
+ if (ADC_GetData(&tmp) == E_OVERFLOW) {
+ result = INT_FULL_SCALE;
+ } else {
+ result = ((tmp << 6) & 0xFFC0) | ((tmp >> 4) & 0x003F);
+ }
+
+ return result;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/MAX3263x.sct Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,16 @@
+; MAX3263x
+; 2MB FLASH (0x200000) @ 0x000000000
+; 512KB RAM (0x80000) @ 0x20000000
+
+LR_IROM1 0x000000000 0x200000 { ; load region size_region
+ ER_IROM1 0x000000000 0x200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110)
+ RW_IRAM1 (0x20000000+0x110) (0x80000-0x110) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,297 @@ +;******************************************************************************* +; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + +__initial_sp EQU 0x20080000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Maxim MAX3263x external interrupts + DCD CLKMAN_IRQHandler ; 16:01 CLKMAN + DCD PWRMAN_IRQHandler ; 17:02 PWRMAN + DCD FLC_IRQHandler ; 18:03 Flash Controller + DCD RTC0_IRQHandler ; 19:04 RTC INT0 + DCD RTC1_IRQHandler ; 20:05 RTC INT1 + DCD RTC2_IRQHandler ; 21:06 RTC INT2 + DCD RTC3_IRQHandler ; 22:07 RTC INT3 + DCD PMU_IRQHandler ; 23:08 PMU + DCD USB_IRQHandler ; 24:09 USB + DCD AES_IRQHandler ; 25:10 AES + DCD MAA_IRQHandler ; 26:11 MAA + DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 + DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW + DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 + DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW + DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 + DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 + DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 + DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 + DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 + DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 + DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 + DCD TMR0_IRQHandler ; 38:23 Timer32-0 + DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 + DCD TMR1_IRQHandler ; 40:25 Timer32-1 + DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 + DCD TMR2_IRQHandler ; 42:27 Timer32-2 + DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 + DCD TMR3_IRQHandler ; 44:29 Timer32-3 + DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 + DCD TMR4_IRQHandler ; 46:31 Timer32-4 + DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 + DCD TMR5_IRQHandler ; 48:33 Timer32-5 + DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 + DCD PT_IRQHandler ; 50:35 PT + DCD UART0_IRQHandler ; 51:36 UART0 + DCD UART1_IRQHandler ; 52:37 UART1 + DCD UART2_IRQHandler ; 53:38 UART0 + DCD UART3_IRQHandler ; 54:39 UART1 + DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 + DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 + DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 + DCD I2CS_IRQHandler ; 58:43 I2C Slave + DCD SPIM0_IRQHandler ; 59:44 SPIM0 + DCD SPIM1_IRQHandler ; 60:45 SPIM1 + DCD SPIM2_IRQHandler ; 61:46 SPIM2 + DCD SPIB_IRQHandler ; 62:47 SPI Bridge + DCD OWM_IRQHandler ; 63:48 SPI Bridge + DCD AFE_IRQHandler ; 64:49 AFE + DCD SPIS_IRQHandler ; 65:50 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + IMPORT PreInit + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 +__SPIN + WFI + BL __SPIN + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B NMI_Handler + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Handler + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B MemManage_Handler + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B BusFault_Handler + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B UsageFault_Handler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B SVC_Handler + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B DebugMon_Handler + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B PendSV_Handler + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B SysTick_Handler + ENDP + +Default_Handler PROC + + ; MAX3263x interrupts + EXPORT CLKMAN_IRQHandler [WEAK] ; 16:01 CLKMAN + EXPORT PWRMAN_IRQHandler [WEAK] ; 17:02 PWRMAN + EXPORT FLC_IRQHandler [WEAK] ; 18:03 Flash Controller + EXPORT RTC0_IRQHandler [WEAK] ; 19:04 RTC INT0 + EXPORT RTC1_IRQHandler [WEAK] ; 20:05 RTC INT1 + EXPORT RTC2_IRQHandler [WEAK] ; 21:06 RTC INT2 + EXPORT RTC3_IRQHandler [WEAK] ; 22:07 RTC INT3 + EXPORT PMU_IRQHandler [WEAK] ; 23:08 PMU + EXPORT USB_IRQHandler [WEAK] ; 24:09 USB + EXPORT AES_IRQHandler [WEAK] ; 25:10 AES + EXPORT MAA_IRQHandler [WEAK] ; 26:11 MAA + EXPORT WDT0_IRQHandler [WEAK] ; 27:12 WATCHDOG0 + EXPORT WDT0_P_IRQHandler [WEAK] ; 28:13 WATCHDOG0 PRE-WINDOW + EXPORT WDT1_IRQHandler [WEAK] ; 29:14 WATCHDOG1 + EXPORT WDT1_P_IRQHandler [WEAK] ; 30:15 WATCHDOG1 PRE-WINDOW + EXPORT GPIO_P0_IRQHandler [WEAK] ; 31:16 GPIO Port 0 + EXPORT GPIO_P1_IRQHandler [WEAK] ; 32:17 GPIO Port 1 + EXPORT GPIO_P2_IRQHandler [WEAK] ; 33:18 GPIO Port 2 + EXPORT GPIO_P3_IRQHandler [WEAK] ; 34:19 GPIO Port 3 + EXPORT GPIO_P4_IRQHandler [WEAK] ; 35:20 GPIO Port 4 + EXPORT GPIO_P5_IRQHandler [WEAK] ; 36:21 GPIO Port 5 + EXPORT GPIO_P6_IRQHandler [WEAK] ; 37:22 GPIO Port 6 + EXPORT TMR0_IRQHandler [WEAK] ; 38:23 Timer32-0 + EXPORT TMR16_0_IRQHandler [WEAK] ; 39:24 Timer16-s0 + EXPORT TMR1_IRQHandler [WEAK] ; 40:25 Timer32-1 + EXPORT TMR16_1_IRQHandler [WEAK] ; 41:26 Timer16-s1 + EXPORT TMR2_IRQHandler [WEAK] ; 42:27 Timer32-2 + EXPORT TMR16_2_IRQHandler [WEAK] ; 43:28 Timer16-s2 + EXPORT TMR3_IRQHandler [WEAK] ; 44:29 Timer32-3 + EXPORT TMR16_3_IRQHandler [WEAK] ; 45:30 Timer16-s3 + EXPORT TMR4_IRQHandler [WEAK] ; 46:31 Timer32-4 + EXPORT TMR16_4_IRQHandler [WEAK] ; 47:32 Timer16-s4 + EXPORT TMR5_IRQHandler [WEAK] ; 48:33 Timer32-5 + EXPORT TMR16_5_IRQHandler [WEAK] ; 49:34 Timer16-s5 + EXPORT PT_IRQHandler [WEAK] ; 50:35 PT + EXPORT UART0_IRQHandler [WEAK] ; 51:36 UART0 + EXPORT UART1_IRQHandler [WEAK] ; 52:37 UART1 + EXPORT UART2_IRQHandler [WEAK] ; 53:38 UART0 + EXPORT UART3_IRQHandler [WEAK] ; 54:39 UART1 + EXPORT I2CM0_IRQHandler [WEAK] ; 55:40 I2C Master 0 + EXPORT I2CM1_IRQHandler [WEAK] ; 56:41 I2C Master 1 + EXPORT I2CM2_IRQHandler [WEAK] ; 57:42 I2C Master 2 + EXPORT I2CS_IRQHandler [WEAK] ; 58:43 I2C Slave + EXPORT SPIM0_IRQHandler [WEAK] ; 59:44 SPIM0 + EXPORT SPIM1_IRQHandler [WEAK] ; 60:45 SPIM1 + EXPORT SPIM2_IRQHandler [WEAK] ; 61:46 SPIM2 + EXPORT SPIB_IRQHandler [WEAK] ; 62:47 SPI Bridge + EXPORT OWM_IRQHandler [WEAK] ; 63:48 SPI Bridge + EXPORT AFE_IRQHandler [WEAK] ; 64:49 AFE + EXPORT SPIS_IRQHandler [WEAK] ; 65:50 SPI Slave + EXPORT GPIO_P7_IRQHandler [WEAK] ; 66:51 GPIO Port 7 + EXPORT GPIO_P8_IRQHandler [WEAK] ; 67:52 GPIO Port 8 + +CLKMAN_IRQHandler +PWRMAN_IRQHandler +FLC_IRQHandler +RTC0_IRQHandler +RTC1_IRQHandler +RTC2_IRQHandler +RTC3_IRQHandler +PMU_IRQHandler +USB_IRQHandler +AES_IRQHandler +MAA_IRQHandler +WDT0_IRQHandler +WDT0_P_IRQHandler +WDT1_IRQHandler +WDT1_P_IRQHandler +GPIO_P0_IRQHandler +GPIO_P1_IRQHandler +GPIO_P2_IRQHandler +GPIO_P3_IRQHandler +GPIO_P4_IRQHandler +GPIO_P5_IRQHandler +GPIO_P6_IRQHandler +TMR0_IRQHandler +TMR16_0_IRQHandler +TMR1_IRQHandler +TMR16_1_IRQHandler +TMR2_IRQHandler +TMR16_2_IRQHandler +TMR3_IRQHandler +TMR16_3_IRQHandler +TMR4_IRQHandler +TMR16_4_IRQHandler +TMR5_IRQHandler +TMR16_5_IRQHandler +PT_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +I2CM0_IRQHandler +I2CM1_IRQHandler +I2CM2_IRQHandler +I2CS_IRQHandler +SPIM0_IRQHandler +SPIM1_IRQHandler +SPIM2_IRQHandler +SPIB_IRQHandler +OWM_IRQHandler +AFE_IRQHandler +SPIS_IRQHandler +GPIO_P7_IRQHandler +GPIO_P8_IRQHandler + + B . + ENDP + ALIGN + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,57 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/max3263x.ld Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,176 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00200000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_GCC_ARM/startup_max3263x.S Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,303 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00005000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x0000A000
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* MAX3263X Interrupts */
+ .long CLKMAN_IRQHandler /* 16:01 CLKMAN */
+ .long PWRMAN_IRQHandler /* 17:02 PWRMAN */
+ .long FLC_IRQHandler /* 18:03 Flash Controller */
+ .long RTC0_IRQHandler /* 19:04 RTC INT0 */
+ .long RTC1_IRQHandler /* 20:05 RTC INT1 */
+ .long RTC2_IRQHandler /* 21:06 RTC INT2 */
+ .long RTC3_IRQHandler /* 22:07 RTC INT3 */
+ .long PMU_IRQHandler /* 23:08 PMU */
+ .long USB_IRQHandler /* 24:09 USB */
+ .long AES_IRQHandler /* 25:10 AES */
+ .long MAA_IRQHandler /* 26:11 MAA */
+ .long WDT0_IRQHandler /* 27:12 WATCHDOG0 */
+ .long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
+ .long WDT1_IRQHandler /* 29:14 WATCHDOG1 */
+ .long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
+ .long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
+ .long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
+ .long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
+ .long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
+ .long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
+ .long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
+ .long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
+ .long TMR0_IRQHandler /* 38:23 Timer32-0 */
+ .long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
+ .long TMR1_IRQHandler /* 40:25 Timer32-1 */
+ .long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
+ .long TMR2_IRQHandler /* 42:27 Timer32-2 */
+ .long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
+ .long TMR3_IRQHandler /* 44:29 Timer32-3 */
+ .long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
+ .long TMR4_IRQHandler /* 46:31 Timer32-4 */
+ .long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
+ .long TMR5_IRQHandler /* 48:33 Timer32-5 */
+ .long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
+ .long UART0_IRQHandler /* 50:35 UART0 */
+ .long UART1_IRQHandler /* 51:36 UART1 */
+ .long UART2_IRQHandler /* 52:37 UART2 */
+ .long UART3_IRQHandler /* 53:38 UART3 */
+ .long PT_IRQHandler /* 54:39 PT */
+ .long I2CM0_IRQHandler /* 55:40 I2C Master 0 */
+ .long I2CM1_IRQHandler /* 56:41 I2C Master 1 */
+ .long I2CM2_IRQHandler /* 57:42 I2C Master 2 */
+ .long I2CS_IRQHandler /* 58:43 I2C Slave */
+ .long SPIM0_IRQHandler /* 59:44 SPIM0 */
+ .long SPIM1_IRQHandler /* 60:45 SPIM1 */
+ .long SPIM2_IRQHandler /* 61:46 SPIM2 */
+ .long SPIB_IRQHandler /* 62:47 SPI Bridge */
+ .long OWM_IRQHandler /* 63:48 One-wire Master */
+ .long AFE_IRQHandler /* 64:49 AFE */
+ .long SPIS_IRQHandler /* 65:50 SPI Slave */
+ .long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
+ .long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =__StackTop
+ mov sp, r0
+
+ /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */
+ ldr r0, =PreInit
+ blx r0
+ cbnz r0, .SKIPRAMINIT
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * _etext: End of code section, i.e., begin of data sections to copy from.
+ * _data /_edata: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+#if 0
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+#else
+ subs r3, r2
+ ble .LC1
+.LC0:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0
+.LC1:
+#endif
+
+/*
+ * Loop to zero out BSS section, which uses following symbols
+ * in linker script:
+ * _bss : start of BSS section. Must align to 4
+ * _ebss : end of BSS section. Must align to 4
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+.SKIPRAMINIT:
+
+ /* Perform system initialization after RAM initialization */
+ ldr r0, =SystemInit
+ blx r0
+
+ /* This must be called to walk the constructor array for static C++ objects */
+ /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */
+ /* where X is {preinit, init, fini} */
+ ldr r0, =_start
+ blx r0
+
+.SPIN:
+ /* Enter LP2 if main() ever returns. */
+ wfi
+ bl .SPIN
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+ def_irq_handler Default_Handler
+
+ /* MAX3263X Interrupts */
+ def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */
+ def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */
+ def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */
+ def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */
+ def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */
+ def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */
+ def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */
+ def_irq_handler PMU_IRQHandler /* 23:08 PMU */
+ def_irq_handler USB_IRQHandler /* 24:09 USB */
+ def_irq_handler AES_IRQHandler /* 25:10 AES */
+ def_irq_handler MAA_IRQHandler /* 26:11 MAA */
+ def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */
+ def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
+ def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */
+ def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
+ def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
+ def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
+ def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
+ def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
+ def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
+ def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
+ def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
+ def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */
+ def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
+ def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */
+ def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
+ def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */
+ def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
+ def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */
+ def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
+ def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */
+ def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
+ def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */
+ def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
+ def_irq_handler PT_IRQHandler /* 50:35 PT */
+ def_irq_handler UART0_IRQHandler /* 51:36 UART0 */
+ def_irq_handler UART1_IRQHandler /* 52:37 UART1 */
+ def_irq_handler UART2_IRQHandler /* 53:38 UART0 */
+ def_irq_handler UART3_IRQHandler /* 54:39 UART1 */
+ def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */
+ def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */
+ def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */
+ def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */
+ def_irq_handler SPIM0_IRQHandler /* 59:44 SPIM0 */
+ def_irq_handler SPIM1_IRQHandler /* 60:45 SPIM1 */
+ def_irq_handler SPIM2_IRQHandler /* 61:46 SPIM2 */
+ def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */
+ def_irq_handler OWM_IRQHandler /* 63:48 SPI Bridge */
+ def_irq_handler AFE_IRQHandler /* 64:49 AFE */
+ def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */
+ def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
+ def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
+ .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/MAX3263x.icf Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,29 @@
+/* [ROM] */
+define symbol __intvec_start__ = 0x00000000;
+define symbol __region_ROM_start__ = 0x00000000;
+define symbol __region_ROM_end__ = 0x001FFFFF;
+
+/* [RAM] Vector table dynamic copy: 68 vectors * 4 bytes = 272 (0x110) bytes */
+define symbol __NVIC_start__ = 0x00000000;
+define symbol __NVIC_end__ = 0x00000110; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000000;
+define symbol __region_RAM_end__ = 0x2007FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x5000;
+define symbol __size_heap__ = 0xA000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_IAR/startup_MAX3263x.S Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,450 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN PreInit + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_modify + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler +__vector_table_modify + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; MAX3263x Specific Interrupts + DCD CLKMAN_IRQHandler ; 16:01 CLKMAN */ + DCD PWRMAN_IRQHandler ; 17:02 PWRMAN */ + DCD FLC_IRQHandler ; 18:03 Flash Controller */ + DCD RTC0_IRQHandler ; 19:04 RTC INT0 */ + DCD RTC1_IRQHandler ; 20:05 RTC INT1 */ + DCD RTC2_IRQHandler ; 21:06 RTC INT2 */ + DCD RTC3_IRQHandler ; 22:07 RTC INT3 */ + DCD PMU_IRQHandler ; 23:08 PMU */ + DCD USB_IRQHandler ; 24:09 USB */ + DCD AES_IRQHandler ; 25:10 AES */ + DCD MAA_IRQHandler ; 26:11 MAA */ + DCD WDT0_IRQHandler ; 27:12 WATCHDOG0 */ + DCD WDT0_P_IRQHandler ; 28:13 WATCHDOG0 PRE-WINDOW */ + DCD WDT1_IRQHandler ; 29:14 WATCHDOG1 */ + DCD WDT1_P_IRQHandler ; 30:15 WATCHDOG1 PRE-WINDOW */ + DCD GPIO_P0_IRQHandler ; 31:16 GPIO Port 0 */ + DCD GPIO_P1_IRQHandler ; 32:17 GPIO Port 1 */ + DCD GPIO_P2_IRQHandler ; 33:18 GPIO Port 2 */ + DCD GPIO_P3_IRQHandler ; 34:19 GPIO Port 3 */ + DCD GPIO_P4_IRQHandler ; 35:20 GPIO Port 4 */ + DCD GPIO_P5_IRQHandler ; 36:21 GPIO Port 5 */ + DCD GPIO_P6_IRQHandler ; 37:22 GPIO Port 6 */ + DCD TMR0_IRQHandler ; 38:23 Timer32-0 */ + DCD TMR16_0_IRQHandler ; 39:24 Timer16-s0 */ + DCD TMR1_IRQHandler ; 40:25 Timer32-1 */ + DCD TMR16_1_IRQHandler ; 41:26 Timer16-s1 */ + DCD TMR2_IRQHandler ; 42:27 Timer32-2 */ + DCD TMR16_2_IRQHandler ; 43:28 Timer16-s2 */ + DCD TMR3_IRQHandler ; 44:29 Timer32-3 */ + DCD TMR16_3_IRQHandler ; 45:30 Timer16-s3 */ + DCD TMR4_IRQHandler ; 46:31 Timer32-4 */ + DCD TMR16_4_IRQHandler ; 47:32 Timer16-s4 */ + DCD TMR5_IRQHandler ; 48:33 Timer32-5 */ + DCD TMR16_5_IRQHandler ; 49:34 Timer16-s5 */ + DCD UART0_IRQHandler ; 50:35 UART0 */ + DCD UART1_IRQHandler ; 51:36 UART1 */ + DCD UART2_IRQHandler ; 52:37 UART2 */ + DCD UART3_IRQHandler ; 53:38 UART3 */ + DCD PT_IRQHandler ; 54:39 PT */ + DCD I2CM0_IRQHandler ; 55:40 I2C Master 0 */ + DCD I2CM1_IRQHandler ; 56:41 I2C Master 1 */ + DCD I2CM2_IRQHandler ; 57:42 I2C Master 2 */ + DCD I2CS_IRQHandler ; 58:43 I2C Slave */ + DCD SPIM0_IRQHandler ; 59:44 SPI Master 0 */ + DCD SPIM1_IRQHandler ; 60:45 SPI Master 1 */ + DCD SPIM2_IRQHandler ; 61:46 SPI Master 2 */ + DCD SPIB_IRQHandler ; 62:47 SPI Bridge */ + DCD OWM_IRQHandler ; 63:48 One-wire Master */ + DCD AFE_IRQHandler ; 64:49 AFE */ + DCD SPIS_IRQHandler ; 65:50 SPI Slave + DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7 + DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8 + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK CLKMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CLKMAN_IRQHandler + B CLKMAN_IRQHandler + + PUBWEAK PWRMAN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWRMAN_IRQHandler + B PWRMAN_IRQHandler + + PUBWEAK FLC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLC_IRQHandler + B FLC_IRQHandler + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B RTC0_IRQHandler + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B RTC1_IRQHandler + + PUBWEAK RTC2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC2_IRQHandler + B RTC2_IRQHandler + + PUBWEAK RTC3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC3_IRQHandler + B RTC3_IRQHandler + + PUBWEAK PMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PMU_IRQHandler + B PMU_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK MAA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MAA_IRQHandler + B MAA_IRQHandler + + PUBWEAK WDT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_IRQHandler + B WDT0_IRQHandler + + PUBWEAK WDT0_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT0_P_IRQHandler + B WDT0_P_IRQHandler + + PUBWEAK WDT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_IRQHandler + B WDT1_IRQHandler + + PUBWEAK WDT1_P_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT1_P_IRQHandler + B WDT1_P_IRQHandler + + PUBWEAK GPIO_P0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P0_IRQHandler + B GPIO_P0_IRQHandler + + PUBWEAK GPIO_P1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P1_IRQHandler + B GPIO_P1_IRQHandler + + PUBWEAK GPIO_P2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P2_IRQHandler + B GPIO_P2_IRQHandler + + PUBWEAK GPIO_P3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P3_IRQHandler + B GPIO_P3_IRQHandler + + PUBWEAK GPIO_P4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P4_IRQHandler + B GPIO_P4_IRQHandler + + PUBWEAK GPIO_P5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P5_IRQHandler + B GPIO_P5_IRQHandler + + PUBWEAK GPIO_P6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P6_IRQHandler + B GPIO_P6_IRQHandler + + PUBWEAK TMR0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR0_IRQHandler + B TMR0_IRQHandler + + PUBWEAK TMR16_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_0_IRQHandler + B TMR16_0_IRQHandler + + PUBWEAK TMR1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR1_IRQHandler + B TMR1_IRQHandler + + PUBWEAK TMR16_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_1_IRQHandler + B TMR16_1_IRQHandler + + PUBWEAK TMR2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR2_IRQHandler + B TMR2_IRQHandler + + PUBWEAK TMR16_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_2_IRQHandler + B TMR16_2_IRQHandler + + PUBWEAK TMR3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR3_IRQHandler + B TMR3_IRQHandler + + PUBWEAK TMR16_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_3_IRQHandler + B TMR16_3_IRQHandler + + PUBWEAK TMR4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR4_IRQHandler + B TMR4_IRQHandler + + PUBWEAK TMR16_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_4_IRQHandler + B TMR16_4_IRQHandler + + PUBWEAK TMR5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR5_IRQHandler + B TMR5_IRQHandler + + PUBWEAK TMR16_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TMR16_5_IRQHandler + B TMR16_5_IRQHandler + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK PT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PT_IRQHandler + B PT_IRQHandler + + PUBWEAK I2CM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM0_IRQHandler + B I2CM0_IRQHandler + + PUBWEAK I2CM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM1_IRQHandler + B I2CM1_IRQHandler + + PUBWEAK I2CM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CM2_IRQHandler + B I2CM2_IRQHandler + + PUBWEAK I2CS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2CS_IRQHandler + B I2CS_IRQHandler + + PUBWEAK SPIM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM0_IRQHandler + B SPIM0_IRQHandler + + PUBWEAK SPIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM1_IRQHandler + B SPIM1_IRQHandler + + PUBWEAK SPIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM2_IRQHandler + B SPIM2_IRQHandler + + PUBWEAK SPIB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIB_IRQHandler + B SPIB_IRQHandler + + PUBWEAK OWM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OWM_IRQHandler + B OWM_IRQHandler + + PUBWEAK AFE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AFE_IRQHandler + B AFE_IRQHandler + + PUBWEAK SPIS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIS_IRQHandler + B SPIS_IRQHandler + + PUBWEAK GPIO_P7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P7_IRQHandler + B GPIO_P7_IRQHandler + + PUBWEAK GPIO_P8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_P8_IRQHandler + B GPIO_P8_IRQHandler + END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,393 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-30 19:43:43 -0500 (Fri, 30 Sep 2016) $
+ * $Revision: 24540 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ADC_REGS_H_
+#define _MXC_ADC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup adc
+ * @defgroup adc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
+ */
+
+/**
+ * @ingroup adc_registers
+ * Structure type to access the ADC Registers.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */
+ __IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */
+ __IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */
+ __IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */
+ __IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */
+ __IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */
+ __IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */
+ __IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */
+ __IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */
+} mxc_adc_regs_t;
+
+
+/* Register offsets for module ADC. */
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_Register_Offsets Register Offsets
+ * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */
+#define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */
+#define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */
+#define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */
+#define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */
+#define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */
+#define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */
+#define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */
+#define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */
+#define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */
+/**@} end of group adc_registers */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_CTRL_Register ADC_CTRL
+ * @brief Field Positions and Bit Masks for the ADC_CTRL register
+ * @{
+ */
+#define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */
+#define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */
+#define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */
+#define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */
+#define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */
+#define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */
+#define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */
+#define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */
+#define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */
+#define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */
+#define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */
+#define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */
+#define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */
+#define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */
+#define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */
+#define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */
+#define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */
+#define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */
+#define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */
+#define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */
+#define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */
+#define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */
+
+#if (MXC_ADC_REV == 0)
+#define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */
+#define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */
+#endif
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */
+#define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */
+#define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */
+
+/**@} end of group adc_ctrl_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_STATUS_Register ADC_STATUS
+ * @brief Field Positions and Bit Masks for the ADC_STATUS register
+ * @{
+ */
+#define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */
+#define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */
+#define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */
+#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */
+#define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */
+/**@} end of group ADC_STATUS_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_DATA_Register ADC_DATA
+ * @brief Field Positions and Bit Masks for the ADC_DATA register
+ * @{
+ */
+#define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */
+#define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */
+/**@} end of group ADC_DATA_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_INTR_Register ADC_INTR Register
+ * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks
+ */
+/**
+ * @ingroup ADC_INTR_Register
+ * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits
+ * @brief Interrupt Enable Bit Positions and Masks
+ * @{
+ */
+#define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */
+#define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */
+/**@} end of group ADC_INTR_IE_Register */
+
+
+/**
+ * @ingroup ADC_INTR_Register
+ * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits
+ * @brief Interrupt Flag Bit Positions and Masks
+ * @{
+ */
+#define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */
+#define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */
+#define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */
+#define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */
+#define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */
+#define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */
+#define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */
+#define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */
+#define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */
+/**@} end of group ADC_INTR_IF_Register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_LIMIT0_Register ADC_LIMIT0
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT0_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_LIMIT1_Register ADC_LIMIT1
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT1_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_LIMIT2_Register ADC_LIMIT2
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT2_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_LIMIT3_Register ADC_LIMIT3
+ * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register
+ * @{
+ */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
+#define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */
+#define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
+#define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
+/**@} end of group ADC_LIMIT3_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL
+ * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register
+ * @{
+ */
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */
+#define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */
+#define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */
+/**@} end of group ADC_AFE_CTRL_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */
+#define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */
+#define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */
+#define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */
+#define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */
+#define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */
+/**@} end of group ADC_RO_CAL0_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */
+#define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */
+#define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */
+#define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */
+/**@} end of group RO_CAL1_register */
+
+/**
+ * @ingroup adc_registers
+ * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2
+ * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register
+ * @{
+ */
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */
+#define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */
+/**@} end of group RO_CAL2_register */
+
+/**
+ * @ingroup ADC_CTRL_Register
+ * @defgroup ADC_CHSEL_values ADC Channel Select Values
+ * @brief Channel Select Values
+ * @{
+ */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */
+
+#if(MXC_ADC_REV > 0)
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */
+#define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */
+#endif
+/**@} end of group ADC_CHSEL_values */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ADC_REGS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/aes_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,188 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24655 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_AES_REGS_H_
+#define _MXC_AES_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup aes
+ * @defgroup aes_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type to access the AES Registers.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_CTRL Register */
+ __RO uint32_t rsv004; /**< <tt>\b 0x0004:</tt> RESERVED */
+ __IO uint32_t erase_all; /**< <tt>\b 0x0008:</tt> AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */
+} mxc_aes_regs_t;
+
+/**
+ * Structure type to access the AES Memory Registers.
+ */
+typedef struct {
+ __IO uint32_t inp[4]; /**< <tt>\b 0x0000-0x000C:</tt> AES Input (128 bits) */
+ __IO uint32_t key[8]; /**< <tt>\b 0x0010-0x002C:</tt> AES Symmetric Key (up to 256 bits) */
+ __IO uint32_t out[4]; /**< <tt>\b 0x0030-0x003C:</tt> AES Output Data (128 bits) */
+ __IO uint32_t expkey[8]; /**< <tt>\b 0x0040-0x005C:</tt> AES Expanded Key Data (256 bits) */
+} mxc_aes_mem_regs_t;
+/**@} end of group aes_registers */
+
+ /**
+ * @ingroup aes_registers
+ * @defgroup AES_Register_Offsets Register Offsets
+ * @brief AES Register Offsets from the AES Base Peripheral Address.
+ * @{
+ */
+/**
+ * AES Register offsets from the AES base peripheral address.
+ */
+#define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
+#define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
+#define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
+#define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0004</tt> */
+#define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
+#define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x000C</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0010</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0014</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0018</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x001C</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0020</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0024</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0028</tt> */
+#define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x002C</tt> */
+#define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0030</tt> */
+#define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0034</tt> */
+#define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0038</tt> */
+#define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x003C</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0040</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0044</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0048</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x004C</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0050</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0054</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0058</tt> */
+#define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x005C</tt> */
+/**@} end of group AES_Register_Offsets */
+
+/**
+ * @ingroup aes_registers
+ * @defgroup AES_CTRL_Register AES_CTRL
+ * @brief Field Positions and Bit Masks for the AES_CTRL register
+ * @{
+ */
+#define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */
+#define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */
+#define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */
+#define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */
+#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */
+#define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */
+#define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */
+#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */
+#define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */
+#define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */
+#define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */
+#define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */
+#define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */
+#define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */
+/**@} end of aes_registers group */
+
+/*
+ Field values and shifted values for module AES.
+*/
+///@cond
+#define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */
+#define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */
+
+#define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/
+#define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/
+
+#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */
+#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */
+
+#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/
+#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/
+
+#define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */
+#define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */
+#define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */
+
+#define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */
+#define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */
+#define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */
+///@endcond
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_AES_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,493 @@
+/**
+ * @file
+ * @brief Type definitions for the Clock Management Interface
+ *
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
+ * $Revision: 24058 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+
+/**
+ * @ingroup clkman
+ * @defgroup clkman_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+
+/**
+ * Structure type for the Clock Management module registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t clk_config; /**< <tt>\b 0x0000: </tt> CLKMAN_CLK_CONFIG Register - System Clock Configuration */
+ __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> CLKMAN_CLK_CTRL Register - System Clock Controls */
+ __IO uint32_t intfl; /**< <tt>\b 0x0008: </tt> CLKMAN_INTFL Register - Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x000C: </tt> CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */
+ __IO uint32_t trim_calc; /**< <tt>\b 0x0010: </tt> CLKMAN_TRIM_CALC Register - Trim Calculation Controls */
+ __IO uint32_t i2c_timer_ctrl; /**< <tt>\b 0x0014: </tt> CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */
+ __IO uint32_t cm4_start_clk_en0; /**< <tt>\b 0x0018: </tt> CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */
+ __IO uint32_t cm4_start_clk_en1; /**< <tt>\b 0x001C: </tt> CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */
+ __IO uint32_t cm4_start_clk_en2; /**< <tt>\b 0x0020: </tt> CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */
+ __RO uint32_t rsv024[7]; /**< <tt>\b 0x0024-0x003C:</tt> RESERVED */
+ __IO uint32_t sys_clk_ctrl_0_cm4; /**< <tt>\b 0x0040: </tt> CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */
+ __IO uint32_t sys_clk_ctrl_1_sync; /**< <tt>\b 0x0044: </tt> CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */
+ __IO uint32_t sys_clk_ctrl_2_spix; /**< <tt>\b 0x0048: </tt> CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */
+ __IO uint32_t sys_clk_ctrl_3_prng; /**< <tt>\b 0x004C: </tt> CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */
+ __IO uint32_t sys_clk_ctrl_4_wdt0; /**< <tt>\b 0x0050: </tt> CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */
+ __IO uint32_t sys_clk_ctrl_5_wdt1; /**< <tt>\b 0x0054: </tt> CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */
+ __IO uint32_t sys_clk_ctrl_6_gpio; /**< <tt>\b 0x0058: </tt> CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */
+ __IO uint32_t sys_clk_ctrl_7_pt; /**< <tt>\b 0x005C: </tt> CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */
+ __IO uint32_t sys_clk_ctrl_8_uart; /**< <tt>\b 0x0060: </tt> CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */
+ __IO uint32_t sys_clk_ctrl_9_i2cm; /**< <tt>\b 0x0064: </tt> CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */
+ __IO uint32_t sys_clk_ctrl_10_i2cs; /**< <tt>\b 0x0068: </tt> CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */
+ __IO uint32_t sys_clk_ctrl_11_spi0; /**< <tt>\b 0x006C: </tt> CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */
+ __IO uint32_t sys_clk_ctrl_12_spi1; /**< <tt>\b 0x0070: </tt> CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */
+ __IO uint32_t sys_clk_ctrl_13_spi2; /**< <tt>\b 0x0074: </tt> CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */
+ __IO uint32_t sys_clk_ctrl_14_spib; /**< <tt>\b 0x0078: </tt> CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */
+ __IO uint32_t sys_clk_ctrl_15_owm; /**< <tt>\b 0x007C: </tt> CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */
+ __IO uint32_t sys_clk_ctrl_16_spis; /**< <tt>\b 0x0080: </tt> CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */
+ __RO uint32_t rsv084[31]; /**< <tt>\b 0x0084-0x00FC:</tt> RESERVED: */
+ __IO uint32_t crypt_clk_ctrl_0_aes; /**< <tt>\b 0x0100: </tt> CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */
+ __IO uint32_t crypt_clk_ctrl_1_maa; /**< <tt>\b 0x0104: </tt> CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */
+ __IO uint32_t crypt_clk_ctrl_2_prng; /**< <tt>\b 0x0108: </tt> CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */
+ __RO uint32_t rsv10C[13]; /**< <tt>\b 0x010C-0x013C:</tt> RESERVED */
+ __IO uint32_t clk_gate_ctrl0; /**< <tt>\b 0x0140: </tt> CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */
+ __IO uint32_t clk_gate_ctrl1; /**< <tt>\b 0x0144: </tt> CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */
+ __IO uint32_t clk_gate_ctrl2; /**< <tt>\b 0x0148: </tt> CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */
+} mxc_clkman_regs_t;
+/**@} end of clkman_registers */
+
+/*
+ Register offsets for module CLKMAN.
+*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup CLKMAN_Register_Offsets Register Offsets
+ * @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0008</tt> */
+#define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x000C</tt> */
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0010</tt> */
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0014</tt> */
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0018</tt> */
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x001C</tt> */
+#define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0020</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0040</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0044</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0048</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x004C</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0050</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0054</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0058</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x005C</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0060</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0064</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0068</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x006C</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0070</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0074</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0078</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x007C</tt> */
+#define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0080</tt> */
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0100</tt> */
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0104</tt> */
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0108</tt> */
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0140</tt> */
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0144</tt> */
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0148</tt> */
+/**@} end of CLKMAN_Register_Offsets */
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */
+#define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_int_flags CLKMAN_INTFL Register
+ * @brief Interrupt Flag Positions and Masks
+ */
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */
+#define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_int_enable CLKMAN_INTEN Register
+ * @brief Interrupt Enable Positions and Masks
+ */
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */
+#define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_cm4 CLKMAN_CM4 Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */
+#define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */
+#define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */
+
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */
+#define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */
+#define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
+/**@}*/
+/**
+ * @ingroup clkman_registers
+ * @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register
+ * @brief Peripheral Clock Gating Field Positions and Masks
+ */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */
+/**@}*/
+/**
+ * @ingroup clkman_clk_config
+ * @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings
+ * @brief Crypto Clock Stability Count Setting Values and Shifted Values
+ */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>8</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>9</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>10</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>11</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>12</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>13</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>14</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>15</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>16</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>17</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>18</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>19</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>20</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>21</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>22</SUP> */
+#define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>23</SUP> */
+
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>8</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>9</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>10</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>11</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>12</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>13</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>14</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>15</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>16</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>17</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>18</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>19</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>20</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>21</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>22</SUP> */
+#define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>23</SUP> */
+
+/**@} clkman_crypto_stability_count */
+
+/**
+ * @ingroup clkman_clk_ctrl
+ * @defgroup clkman_sysclock_select System Clock Select Values
+ * @brief System Clock Selection Values and Shifted Values for selecting the system clock source
+ * @{
+ */
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
+#define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
+#define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */
+/**@} end of clkman_sysclock_select group */
+///@cond
+
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
+#define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
+#define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
+#define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+#define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
+///@endcond
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_CLKMAN_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/cmsis.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max3263x.h" +#include "nvic_table.h" + +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/crc_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,133 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24657 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_CRC_REGS_H_
+#define _MXC_CRC_REGS_H_
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup crc
+ * @defgroup crc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type for the CRC peripheral registers for reseeding and seeding the CRC16/32
+ */
+typedef struct {
+ __IO uint32_t reseed; /**< <tt>\b 0x0000:</tt> CRC_RESEED Register */
+ __IO uint32_t seed16; /**< <tt>\b 0x0004:</tt> CRC_SEED16 Register */
+ __IO uint32_t seed32; /**< <tt>\b 0x0008:</tt> CRC_SEED32 Register */
+} mxc_crc_regs_t;
+
+/**
+ * Structure type for the CRC Data Values.
+ */
+typedef struct {
+ __IO uint32_t value16[512]; /**< <tt>\b 0x0000:</tt> CRC16_DATA Register */
+ __IO uint32_t value32[512]; /**< <tt>\b 0x8000:</tt> CRC32_DATA Register */
+} mxc_crc_data_regs_t;
+/**@} end of group crc_registers */
+
+/* Register offsets for module CRC. */
+/**
+ * @ingroup crc_registers
+ * @defgroup CRC_Register_Offsets Register Offsets
+ * @brief CRC Peripheral Module Register Offsets from the CRC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_CRC_OFFS_RESEED ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_CRC_OFFS_SEED16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_CRC_OFFS_SEED32 ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: <tt>\b 0x0008</tt> */
+#define MXC_R_CRC_DATA_OFFS_VALUE16 ((uint32_t)0x00000000UL) /**< Offset from CRC DATA Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_CRC_DATA_OFFS_VALUE32 ((uint32_t)0x00000800UL) /**< Offset from CRC DATA Base Address: <tt>\b 0x8000</tt> */
+/**@} end of group CRC_Register_offsets */
+
+/**
+ * @ingroup crc_registers
+ * @defgroup CRC_RESEED_Register CRC_RESEED
+ * @brief Field Positions and Bit Masks for the CRC_RESEED register
+ * @{
+ */
+#define MXC_F_CRC_RESEED_CRC16_POS 0 /**< CRC16 Position */
+#define MXC_F_CRC_RESEED_CRC16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS)) /**< CRC16 Mask */
+#define MXC_F_CRC_RESEED_CRC32_POS 1 /**< CRC32 Position */
+#define MXC_F_CRC_RESEED_CRC32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS)) /**< CRC32 Mask */
+#define MXC_F_CRC_RESEED_REV_ENDIAN16_POS 4 /**< REV_ENDIAN16 Position */
+#define MXC_F_CRC_RESEED_REV_ENDIAN16 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN16_POS)) /**< REV_ENDIAN16 Mask */
+#define MXC_F_CRC_RESEED_REV_ENDIAN32_POS 5 /**< REV_ENDIAN32 Position */
+#define MXC_F_CRC_RESEED_REV_ENDIAN32 ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_REV_ENDIAN32_POS)) /**< REV_ENDIAN32 Mask */
+#define MXC_F_CRC_RESEED_CCITT_MODE_POS 8 /**< CCITT_MODE Position */
+#define MXC_F_CRC_RESEED_CCITT_MODE ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CCITT_MODE_POS)) /**< CCITT_MODE Mask */
+/**@} end of CRC_RESEED_Fields */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_CRC_REGS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/flc_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,395 @@
+/**
+ * @file
+ * @brief registers, bit masks and bit positions for the Flash
+ * Controller (FLC) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, Maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24658 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_FLC_REGS_H_
+#define _MXC_FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+/**
+ * @ingroup flc
+ * @defgroup flc_registers Registers
+ * @brief Registers, Bit Masks, Bit Positions and Values for the FLC Peripheral Module.
+ */
+/* **** Definitions **** */
+/**
+ * @ingroup flc_registers
+ * @defgroup flc_special_codes Flash Controller Codes/Keys.
+ * @brief Required values to pass to the flash controller to perform restricted
+ * operations.
+ * @{
+ */
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55) /**< Page Erase Code required to perform a page erase operation */
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA) /**< Mass Erase Code required to perform a page erase operation */
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2) /**< Unlock Code required to unlock the flash for erase and write functions */
+/**@} end of flc_special_codes */
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/**
+ * @ingroup flc_registers
+ * @brief Structure type to access the Flash Controller registers with
+ * direct 32-bit access to each.
+ */
+typedef struct {
+ __IO uint32_t faddr; /**< <tt>\b 0x0000: </tt> FLC_FADDR Register - Flash Operation Address */
+ __IO uint32_t fckdiv; /**< <tt>\b 0x0004: </tt> FLC_FCKDIV Register - Flash Clock Pulse Divisor */
+ __IO uint32_t ctrl; /**< <tt>\b 0x0008: </tt> FLC_CTRL Register - Flash Control Register */
+ __RO uint32_t rsv00C[6]; /**< <tt>\b 0x000C-0x0020:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t intr; /**< <tt>\b 0x0024: </tt> FLC_INTR Register - Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __RO uint32_t rsv028[2]; /**< <tt>\b 0x0028-0x002C:</tt> RESERVED */
+ __IO uint32_t fdata; /**< <tt>\b 0x0030: </tt> FLC_FDATA Register - Flash Operation Data Register */
+ __RO uint32_t rsv034[7]; /**< <tt>\b 0x0034-0x004C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t perform; /**< <tt>\b 0x0050: </tt> FLC_PERFORM Register - Flash Performance Settings */
+ __IO uint32_t tacc; /**< <tt>\b 0x0054: </tt> FLC_TACC Register - Flash Read Cycle Config */
+ __IO uint32_t tprog; /**< <tt>\b 0x0058: </tt> FLC_TPROG Register - Flash Write Cycle Config */
+ __RO uint32_t rsv05C[9]; /**< <tt>\b 0x005C-0x007C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t status; /**< <tt>\b 0x0080: </tt> FLC_STATUS Register - Security Status Flags */
+ __RO uint32_t rsv084; /**< <tt>\b 0x0084: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t security; /**< <tt>\b 0x0088: </tt> FLC_SECURITY Register - Flash Controller Security Settings */
+ __RO uint32_t rsv08C[4]; /**< <tt>\b 0x008C-0x0098:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t bypass; /**< <tt>\b 0x009C: </tt> FLC_BYPASS Register - Status Flags for DSB Operations */
+ __RO uint32_t rsv0A0[24]; /**< <tt>\b 0x00A0-0x00FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t user_option; /**< <tt>\b 0x0100: </tt> FLC_USER_OPTION Register - Used to set DSB Access code and Auto-Lock in info block */
+ __RO uint32_t rsv104[15]; /**< <tt>\b 0x0104-0x013C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t ctrl2; /**< <tt>\b 0x0140: </tt> FLC_CTRL2 Register - Flash Control Register 2 */
+ __IO uint32_t intfl1; /**< <tt>\b 0x0144: </tt> FLC_INTFL1 Register - Interrupt Flags Register 1 */
+ __IO uint32_t inten1; /**< <tt>\b 0x0148: </tt> FLC_INTEN1 Register - Interrupt Enable/Disable Register 1 */
+ __RO uint32_t rsv14C[9]; /**< <tt>\b 0x014C-0x016C:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t bl_ctrl; /**< <tt>\b 0x0170: </tt> FLC_BL_CTRL Register - Bootloader Control Register */
+ __IO uint32_t twk; /**< <tt>\b 0x0174: </tt> FLC_TWK Register - PDM33 Register */
+ __RO uint32_t rsv178; /**< <tt>\b 0x0178: </tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t slm; /**< <tt>\b 0x017C: </tt> FLC_SLM Register - Sleep Mode Register */
+ __RO uint32_t rsv180[32]; /**< <tt>\b 0x0180-0x01FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t disable_xr0; /**< <tt>\b 0x0200: </tt> FLC_DISABLE_XR0 Register - Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /**< <tt>\b 0x0204: </tt> FLC_DISABLE_XR1 Register - Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /**< <tt>\b 0x0208: </tt> FLC_DISABLE_XR2 Register - Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /**< <tt>\b 0x020C: </tt> FLC_DISABLE_XR3 Register - Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_xr4; /**< <tt>\b 0x0210: </tt> FLC_DISABLE_XR4 Register - Disable Flash Page Exec/Read Register 4 */
+ __IO uint32_t disable_xr5; /**< <tt>\b 0x0214: </tt> FLC_DISABLE_XR5 Register - Disable Flash Page Exec/Read Register 5 */
+ __IO uint32_t disable_xr6; /**< <tt>\b 0x0218: </tt> FLC_DISABLE_XR6 Register - Disable Flash Page Exec/Read Register 6 */
+ __IO uint32_t disable_xr7; /**< <tt>\b 0x021C: </tt> FLC_DISABLE_XR7 Register - Disable Flash Page Exec/Read Register 7 */
+ __RO uint32_t rsv220[56]; /**< <tt>\b 0x0220-0x02FC:</tt> RESERVED \warning Do Not Modify Reserved Locations! */
+ __IO uint32_t disable_we0; /**< <tt>\b 0x0300: </tt> FLC_DISABLE_WE0 Register - Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /**< <tt>\b 0x0304: </tt> FLC_DISABLE_WE1 Register - Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /**< <tt>\b 0x0308: </tt> FLC_DISABLE_WE2 Register - Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /**< <tt>\b 0x030C: </tt> FLC_DISABLE_WE3 Register - Disable Flash Page Write/Erase Register 3 */
+ __IO uint32_t disable_we4; /**< <tt>\b 0x0310: </tt> FLC_DISABLE_WE4 Register - Disable Flash Page Write/Erase Register 4 */
+ __IO uint32_t disable_we5; /**< <tt>\b 0x0314: </tt> FLC_DISABLE_WE5 Register - Disable Flash Page Write/Erase Register 5 */
+ __IO uint32_t disable_we6; /**< <tt>\b 0x0318: </tt> FLC_DISABLE_WE6 Register - Disable Flash Page Write/Erase Register 6 */
+ __IO uint32_t disable_we7; /**< <tt>\b 0x031C: </tt> FLC_DISABLE_WE7 Register - Disable Flash Page Write/Erase Register 7 */
+} mxc_flc_regs_t;
+/*
+ Register offsets for module FLC.
+*/
+
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_Register_Offsets Register Offsets
+ * @brief Flash Controller Register Offsets from the FLC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt>\b 0x0008</tt> */
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt>\b 0x0024</tt> */
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt>\b 0x0030</tt> */
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL) /**< Offset from FLC Base Address: <tt>\b 0x0050</tt> */
+#define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL) /**< Offset from FLC Base Address: <tt>\b 0x0054</tt> */
+#define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL) /**< Offset from FLC Base Address: <tt>\b 0x0058</tt> */
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt>\b 0x0080</tt> */
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt>\b 0x0088</tt> */
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt>\b 0x009C</tt> */
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL) /**< Offset from FLC Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL) /**< Offset from FLC Base Address: <tt>\b 0x0140</tt> */
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL) /**< Offset from FLC Base Address: <tt>\b 0x0144</tt> */
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL) /**< Offset from FLC Base Address: <tt>\b 0x0148</tt> */
+#define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL) /**< Offset from FLC Base Address: <tt>\b 0x0170</tt> */
+#define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL) /**< Offset from FLC Base Address: <tt>\b 0x0174</tt> */
+#define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL) /**< Offset from FLC Base Address: <tt>\b 0x017C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL) /**< Offset from FLC Base Address: <tt>\b 0x0200</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL) /**< Offset from FLC Base Address: <tt>\b 0x0204</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL) /**< Offset from FLC Base Address: <tt>\b 0x0208</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL) /**< Offset from FLC Base Address: <tt>\b 0x020C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL) /**< Offset from FLC Base Address: <tt>\b 0x0210</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL) /**< Offset from FLC Base Address: <tt>\b 0x0214</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL) /**< Offset from FLC Base Address: <tt>\b 0x0218</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL) /**< Offset from FLC Base Address: <tt>\b 0x021C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL) /**< Offset from FLC Base Address: <tt>\b 0x0300</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL) /**< Offset from FLC Base Address: <tt>\b 0x0304</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL) /**< Offset from FLC Base Address: <tt>\b 0x0308</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL) /**< Offset from FLC Base Address: <tt>\b 0x030C</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL) /**< Offset from FLC Base Address: <tt>\b 0x0310</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL) /**< Offset from FLC Base Address: <tt>\b 0x0314</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL) /**< Offset from FLC Base Address: <tt>\b 0x0318</tt> */
+#define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL) /**< Offset from FLC Base Address: <tt>\b 0x031C</tt> */
+/**@} end of group FLC_Register_Offsets */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_FADDR_Register FLC_FADDR
+ * @brief Field Positions and Bit Masks for the FLC_FADDR register.
+ * @{
+ */
+#define MXC_F_FLC_FADDR_FADDR_POS 0 /**< FADDR Position */
+#define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS)) /**< FADDR Mask */
+/**@} end of group FLC_FADDR */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_FCKDIV_Register FLC_FCKDIV
+ * @brief Field Positions and Bit Masks for the FLC_FCKDIV register.
+ * @{
+ */
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS /**< FCKDIV Position */
+#define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS)) /**< FCKDIV Mask */
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16 /**< AUTO_FCKDIV_RESULT Position */
+#define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS)) /**< AUTO_FCKDIV_RESULT Mask */
+/**@} end of group FLC_FCKDIV */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_CTRL_Register FLC_CTRL
+ * @brief Field Positions and Bit Masks for the FLC_CTRL register.
+ * @{
+ */
+#define MXC_F_FLC_CTRL_WRITE_POS 0 /**< WRITE Position */
+#define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< WRITE Mask */
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< MASS_ERASE Position */
+#define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< MASS_ERASE Mask */
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< PAGE_ERASE Position */
+#define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< PAGE_ERASE Mask */
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< ERASE_CODE Position */
+#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< ERASE_CODE Mask */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16 /**< INFO_BLOCK_UNLOCK Position */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS)) /**< INFO_BLOCK_UNLOCK Mask */
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17 /**< WRITE_ENABLE Position */
+#define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS)) /**< WRITE_ENABLE Mask */
+#define MXC_F_FLC_CTRL_PENDING_POS 24 /**< PENDING Position */
+#define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS)) /**< PENDING Mask */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25 /**< INFO_BLOCK_VALID Position */
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27 /**< AUTO_INCRE_MODE Position */
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS)) /**< AUTO_INCRE_MODE Mask */
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28 /**< FLSH_UNLOCK Position */
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS)) /**< FLSH_UNLOCK Mask */
+/**@} end of group FLC_CTRL */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_INTR_Register FLC_INTR
+ * @brief Field Positions and Bit Masks for the FLC_INTR register.
+ * @{
+ */
+#define MXC_F_FLC_INTR_FINISHED_IF_POS 0 /**< FINISHED_IF Position */
+#define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS)) /**< FINISHED_IF Mask */
+#define MXC_F_FLC_INTR_FAILED_IF_POS 1 /**< FAILED_IF Position */
+#define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS)) /**< FAILED_IF Mask */
+#define MXC_F_FLC_INTR_FINISHED_IE_POS 8 /**< FINISHED_IE Position */
+#define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS)) /**< FINISHED_IE Mask */
+#define MXC_F_FLC_INTR_FAILED_IE_POS 9 /**< FAILED_IE Position */
+#define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS)) /**< FAILED_IE Mask */
+#define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16 /**< FAIL_FLAGS Position */
+#define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS)) /**< FAIL_FLAGS Mask */
+/**@} end of group FLC_INTR */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_PERFORM_Register FLC_PERFORM
+ * @brief Field Positions and Bit Masks for the FLC_PERFORM register.
+ * @{
+ */
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0 /**< DELAY_SE_EN Position */
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS)) /**< DELAY_SE_EN Mask */
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8 /**< FAST_READ_MODE_EN Position */
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS)) /**< FAST_READ_MODE_EN Mask */
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12 /**< EN_PREVENT_FAIL Position */
+#define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS)) /**< EN_PREVENT_FAIL Mask */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16 /**< EN_BACK2BACK_RDS Position */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS)) /**< EN_BACK2BACK_RDS Mask */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20 /**< EN_BACK2BACK_WRS Position */
+#define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS)) /**< EN_BACK2BACK_WRS Mask */
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24 /**< EN_MERGE_GRAB_GNT Position */
+#define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS)) /**< EN_MERGE_GRAB_GNT Mask */
+#define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28 /**< AUTO_TACC Position */
+#define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS)) /**< AUTO_TACC Mask */
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29 /**< AUTO_CLKDIV Position */
+#define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS)) /**< AUTO_CLKDIV Mask */
+/**@} end of group FLC_PERFORM */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_STATUS_Register FLC_STATUS
+ * @brief Field Positions and Bit Masks for the FLC_STATUS register.
+ * @{
+ */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0 /**< JTAG_LOCK_WINDOW Position */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS)) /**< JTAG_LOCK_WINDOW Mask */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1 /**< JTAG_LOCK_STATIC Position */
+#define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS)) /**< JTAG_LOCK_STATIC Mask */
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3 /**< AUTO_LOCK Position */
+#define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS)) /**< AUTO_LOCK Mask */
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30 /**< INFO_BLOCK_VALID Position */
+#define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS)) /**< INFO_BLOCK_VALID Mask */
+/**@} end of group FLC_STATUS*/
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_SECURITY_Register FLC_SECURITY
+ * @brief Field Positions and Bit Masks for the FLC_SECURITY register.
+ * @{
+ */
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0 /**< DEBUG_DISABLE Position */
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS)) /**< DEBUG_DISABLE Mask */
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8 /**< MASS_ERASE_LOCK Position */
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS)) /**< MASS_ERASE_LOCK Mask */
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16 /**< DISABLE_AHB_WR Position */
+#define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS)) /**< DISABLE_AHB_WR Mask */
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24 /**< FLC_SETTINGS_LOCK Position */
+#define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS)) /**< FLC_SETTINGS_LOCK Mask */
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28 /**< SECURITY_LOCK Position */
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS)) /**< SECURITY_LOCK Mask */
+/**@} end of group FLC_SECURITY */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_BYPASS_Register FLC_BYPASS
+ * @brief Field Positions and Bit Masks for the FLC_BYPASS register.
+ * @{
+ */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0 /**< DESTRUCT_BYPASS_ERASE Position */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS)) /**< DESTRUCT_BYPASS_ERASE Mask */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1 /**< SUPERWIPE_ERASE Position */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS)) /**< SUPERWIPE_ERASE Mask */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2 /**< DESTRUCT_BYPASS_COMPLETE Position */
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS)) /**< DESTRUCT_BYPASS_COMPLETE Mask */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3 /**< SUPERWIPE_COMPLETE Position */
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS)) /**< SUPERWIPE_COMPLETE Mask */
+/**@} end of group FLC_BYPASS*/
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_CTRL2_Register FLC_CTRL2
+ * @brief Field Positions and Bit Masks for the FLC_CTRL2 register.
+ * @{
+ */
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0 /**< FLASH_LVE Position */
+#define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS)) /**< FLASH_LVE Mask */
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1 /**< FRC_FCLK1_ON Position */
+#define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS)) /**< FRC_FCLK1_ON Mask */
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3 /**< EN_WRITE_ALL_ZEROES Position */
+#define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS)) /**< EN_WRITE_ALL_ZEROES Mask */
+#define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4 /**< EN_CHANGE Position */
+#define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS)) /**< EN_CHANGE Mask */
+#define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5 /**< SLOW_CLK Position */
+#define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS)) /**< SLOW_CLK Mask */
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6 /**< ENABLE_RAM_HRESP Position */
+#define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS)) /**< ENABLE_RAM_HRESP Mask */
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8 /**< BYPASS_AHB_FAIL Position */
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS)) /**< BYPASS_AHB_FAIL Mask */
+/**@} end of group FLC_CTRL2*/
+ /**
+ * @ingroup flc_registers
+ * @defgroup FLC_INTFL1_Register FLC_INTFL1
+ * @brief Field Positions and Bit Masks for the FLC_INTFL1 register.
+ * @{
+ */
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
+#define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
+#define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
+/**@} end of group FLC_INTFL1 */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_INTEN1_Register FLC_INTEN1
+ * @brief Field Positions and Bit Masks for the FLC_INTEN1 register.
+ * @{
+ */
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0 /**< SRAM_ADDR_WRAPPED Position */
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS)) /**< SRAM_ADDR_WRAPPED Mask */
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1 /**< INVALID_FLASH_ADDR Position */
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS)) /**< INVALID_FLASH_ADDR Mask */
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2 /**< FLASH_READ_LOCKED Position */
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS)) /**< FLASH_READ_LOCKED Mask */
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3 /**< TRIM_UPDATE_DONE Position */
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS)) /**< TRIM_UPDATE_DONE Mask */
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4 /**< FLC_STATE_DONE Position */
+#define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS)) /**< FLC_STATE_DONE Mask */
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5 /**< FLC_PROG_COMPLETE Position */
+#define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS)) /**< FLC_PROG_COMPLETE Mask */
+/**@} end of group FLC_INTEN1*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_FLC_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,668 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24659 $
+ *
+*************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup gpio
+ * @defgroup gpio_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
+ * @{
+ */
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/**
+ * Structure type to access the GPIO Registers
+ */
+typedef struct {
+ __IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */
+ __IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */
+ __IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */
+ __IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */
+ __IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */
+ __IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */
+ __IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */
+ __IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */
+ __IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */
+ __IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */
+} mxc_gpio_regs_t;
+/**@} end of gpio_registers group */
+
+/*
+ Register offsets for module GPIO.
+*/
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_Register_Offsets Register Offsets
+ * @brief GPIO Register Offsets from the GPIO Base Address.
+ * @{
+ */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets
+ * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */
+#define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */
+/**@} end of gpio_rst_mode group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets
+ * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */
+#define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */
+/**@} end of gpio_free group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers
+ * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */
+/**@} end of gpio_out_mode group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers
+ * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */
+#define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */
+/**@} end of gpio_out_val group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers
+ * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */
+/**@} end of gpio_func_sel */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers
+ * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */
+#define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */
+/**@} end of gpio_in_mode group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers
+ * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */
+#define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */
+/**@} end of gpio_in_val group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers
+ * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */
+#define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */
+/**@} end of gpio_int_mode group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers
+ * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */
+#define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */
+/**@} end of gpio_int_flag group */
+/**
+ * @ingroup GPIO_Register_Offsets
+ * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers
+ * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */
+#define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */
+/**@}*/
+/**@} end of GPIO_Register_Offsets */
+
+/*
+ Field positions and masks for module GPIO.
+*/
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE
+ * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FREE */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_FREE_Register GPIO_FREE
+ * @brief Field Positions and Bit Masks for the GPIO_FREE register.
+ * @{
+ */
+#define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FREE */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE
+ * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_OUT_MODE */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL
+ * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register.
+ * @{
+ */
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_OUT_VAL */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL
+ * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register.
+ * @{
+ */
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_FUNC_SEL */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE
+ * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_IN_MODE */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL
+ * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register.
+ * @{
+ */
+#define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_IN_VAL */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE
+ * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register.
+ * @{
+ */
+#define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */
+#define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */
+#define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */
+#define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */
+#define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */
+#define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */
+#define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */
+#define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_INT_MODE */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_INTFL_Register GPIO_INTFL
+ * @brief Field Positions and Bit Masks for the GPIO_INTFL register.
+ * @{
+ */
+#define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */
+/**@} end of group GPIO_INTFL */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_INTEN_Register GPIO_INTEN
+ * @brief Field Positions and Bit Masks for the GPIO_INTEN register.
+ * @{
+ */
+#define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */
+#define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */
+#define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */
+#define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */
+#define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */
+#define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */
+#define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */
+#define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */
+#define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */
+#define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */
+#define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */
+#define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */
+#define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */
+#define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */
+#define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */
+#define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */
+/**@} end group GPIO_INTEN_Register */
+
+
+/*
+ Field values and shifted values for module GPIO.
+*/
+/**
+ * @ingroup GPIO_RST_MODE_Register
+ * @defgroup GPIO_RST_MODE_Values Reset Mode Values
+ * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes
+ * @{
+ */
+#define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */
+#define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */
+#define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */
+#define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */
+/**@}*/
+
+/**
+ * @ingroup GPIO_FREE_Register
+ * @defgroup GPIO_FREE_Values Reset Mode Values
+ * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable
+ * @{
+ */
+#define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */
+#define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */
+/**@}*/
+
+/**
+ * @ingroup GPIO_FREE_Register
+ * @defgroup GPIO_OUT_MODE_Values Output Mode Values
+ * @brief GPIO_OUT_MODE values for setting the different port pin output modes
+ * @{
+ */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */
+#define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */
+/**@}*/
+
+/**
+ * @ingroup GPIO_FUNC_SEL_Register
+ * @defgroup GPIO_FUNC_SEL_Values Function type selection values
+ * @brief Function selection values for the GPIO_FUNC_SEL Register.
+ * @{
+ */
+#define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */
+#define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */
+#define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */
+/**@}*/
+
+/**
+ * @ingroup GPIO_IN_MODE_Register
+ * @defgroup GPIO_IN_MODE_Values Input mode selection values
+ * @brief Input mode values for selecting the GPIO input mode.
+ * @{
+ */
+#define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */
+#define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */
+#define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */
+/**@}*/
+
+/**
+ * @ingroup GPIO_INT_MODE_Register
+ * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values
+ * @brief Values for setting the interrupt mode of a GPIO input pin.
+ * @{
+ */
+#define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */
+#define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */
+#define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */
+#define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */
+/**@}*/
+
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_GPIO_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cm_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,282 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24660 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_I2CM_REGS_H_
+#define _MXC_I2CM_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+#define MXC_S_I2CM_TRANS_TAG_START 0x000
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
+#define MXC_S_I2CM_TRANS_TAG_STOP 0x700
+#define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
+#define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
+///@endcond
+
+/**
+ * @ingroup i2cm
+ * @defgroup i2cm_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type to access the I2CM Peripheral Module Registers
+ */
+typedef struct {
+ __IO uint32_t fs_clk_div; /**< <tt>\b 0x0000 </tt> \b I2CM_FS_CLK_DIV Register - Full Speed SCL Clock Settings */
+ __RO uint32_t rsv004[2]; /**< <tt>\b 0x0004-0x0008 </tt> \b RESERVED \warning Do Not Modify, Read Only */
+ __IO uint32_t timeout; /**< <tt>\b 0x000C </tt> \b I2CM_TIMEOUT Register - Timeout and Auto-Stop Settings */
+ __IO uint32_t ctrl; /**< <tt>\b 0x0010 </tt> \b I2CM_CTRL Register - Master Control Register */
+ __IO uint32_t trans; /**< <tt>\b 0x0014 </tt> \b I2CM_TRANS Register - Master Transaction Start and Status Flags */
+ __IO uint32_t intfl; /**< <tt>\b 0x0018 </tt> \b I2CM_INTFL Register - Master Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x001C </tt> \b I2CM_INTEN Register - Master Interrupt Enable/Disable Controls */
+ __RO uint32_t rsv020[2]; /**< <tt>\b 0x0020-0x0024 </tt> \b RESERVED \warning Do Not Modify, Read Only */
+ __IO uint32_t bb; /**< <tt>\b 0x0028 </tt> \b I2CM_BB Register - Master Bit-Bang Control Register */
+} mxc_i2cm_regs_t;
+
+
+/**
+ * Structure type for the I2CM Transmit and Receive FIFOs.
+ * The @c tx member is the write location for transmitting data and @c rx member is the read point for reading data.
+ *
+ */
+typedef struct {
+ union {
+ __IO uint16_t tx; /**< tx FIFO address */
+ __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO */
+ __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO */
+ __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO */
+ };
+ union {
+ __IO uint16_t rx; /**< RX FIFO address */
+ __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO */
+ __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO */
+ __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO */
+ };
+} mxc_i2cm_fifo_regs_t;
+/**@} end of group i2cm_registers */
+
+/*
+ Register offsets for module I2CM.
+*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_Register_Offsets Register Offsets
+ * @brief I2C Master Register Offsets from the I2CM[n] Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CM Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) /**< Offset from I2CM Base Address: <tt>\b 0x000C</tt> */
+#define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) /**< Offset from I2CM Base Address: <tt>\b 0x0010</tt> */
+#define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) /**< Offset from I2CM Base Address: <tt>\b 0x0014</tt> */
+#define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) /**< Offset from I2CM Base Address: <tt>\b 0x0018</tt> */
+#define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) /**< Offset from I2CM Base Address: <tt>\b 0x001C</tt> */
+#define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) /**< Offset from I2CM Base Address: <tt>\b 0x0028</tt> */
+#define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x8000</tt> */
+/**@} end of group i2cm_registers */
+
+/*
+ Field positions and masks for module I2CM.
+*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_FS_CLK_DIV_Register I2CM_FS_CLK_DIV
+ * @brief Field Positions and Bit Masks for the I2CM_FS_CLK_DIV register
+ * @{
+ */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 /**< FS_FILTER_CLK_DIV Position */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) /**< FS_FILTER_CLK_DIV Mask */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 /**< FS_SCL_LO_CNT Position */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) /**< FS_SCL_LO_CNT Mask */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 /**< FS_SCL_HI_CNT Position */
+#define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) /**< FS_SCL_HI_CNT Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_TIMEOUT_Register I2CM_TIMEOUT
+ * @brief Field Positions and Bit Masks for the I2CM_TIMEOUT register
+ * @{
+ */
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 /**< TX_TIMEOUT Position */
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 /**< AUTO_STOP_EN Position */
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) /**< AUTO_STOP_EN Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_CTRL_Register I2CM_CTRL
+ * @brief Field Positions and Bit Masks for the I2CM_CTRL register
+ * @{
+ */
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 /**< TX_FIFO_EN Position */
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 /**< RX_FIFO_EN Position */
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 /**< MSTR_RESET_EN Position */
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) /**< MSTR_RESET_EN Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_TRANS_Register I2CM_TRANS
+ * @brief Field Positions and Bit Masks for the I2CM_TRANS register
+ * @{
+ */
+#define MXC_F_I2CM_TRANS_TX_START_POS 0 /**< TX_START Position */
+#define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) /**< TX_START Mask */
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 /**< TX_IN_PROGRESS Position */
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) /**< TX_IN_PROGRESS Mask */
+#define MXC_F_I2CM_TRANS_TX_DONE_POS 2 /**< TX_DONE Position */
+#define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) /**< TX_DONE Mask */
+#define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 /**< TX_NACKED Position */
+#define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) /**< TX_NACKED Mask */
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 /**< TX_LOST_ARBITR Position */
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 /**< TX_TIMEOUT Position */
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_INTFL_Register I2CM_INTFL
+ * @brief Field Positions and Bit Masks for the I2CM_INTFL register
+ * @{
+ */
+#define MXC_F_I2CM_INTFL_TX_DONE_POS 0 /**< TX_DONE Position */
+#define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) /**< TX_DONE Mask */
+#define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 /**< TX_NACKED Position */
+#define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) /**< TX_NACKED Mask */
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_INTEN_Register I2CM_INTEN
+ * @brief Field Positions and Bit Masks for the I2CM_INTEN register
+ * @{
+ */
+#define MXC_F_I2CM_INTEN_TX_DONE_POS 0 /**< TX_DONE Position */
+#define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) /**< TX_DONE Mask */
+#define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 /**< TX_NACKED Position */
+#define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) /**< TX_NACKED Mask */
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */
+#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */
+#define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */
+/**@}*/
+/**
+ * @ingroup i2cm_registers
+ * @defgroup I2CM_BB_Register I2CM_BB
+ * @brief Field Positions and Bit Masks for the I2CM_BB register
+ * @{
+ */
+#define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 /**< BB_SCL_OUT Position */
+#define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) /**< BB_SCL_OUT Mask */
+#define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 /**< BB_SDA_OUT Position */
+#define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) /**< BB_SDA_OUT Mask */
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 /**< BB_SCL_IN_VAL Position */
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) /**< BB_SCL_IN_VAL Mask */
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 /**< BB_SDA_IN_VAL Position */
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) /**< BB_SDA_IN_VAL Mask */
+#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 /**< RX_FIFO_CNT Position */
+#define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) /**< RX_FIFO_CNT Mask */
+/**@}*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_I2CM_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/i2cs_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,291 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24661 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_I2CS_REGS_H_
+#define _MXC_I2CS_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup i2cs
+ * @defgroup i2cs_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type to access the I2CS Peripheral Module Registers
+ */
+ typedef struct {
+ __IO uint32_t clk_div; /**< <tt>\b 0x0000:</tt> I2CS_CLK_DIV Register - Clock Divisor Control */
+ __IO uint32_t dev_id; /**< <tt>\b 0x0004:</tt> I2CS_DEV_ID Register - Device ID Register */
+ __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> I2CS_INTFL Register - Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> I2CS_INTEN Register - Interrupt Enable */
+ __IO uint32_t data_byte[32]; /**< <tt>\b 0x0010-0x008C:</tt> I2CS_DATA_BYTE - Data Byte */
+} mxc_i2cs_regs_t;
+/**@} end of i2cs_registers */
+
+
+/*
+ Register offsets for module I2CS.
+*/
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_Register_Offsets Register Offsets
+ * @brief I2C Slave Register Offsets from the I2CS Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0000</tt> */
+#define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0004</tt> */
+#define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0008</tt> */
+#define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x000C</tt> */
+#define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0010-0x008C</tt> */
+/**@} I2CS_Register_Offsets */
+/*
+ Field positions and masks for module I2CS.
+*/
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_CLK_DIV_Register I2CS_CLK_DIV
+ * @brief Field Positions and Bit Masks for the I2CS_CLK_DIV register
+ * @{
+ */
+#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 /**< FS_FILTER_CLOCK_DIV Position */
+#define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) /**< FS_FILTER_CLOCK_DIV Mask */
+/**@} end group I2CS_CLK_DIV */
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_DEV_ID_Register I2CS_DEV_ID
+ * @brief Field Positions and Bit Masks for the I2CS_DEV_ID register
+ * @{
+ */
+#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 /**< SLAVE_DEV_ID Position */
+#define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) /**< SLAVE_DEV_ID Mask */
+#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 /**< TEN_BIT_ID_MODE Position */
+#define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) /**< TEN_BIT_ID_MODE Mask */
+#define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 /**< SLAVE_RESET Position */
+#define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) /**< SLAVE_RESET Mask */
+/**@} end group I2CS_DEV_ID */
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_INTFL_Register I2CS_INTFL
+ * @brief Field Positions and Bit Masks for the I2CS_INTFL register
+ * @{
+ */
+#define MXC_F_I2CS_INTFL_BYTE0_POS 0 /**< BYTE0 Position */
+#define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) /**< BYTE0 Mask */
+#define MXC_F_I2CS_INTFL_BYTE1_POS 1 /**< BYTE1 Position */
+#define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) /**< BYTE1 Mask */
+#define MXC_F_I2CS_INTFL_BYTE2_POS 2 /**< BYTE2 Position */
+#define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) /**< BYTE2 Mask */
+#define MXC_F_I2CS_INTFL_BYTE3_POS 3 /**< BYTE3 Position */
+#define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) /**< BYTE3 Mask */
+#define MXC_F_I2CS_INTFL_BYTE4_POS 4 /**< BYTE4 Position */
+#define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) /**< BYTE4 Mask */
+#define MXC_F_I2CS_INTFL_BYTE5_POS 5 /**< BYTE5 Position */
+#define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) /**< BYTE5 Mask */
+#define MXC_F_I2CS_INTFL_BYTE6_POS 6 /**< BYTE6 Position */
+#define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) /**< BYTE6 Mask */
+#define MXC_F_I2CS_INTFL_BYTE7_POS 7 /**< BYTE7 Position */
+#define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) /**< BYTE7 Mask */
+#define MXC_F_I2CS_INTFL_BYTE8_POS 8 /**< BYTE8 Position */
+#define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) /**< BYTE8 Mask */
+#define MXC_F_I2CS_INTFL_BYTE9_POS 9 /**< BYTE9 Position */
+#define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) /**< BYTE9 Mask */
+#define MXC_F_I2CS_INTFL_BYTE10_POS 10 /**< BYTE10 Position */
+#define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) /**< BYTE10 Mask */
+#define MXC_F_I2CS_INTFL_BYTE11_POS 11 /**< BYTE11 Position */
+#define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) /**< BYTE11 Mask */
+#define MXC_F_I2CS_INTFL_BYTE12_POS 12 /**< BYTE12 Position */
+#define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) /**< BYTE12 Mask */
+#define MXC_F_I2CS_INTFL_BYTE13_POS 13 /**< BYTE13 Position */
+#define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) /**< BYTE13 Mask */
+#define MXC_F_I2CS_INTFL_BYTE14_POS 14 /**< BYTE14 Position */
+#define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) /**< BYTE14 Mask */
+#define MXC_F_I2CS_INTFL_BYTE15_POS 15 /**< BYTE15 Position */
+#define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) /**< BYTE15 Mask */
+#define MXC_F_I2CS_INTFL_BYTE16_POS 16 /**< BYTE16 Position */
+#define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) /**< BYTE16 Mask */
+#define MXC_F_I2CS_INTFL_BYTE17_POS 17 /**< BYTE17 Position */
+#define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) /**< BYTE17 Mask */
+#define MXC_F_I2CS_INTFL_BYTE18_POS 18 /**< BYTE18 Position */
+#define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) /**< BYTE18 Mask */
+#define MXC_F_I2CS_INTFL_BYTE19_POS 19 /**< BYTE19 Position */
+#define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) /**< BYTE19 Mask */
+#define MXC_F_I2CS_INTFL_BYTE20_POS 20 /**< BYTE20 Position */
+#define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) /**< BYTE20 Mask */
+#define MXC_F_I2CS_INTFL_BYTE21_POS 21 /**< BYTE21 Position */
+#define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) /**< BYTE21 Mask */
+#define MXC_F_I2CS_INTFL_BYTE22_POS 22 /**< BYTE22 Position */
+#define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) /**< BYTE22 Mask */
+#define MXC_F_I2CS_INTFL_BYTE23_POS 23 /**< BYTE23 Position */
+#define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) /**< BYTE23 Mask */
+#define MXC_F_I2CS_INTFL_BYTE24_POS 24 /**< BYTE24 Position */
+#define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) /**< BYTE24 Mask */
+#define MXC_F_I2CS_INTFL_BYTE25_POS 25 /**< BYTE25 Position */
+#define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) /**< BYTE25 Mask */
+#define MXC_F_I2CS_INTFL_BYTE26_POS 26 /**< BYTE26 Position */
+#define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) /**< BYTE26 Mask */
+#define MXC_F_I2CS_INTFL_BYTE27_POS 27 /**< BYTE27 Position */
+#define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) /**< BYTE27 Mask */
+#define MXC_F_I2CS_INTFL_BYTE28_POS 28 /**< BYTE28 Position */
+#define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) /**< BYTE28 Mask */
+#define MXC_F_I2CS_INTFL_BYTE29_POS 29 /**< BYTE29 Position */
+#define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) /**< BYTE29 Mask */
+#define MXC_F_I2CS_INTFL_BYTE30_POS 30 /**< BYTE30 Position */
+#define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) /**< BYTE30 Mask */
+#define MXC_F_I2CS_INTFL_BYTE31_POS 31 /**< BYTE31 Position */
+#define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) /**< BYTE31 Mask */
+/**@} end group I2CS_INTFL */
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_INTEN_Register I2CS_INTEN
+ * @brief Field Positions and Bit Masks for the I2CS_INTEN register
+ * @{
+ */
+#define MXC_F_I2CS_INTEN_BYTE0_POS 0 /**< BYTE0 Position */
+#define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) /**< BYTE0 Mask */
+#define MXC_F_I2CS_INTEN_BYTE1_POS 1 /**< BYTE1 Position */
+#define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) /**< BYTE1 Mask */
+#define MXC_F_I2CS_INTEN_BYTE2_POS 2 /**< BYTE2 Position */
+#define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) /**< BYTE2 Mask */
+#define MXC_F_I2CS_INTEN_BYTE3_POS 3 /**< BYTE3 Position */
+#define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) /**< BYTE3 Mask */
+#define MXC_F_I2CS_INTEN_BYTE4_POS 4 /**< BYTE4 Position */
+#define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) /**< BYTE4 Mask */
+#define MXC_F_I2CS_INTEN_BYTE5_POS 5 /**< BYTE5 Position */
+#define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) /**< BYTE5 Mask */
+#define MXC_F_I2CS_INTEN_BYTE6_POS 6 /**< BYTE6 Position */
+#define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) /**< BYTE6 Mask */
+#define MXC_F_I2CS_INTEN_BYTE7_POS 7 /**< BYTE7 Position */
+#define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) /**< BYTE7 Mask */
+#define MXC_F_I2CS_INTEN_BYTE8_POS 8 /**< BYTE8 Position */
+#define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) /**< BYTE8 Mask */
+#define MXC_F_I2CS_INTEN_BYTE9_POS 9 /**< BYTE9 Position */
+#define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) /**< BYTE9 Mask */
+#define MXC_F_I2CS_INTEN_BYTE10_POS 10 /**< BYTE10 Position */
+#define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) /**< BYTE10 Mask */
+#define MXC_F_I2CS_INTEN_BYTE11_POS 11 /**< BYTE11 Position */
+#define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) /**< BYTE11 Mask */
+#define MXC_F_I2CS_INTEN_BYTE12_POS 12 /**< BYTE12 Position */
+#define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) /**< BYTE12 Mask */
+#define MXC_F_I2CS_INTEN_BYTE13_POS 13 /**< BYTE13 Position */
+#define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) /**< BYTE13 Mask */
+#define MXC_F_I2CS_INTEN_BYTE14_POS 14 /**< BYTE14 Position */
+#define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) /**< BYTE14 Mask */
+#define MXC_F_I2CS_INTEN_BYTE15_POS 15 /**< BYTE15 Position */
+#define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) /**< BYTE15 Mask */
+#define MXC_F_I2CS_INTEN_BYTE16_POS 16 /**< BYTE16 Position */
+#define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) /**< BYTE16 Mask */
+#define MXC_F_I2CS_INTEN_BYTE17_POS 17 /**< BYTE17 Position */
+#define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) /**< BYTE17 Mask */
+#define MXC_F_I2CS_INTEN_BYTE18_POS 18 /**< BYTE18 Position */
+#define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) /**< BYTE18 Mask */
+#define MXC_F_I2CS_INTEN_BYTE19_POS 19 /**< BYTE19 Position */
+#define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) /**< BYTE19 Mask */
+#define MXC_F_I2CS_INTEN_BYTE20_POS 20 /**< BYTE20 Position */
+#define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) /**< BYTE20 Mask */
+#define MXC_F_I2CS_INTEN_BYTE21_POS 21 /**< BYTE21 Position */
+#define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) /**< BYTE21 Mask */
+#define MXC_F_I2CS_INTEN_BYTE22_POS 22 /**< BYTE22 Position */
+#define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) /**< BYTE22 Mask */
+#define MXC_F_I2CS_INTEN_BYTE23_POS 23 /**< BYTE23 Position */
+#define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) /**< BYTE23 Mask */
+#define MXC_F_I2CS_INTEN_BYTE24_POS 24 /**< BYTE24 Position */
+#define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) /**< BYTE24 Mask */
+#define MXC_F_I2CS_INTEN_BYTE25_POS 25 /**< BYTE25 Position */
+#define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) /**< BYTE25 Mask */
+#define MXC_F_I2CS_INTEN_BYTE26_POS 26 /**< BYTE26 Position */
+#define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) /**< BYTE26 Mask */
+#define MXC_F_I2CS_INTEN_BYTE27_POS 27 /**< BYTE27 Position */
+#define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) /**< BYTE27 Mask */
+#define MXC_F_I2CS_INTEN_BYTE28_POS 28 /**< BYTE28 Position */
+#define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) /**< BYTE28 Mask */
+#define MXC_F_I2CS_INTEN_BYTE29_POS 29 /**< BYTE29 Position */
+#define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) /**< BYTE29 Mask */
+#define MXC_F_I2CS_INTEN_BYTE30_POS 30 /**< BYTE30 Position */
+#define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) /**< BYTE30 Mask */
+#define MXC_F_I2CS_INTEN_BYTE31_POS 31 /**< BYTE31 Position */
+#define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) /**< BYTE31 Mask */
+/**@} end group I2CS_INTEN */
+/**
+ * @ingroup i2cs_registers
+ * @defgroup I2CS_DATA_BYTE_Register I2CS_DATA_BYTE
+ * @brief Field Positions and Bit Masks for the I2CS_DATA_BYTE register
+ * @{
+ */
+#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 /**< DATA_FIELD Position */
+#define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) /**< DATA_FIELD */
+#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 /**< READ_ONLY_FL Position */
+#define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) /**< READ_ONLY_FL */
+#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 /**< DATA_UPDATED_FL Position */
+#define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) /**< DATA_UPDATED_FL */
+/**@} end group I2CS_DATA_BYTE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_I2CS_REGS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/icc_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,157 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the Instruction Cache Controller.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24662 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup icc
+ * @defgroup icc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the ICC.
+ * @{
+ */
+
+/**
+ * Structure type to access the ICC Registers.
+ */
+typedef struct {
+ __IO uint32_t id; /**< <tt>\b 0x0000: </tt> ICC_ID Register \warning INTERNAL USE ONLY, DO NOT MODIFY */
+ __IO uint32_t mem_cfg; /**< <tt>\b 0x0004: </tt> ICC_MEM_CFG Register */
+ __RO uint32_t rsv008[62]; /**< <tt>\b 0x0008-0x00FC: </tt> RESERVED */
+ __IO uint32_t ctrl_stat; /**< <tt>\b 0x0100: </tt> ICC_CTRL_STAT Register */
+ __RO uint32_t rsv104[383]; /**< <tt>\b 0x0104-0x06FC: </tt> RESERVED */
+ __IO uint32_t invdt_all; /**< <tt>\b 0x0700: </tt> ICC_INVDT_ALL Register */
+} mxc_icc_regs_t;
+/**@} end of group icc_registers*/
+
+
+
+
+
+/*
+ Register offsets for module ICC.
+*/
+/**
+ * @ingroup icc_registers
+ * @defgroup ICC_Register_Offsets Register Offsets
+ * @brief Instruction Cache Controller Register Offsets from the ICC Base Address.
+ * @{
+ */
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt>\b 0x0000</tt> */
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt>\b 0x0004</tt> */
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt>\b 0x0100</tt> */
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt>\b 0x0700</tt> */
+/**@} end of group icc_registers */
+
+/*
+ Field positions and masks for module ICC.
+*/
+/**
+ * @ingroup icc_registers
+ * @defgroup ICC_ID_Register ICC_ID
+ * @brief Field Positions and Bit Masks for the ICC_ID register
+ * @{
+ */
+#define MXC_F_ICC_ID_RTL_VERSION_POS 0 /**< RTL_VERSION Position */
+#define MXC_F_ICC_ID_RTL_VERSION ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS)) /**< RTL_VERSION Mask */
+#define MXC_F_ICC_ID_PART_NUM_POS 6 /**< PART_NUM Position */
+#define MXC_F_ICC_ID_PART_NUM ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS)) /**< PART_NUM Mask */
+#define MXC_F_ICC_ID_CACHE_ID_POS 10 /**< CACHE_ID Position */
+#define MXC_F_ICC_ID_CACHE_ID ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS)) /**< CACHE_ID Mask */
+/**@} end of group ICC_ID_register */
+/**
+ * @ingroup icc_registers
+ * @defgroup ICC_MEM_CFG_Register ICC_MEM_CFG
+ * @brief Field Positions and Bit Masks for the ICC_MEM_CFG register
+ * @{
+ */
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS 0 /**< CACHE_SIZE Position */
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS)) /**< CACHE_SIZE Mask */
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS 16 /**< MAIN_MEMORY_SIZE Position */
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS)) /**< MAIN_MEMORY_SIZE Mask */
+/**@} end of group ICC_MEM_CFG_register */
+/**
+ * @ingroup icc_registers
+ * @defgroup ICC_CTRL_STAT_Register ICC_CTRL_STAT
+ * @brief Field Positions and Bit Masks for the ICC_CTRL_STAT register
+ * @{
+ */
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS 0 /**< ENABLE Position */
+#define MXC_F_ICC_CTRL_STAT_ENABLE ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS)) /**< ENABLE Mask */
+#define MXC_F_ICC_CTRL_STAT_READY_POS 16 /**< READY Position */
+#define MXC_F_ICC_CTRL_STAT_READY ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS)) /**< READY Mask */
+/**@} end of group ICC_CTRL_STAT_register */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ICC_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1163 @@
+/**
+ * @file
+ * @brief IOMAN hardware register definitions.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-31 17:07:02 -0500 (Mon, 31 Oct 2016) $
+ * $Revision: 24857 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion. */
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+///@cond
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/* **** Definitions **** */
+/**
+ * Structure type for wakeup detection @b request for port 4, port 5, port 6 and port 7.
+ */
+typedef struct {
+ uint32_t wud_req_p4 : 8; /**< Port 4 wake-up detection @b request bit field. */
+ uint32_t wud_req_p5 : 8; /**< Port 5 wake-up detection @b request bit field. */
+ uint32_t wud_req_p6 : 8; /**< Port 6 wake-up detection @b request bit field. */
+ uint32_t wud_req_p7 : 8; /**< Port 7 wake-up detection @b request bit field. */
+} mxc_ioman_wud_req1_t;
+/**
+ * Structure type for wakeup detection @b acknowledgement for port 0, port 1, port 2 and port 3.
+ */
+typedef struct {
+ uint32_t wud_ack_p0 : 8; /**< Port 0 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p1 : 8; /**< Port 1 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p2 : 8; /**< Port 2 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p3 : 8; /**< Port 3 wake-up detection @b acknowledgement bit field. */
+} mxc_ioman_wud_ack0_t;
+
+/**
+ * @ingroup ioman
+ * @defgroup ioman_req_ack_bit_fields IOMAN Bit Field Structures
+ * @brief Bit Field Structes used to request and configure all I/O for all
+ * port pins and peripherals with external I/O.
+ * @{
+ */
+typedef struct {
+ uint32_t wud_req_p0 : 8; /**< Port 0 wake-up detection @b request bit field. */
+ uint32_t wud_req_p1 : 8; /**< Port 1 wake-up detection @b request bit field. */
+ uint32_t wud_req_p2 : 8; /**< Port 2 wake-up detection @b request bit field. */
+ uint32_t wud_req_p3 : 8; /**< Port 3 wake-up detection @b request bit field. */
+} mxc_ioman_wud_req0_t;
+/**
+ * Structure type for wakeup detection @b acknowledgement for port 4, port 5, port 6 and port 7.
+ */
+typedef struct {
+ uint32_t wud_ack_p4 : 8; /**< Port 4 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p5 : 8; /**< Port 5 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p6 : 8; /**< Port 6 wake-up detection @b acknowledgement bit field. */
+ uint32_t wud_ack_p7 : 8; /**< Port 7 wake-up detection @b acknowledgement bit field. */
+} mxc_ioman_wud_ack1_t;
+/**
+ * Structure type for analog input @b request for port 0, port 1, port 2 and port 3.
+ */
+typedef struct {
+ uint32_t ali_req_p0 : 8; /**< Port 0 analog input @b request bit field. */
+ uint32_t ali_req_p1 : 8; /**< Port 1 analog input @b request bit field. */
+ uint32_t ali_req_p2 : 8; /**< Port 2 analog input @b request bit field. */
+ uint32_t ali_req_p3 : 8; /**< Port 3 analog input @b request bit field. */
+} mxc_ioman_ali_req0_t;
+/**
+ * Structure type for analog input @b request for port 4, port 5, port 6 and port 7.
+ */
+typedef struct {
+ uint32_t ali_req_p4 : 8; /**< Port 4 analog input @b request bit field. */
+ uint32_t ali_req_p5 : 8; /**< Port 5 analog input @b request bit field. */
+ uint32_t ali_req_p6 : 8; /**< Port 6 analog input @b request bit field. */
+ uint32_t ali_req_p7 : 8; /**< Port 7 analog input @b request bit field. */
+} mxc_ioman_ali_req1_t;
+/**
+ * Structure type for analog input @b acknowledgement for port 0, port 1, port 2 and port 3.
+ */
+typedef struct {
+ uint32_t ali_ack_p0 : 8; /**< Port 0 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p1 : 8; /**< Port 1 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p2 : 8; /**< Port 2 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p3 : 8; /**< Port 3 analog input @b acknowledgement bit field. */
+} mxc_ioman_ali_ack0_t;
+/**
+ * Structure type for analog input @b acknowledgement for port 4, port 5, port 6 and port 7.
+ */
+typedef struct {
+ uint32_t ali_ack_p4 : 8; /**< Port 4 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p5 : 8; /**< Port 5 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p6 : 8; /**< Port 6 analog input @b acknowledgement bit field. */
+ uint32_t ali_ack_p7 : 8; /**< Port 7 analog input @b acknowledgement bit field. */
+} mxc_ioman_ali_ack1_t;
+/**
+ * Structure type for SPI XIP configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to request the SPIX core external pins. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
+ uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
+ uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
+ uint32_t : 1; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
+ uint32_t : 15; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spix_req_t;
+/**
+ * Structure type for SPI XIP configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Is set if the request for the SPIX core external pins succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
+ uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
+ uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
+ uint32_t : 1; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 15; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spix_ack_t;
+/**
+ * Structure type for UART0 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
+ uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
+ uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart0_req_t;
+/**
+ * Structure type for UART0 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart0_ack_t;
+/**
+ * Structure type for UART1 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
+ uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
+ uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart1_req_t;
+/**
+ * Structure type for UART1 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart1_ack_t;
+/**
+ * Structure type for UART2 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
+ uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
+ uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart2_req_t;
+/**
+ * Structure type for UART2 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart2_ack_t;
+/**
+ * Structure type for UART3 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
+ uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
+ uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart3_req_t;
+/**
+ * Structure type for UART3 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 25; /**< Reserved: Do No Modify. */
+} mxc_ioman_uart3_ack_t;
+/**
+ * Structure type for I2C Master 0 configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do No Modify. */
+ uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM0 pins. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm0_req_t;
+/**
+ * Structure type for I2C Master 0 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do No Modify. */
+ uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm0_ack_t;
+/**
+ * Structure type for I2C Master 1 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM1 CLK and Data pins. */
+ uint32_t : 2; /**< Reserved: Do No Modify. */
+ uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM1 pins. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm1_req_t;
+/**
+ * Structure type for I2C Master 1 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */
+ uint32_t : 2; /**< Reserved: Do No Modify. */
+ uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm1_ack_t;
+/**
+ * Structure type for I2C Master 2 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM2 CLK and Data pins. */
+ uint32_t : 2; /**< Reserved: Do No Modify. */
+ uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM2 pins. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm2_req_t;
+/**
+ * Structure type for I2C Master 2 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */
+ uint32_t : 2; /**< Reserved: Do No Modify. */
+ uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cm2_ack_t;
+/**
+ * Structure type for I2C Slave 0 configuration @b requests.
+ */
+typedef struct {
+ uint32_t io_sel : 3; /**< Value for the desired pin mapping for the I2CS0 CLK and Data pins. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CS0 pins. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cs_req_t;
+/**
+ * Structure type for I2C Slave 0 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t io_sel : 3; /**< Non-zero if mapping request successful. */
+ uint32_t : 1; /**< Reserved: Do No Modify. */
+ uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
+ uint32_t : 27; /**< Reserved: Do No Modify. */
+} mxc_ioman_i2cs_ack_t;
+/**
+ * Structure type for SPI Master 0 configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to request the SPIM0 core external pins. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
+ uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
+ uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
+ uint32_t ss3_io_req : 1; /**< Set to request slave select 3 active out. */
+ uint32_t ss4_io_req : 1; /**< Set to request slave select 4 active out. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to 1 to request Quad I/O for SPIM0. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation for SPIM0. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim0_req_t;
+/**
+ * Structure type for SPI Master 0 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM0 core external pins succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
+ uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
+ uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
+ uint32_t ss3_io_ack : 1; /**< Is set if the request for the slave select 3 active out succeeded. */
+ uint32_t ss4_io_ack : 1; /**< Is set if the request for the slave select 4 active out succeeded. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim0_ack_t;
+/**
+ * Structure type for SPI Master 1 configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to request the SPIM1 core external pins. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
+ uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
+ uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
+ uint32_t : 9; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim1_req_t;
+/**
+ * Structure type for SPI Master 1 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM1 core external pins succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
+ uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
+ uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
+ uint32_t : 9; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim1_ack_t;
+/**
+ * Structure type for SPI Master 2 configuration @b requests.
+ */
+typedef struct {
+ uint32_t mapping_req : 2; /**< Set to the desired port pin mapping for the SPIM2. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to request the SPIM2 core external pins. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
+ uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
+ uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
+ uint32_t : 5; /**< Reserved: Do Not Modify. */
+ uint32_t sr0_io_req : 1; /**< Set to 1 to request slave ready 0 input. */
+ uint32_t sr1_io_req : 1; /**< Set to 1 to request slave ready 1 input. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim2_req_t;
+/**
+ * Structure type for SPI Master 2 configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM2 core external pins succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
+ uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
+ uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
+ uint32_t : 5; /**< Reserved: Do Not Modify. */
+ uint32_t sr0_io_req : 1; /**< Is set if the request for the slave ready 0 active input succeeded. */
+ uint32_t sr1_io_req : 1; /**< Is set if the request for the slave ready 1 active input succeeded. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 7; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spim2_ack_t;
+/**
+ * Structure type for SPI Bridge configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to request the SPIB core external pins. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
+ uint32_t : 19; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spib_req_t;
+/**
+ * Structure type for SPI Bridge configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Non-zero if mapping request successful. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 19; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spib_ack_t;
+/**
+ * Structure type for 1-Wire Master (OWM) configuration @b requests.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t mapping_req : 1; /**< Set to the desired port pin mapping for the 1-Wire Master. */
+ uint32_t epu_io_req : 1; /**< Set to 1 to request External Pull-up for the 1-Wire Master. */
+ uint32_t : 26; /**< Reserved: Do Not Modify. */
+} mxc_ioman_owm_req_t;
+/**
+ * Structure type for 1-Wire Master configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t : 4; /**< Reserved: Do Not Modify. */
+ uint32_t mapping_ack : 1; /**< Non-zero if mapping request successful. */
+ uint32_t epu_io_ack : 1; /**< Non-zero if external pull-up request successful. */
+ uint32_t : 26; /**< Reserved: Do Not Modify. */
+} mxc_ioman_owm_ack_t;
+/**
+ * Structure type for SPI Slave configuration @b requests.
+ */
+typedef struct {
+ uint32_t mapping_req : 2; /**< Set to desired port pin mapping for the SPIS peripheral. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_req : 1; /**< Set to 1 to request the I/O be assigned to the SPIS. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
+ uint32_t : 19; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spis_req_t;
+/**
+ * Structure type for SPI Slave configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */
+ uint32_t : 2; /**< Reserved: Do Not Modify. */
+ uint32_t core_io_ack : 1; /**< Non-zero if core io request successful. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
+ uint32_t : 3; /**< Reserved: Do Not Modify. */
+ uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
+ uint32_t : 19; /**< Reserved: Do Not Modify. */
+} mxc_ioman_spis_ack_t;
+/**
+ * Structure type to configure the I/O pad mode options.
+ */
+typedef struct {
+ uint32_t slow_mode : 1; /**< Slow mode I/O operation */
+ uint32_t alt_rcvr_mode : 1; /**< Alternative receive mode. */
+ uint32_t : 30; /**< Reserved: Do not modify. */
+} mxc_ioman_pad_mode_t;
+/**
+ * Structure type for Wake-Up Detect (WUD) configuration @b requests.
+ */
+typedef struct {
+ uint32_t wud_req_p8 : 2; /**< Request bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */
+ uint32_t : 30; /**< Reserved: Do not modify. */
+} mxc_ioman_wud_req2_t;
+/**
+ * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t wud_ack_p8 : 2; /**< Acknowledgement bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */
+ uint32_t : 30; /**< Reserved: Do not modify. */
+} mxc_ioman_wud_ack2_t;
+/**
+ * Structure type for Analog Wake-Up Detect (WUD) configuration @b requests.
+ */
+typedef struct {
+ uint32_t ali_req_p8 : 2; /**< Request bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */
+ uint32_t : 30; /**< Reserved: Do not modify. */
+} mxc_ioman_ali_req2_t;
+/**
+ * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements.
+ */
+typedef struct {
+ uint32_t ali_ack_p8 : 2; /**< Acknowledgement bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */
+ uint32_t : 30; /**< Reserved: Do not modify. */
+} mxc_ioman_ali_ack2_t;
+/**@} end of group ioman_req_ack_bit_fields */
+/**
+ * @ingroup ioman
+ * @defgroup ioman_registers IOMAN Registers
+ * @{
+ * Structure type for the IOMAN Register Interface.
+ * The table below shows the IOMAN Regsiter Offsets from the Base IOMAN Peripheral Address #MXC_BASE_IOMAN.
+ */
+typedef struct {
+ __IO uint32_t wud_req0; /**< Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_req1; /**< Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t wud_ack0; /**< Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t wud_ack1; /**< Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_req0; /**< Analog Input Request Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_req1; /**< Analog Input Request Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_ack0; /**< Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */
+ __IO uint32_t ali_ack1; /**< Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */
+ __IO uint32_t ali_connect0; /**< Analog I/O Connection Control Register 0 */
+ __IO uint32_t ali_connect1; /**< Analog I/O Connection Control Register 1 */
+ __IO uint32_t spix_req; /**< SPIX I/O Mode Request */
+ __IO uint32_t spix_ack; /**< SPIX I/O Mode Acknowledge */
+ __IO uint32_t uart0_req; /**< UART0 I/O Mode Request */
+ __IO uint32_t uart0_ack; /**< UART0 I/O Mode Acknowledge */
+ __IO uint32_t uart1_req; /**< UART1 I/O Mode Request */
+ __IO uint32_t uart1_ack; /**< UART1 I/O Mode Acknowledge */
+ __IO uint32_t uart2_req; /**< UART2 I/O Mode Request */
+ __IO uint32_t uart2_ack; /**< UART2 I/O Mode Acknowledge */
+ __IO uint32_t uart3_req; /**< UART3 I/O Mode Request */
+ __IO uint32_t uart3_ack; /**< UART3 I/O Mode Acknowledge */
+ __IO uint32_t i2cm0_req; /**< I2C Master 0 I/O Request */
+ __IO uint32_t i2cm0_ack; /**< I2C Master 0 I/O Acknowledge */
+ __IO uint32_t i2cm1_req; /**< I2C Master 1 I/O Request */
+ __IO uint32_t i2cm1_ack; /**< I2C Master 1 I/O Acknowledge */
+ __IO uint32_t i2cm2_req; /**< I2C Master 2 I/O Request */
+ __IO uint32_t i2cm2_ack; /**< I2C Master 2 I/O Acknowledge */
+ __IO uint32_t i2cs_req; /**< I2C Slave I/O Request */
+ __IO uint32_t i2cs_ack; /**< I2C Slave I/O Acknowledge */
+ __IO uint32_t spim0_req; /**< SPI Master 0 I/O Mode Request */
+ __IO uint32_t spim0_ack; /**< SPI Master 0 I/O Mode Acknowledge */
+ __IO uint32_t spim1_req; /**< SPI Master 1 I/O Mode Request */
+ __IO uint32_t spim1_ack; /**< SPI Master 1 I/O Mode Acknowledge */
+ __IO uint32_t spim2_req; /**< SPI Master 2 I/O Mode Request */
+ __IO uint32_t spim2_ack; /**< SPI Master 2 I/O Mode Acknowledge */
+ __IO uint32_t spib_req; /**< SPI Bridge I/O Mode Request */
+ __IO uint32_t spib_ack; /**< SPI Bridge I/O Mode Acknowledge */
+ __IO uint32_t owm_req; /**< 1-Wire Master I/O Mode Request */
+ __IO uint32_t owm_ack; /**< 1-Wire Master I/O Mode Acknowledge */
+ __IO uint32_t spis_req; /**< SPI Slave I/O Mode Request */
+ __IO uint32_t spis_ack; /**< SPI Slave I/O Mode Acknowledge */
+ __RO uint32_t rsv0A0[24]; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t use_vddioh_0; /**< Enable VDDIOH Register 0 */
+ __IO uint32_t use_vddioh_1; /**< Enable VDDIOH Register 1 */
+ __IO uint32_t use_vddioh_2; /**< Enable VDDIOH Register 2 */
+ __RO uint32_t rsv10C; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t pad_mode; /**< Pad Mode Control Register */
+ __RO uint32_t rsv114[27]; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t wud_req2; /**< Wakeup Detect Mode Request Register 2 (Port 8) */
+ __RO uint32_t rsv184; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t wud_ack2; /**< Wakeup Detect Mode Acknowledge Register 2 (Port 8) */
+ __RO uint32_t rsv18C; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t ali_req2; /**< Analog Input Request Register 2 (Port 8) */
+ __RO uint32_t rsv194; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t ali_ack2; /**< Analog Input Acknowledge Register 2 (Port 8) */
+ __RO uint32_t rsv19C; /**< RESERVED: DO NOT MODIFY */
+ __IO uint32_t ali_connect2; /**< Analog I/O Connection Control Register 2 */
+} mxc_ioman_regs_t;
+/**@}*/
+
+/*
+ Register offsets for module IOMAN.
+*/
+/**
+ * @ingroup ioman_registers
+ * @defgroup ioman_reg_offs IOMAN Register Offsets
+ * @{
+ * @details The @ref IOMAN_REGS_OFFS_TABLE "IOMAN Register Offset Table"
+ * shows the register offsets for the IOMAN registers from the base
+ * IOMAN peripheral address, #MXC_BASE_IOMAN.
+ * @anchor IOMAN_REGS_OFFS_TABLE
+ * | Register | Offset |
+ * | :----------- | ------:|
+ * | WUD_REQ0 | 0x0000 |
+ * | WUD_REQ1 | 0x0004 |
+ * | WUD_ACK0 | 0x0008 |
+ * | WUD_ACK1 | 0x000C |
+ * | ALI_REQ0 | 0x0010 |
+ * | ALI_REQ1 | 0x0014 |
+ * | ALI_ACK0 | 0x0018 |
+ * | ALI_ACK1 | 0x001C |
+ * | ALI_CONNECT0 | 0x0020 |
+ * | ALI_CONNECT1 | 0x0024 |
+ * | SPIX_REQ | 0x0028 |
+ * | SPIX_ACK | 0x002C |
+ * | UART0_REQ | 0x0030 |
+ * | UART0_ACK | 0x0034 |
+ * | UART1_REQ | 0x0038 |
+ * | UART1_ACK | 0x003C |
+ * | UART2_REQ | 0x0040 |
+ * | UART2_ACK | 0x0044 |
+ * | UART3_REQ | 0x0048 |
+ * | UART3_ACK | 0x004C |
+ * | I2CM0_REQ | 0x0050 |
+ * | I2CM0_ACK | 0x0054 |
+ * | I2CM1_REQ | 0x0058 |
+ * | I2CM1_ACK | 0x005C |
+ * | I2CM2_REQ | 0x0060 |
+ * | I2CM2_ACK | 0x0064 |
+ * | I2CS_REQ | 0x0068 |
+ * | I2CS_ACK | 0x006C |
+ * | SPIM0_REQ | 0x0070 |
+ * | SPIM0_ACK | 0x0074 |
+ * | SPIM1_REQ | 0x0078 |
+ * | SPIM1_ACK | 0x007C |
+ * | SPIM2_REQ | 0x0080 |
+ * | SPIM2_ACK | 0x0084 |
+ * | SPIB_REQ | 0x0088 |
+ * | SPIB_ACK | 0x008C |
+ * | OWM_REQ | 0x0090 |
+ * | OWM_ACK | 0x0094 |
+ * | SPIS_REQ | 0x0098 |
+ * | SPIS_ACK | 0x009C |
+ * | USE_VDDIOH_0 | 0x0100 |
+ * | USE_VDDIOH_1 | 0x0104 |
+ * | USE_VDDIOH_2 | 0x0108 |
+ * | PAD_MODE | 0x0110 |
+ * | WUD_REQ2 | 0x0180 |
+ * | WUD_ACK2 | 0x0188 |
+ * | ALI_REQ2 | 0x0190 |
+ * | ALI_ACK2 | 0x0198 |
+ * | ALI_CONNECT2 | 0x01A0 |
+ */
+#define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) /**< WUD_REQ0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) /**< WUD_REQ1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) /**< WUD_ACK0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) /**< WUD_ACK1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) /**< ALI_REQ0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) /**< ALI_REQ1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) /**< ALI_ACK0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) /**< ALI_ACK1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) /**< ALI_CONNECT0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) /**< ALI_CONNECT1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) /**< SPIX_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) /**< SPIX_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) /**< UART0_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) /**< UART0_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) /**< UART1_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) /**< UART1_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) /**< UART2_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) /**< UART2_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) /**< UART3_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) /**< UART3_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) /**< I2CM0_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) /**< I2CM0_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) /**< I2CM1_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) /**< I2CM1_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) /**< I2CM2_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) /**< I2CM2_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) /**< I2CS_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) /**< I2CS_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) /**< SPIM0_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) /**< SPIM0_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) /**< SPIM1_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) /**< SPIM1_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) /**< SPIM2_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) /**< SPIM2_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) /**< SPIB_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) /**< SPIB_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) /**< OWM_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) /**< OWM_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) /**< SPIS_REQ Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) /**< SPIS_ACK Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) /**< USE_VDDIOH_0 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) /**< USE_VDDIOH_1 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) /**< USE_VDDIOH_2 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) /**< PAD_MODE Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) /**< WUD_REQ2 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) /**< WUD_ACK2 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) /**< ALI_REQ2 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) /**< ALI_ACK2 Register Offset from base IOMAN Peripheral Address. */
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) /**< ALI_CONNECT2 Register Offset from base IOMAN Peripheral Address. */
+/**@}*/
+
+/*
+ Field positions and masks for module IOMAN.
+*/
+/**
+ * @ingroup ioman_registers
+ * @defgroup Bit and Field Positions Masks for the IOMAN Registers.
+ * @{
+ */
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24
+#define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24
+#define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24
+#define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24
+#define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24
+#define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24
+#define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24
+#define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24
+#define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS))
+
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16
+#define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4
+#define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS))
+#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5
+#define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS))
+#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6
+#define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS))
+
+#define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0
+#define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1
+#define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2
+#define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS))
+#define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4
+#define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS))
+#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5
+#define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS))
+#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6
+#define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS))
+
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0
+#define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS))
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS))
+
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11
+#define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12
+#define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11
+#define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12
+#define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0
+#define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9
+#define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10
+#define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20
+#define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0
+#define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9
+#define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10
+#define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16
+#define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17
+#define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20
+#define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24
+#define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4
+#define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5
+#define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS))
+
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4
+#define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5
+#define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS))
+
+#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0
+#define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4
+#define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8
+#define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS))
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0
+#define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4
+#define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8
+#define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS))
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12
+#define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0
+#define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS))
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1
+#define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS))
+
+#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0
+#define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS))
+
+#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0
+#define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS))
+
+#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0
+#define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS))
+
+#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0
+#define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS))
+
+/*
+ Generic field positions and masks
+*/
+#define MXC_F_IOMAN_UART_REQ_IO_REQ MXC_F_IOMAN_UART0_REQ_IO_REQ
+#define MXC_F_IOMAN_UART_ACK_IO_ACK MXC_F_IOMAN_UART0_ACK_IO_ACK
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_IOMAN_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/maa_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,212 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24665 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_MAA_REGS_H_
+#define _MXC_MAA_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+
+
+/**
+ * @ingroup icc_registers
+ * @defgroup maa_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the MAA Peripheral Module.
+x * @{
+ */
+
+/**
+ * Structure type to access the MAA Peripheral Module Registers.
+ */
+ typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> MAA_CTRL - MAA Control, Configuration and Status */
+ __IO uint32_t maws; /**< <tt>\b 0x0004</tt> MAA_MAWS - MAA Word (Operand) Size, Big/Little Endian Mode Select */
+} mxc_maa_regs_t;
+/**@} end of maa_registers group */
+
+
+/**
+ * @ingroup maa
+ * @defgroup maa_mem_segments Memory Segment Registers
+ * @brief Registers, Bit Masks and Bit Positions for the MAA Memory Mapped Segments
+ * @{
+ */
+/**
+ * Structure type to access the MAA Peripheral Module Memory Mapped Registers.
+ */
+typedef struct {
+ __IO uint32_t seg0[32]; /* 0x0000-0x007C [128 bytes] MAA Memory Segment 0 */
+ __IO uint32_t seg1[32]; /* 0x0080-0x00FC [128 bytes] MAA Memory Segment 1 */
+ __IO uint32_t seg2[32]; /* 0x0100-0x017C [128 bytes] MAA Memory Segment 2 */
+ __IO uint32_t seg3[32]; /* 0x0180-0x01FC [128 bytes] MAA Memory Segment 3 */
+ __IO uint32_t seg4[32]; /* 0x0200-0x027C [128 bytes] MAA Memory Segment 4 */
+ __IO uint32_t seg5[32]; /* 0x0280-0x02FC [128 bytes] MAA Memory Segment 5 */
+} mxc_maa_mem_regs_t;
+/**@} end of maa_mem_segments group */
+
+/**
+ * @ingroup maa_registers
+ * @defgroup MAA_Register_Offsets Register Offsets
+ * @brief MAA Register Offsets from the MAA Peripheral Module Base Address.
+ * @{
+ */
+#define MXC_R_MAA_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0000</tt> */
+#define MXC_R_MAA_OFFS_MAWS ((uint32_t)0x00000004UL) /**< Offset from MAA Base Peripheral Address: <tt>\b 0x0004</tt> */
+/**@} end of group MAA_Register_Offsets */
+/**
+ * @ingroup maa_mem_segments
+ * @defgroup MAA_Register_Mem_Offsets Register Offsets
+ * @brief MAA Memory Mapped Register Offsets from the MAA Peripheral Module Base Memory Mapped Address.
+ * @{
+ */
+#define MXC_R_MAA_MEM_OFFS_SEG0 ((uint32_t)0x00000000UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0000</tt> */
+#define MXC_R_MAA_MEM_OFFS_SEG1 ((uint32_t)0x00000080UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0080</tt> */
+#define MXC_R_MAA_MEM_OFFS_SEG2 ((uint32_t)0x00000100UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0100</tt> */
+#define MXC_R_MAA_MEM_OFFS_SEG3 ((uint32_t)0x00000180UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0180</tt> */
+#define MXC_R_MAA_MEM_OFFS_SEG4 ((uint32_t)0x00000200UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0200</tt> */
+#define MXC_R_MAA_MEM_OFFS_SEG5 ((uint32_t)0x00000280UL) /**< Offset from MAA Base Peripheral Memory Address: <tt>\b 0x0280</tt> */
+/**@} end of group MAA_Register_Mem_Offsets */
+
+/*
+ Field positions and masks for module MAA.
+*/
+/**
+ * @ingroup maa_registers
+ * @defgroup maa_ctrl MAA_CTRL
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_MAA_CTRL_START_POS 0 /**< START Position */
+#define MXC_F_MAA_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS)) /**< START Mask */
+#define MXC_F_MAA_CTRL_OPSEL_POS 1 /**< OPSEL Position */
+#define MXC_F_MAA_CTRL_OPSEL ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< OPSEL Mask */
+#define MXC_F_MAA_CTRL_OCALC_POS 4 /**< OCALC Position */
+#define MXC_F_MAA_CTRL_OCALC ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS)) /**< OCALC Mask */
+#define MXC_F_MAA_CTRL_IF_DONE_POS 5 /**< IF_DONE Position */
+#define MXC_F_MAA_CTRL_IF_DONE ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS)) /**< IF_DONE Mask */
+#define MXC_F_MAA_CTRL_INTEN_POS 6 /**< INTEN Position */
+#define MXC_F_MAA_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS)) /**< INTEN Mask */
+#define MXC_F_MAA_CTRL_IF_ERROR_POS 7 /**< IF_ERROR Position */
+#define MXC_F_MAA_CTRL_IF_ERROR ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS)) /**< IF_ERROR Mask */
+#define MXC_F_MAA_CTRL_OFS_A_POS 8 /**< OFS_A Position */
+#define MXC_F_MAA_CTRL_OFS_A ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS)) /**< OFS_A Mask */
+#define MXC_F_MAA_CTRL_OFS_B_POS 10 /**< OFS_B Position */
+#define MXC_F_MAA_CTRL_OFS_B ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS)) /**< OFS_B Mask */
+#define MXC_F_MAA_CTRL_OFS_EXP_POS 12 /**< OFS_EXP Position */
+#define MXC_F_MAA_CTRL_OFS_EXP ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS)) /**< OFS_EXP Mask */
+#define MXC_F_MAA_CTRL_OFS_MOD_POS 14 /**< OFS_MOD Position */
+#define MXC_F_MAA_CTRL_OFS_MOD ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS)) /**< OFS_MOD Mask */
+#define MXC_F_MAA_CTRL_SEG_A_POS 16 /**< SEG_A Position */
+#define MXC_F_MAA_CTRL_SEG_A ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS)) /**< SEG_A Mask */
+#define MXC_F_MAA_CTRL_SEG_B_POS 20 /**< SEG_B Position */
+#define MXC_F_MAA_CTRL_SEG_B ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS)) /**< SEG_B Mask */
+#define MXC_F_MAA_CTRL_SEG_RES_POS 24 /**< SEG_RES Position */
+#define MXC_F_MAA_CTRL_SEG_RES ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS)) /**< SEG_RES Mask */
+#define MXC_F_MAA_CTRL_SEG_TMP_POS 28 /**< SEG_TMP Position */
+#define MXC_F_MAA_CTRL_SEG_TMP ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS)) /**< SEG_TMP Mask */
+/**@} end of maa_ctrl group */
+
+/**
+ * @ingroup maa_registers
+ * @defgroup maa_maws MAA_MAWS
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_MAA_MAWS_MODLEN_POS 0 /**< MODLEN Position */
+#define MXC_F_MAA_MAWS_MODLEN ((uint32_t)(0x000007FFUL << MXC_F_MAA_MAWS_MODLEN_POS)) /**< MODLEN Mask */
+#define MXC_F_MAA_MAWS_BYTESWAP_POS 15 /**< BYTESWAP Position */
+#define MXC_F_MAA_MAWS_BYTESWAP ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS)) /**< BYTESWAP Mask */
+/**@} end of group MAA_MAWS */
+
+
+/*
+ Field values and shifted values for module MAA.
+*/
+/**
+ * @ingroup maa_ctrl
+ * @defgroup maa_oppsel MAA_OPSEL
+ * @brief MAA Operation Select - Field Values and Shifted Field Values.
+ */
+#define MXC_V_MAA_OPSEL_EXP ((uint32_t)(0x00000000UL)) /**< Field Value: OPSEL_EXP */
+#define MXC_V_MAA_OPSEL_SQR ((uint32_t)(0x00000001UL)) /**< Field Value: OPSEL_SQR */
+#define MXC_V_MAA_OPSEL_MUL ((uint32_t)(0x00000002UL)) /**< Field Value: OPSEL_MUL */
+#define MXC_V_MAA_OPSEL_SQRMUL ((uint32_t)(0x00000003UL)) /**< Field Value: OPSEL_SQRMUL */
+#define MXC_V_MAA_OPSEL_ADD ((uint32_t)(0x00000004UL)) /**< Field Value: OPSEL_ADD */
+#define MXC_V_MAA_OPSEL_SUB ((uint32_t)(0x00000005UL)) /**< Field Value: OPSEL_SUB */
+
+#define MXC_S_MAA_OPSEL_EXP ((uint32_t)(MXC_V_MAA_OPSEL_EXP << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_EXP */
+#define MXC_S_MAA_OPSEL_SQR ((uint32_t)(MXC_V_MAA_OPSEL_SQR << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQR */
+#define MXC_S_MAA_OPSEL_MUL ((uint32_t)(MXC_V_MAA_OPSEL_MUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_MUL */
+#define MXC_S_MAA_OPSEL_SQRMUL ((uint32_t)(MXC_V_MAA_OPSEL_SQRMUL << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SQRMUL */
+#define MXC_S_MAA_OPSEL_ADD ((uint32_t)(MXC_V_MAA_OPSEL_ADD << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_ADD */
+#define MXC_S_MAA_OPSEL_SUB ((uint32_t)(MXC_V_MAA_OPSEL_SUB << MXC_F_MAA_CTRL_OPSEL_POS)) /**< Shifted Field Value: OPSEL_SUB */
+/**@} end of group maa_opsel_values */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_MAA_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/max3263x.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,998 @@
+/**
+ * @file
+ * @brief MAX3263X device specific definitions for the core, peripherals,
+ * features, memory, and IRQs.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2016-10-31 17:08:23 -0500 (Mon, 31 Oct 2016) $
+ * $Revision: 24858 $
+ *
+*************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/* Define to prevent redundant inclusion */
+#ifndef _MAX3263X_H_
+#define _MAX3263X_H_
+
+
+/**
+ * @ingroup cmsis_product
+ * @defgroup product_name MAX3263X
+ * @brief MAX3263X device specific definitions for the core, peripherals,
+ * features, memory, and IRQs.
+ * @details The <b><em>MAX32630/MAX32631</em></b> is an ARM®
+ * Cortex®-M4F 32-bit microcontroller with a floating point
+ * unit, ideal for the emerging category of wearable medical and
+ * fitness applications. The architecture combines ultra-low power
+ * high-efficiency signal processing functionality with
+ * significantly reduced power consumption and ease of use. The
+ * device features four powerful and flexible power modes. A
+ * peripheral management unit (PMU) enables intelligent peripheral
+ * control with up to six channels to significantly reduce power
+ * consumption. Built-in dynamic clock gating and
+ * firmware-controlled power gating allows the user to optimize
+ * power for the specific application. Multiple SPI, UART and
+ * I²C serial interfaces, as well as 1-Wire® master and
+ * USB, allow for interconnection to a wide variety of external
+ * sensors. A four-input, 10-bit ADC with selectable references is
+ * available to monitor analog input from external sensors and
+ * meters. The small 100-ball WLP package provides a tiny, 4.37mm x
+ * 4.37mm footprint. The <b><em>MAX32630/MAX32631</em></b> include
+ * a hardware AES engine. The <b>@em MAX32631</b> is a secure
+ * version of the <b>@em MAX32630</b>. It incorporates a trust
+ * protection unit (TPU) with encryption and advanced security
+ * features. These features include a modular arithmetic
+ * accelerator (MAA) for fast ECDSA, a hardware PRNG entropy
+ * generator, and a secure boot loader.
+ * @{
+ */
+#ifndef FALSE
+/**
+ * @internal False
+ */
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+/**
+ * @internal True
+ */
+#define TRUE (1)
+#endif
+
+/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
+#if defined ( __GNUC__ )
+#define __weak __attribute__((weak)) /**< GNUC weak function keyword. */
+#elif defined ( __CC_ARM)
+#define inline __inline /**< inline keyword for Keil compiler. */
+#pragma anon_unions
+#endif
+/**@}*/
+/**
+ * @ingroup product_name
+ * @defgroup nvic_table Nested Interrupt Vector Table (NVIC)
+ * Device specific interrupt request NVIC entries.
+ * @{
+ */
+/**
+ * \MXIM_Device Nested Interrupt Vector Table (NVIC).
+ * @details
+ * NVIC Peripheral Entry numbers and Offsets are shown in the table below.
+ *
+ * | Entry | Offset | Peripheral |
+ * |-------: | ------: | :------------------------------------ |
+ * | 0x10 | 0x0040 | CLKMAN |
+ * | 0x11 | 0x0044 | PWRMAN |
+ * | 0x12 | 0x0048 | Flash Controller |
+ * | 0x13 | 0x004C | RTC Counter match with Compare 0 |
+ * | 0x14 | 0x0050 | RTC Counter match with Compare 1 |
+ * | 0x15 | 0x0054 | RTC Prescaler interval compare match |
+ * | 0x16 | 0x0058 | RTC Overflow |
+ * | 0x17 | 0x005C | Peripheral Management Unit (PMU/DMA) |
+ * | 0x18 | 0x0060 | USB |
+ * | 0x19 | 0x0064 | AES |
+ * | 0x1A | 0x0068 | MAA |
+ * | 0x1B | 0x006C | Watchdog 0 timeout |
+ * | 0x1C | 0x0070 | Watchdog 0 pre-window (fed too early)|
+ * | 0x1D | 0x0074 | Watchdog 1 timeout |
+ * | 0x1E | 0x0078 | Watchdog 1 pre-window (fed too early)|
+ * | 0x1F | 0x007C | GPIO Port 0 |
+ * | 0x20 | 0x0080 | GPIO Port 1 |
+ * | 0x21 | 0x0084 | GPIO Port 2 |
+ * | 0x22 | 0x0088 | GPIO Port 3 |
+ * | 0x23 | 0x008C | GPIO Port 4 |
+ * | 0x24 | 0x0090 | GPIO Port 5 |
+ * | 0x25 | 0x0094 | GPIO Port 6 |
+ * | 0x26 | 0x0098 | Timer 0 (32-bit, 16-bit #0) |
+ * | 0x27 | 0x009C | Timer 0 (16-bit #1) |
+ * | 0x28 | 0x00A0 | Timer 1 (32-bit, 16-bit #0) |
+ * | 0x29 | 0x00A4 | Timer 1 (16-bit #1) |
+ * | 0x2A | 0x00A8 | Timer 2 (32-bit, 16-bit #0) |
+ * | 0x2B | 0x00AC | Timer 2 (16-bit #1) |
+ * | 0x2C | 0x00B0 | Timer 3 (32-bit, 16-bit #0) |
+ * | 0x2D | 0x00B4 | Timer 3 (16-bit #1) |
+ * | 0x2E | 0x00B8 | Timer 4 (32-bit, 16-bit #0) |
+ * | 0x2F | 0x00BC | Timer 4 (16-bit #1) |
+ * | 0x30 | 0x00C0 | Timer 5 (32-bit, 16-bit #0) |
+ * | 0x31 | 0x00C4 | Timer 5 (16-bit #1) |
+ * | 0x32 | 0x00C8 | UART 0 |
+ * | 0x33 | 0x00CC | UART 1 |
+ * | 0x34 | 0x00D0 | UART 2 |
+ * | 0x35 | 0x00D4 | UART 3 |
+ * | 0x36 | 0x00D8 | Pulse Trains |
+ * | 0x37 | 0x00DC | I2C Master 0 |
+ * | 0x38 | 0x00E0 | I2C Master 1 |
+ * | 0x39 | 0x00E4 | I2C Master 2 |
+ * | 0x3A | 0x00E8 | I2C Slave |
+ * | 0x3B | 0x00EC | SPI Master 0 |
+ * | 0x3C | 0x00F0 | SPI Master 1 |
+ * | 0x3D | 0x00F4 | SPI Master 2 |
+ * | 0x3E | 0x00F8 | SPI Bridge |
+ * | 0x3F | 0x00FC | 1-Wire Master |
+ * | 0x40 | 0x0100 | ADC |
+ * | 0x41 | 0x0104 | SPI Slave |
+ * | 0x42 | 0x0108 | GPIO Port 7 |
+ * | 0x43 | 0x010C | GPIO Port 8 |
+ */
+
+/**
+ * Enumeration type of all \MXIM_Device NVIC entries.
+ */
+typedef enum {
+ NonMaskableInt_IRQn = -14, /**< ARM Core : Non-maskable IRQ */
+ HardFault_IRQn = -13, /**< ARM Core : Hard Fault IRQ */
+ MemoryManagement_IRQn = -12, /**< ARM Core : Memory Management IRQ */
+ BusFault_IRQn = -11, /**< ARM Core : Bus Fault IRQ */
+ UsageFault_IRQn = -10, /**< ARM Core : Usage Fault IRQ */
+ SVCall_IRQn = -5, /**< ARM Core : SVCall IRQ */
+ DebugMonitor_IRQn = -4, /**< ARM Core : Debug Monitor IRQ */
+ PendSV_IRQn = -2, /**< ARM Core : PendSV IRQ */
+ SysTick_IRQn = -1, /**< ARM Core : SysTick IRQ */
+ CLKMAN_IRQn = 0, /**< CLKMAN */
+ PWRMAN_IRQn, /**< PWRMAN */
+ FLC_IRQn, /**< Flash Controller */
+ RTC0_IRQn, /**< RTC Counter match with Compare 0 */
+ RTC1_IRQn, /**< RTC Counter match with Compare 1 */
+ RTC2_IRQn, /**< RTC Prescaler interval compare match */
+ RTC3_IRQn, /**< RTC Overflow */
+ PMU_IRQn, /**< Peripheral Management Unit (PMU/DMA) */
+ USB_IRQn, /**< USB */
+ AES_IRQn, /**< AES */
+ MAA_IRQn, /**< MAA */
+ WDT0_IRQn, /**< Watchdog 0 timeout */
+ WDT0_P_IRQn, /**< Watchdog 0 pre-window (fed too early) */
+ WDT1_IRQn, /**< Watchdog 1 timeout */
+ WDT1_P_IRQn, /**< Watchdog 1 pre-window (fed too early) */
+ GPIO_P0_IRQn, /**< GPIO Port 0 */
+ GPIO_P1_IRQn, /**< GPIO Port 1 */
+ GPIO_P2_IRQn, /**< GPIO Port 2 */
+ GPIO_P3_IRQn, /**< GPIO Port 3 */
+ GPIO_P4_IRQn, /**< GPIO Port 4 */
+ GPIO_P5_IRQn, /**< GPIO Port 5 */
+ GPIO_P6_IRQn, /**< GPIO Port 6 */
+ TMR0_0_IRQn, /**< Timer 0 (32-bit, 16-bit #0) */
+ TMR0_1_IRQn, /**< Timer 0 (16-bit #1) */
+ TMR1_0_IRQn, /**< Timer 1 (32-bit, 16-bit #0) */
+ TMR1_1_IRQn, /**< Timer 1 (16-bit #1) */
+ TMR2_0_IRQn, /**< Timer 2 (32-bit, 16-bit #0) */
+ TMR2_1_IRQn, /**< Timer 2 (16-bit #1) */
+ TMR3_0_IRQn, /**< Timer 3 (32-bit, 16-bit #0) */
+ TMR3_1_IRQn, /**< Timer 3 (16-bit #1) */
+ TMR4_0_IRQn, /**< Timer 4 (32-bit, 16-bit #0) */
+ TMR4_1_IRQn, /**< Timer 4 (16-bit #1) */
+ TMR5_0_IRQn, /**< Timer 5 (32-bit, 16-bit #0) */
+ TMR5_1_IRQn, /**< Timer 5 (16-bit #1) */
+ UART0_IRQn, /**< UART 0 */
+ UART1_IRQn, /**< UART 1 */
+ UART2_IRQn, /**< UART 2 */
+ UART3_IRQn, /**< UART 3 */
+ PT_IRQn, /**< Pulse Trains */
+ I2CM0_IRQn, /**< I2C Master 0 */
+ I2CM1_IRQn, /**< I2C Master 1 */
+ I2CM2_IRQn, /**< I2C Master 2 */
+ I2CS_IRQn, /**< I2C Slave */
+ SPIM0_IRQn, /**< SPI Master 0 */
+ SPIM1_IRQn, /**< SPI Master 1 */
+ SPIM2_IRQn, /**< SPI Master 2 */
+ SPIB_IRQn, /**< SPI Bridge */
+ OWM_IRQn, /**< 1-Wire Master */
+ AFE_IRQn, /**< ADC */
+ SPIS_IRQn, /**< SPI Slave */
+ GPIO_P7_IRQn, /**< GPIO Port 7 */
+ GPIO_P8_IRQn, /**< GPIO Port 8 */
+ MXC_IRQ_EXT_COUNT /**< Total number of non-core IRQ vectors. */
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) /**< Total number of device IRQs inclusive of core and non-core IRQ vectors. */
+/**@}end of group nvic_table*/
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+/**
+ * @ingroup product_name
+ * @defgroup Cortex_M4 Cortex-M Configuration
+ * @{
+ */
+/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
+#define __CM4_REV 0x0100 /**< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /**< MPU is present */
+#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for IRQ Priority Levels */
+#define __Vendor_SysTickConfig 0 /**< Using standard CMSIS SysTickConfig */
+#define __FPU_PRESENT 1 /**< FPU is Present */
+/**@} end of ingroup Cortex_M4*/
+#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
+#include "system_max3263x.h" /*!< System Header */
+
+
+/* ================================================================================ */
+/* ================== Device Specific Memory Section ================== */
+/* ================================================================================ */
+/**
+ * @ingroup product_name
+ * @{
+ */
+#define MXC_FLASH_MEM_BASE 0x00000000UL /**< Internal Flash Memory Start Address. */
+#define MXC_FLASH_PAGE_SIZE 0x00002000UL /**< Internal Flash Memory Page Size. */
+#define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL /**< Internal Flash Memory Size. */
+#define MXC_SYS_MEM_BASE 0x20000000UL /**< System Memory Start Address. */
+#define MXC_SRAM_FULL_MEM_SIZE 0x00080000UL /**< Internal SRAM Size. */
+#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL /**< External Flash Memory Start Address, SPIX interface. */
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+
+/*
+ Base addresses and configuration settings for all MAX3263X peripheral modules.
+*/
+
+
+/* *************************************************************************** */
+/* System Manager Settings */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
+#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
+
+
+
+/* *************************************************************************** */
+/* System Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+
+/* *************************************************************************** */
+/* System Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+
+
+/* *************************************************************************** */
+/* Real Time Clock */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+
+#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \
+ i == 1 ? RTC1_IRQn : \
+ i == 2 ? RTC2_IRQn : \
+ i == 3 ? RTC3_IRQn : 0)
+
+
+
+/* *************************************************************************** */
+/* Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+
+
+/* *************************************************************************** */
+/* System I/O Manager */
+/**@} end of ingroup product_name*/
+/**
+ * @ingroup ioman_registers
+ * @{
+ */
+#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) /**< Base Peripheral Address for IOMAN */
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) /**< Pointer to the #mxc_ioman_regs_t structure representing the IOMAN Registers. */
+/**@}*/
+
+/**
+ * @ingroup product_name
+ * @{
+ */
+/* *************************************************************************** */
+/* Shadow Trim Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
+#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
+
+
+
+/* *************************************************************************** */
+/* Flash Controller */
+
+#define MXC_BASE_FLC ((uint32_t)0x40002000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+
+#define MXC_FLC_PAGE_SIZE_SHIFT (13)
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+
+
+/* *************************************************************************** */
+/* Instruction Cache */
+
+#define MXC_BASE_ICC ((uint32_t)0x40003000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+
+/**@} end of ingroup product_name*/
+/* *************************************************************************** */
+/* SPI XIP Interface */
+/**
+ * @ingroup spix_registers
+ * @{
+ */
+#define MXC_BASE_SPIX ((uint32_t)0x40004000UL) /**< SPIX Base Peripheral Address. */
+#define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX) /**< SPIX pointer to the #mxc_spix_regs_t register structure type. */
+/**@} end of ingroup spix_registers*/
+
+/**
+ * @ingroup product_name
+ * @{
+ */
+/* *************************************************************************** */
+/* Peripheral Management Unit */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
+ (i) == 1 ? MXC_BASE_PMU1 : \
+ (i) == 2 ? MXC_BASE_PMU2 : \
+ (i) == 3 ? MXC_BASE_PMU3 : \
+ (i) == 4 ? MXC_BASE_PMU4 : \
+ (i) == 5 ? MXC_BASE_PMU5 : 0)
+
+#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
+ (i) == 1 ? MXC_PMU1 : \
+ (i) == 2 ? MXC_PMU2 : \
+ (i) == 3 ? MXC_PMU3 : \
+ (i) == 4 ? MXC_PMU4 : \
+ (i) == 5 ? MXC_PMU5 : 0)
+
+#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
+ (p) == MXC_PMU1 ? 1 : \
+ (p) == MXC_PMU2 ? 2 : \
+ (p) == MXC_PMU3 ? 3 : \
+ (p) == MXC_PMU4 ? 4 : \
+ (p) == MXC_PMU5 ? 5 : -1)
+
+/* *************************************************************************** */
+/* USB Device Controller */
+
+#define MXC_BASE_USB ((uint32_t)0x40100000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+
+/* *************************************************************************** */
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40006000UL)
+#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
+#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/* *************************************************************************** */
+/* Pseudo-random number generator (PRNG) */
+
+#define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
+#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
+
+/* *************************************************************************** */
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40007400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+/* *************************************************************************** */
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40007800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/* *************************************************************************** */
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40007000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+/**@} end of ingroup product_name*/
+/* *************************************************************************** */
+/* Watchdog Timers */
+/**
+ * @ingroup wdt_registers
+ * @{
+ */
+#define MXC_CFG_WDT_INSTANCES (2) /**< Define for the number of timers on the \MXIM_Device */
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) /**< Base Peripheral Address for WDT 0 */
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT0 Registers. */
+#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) /**< Base Peripheral Address for WDT 1 */
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) /**< Pointer to the #mxc_wdt_regs_t structure representing WDT1 Registers. */
+/**
+ * Macro that returns the WDT[i] IRQ, where i=0 to i < #MXC_CFG_WDT_INSTANCES.
+ */
+#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+/**
+ * Macro to return the base address for a requested Watchdog Timer index number.
+ * @p i WDT instance number.
+ * @p returns the base peripheral address for the requested Watchdog Timer instance.
+ */
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+/**
+ * Macro to return a pointer to the #mxc_tmr_regs_t object for the requested Watchdog Timer.
+ * @p i Watchdog Timer instance number.
+ * @p returns a pointer to a #mxc_wdt_regs_t for the requested WDT number.
+ */
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+/**
+ * Macro to return the index number for a given #mxc_wdt_regs_t structure.
+ * @p p pointer to a #mxc_wdt_regs_t structure.
+ * @p returns a watchdog timer instance number.
+ */
+#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
+ (i) == MXC_WDT1 ? 1: -1)
+
+/**@} end of ingroup wdt_registers */
+/* *************************************************************************** */
+/* Always-On Watchdog Timer */
+/**
+ * @ingroup wdt2_registers
+ * @{
+ */
+#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) /**< Base Peripheral Address for WDT 2 */
+#define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2) /**< Pointer to the #mxc_wdt2_regs_t structure representing the WDT2 hardware registers. */
+/**@} end of ingroup wdt2_registers */
+
+
+/* *************************************************************************** */
+/* General Purpose I/O Ports (GPIO) */
+/**
+ * @ingroup gpio_registers
+ * @{
+ */
+#define MXC_GPIO_NUM_PORTS (9) /**< Number of GPIO Ports for the \MXIM_Device. */
+#define MXC_GPIO_MAX_PINS_PER_PORT (8) /**< Number of port pins per port for the \MXIM_Device */
+
+#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) /**< GPIO Base Peripheral Offset */
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) /**< Pointer to the #mxc_gpio_regs_t object representing GPIO Registers. */
+/**
+ * Macro that returns the GPIO[i] IRQ, where i=0 to i < #MXC_GPIO_NUM_PORTS.
+ */
+#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
+ (i) == 1 ? GPIO_P1_IRQn : \
+ (i) == 2 ? GPIO_P2_IRQn : \
+ (i) == 3 ? GPIO_P3_IRQn : \
+ (i) == 4 ? GPIO_P4_IRQn : \
+ (i) == 5 ? GPIO_P5_IRQn : \
+ (i) == 6 ? GPIO_P6_IRQn : \
+ (i) == 7 ? GPIO_P7_IRQn : \
+ (i) == 8 ? GPIO_P8_IRQn : 0)
+
+/**@} end of ingroup gpio_registers */
+
+/* *************************************************************************** */
+/* 16/32 bit Timer/Counters */
+/**
+ * @ingroup tmr_registers
+ * @{
+ */
+#define MXC_CFG_TMR_INSTANCES (6) /**< Define for the number of timers on the \MXIM_Device */
+#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) /**< Base Address for Timer 0 */
+#define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 0 */
+#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) /**< Base Address for Timer 1 */
+#define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 1 */
+#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) /**< Base Address for Timer 2 */
+#define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 2 */
+#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) /**< Base Address for Timer 3 */
+#define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 3 */
+#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) /**< Base Address for Timer 4 */
+#define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 4 */
+#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) /**< Base Address for Timer 5 */
+#define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) /**< Pointer to a #mxc_tmr_regs_t structure representing Timer 5 */
+
+/**
+ * Macro that returns an #IRQn_Type for the requested 32-bit timer interrupt.
+ */
+#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : 0)
+/**
+ * Macro that returns an IRQn_Type for the requested 16-bit timer interrupt number.
+ */
+#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
+ (i) == 1 ? TMR1_0_IRQn : \
+ (i) == 2 ? TMR2_0_IRQn : \
+ (i) == 3 ? TMR3_0_IRQn : \
+ (i) == 4 ? TMR4_0_IRQn : \
+ (i) == 5 ? TMR5_0_IRQn : \
+ (i) == 6 ? TMR0_1_IRQn : \
+ (i) == 7 ? TMR1_1_IRQn : \
+ (i) == 8 ? TMR2_1_IRQn : \
+ (i) == 9 ? TMR3_1_IRQn : \
+ (i) == 10 ? TMR4_1_IRQn : \
+ (i) == 11 ? TMR5_1_IRQn : 0)
+/**
+ * Macro to return the base address for a given Timer index number.
+ * @p i Timer instance number.
+ * @p returns the base peripheral address for the requested timer instance.
+ */
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : \
+ (i) == 4 ? MXC_BASE_TMR4 : \
+ (i) == 5 ? MXC_BASE_TMR5 : 0)
+/**
+ * Macro to return a pointer to the #mxc_tmr_regs_t structure for a given Timer Instance.
+ * @p i Timer instance number.
+ * @p returns a pointer to a #mxc_tmr_regs_t for the requested timer number.
+ */
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : \
+ (i) == 4 ? MXC_TMR4 : \
+ (i) == 5 ? MXC_TMR5 : 0)
+/**
+ * Macro to return the index number for a given pointer to a #mxc_tmr_regs_t structure.
+ * @p p pointer to a #mxc_tmr_regs_t structure.
+ * @p returns a timer instance number.
+ */
+#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
+ (p) == MXC_TMR1 ? 1 : \
+ (p) == MXC_TMR2 ? 2 : \
+ (p) == MXC_TMR3 ? 3 : \
+ (p) == MXC_TMR4 ? 4 : \
+ (p) == MXC_TMR5 ? 5 : -1)
+
+/**@} end of ingroup tmr_registers */
+
+/**
+ * @ingroup product_name
+ * @{
+ */
+/* *************************************************************************** */
+/* Pulse Train Generation */
+#define MXC_CFG_PT_INSTANCES (16)
+
+#define MXC_BASE_PTG ((uint32_t)0x40011000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
+#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
+#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
+#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
+#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
+#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
+#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
+#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
+#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
+#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
+#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
+#define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
+#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
+
+#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
+ (i) == 1 ? MXC_BASE_PT1 : \
+ (i) == 2 ? MXC_BASE_PT2 : \
+ (i) == 3 ? MXC_BASE_PT3 : \
+ (i) == 4 ? MXC_BASE_PT4 : \
+ (i) == 5 ? MXC_BASE_PT5 : \
+ (i) == 6 ? MXC_BASE_PT6 : \
+ (i) == 7 ? MXC_BASE_PT7 : \
+ (i) == 8 ? MXC_BASE_PT8 : \
+ (i) == 9 ? MXC_BASE_PT9 : \
+ (i) == 10 ? MXC_BASE_PT10 : \
+ (i) == 11 ? MXC_BASE_PT11 : \
+ (i) == 12 ? MXC_BASE_PT12 : \
+ (i) == 13 ? MXC_BASE_PT13 : \
+ (i) == 14 ? MXC_BASE_PT14 : \
+ (i) == 15 ? MXC_BASE_PT15 : 0)
+
+#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
+ (i) == 1 ? MXC_PT1 : \
+ (i) == 2 ? MXC_PT2 : \
+ (i) == 3 ? MXC_PT3 : \
+ (i) == 4 ? MXC_PT4 : \
+ (i) == 5 ? MXC_PT5 : \
+ (i) == 6 ? MXC_PT6 : \
+ (i) == 7 ? MXC_PT7 : \
+ (i) == 8 ? MXC_PT8 : \
+ (i) == 9 ? MXC_PT9 : \
+ (i) == 10 ? MXC_PT10 : \
+ (i) == 11 ? MXC_PT11 : \
+ (i) == 12 ? MXC_PT12 : \
+ (i) == 13 ? MXC_PT13 : \
+ (i) == 14 ? MXC_PT14 : \
+ (i) == 15 ? MXC_PT15 : 0)
+
+#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
+ (p) == MXC_PT1 ? 1 : \
+ (p) == MXC_PT2 ? 2 : \
+ (p) == MXC_PT3 ? 3 : \
+ (p) == MXC_PT4 ? 4 : \
+ (p) == MXC_PT5 ? 5 : \
+ (p) == MXC_PT6 ? 6 : \
+ (p) == MXC_PT7 ? 7 : \
+ (p) == MXC_PT8 ? 8 : \
+ (p) == MXC_PT9 ? 9 : \
+ (p) == MXC_PT10 ? 10 : \
+ (p) == MXC_PT11 ? 11 : \
+ (p) == MXC_PT12 ? 12 : \
+ (p) == MXC_PT13 ? 13 : \
+ (p) == MXC_PT14 ? 14 : \
+ (p) == MXC_PT15 ? 15 : -1)
+
+
+
+/* *************************************************************************** */
+/* UART / Serial Port Interface */
+
+#define MXC_CFG_UART_INSTANCES (4)
+#define MXC_UART_FIFO_DEPTH (32)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+#define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) /**< UART Port 1 Base Address */
+#define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
+#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
+#define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
+#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
+#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
+#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
+#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
+#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
+#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
+#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
+#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
+#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
+
+#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : \
+ (i) == 2 ? UART2_IRQn : \
+ (i) == 3 ? UART3_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : \
+ (i) == 2 ? MXC_BASE_UART2 : \
+ (i) == 3 ? MXC_BASE_UART3 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : \
+ (i) == 2 ? MXC_UART2 : \
+ (i) == 3 ? MXC_UART3 : 0)
+
+#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
+ (p) == MXC_UART1 ? 1 : \
+ (p) == MXC_UART2 ? 2 : \
+ (p) == MXC_UART3 ? 3 : -1)
+
+#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
+ (i) == 1 ? MXC_BASE_UART1_FIFO : \
+ (i) == 2 ? MXC_BASE_UART2_FIFO : \
+ (i) == 3 ? MXC_BASE_UART3_FIFO : 0)
+
+#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
+ (i) == 1 ? MXC_UART1_FIFO : \
+ (i) == 2 ? MXC_UART2_FIFO : \
+ (i) == 3 ? MXC_UART3_FIFO : 0)
+
+
+
+/* *************************************************************************** */
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (3)
+#define MXC_I2CM_FIFO_DEPTH (8)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
+#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
+#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
+#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
+#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
+#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
+#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
+#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
+
+#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : \
+ (i) == 2 ? I2CM2_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : \
+ (i) == 2 ? MXC_BASE_I2CM2 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : \
+ (i) == 2 ? MXC_I2CM2 : 0)
+
+#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
+ (p) == MXC_I2CM1 ? 1 : \
+ (p) == MXC_I2CM2 ? 2 : -1)
+
+#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_FIFO : \
+ (i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
+
+#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
+ (i) == 1 ? MXC_I2CM1_FIFO : \
+ (i) == 2 ? MXC_I2CM2_FIFO : 0)
+
+
+
+/* *************************************************************************** */
+/* I2C Slave Interface (Mailbox type) */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+#define MXC_CFG_I2CS_BUFFER_SIZE (32)
+
+#define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
+#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
+
+#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
+
+#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
+
+#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
+
+#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
+
+/* *************************************************************************** */
+/* SPI Master Interface */
+
+#define MXC_CFG_SPIM_INSTANCES (3)
+#define MXC_CFG_SPIM_FIFO_DEPTH (16)
+
+#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
+#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
+#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
+#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
+#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
+#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
+#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
+#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
+#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
+#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
+#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
+#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
+
+#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
+ (i) == 1 ? SPIM1_IRQn : \
+ (i) == 2 ? SPIM2_IRQn : 0)
+
+#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
+ (i) == 1 ? MXC_BASE_SPIM1 : \
+ (i) == 2 ? MXC_BASE_SPIM2 : 0)
+
+#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
+ (i) == 1 ? MXC_SPIM1 : \
+ (i) == 2 ? MXC_SPIM2 : 0)
+
+#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
+ (p) == MXC_SPIM1 ? 1 : \
+ (p) == MXC_SPIM2 ? 2 : -1)
+
+#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
+ (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
+ (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
+
+#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
+ (i) == 1 ? MXC_SPIM1_FIFO : \
+ (i) == 2 ? MXC_SPIM2_FIFO : 0)
+
+
+
+/* *************************************************************************** */
+/* 1-Wire Master Interface */
+
+#define MXC_CFG_OWM_INSTANCES (1)
+
+#define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
+#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
+
+#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
+
+#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
+
+#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
+
+#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
+
+
+/* *************************************************************************** */
+/* ADC / AFE */
+
+#define MXC_CFG_ADC_FIFO_DEPTH (32)
+
+#define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+
+
+/* *************************************************************************** */
+/* SPIB AHB-to-SPI Bridge */
+
+#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
+#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
+
+
+
+/* *************************************************************************** */
+/* SPI Slave Interface */
+
+#define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
+#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
+#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
+#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
+
+
+
+/* *************************************************************************** */
+/* Bit Shifting */
+
+#define MXC_F_BIT_0 (1 << 0)
+#define MXC_F_BIT_1 (1 << 1)
+#define MXC_F_BIT_2 (1 << 2)
+#define MXC_F_BIT_3 (1 << 3)
+#define MXC_F_BIT_4 (1 << 4)
+#define MXC_F_BIT_5 (1 << 5)
+#define MXC_F_BIT_6 (1 << 6)
+#define MXC_F_BIT_7 (1 << 7)
+#define MXC_F_BIT_8 (1 << 8)
+#define MXC_F_BIT_9 (1 << 9)
+#define MXC_F_BIT_10 (1 << 10)
+#define MXC_F_BIT_11 (1 << 11)
+#define MXC_F_BIT_12 (1 << 12)
+#define MXC_F_BIT_13 (1 << 13)
+#define MXC_F_BIT_14 (1 << 14)
+#define MXC_F_BIT_15 (1 << 15)
+#define MXC_F_BIT_16 (1 << 16)
+#define MXC_F_BIT_17 (1 << 17)
+#define MXC_F_BIT_18 (1 << 18)
+#define MXC_F_BIT_19 (1 << 19)
+#define MXC_F_BIT_20 (1 << 20)
+#define MXC_F_BIT_21 (1 << 21)
+#define MXC_F_BIT_22 (1 << 22)
+#define MXC_F_BIT_23 (1 << 23)
+#define MXC_F_BIT_24 (1 << 24)
+#define MXC_F_BIT_25 (1 << 25)
+#define MXC_F_BIT_26 (1 << 26)
+#define MXC_F_BIT_27 (1 << 27)
+#define MXC_F_BIT_28 (1 << 28)
+#define MXC_F_BIT_29 (1 << 29)
+#define MXC_F_BIT_30 (1 << 30)
+#define MXC_F_BIT_31 (1 << 31)
+
+/* *************************************************************************** */
+
+#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
+
+/* *************************************************************************** */
+
+#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
+#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
+#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+
+/* *************************************************************************** */
+
+/* SCB CPACR Register Definitions */
+/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
+#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
+#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
+#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
+#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
+/**@} end of ingroup product_name */
+#endif /* _MAX3263X_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/mxc_device.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-23 15:28:53 -0500 (Wed, 23 Mar 2016) $ + * $Revision: 22067 $ + * + ******************************************************************************/ + +#ifndef _MXC_DEVICE_H_ +#define _MXC_DEVICE_H_ + +#include "max3263x.h" + +#ifndef TARGET +#error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV +#error TARGET_REV NOT DEFINED +#endif + +#if((TARGET_REV == 0x4131) || (TARGET_REV == 0x4132)) +// A1 or A2 +#define MXC_ADC_REV 0 +#define MXC_AES_REV 0 +#define MXC_CRC_REV 0 +#define MXC_FLC_REV 0 +#define MXC_GPIO_REV 0 +#define MXC_I2CM_REV 0 +#define MXC_I2CS_REV 0 +#define MXC_ICC_REV 0 +#define MXC_MAA_REV 0 +#define MXC_OWM_REV 0 +#define MXC_PMU_REV 0 +#define MXC_PRNG_REV 0 +#define MXC_PT_REV 0 +#define MXC_RTC_REV 0 +#define MXC_SPIM_REV 0 +#define MXC_SPIS_REV 0 +#define MXC_SPIX_REV 0 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 0 +#define MXC_USB_REV 0 +#define MXC_WDT2_REV 0 +#define MXC_WDT_REV 0 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif /* if(TARGET_REV == 0x4132) */ + +#endif /* _MXC_DEVICE_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/owm_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,218 @@
+/**
+ * @file
+ * @brief Type definitions for the 1-Wire Master Interface
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:22:03 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24666 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_OWM_REGS_H_
+#define _MXC_OWM_REGS_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+///@cond
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+
+/**
+ * @ingroup owm
+ * @defgroup owm_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+/**
+ * Structure type for the 1-Wire Master module registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM_CFG Register - 1-Wire Master Configuration */
+ __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM_CLK_DIV_1US Register - 1-Wire Master Clock Divisor */
+ __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM_CTRL_STAT Register - 1-Wire Master Control/Status */
+ __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM_DATA Register - 1-Wire Master Data Buffer */
+ __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM_INTFL Register - 1-Wire Master Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM_INTEN Register - 1-Wire Master Interrupt Enables */
+} mxc_owm_regs_t;
+/**@} end of group owm_registers */
+
+/**
+ * @ingroup owm_registers
+ * @defgroup OWM_Register_Offsets Register Offsets
+ * @brief 1-Wire Master register offsets from the 1-Wire Master Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_OWM_OFFS_CFG ((uint32_t)0x00000000UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0000:</tt>*/
+#define MXC_R_OWM_OFFS_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0004:</tt>*/
+#define MXC_R_OWM_OFFS_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0008:</tt>*/
+#define MXC_R_OWM_OFFS_DATA ((uint32_t)0x0000000CUL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x000C:</tt>*/
+#define MXC_R_OWM_OFFS_INTFL ((uint32_t)0x00000010UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0010:</tt>*/
+#define MXC_R_OWM_OFFS_INTEN ((uint32_t)0x00000014UL) /**< Offset from the OWM Base Peripheral Address:<tt>\b 0x0014:</tt>*/
+/**@} end of group OWM_Register_Offsets */
+
+/*
+ Field positions and masks for module OWM.
+*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_cfg OWM_CFG
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< LONG_LINE_MODE Position */
+#define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< LONG_LINE_MODE Mask */
+#define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< FORCE_PRES_DET Position */
+#define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< FORCE_PRES_DET Mask */
+#define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< BIT_BANG_EN Position */
+#define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< BIT_BANG_EN Mask */
+#define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< EXT_PULLUP_MODE Position */
+#define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< EXT_PULLUP_MODE Mask */
+#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< EXT_PULLUP_ENABLE Position */
+#define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< EXT_PULLUP_ENABLE Mask */
+#define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< SINGLE_BIT_MODE Position */
+#define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< SINGLE_BIT_MODE Mask */
+#define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< OVERDRIVE Position */
+#define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< OVERDRIVE Mask */
+#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< INT_PULLUP_ENABLE Position */
+#define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< INT_PULLUP_ENABLE Mask */
+/**@} end of group owm_cfg*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_clk_div OWM_CLK_DIV
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< 1US_DIVISOR Position */
+#define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< 1US_DIVISOR Mask */
+/**@} end of group owm_clk_cfg*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_ctrl_stat OWM_CTRL_STAT
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< START_OW_RESET Position */
+#define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< START_OW_RESET Mask */
+#define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< SRA_MODE Position */
+#define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< SRA_MODE Mask */
+#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< BIT_BANG_OE Position */
+#define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< BIT_BANG_OE Mask */
+#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< OW_INPUT Position */
+#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< OW_INPUT Mask */
+#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< OD_SPEC_MODE Position */
+#define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< OD_SPEC_MODE Mask */
+#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS 5 /**< EXT_PULLUP_POL Position */
+#define MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS)) /**< EXT_PULLUP_POL Mask */
+#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< PRESENCE_DETECT Position */
+#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x00000001UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< PRESENCE_DETECT Mask */
+/**@} end of group owm_ctrl*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_data OWM_DATA
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_DATA_TX_RX_POS 0 /**< TX_RX Position */
+#define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0x000000FFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< TX_RX Mask */
+/**@} end of group owm_data*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_intfl OWM_INTFL
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
+#define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
+#define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
+#define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
+#define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
+#define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
+#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
+#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
+#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< LINE_LOW Position */
+#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< LINE_LOW Mask */
+/**@} end of group owm_intfl*/
+/**
+ * @ingroup owm_registers
+ * @defgroup owm_inten OWM_INTEN
+ * @brief Field Positions and Masks
+ */
+#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< OW_RESET_DONE Position */
+#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< OW_RESET_DONE Mask */
+#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< TX_DATA_EMPTY Position */
+#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< TX_DATA_EMPTY Mask */
+#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< RX_DATA_READY Position */
+#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< RX_DATA_READY Mask */
+#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< LINE_SHORT Position */
+#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< LINE_SHORT Mask */
+#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< LINE_LOW Position */
+#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x00000001UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< LINE_LOW Mask */
+/**@} end of group owm_inten*/
+/**
+ * @ingroup owm_cfg
+ * @{
+ */
+#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED ((uint32_t)(0x00000000UL)) /**< External Pullup Mode Value: Unused */
+#define MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED ((uint32_t)(0x00000001UL)) /**< External Pullup Mode Value: Used */
+/**@}*/
+/**
+ * @ingroup owm_ctrl_stat
+ * @{
+ */
+#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US ((uint32_t)(0x00000000UL)) /**< Overdrive speed setting 12us. */
+#define MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US ((uint32_t)(0x00000001UL)) /**< Overdrive speed setting 10us. */
+
+#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH ((uint32_t)(0x00000000UL)) /**< External Pullup Pin Polarity Active High */
+#define MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW ((uint32_t)(0x00000001UL)) /**< External Pullup Pin Polarity Active Low */
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_OWM_REGS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,411 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24667 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_PMU_REGS_H_
+#define _MXC_PMU_REGS_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+/**
+ * @ingroup pmuGroup
+ * @defgroup pmu_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
+ * @{
+ */
+/**
+ * Structure type for the PMU Registers
+ */
+typedef struct {
+ __IO uint32_t dscadr; /**< <tt>\b 0x0000:</tt> PMU Channel Next Descriptor Address */
+ __IO uint32_t cfg; /**< <tt>\b 0x0004:</tt> PMU Channel Configuration */
+ __IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PMU Channel Loop Counters */
+ __RO uint32_t rsv00C[5]; /**< <tt>\b 0x000C-0x001C:</tt> RESERVED */
+} mxc_pmu_regs_t;
+/**@} end of group pmu_registers */
+
+/*
+ Register offsets for module PMU.
+*/
+/**
+ * @ingroup pmu_registers
+ * @defgroup PMU_Register_Offsets Register Offsets
+ * @brief PMU Register Offsets from the PMU Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) /**< Offset from the PMU Base Address: <tt>\b 0x0000</tt>*/
+#define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) /**< Offset from the PMU Base Address: <tt>\b 0x0004</tt>*/
+#define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PMU Base Address: <tt>\b 0x0008</tt>*/
+/**@} end of group PMU_Register_Offsets */
+
+/*
+ Field positions and masks for module PMU.
+*/
+///@cond
+#define MXC_F_PMU_CFG_ENABLE_POS 0
+#define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
+#define MXC_F_PMU_CFG_LL_STOPPED_POS 2
+#define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
+#define MXC_F_PMU_CFG_MANUAL_POS 3
+#define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
+#define MXC_F_PMU_CFG_BUS_ERROR_POS 4
+#define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
+#define MXC_F_PMU_CFG_TO_STAT_POS 6
+#define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
+#define MXC_F_PMU_CFG_TO_SEL_POS 11
+#define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
+#define MXC_F_PMU_CFG_PS_SEL_POS 14
+#define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
+#define MXC_F_PMU_CFG_INTERRUPT_POS 16
+#define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
+#define MXC_F_PMU_CFG_INT_EN_POS 17
+#define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
+#define MXC_F_PMU_CFG_BURST_SIZE_POS 24
+#define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
+
+#define MXC_F_PMU_LOOP_COUNTER_0_POS 0
+#define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
+#define MXC_F_PMU_LOOP_COUNTER_1_POS 16
+#define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
+
+/*
+ Field values
+*/
+
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
+#define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
+
+#define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
+#define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
+#define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
+
+/* Op codes */
+#define PMU_MOVE_OP 0
+#define PMU_WRITE_OP 1
+#define PMU_WAIT_OP 2
+#define PMU_JUMP_OP 3
+#define PMU_LOOP_OP 4
+#define PMU_POLL_OP 5
+#define PMU_BRANCH_OP 6
+#define PMU_TRANSFER_OP 7
+
+/* Bit values used in all decroptiors */
+#define PMU_NO_INTERRUPT 0 /**< Interrupt flag is NOT set at end of channel execution */
+#define PMU_INTERRUPT 1 /**< Interrupt flag is set at end of channel execution */
+
+#define PMU_NO_STOP 0 /**< Do not stop channel after this descriptor ends */
+#define PMU_STOP 1 /**< Halt PMU channel after this descriptor ends */
+
+/* Interrupt and Stop bit positions */
+#define PMU_INT_POS 3
+#define PMU_STOP_POS 4
+
+/* MOVE descriptor bit values */
+#define PMU_MOVE_READ_8_BIT 0 /**< Read size = 8 */
+#define PMU_MOVE_READ_16_BIT 1 /**< Read size = 16 */
+#define PMU_MOVE_READ_32_BIT 2 /**< Read size = 32 */
+
+#define PMU_MOVE_READ_NO_INC 0 /**< read address not incremented */
+#define PMU_MOVE_READ_INC 1 /**< Auto-Increment read address */
+
+#define PMU_MOVE_WRITE_8_BIT 0 /**< Write Size = 8 */
+#define PMU_MOVE_WRITE_16_BIT 1 /**< Write Size = 16 */
+#define PMU_MOVE_WRITE_32_BIT 2 /**< Write Size = 32 */
+
+#define PMU_MOVE_WRITE_NO_INC 0 /**< Write address not incremented */
+#define PMU_MOVE_WRITE_INC 1 /**< Auto_Increment write address */
+
+#define PMU_MOVE_NO_CONT 0 /**< MOVE does not rely on previous MOVE */
+#define PMU_MOVE_CONT 1 /**< MOVE continues from read/write address and INC values defined in previous MOVE */
+
+/* MOVE bit positions */
+#define PMU_MOVE_READS_POS 5
+#define PMU_MOVE_READI_POS 7
+#define PMU_MOVE_WRITES_POS 8
+#define PMU_MOVE_WRITEI_POS 10
+#define PMU_MOVE_CONT_POS 11
+#define PMU_MOVE_LEN_POS 12
+
+/* WRITE descriptor bit values */
+#define PMU_WRITE_MASKED_WRITE_VALUE 0 /**< Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
+#define PMU_WRITE_PLUS_1 1 /**< Value = READ_VALUE + 1 */
+#define PMU_WRITE_MINUS_1 2 /**< Value = READ_VALUE - 1 */
+#define PMU_WRITE_SHIFT_RT_1 3 /**< Value = READ_VALUE >> 1 */
+#define PMU_WRITE_SHIFT_LT_1 4 /**< Value = READ_VALUE << 1 */
+#define PMU_WRITE_ROTATE_RT_1 5 /**< Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
+#define PMU_WRITE_ROTATE_LT_1 6 /**< Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
+#define PMU_WRITE_NOT_READ_VAL 7 /**< Value = ~READ_VALUE */
+#define PMU_WRITE_XOR_MASK 8 /**< Value = READ_VALUE XOR WRITE_MASK */
+#define PMU_WRITE_OR_MASK 9 /**< Value = READ_VALUE | WRITE_MASK */
+#define PMU_WRITE_AND_MASK 10 /**< Value = READ_VALUE & WRITE_MASK */
+
+/* WRITE bit positions */
+#define PMU_WRITE_METHOD_POS 8
+
+/* WAIT descriptor bit values */
+#define PMU_WAIT_SEL_0 0 /**< Select the interrupt source */
+#define PMU_WAIT_SEL_1 1
+
+/* WAIT bit positions */
+#define PMU_WAIT_WAIT_POS 5
+#define PMU_WAIT_SEL_POS 6
+
+/* LOOP descriptor bit values */
+#define PMU_LOOP_SEL_COUNTER0 0 /**< select Counter0 to count down from */
+#define PMU_LOOP_SEL_COUNTER1 1 /**< select Counter1 to count down from */
+
+/* LOOP bit positions */
+#define PMU_LOOP_SEL_COUNTER_POS 5
+
+/* POLL descriptor bit values */
+#define PMU_POLL_OR 0 /**< polling ends when at least one mask bit matches expected data */
+#define PMU_POLL_AND 1 /**< polling ends when all mask bits matches expected data */
+
+/* POLL bit positions */
+#define PMU_POLL_AND_POS 7
+
+/* BRANCH descriptor bit values */
+#define PMU_BRANCH_OR 0 /**< branch when any mask bit = or != expected data (based on = or != branch type) */
+#define PMU_BRANCH_AND 1 /**< branch when all mask bit = or != expected data (based on = or != branch type) */
+
+#define PMU_BRANCH_TYPE_NOT_EQUAL 0 /**< Branch when polled data != expected data */
+#define PMU_BRANCH_TYPE_EQUAL 1 /**< Branch when polled data = expected data */
+#define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /**< Branch when polled data <= expected data */
+#define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /**< Branch when polled data >= expected data */
+#define PMU_BRANCH_TYPE_LESSER 4 /**< Branch when polled data < expected data */
+#define PMU_BRANCH_TYPE_GREATER 5 /**< Branch when polled data > expected data */
+
+/* BRANCH bit positions */
+#define PMU_BRANCH_AND_POS 7
+#define PMU_BRANCH_TYPE_POS 8
+
+/* TRANSFER descriptor bit values */
+#define PMU_TX_READ_8_BIT 0 /**< Read size = 8 */
+#define PMU_TX_READ_16_BIT 1 /**< Read size = 16 */
+#define PMU_TX_READ_32_BIT 2 /**< Read size = 32 */
+
+#define PMU_TX_READ_NO_INC 0 /**< read address not incremented */
+#define PMU_TX_READ_INC 1 /**< Auto-Increment read address */
+
+#define PMU_TX_WRITE_8_BIT 0 /**< Write Size = 8 */
+#define PMU_TX_WRITE_16_BIT 1 /**< Write Size = 16 */
+#define PMU_TX_WRITE_32_BIT 2 /**< Write Size = 32 */
+
+#define PMU_TX_WRITE_NO_INC 0 /**< Write address not incremented */
+#define PMU_TX_WRITE_INC 1 /**< Auto_Increment write address */
+
+/* TRANSFER bit positions */
+#define PMU_TX_READS_POS 5
+#define PMU_TX_READI_POS 7
+#define PMU_TX_WRITES_POS 8
+#define PMU_TX_WRITEI_POS 10
+#define PMU_TX_LEN_POS 12
+#define PMU_TX_BS_POS 26
+
+/* PMU interrupt sources for the WAIT opcode */
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
+#define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
+#define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
+#define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
+#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
+#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
+#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
+#define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
+#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
+#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
+#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
+#define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
+#define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
+#define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
+#define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
+#define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
+#define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
+#define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
+#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
+#define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
+#define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
+#define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
+#define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
+#define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
+#define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
+#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
+#define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
+#define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
+#define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
+#define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
+
+/* PMU interrupt sources for the TRANSFER opcode */
+#define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
+#define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
+#define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
+#define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
+#define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
+#define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
+#define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
+#define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
+#define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
+#define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
+#define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
+#define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
+#define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
+#define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
+#define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
+#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
+#define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
+#define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
+#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
+#define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
+#define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
+#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
+#define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
+#define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
+#define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
+///@endcond
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PMU_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/prng_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,98 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2015-11-02 13:19:39 -0600 (Mon, 02 Nov 2015) $
+ * $Revision: 19838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PRNG_REGS_H_
+#define _MXC_PRNG_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t user_entropy; /* 0x0000 PRNG User Entropy and Status */
+ __IO uint32_t rnd_num; /* 0x0004 PRNG Seed Output */
+} mxc_prng_regs_t;
+
+/*
+ Register offsets for module PRNG.
+*/
+
+#define MXC_R_PRNG_OFFS_USER_ENTROPY ((uint32_t)0x00000000UL)
+#define MXC_R_PRNG_OFFS_RND_NUM ((uint32_t)0x00000004UL)
+
+/*
+ Field positions and masks for module PRNG.
+*/
+
+#define MXC_F_PRNG_USER_ENTROPY_VALUE_POS 0
+#define MXC_F_PRNG_USER_ENTROPY_VALUE ((uint32_t)(0x000000FFUL << MXC_F_PRNG_USER_ENTROPY_VALUE_POS))
+#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS 8
+#define MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY ((uint32_t)(0x00000001UL << MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PRNG_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pt_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,404 @@
+/**
+ * @file
+ * @brief Type definitions for the Pulse Train Engine.
+ *
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24669 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_PT_REGS_H_
+#define _MXC_PT_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup pulsetrain
+ * @defgroup pulsetrain_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+
+/**
+ * Structure type for the Pulse Train Global module registers allowing direct 32-bit access to each register.
+ */
+ typedef struct {
+ __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> \c PTG_ENABLE Register - Global Enable/Disable Controls for All Pulse Trains. */
+ __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> \c PTG_RESYNC Register - Global Resync (All Pulse Trains) Control. */
+ __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> \c PTG_INTFL Register - Pulse Train Interrupt Flags. */
+ __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> \c PTG_INTEN Register - Pulse Train Interrupt Enable/Disable. */
+} mxc_ptg_regs_t;
+
+/**
+ * Structure type for the Pulse Train configuration registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t rate_length; /**< <tt>\b 0x0000:</tt>\c PT_RATE_LENGTH Register - Pulse Train Configuration. */
+ __IO uint32_t train; /**< <tt>\b 0x0004:</tt>\c PT_TRAIN Register - Pulse Train Output Pattern. */
+ __IO uint32_t loop; /**< <tt>\b 0x0008:</tt>\c PT_LOOP Register - Pulse Train Loop Configuration. */
+ __IO uint32_t restart; /**< <tt>\b 0x000C:</tt>\c PT_RESTART Register - Pulse Train Auto-Restart Configuration. */
+} mxc_pt_regs_t;
+/**@} end of pulsetrain_registers group*/
+
+/*
+ Register offsets for module PT.
+*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PTG_Register_Offsets Global Register Offsets
+ * @brief Pluse Train Global Control Register Offsets from the Pulse Train Global Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x0008</tt> */
+#define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the PTG Base Peripheral Address:<tt>\b 0x000C</tt> */
+/**@} end of group PTG_Register_Offsets*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_Register_Offsets Register Offsets: Configuration
+ * @brief Pluse Train Configuration Register Offsets from the Pulse Train Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x0008</tt> */
+#define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) /**< Offset from the PT Base Peripheral Address:<tt>\b 0x000C</tt> */
+/**@} end of group PT_Register_Offsets*/
+
+/*
+ Field positions and masks for module PT.
+*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_ENABLE_Register PT_ENABLE
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_ENABLE_PT0_POS 0 /**< PT0 Position */
+#define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) /**< PT0 Mask */
+#define MXC_F_PT_ENABLE_PT1_POS 1 /**< PT1 Position */
+#define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) /**< PT1 Mask */
+#define MXC_F_PT_ENABLE_PT2_POS 2 /**< PT2 Position */
+#define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) /**< PT2 Mask */
+#define MXC_F_PT_ENABLE_PT3_POS 3 /**< PT3 Position */
+#define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) /**< PT3 Mask */
+#define MXC_F_PT_ENABLE_PT4_POS 4 /**< PT4 Position */
+#define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) /**< PT4 Mask */
+#define MXC_F_PT_ENABLE_PT5_POS 5 /**< PT5 Position */
+#define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) /**< PT5 Mask */
+#define MXC_F_PT_ENABLE_PT6_POS 6 /**< PT6 Position */
+#define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) /**< PT6 Mask */
+#define MXC_F_PT_ENABLE_PT7_POS 7 /**< PT7 Position */
+#define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) /**< PT7 Mask */
+#define MXC_F_PT_ENABLE_PT8_POS 8 /**< PT8 Position */
+#define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) /**< PT8 Mask */
+#define MXC_F_PT_ENABLE_PT9_POS 9 /**< PT9 Position */
+#define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) /**< PT9 Mask */
+#define MXC_F_PT_ENABLE_PT10_POS 10 /**< PT10 Position */
+#define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) /**< PT10 Mask */
+#define MXC_F_PT_ENABLE_PT11_POS 11 /**< PT11 Position */
+#define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) /**< PT11 Mask */
+#define MXC_F_PT_ENABLE_PT12_POS 12 /**< PT12 Position */
+#define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) /**< PT12 Mask */
+#define MXC_F_PT_ENABLE_PT13_POS 13 /**< PT13 Position */
+#define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) /**< PT13 Mask */
+#define MXC_F_PT_ENABLE_PT14_POS 14 /**< PT14 Position */
+#define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) /**< PT14 Mask */
+#define MXC_F_PT_ENABLE_PT15_POS 15 /**< PT15 Position */
+#define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) /**< PT15 Mask */
+/**@} PT_ENABLE_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_RESYNC_Register PT_RESYNC
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_RESYNC_PT0_POS 0 /**< PT0 Position */
+#define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) /**< PT0 Mask */
+#define MXC_F_PT_RESYNC_PT1_POS 1 /**< PT1 Position */
+#define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) /**< PT1 Mask */
+#define MXC_F_PT_RESYNC_PT2_POS 2 /**< PT2 Position */
+#define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) /**< PT2 Mask */
+#define MXC_F_PT_RESYNC_PT3_POS 3 /**< PT3 Position */
+#define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) /**< PT3 Mask */
+#define MXC_F_PT_RESYNC_PT4_POS 4 /**< PT4 Position */
+#define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) /**< PT4 Mask */
+#define MXC_F_PT_RESYNC_PT5_POS 5 /**< PT5 Position */
+#define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) /**< PT5 Mask */
+#define MXC_F_PT_RESYNC_PT6_POS 6 /**< PT6 Position */
+#define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) /**< PT6 Mask */
+#define MXC_F_PT_RESYNC_PT7_POS 7 /**< PT7 Position */
+#define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) /**< PT7 Mask */
+#define MXC_F_PT_RESYNC_PT8_POS 8 /**< PT8 Position */
+#define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) /**< PT8 Mask */
+#define MXC_F_PT_RESYNC_PT9_POS 9 /**< PT9 Position */
+#define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) /**< PT9 Mask */
+#define MXC_F_PT_RESYNC_PT10_POS 10 /**< PT10 Position */
+#define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) /**< PT10 Mask */
+#define MXC_F_PT_RESYNC_PT11_POS 11 /**< PT11 Position */
+#define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) /**< PT11 Mask */
+#define MXC_F_PT_RESYNC_PT12_POS 12 /**< PT12 Position */
+#define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) /**< PT12 Mask */
+#define MXC_F_PT_RESYNC_PT13_POS 13 /**< PT13 Position */
+#define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) /**< PT13 Mask */
+#define MXC_F_PT_RESYNC_PT14_POS 14 /**< PT14 Position */
+#define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) /**< PT14 Mask */
+#define MXC_F_PT_RESYNC_PT15_POS 15 /**< PT15 Position */
+#define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) /**< PT15 Mask */
+/**@} PT_RESYNC_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_INTFL_Register PT_INTFL
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_INTFL_PT0_POS 0 /**< PT0 Position */
+#define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) /**< PT0 Mask */
+#define MXC_F_PT_INTFL_PT1_POS 1 /**< PT1 Position */
+#define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) /**< PT1 Mask */
+#define MXC_F_PT_INTFL_PT2_POS 2 /**< PT2 Position */
+#define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) /**< PT2 Mask */
+#define MXC_F_PT_INTFL_PT3_POS 3 /**< PT3 Position */
+#define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) /**< PT3 Mask */
+#define MXC_F_PT_INTFL_PT4_POS 4 /**< PT4 Position */
+#define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) /**< PT4 Mask */
+#define MXC_F_PT_INTFL_PT5_POS 5 /**< PT5 Position */
+#define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) /**< PT5 Mask */
+#define MXC_F_PT_INTFL_PT6_POS 6 /**< PT6 Position */
+#define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) /**< PT6 Mask */
+#define MXC_F_PT_INTFL_PT7_POS 7 /**< PT7 Position */
+#define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) /**< PT7 Mask */
+#define MXC_F_PT_INTFL_PT8_POS 8 /**< PT8 Position */
+#define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) /**< PT8 Mask */
+#define MXC_F_PT_INTFL_PT9_POS 9 /**< PT9 Position */
+#define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) /**< PT9 Mask */
+#define MXC_F_PT_INTFL_PT10_POS 10 /**< PT10 Position */
+#define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) /**< PT10 Mask */
+#define MXC_F_PT_INTFL_PT11_POS 11 /**< PT11 Position */
+#define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) /**< PT11 Mask */
+#define MXC_F_PT_INTFL_PT12_POS 12 /**< PT12 Position */
+#define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) /**< PT12 Mask */
+#define MXC_F_PT_INTFL_PT13_POS 13 /**< PT13 Position */
+#define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) /**< PT13 Mask */
+#define MXC_F_PT_INTFL_PT14_POS 14 /**< PT14 Position */
+#define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) /**< PT14 Mask */
+#define MXC_F_PT_INTFL_PT15_POS 15 /**< PT15 Position */
+#define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) /**< PT15 Mask */
+/**@} PT_INTFL_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_INTEN_Register PT_INTEN
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_INTEN_PT0_POS 0 /**< PT0 Position */
+#define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) /**< PT0 Mask */
+#define MXC_F_PT_INTEN_PT1_POS 1 /**< PT1 Position */
+#define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) /**< PT1 Mask */
+#define MXC_F_PT_INTEN_PT2_POS 2 /**< PT2 Position */
+#define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) /**< PT2 Mask */
+#define MXC_F_PT_INTEN_PT3_POS 3 /**< PT3 Position */
+#define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) /**< PT3 Mask */
+#define MXC_F_PT_INTEN_PT4_POS 4 /**< PT4 Position */
+#define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) /**< PT4 Mask */
+#define MXC_F_PT_INTEN_PT5_POS 5 /**< PT5 Position */
+#define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) /**< PT5 Mask */
+#define MXC_F_PT_INTEN_PT6_POS 6 /**< PT6 Position */
+#define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) /**< PT6 Mask */
+#define MXC_F_PT_INTEN_PT7_POS 7 /**< PT7 Position */
+#define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) /**< PT7 Mask */
+#define MXC_F_PT_INTEN_PT8_POS 8 /**< PT8 Position */
+#define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) /**< PT8 Mask */
+#define MXC_F_PT_INTEN_PT9_POS 9 /**< PT9 Position */
+#define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) /**< PT9 Mask */
+#define MXC_F_PT_INTEN_PT10_POS 10 /**< PT10 Position*/
+#define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) /**< PT10 Mask */
+#define MXC_F_PT_INTEN_PT11_POS 11 /**< PT11 Position*/
+#define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) /**< PT11 Mask */
+#define MXC_F_PT_INTEN_PT12_POS 12 /**< PT12 Position*/
+#define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) /**< PT12 Mask */
+#define MXC_F_PT_INTEN_PT13_POS 13 /**< PT13 Position*/
+#define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) /**< PT13 Mask */
+#define MXC_F_PT_INTEN_PT14_POS 14 /**< PT14 Position*/
+#define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) /**< PT14 Mask */
+#define MXC_F_PT_INTEN_PT15_POS 15 /**< PT15 Position*/
+#define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) /**< PT15 Mask */
+/**@} PT_INTEN_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_RATE_LENGTH_Register PT_RATE_LENGTH
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_CONTROL Position */
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_CONTROL Mask */
+#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< MODE Position */
+#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< MODE Mask */
+/**@} PT_RATE_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_LOOP_Register PT_LOOP
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_LOOP_COUNT_POS 0 /**< COUNT Position */
+#define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< COUNT Mask */
+#define MXC_F_PT_LOOP_DELAY_POS 16 /**< DELAY Position */
+#define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< DELAY Mask */
+/**@}PT_LOOP_Register*/
+/**
+ * @ingroup pulsetrain_registers
+ * @defgroup PT_RESTART_Register PT_RESTART
+ * @brief Field Positions and Masks
+ * @{
+ */
+#define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< PT_X_SELECT Position */
+#define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< PT_X_SELECT Mask */
+#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< ON_PT_X_LOOP_EXIT Position */
+#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< ON_PT_X_LOOP_EXIT Mask */
+#define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< PT_Y_SELECT Position */
+#define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< PT_Y_SELECT Mask */
+#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< ON_PT_Y_LOOP_EXIT Position */
+#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< ON_PT_Y_LOOP_EXIT Mask */
+/**@} PT_RESTART_Register */
+
+
+/*
+ Field values and shifted values for module PT.
+*/
+/**
+ * @ingroup PT_RATE_LENGTH_Register
+ * @defgroup pt_mode_v_sv Mode Field Values and Shifted Values
+ * @brief Mode selection values and shifted values to set the PT_RATE_LENGTH register MODE Field.
+ */
+#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) /**< Value for 32-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) /**< Value for SQUARE_WAVE. */
+#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) /**< Value for 2-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) /**< Value for 3-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) /**< Value for 4-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) /**< Value for 5-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) /**< Value for 6-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) /**< Value for 7-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) /**< Value for 8-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) /**< Value for 9-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) /**< Value for 10-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) /**< Value for 11-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) /**< Value for 12-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) /**< Value for 13-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) /**< Value for 14-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) /**< Value for 15-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) /**< Value for 16-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) /**< Value for 17-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) /**< Value for 18-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) /**< Value for 19-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) /**< Value for 20-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) /**< Value for 21-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) /**< Value for 22-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) /**< Value for 23-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) /**< Value for 24-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) /**< Value for 25-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) /**< Value for 26-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) /**< Value for 27-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) /**< Value for 28-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) /**< Value for 29-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) /**< Value for 30-BIT. */
+#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) /**< Value for 31-BIT. */
+
+#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 32-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for SQUARE_WAVE. */
+#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 2-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 3-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 4-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 5-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 6-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 7-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 8-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 9-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 10-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 11-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 12-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 13-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 14-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 15-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 16-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 17-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 18-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 19-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 20-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 21-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 22-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 23-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 24-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 25-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 26-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 27-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 28-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 29-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 30-BIT. */
+#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< Shifted Value for 31-BIT. */
+/**@} pt_mode_v_sv*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PT_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrman_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,435 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+ /** WUD Mode for Selected PAD = Clear/Activate */
+ MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+ /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+ MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+ /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+ MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+ /** WUD Mode for Selected PAD = No pad state change */
+ MXC_E_PWRMAN_PAD_MODE_NONE
+}
+mxc_pwrman_pad_mode_t;
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
+ __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
+ __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
+ __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
+ __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
+ __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
+ __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
+ __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
+ __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
+ __IO uint32_t wud_seen2; /* 0x0024 Wake-up Detect Status for P8 */
+ __RO uint32_t rsv028[2]; /* 0x0028-0x002C */
+ __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
+ __RO uint32_t rsv034; /* 0x0034 */
+ __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
+ __IO uint32_t base_part_num; /* 0x003C Base Part Number */
+ __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
+ __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
+ __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
+} mxc_pwrman_regs_t;
+
+
+/*
+ Register offsets for module PWRMAN.
+*/
+
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN2 ((uint32_t)0x00000024UL)
+#define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
+
+
+/*
+ Field positions and masks for module PWRMAN.
+*/
+
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000007FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
+#define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS 8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS 9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS 10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS 11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS 12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS 13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS 14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS 15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS 16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS 17
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS 18
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS 19
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS 20
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS 21
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS 22
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS 23
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS 24
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS 25
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS 26
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS 27
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS 28
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS 29
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS 30
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS 31
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS 0
+#define MXC_F_PWRMAN_WUD_SEEN2_GPIO64 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO64_POS))
+#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS 1
+#define MXC_F_PWRMAN_WUD_SEEN2_GPIO65 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN2_GPIO65_POS))
+
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
+#define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS 18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS 21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS 26
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRMAN_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,431 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_PWRSEQ_REGS_H_
+#define _MXC_PWRSEQ_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
+ __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
+ __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
+ __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
+ __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
+ __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
+ __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
+ __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
+ __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
+ __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
+ __RO uint32_t rsv028; /* 0x0028 */
+ __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
+ __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
+ __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
+ __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
+ __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
+} mxc_pwrseq_regs_t;
+
+
+/*
+ Register offsets for module PWRSEQ.
+*/
+
+#define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
+#define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
+#define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
+#define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
+#define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module PWRSEQ.
+*/
+
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
+#define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
+#define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
+#define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
+#define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
+#define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
+#define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
+#define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
+#define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
+#define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
+#define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
+#define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
+#define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
+#define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
+#define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
+#define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
+#define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
+#define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
+#define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
+#define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
+#define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
+#define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
+#define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
+#define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
+#define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
+#define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
+#define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
+#define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
+#define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
+#define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
+#define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
+#define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
+#define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
+#define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
+#define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
+#define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
+#define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
+#define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
+#define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
+
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
+#define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
+#define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
+
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
+#define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
+#define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
+#define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
+#define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
+#define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
+#define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
+
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
+#define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
+#define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
+
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
+#define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
+
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
+#define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
+#define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
+#define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_PWRSEQ_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/rtc_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,362 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the Real-Time Clock.
+ *
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24670 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_RTC_REGS_H_
+#define _MXC_RTC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+/// @cond
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+
+/**
+ * @ingroup rtc
+ * @defgroup rtc_registers RTC Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+
+/**
+ * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register.
+ */
+ typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */
+ __IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */
+ __IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */
+ __IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */
+ __IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */
+ __IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */
+ __IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */
+ __RO uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */
+ __IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */
+ __IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */
+ __IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */
+} mxc_rtctmr_regs_t;
+
+
+/**
+ * Structure type for access to the RTC CFG hardware.
+ */
+typedef struct {
+ __IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */
+ __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */
+ __RO uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */
+ __IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */
+} mxc_rtccfg_regs_t;
+/**@} end of group rtc_registers.*/
+
+/*
+ Register offsets for module RTC.
+*/
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_Register_Offsets Register Offsets
+ * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */
+#define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
+#define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */
+#define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */
+#define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */
+#define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */
+/**@} end of group RTC_Register_Offsets */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets
+ * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
+/**@} end of group RTCCFG_Register_Offsets */
+
+/*
+ Field positions and masks for module RTC.
+*/
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_CTRL_Register RTC_CTRL
+ * @{
+ */
+#define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */
+#define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */
+#define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */
+#define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */
+#define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */
+#define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */
+#define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */
+#define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */
+#define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */
+#define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */
+/**@} end of group RTC_CTRL*/
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_FLAGS_Register RTC_FLAGS
+ * @{
+ */
+#define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */
+#define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */
+#define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */
+#define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */
+#define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */
+#define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */
+#define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */
+#define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */
+#define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */
+#define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */
+#define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */
+/**@} end of group RTC_FLAGS_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL.
+ * @{
+ */
+#define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */
+#define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */
+/**@} end of group RTC_SNZ_VAL_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_INTEN_Register RTC_INTEN.
+ * @{
+ */
+#define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */
+#define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */
+#define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */
+#define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
+#define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
+#define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */
+#define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */
+#define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */
+#define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */
+/**@} end of group RTC_INTEN_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_PRESCALE_Register RTC_PRESCALE.
+ * @{
+ */
+#define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */
+#define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */
+/**@} end of group RTC_INTEN_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK.
+ * @{
+ */
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */
+#define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */
+/**@} end of group RTC_PRESCALE_MASK_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL.
+ * @{
+ */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */
+/**@} end of group RTC_TRIM_CTRL_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE.
+ * @{
+ */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */
+#define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */
+/**@} end of group RTC_TRIM_VALUE_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR.
+ * @{
+ */
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */
+/**@} end of group RTC_NANO_CNTR_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL.
+ * @{
+ */
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */
+#define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */
+/**@} end of group RTC_CLK_CTRL_Register */
+/**
+ * @ingroup rtc_registers
+ * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL.
+ * @{
+ */
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */
+#define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */
+/**@} end of group RTC_OSC_CTRL_Register */
+
+/*
+ Field values
+*/
+/**
+ * @ingroup RTC_CTRL_Register
+ * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values
+ * @{
+ */
+#define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */
+#define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */
+/**@} end of group rtc_snz_mode_values */
+/**
+ * @ingroup RTC_PRESCALE_Register
+ * @defgroup rtc_prescale_values RTC Prescale Values
+ * @{
+ */
+#define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/
+#define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/
+/**@} end of group rtc_prescale_values*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_RTC_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spib_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,244 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_SPIB_REGS_H_
+#define _MXC_SPIB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */
+ __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */
+ __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */
+ __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */
+ __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */
+} mxc_spib_regs_t;
+
+
+/*
+ Register offsets for module SPIB.
+*/
+
+#define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
+#define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL)
+#define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL)
+#define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL)
+#define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL)
+
+
+/*
+ Field positions and masks for module SPIB.
+*/
+
+#define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0
+#define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
+#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2
+#define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
+#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8
+#define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS))
+#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12
+#define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS))
+#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16
+#define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
+#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18
+#define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
+
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2
+#define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
+
+#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0
+#define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
+#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1
+#define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
+#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2
+#define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
+
+#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0
+#define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
+#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1
+#define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
+#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2
+#define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
+
+#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0
+#define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS))
+#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1
+#define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS))
+#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2
+#define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
+#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8
+#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS))
+#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16
+#define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS))
+
+
+
+/*
+ Field values and shifted values for module SPIB.
+*/
+
+#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
+
+#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
+#define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS))
+
+#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
+#define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS))
+
+#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
+#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
+#define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
+
+#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS))
+
+#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
+#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
+#define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
+
+#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
+#define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS))
+
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS))
+
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS))
+
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
+#define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS))
+
+#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
+#define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS))
+
+#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
+#define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS))
+
+#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
+#define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS))
+
+#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
+#define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS))
+
+#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
+#define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS))
+
+#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
+#define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS))
+
+#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL))
+#define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL))
+
+#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
+#define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SPIB_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spim_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,332 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24672 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_SPIM_REGS_H_
+#define _MXC_SPIM_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+
+/**
+ * @ingroup spim
+ * @defgroup spim_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type to access the SPIM Peripheral Module Registers
+ */
+typedef struct {
+ __IO uint32_t mstr_cfg; /**< <tt>\b 0x0000:</tt> SPIM_MSTR_CFG Register - SPI Master Configuration Register */
+ __IO uint32_t ss_sr_polarity; /**< <tt>\b 0x0004:</tt> SPIM_SS_SR_POLARITY Register - SPI Master Polarity Control for SS and SR Signals */
+ __IO uint32_t gen_ctrl; /**< <tt>\b 0x0008:</tt> SPIM_GEN_CTRL Register - SPI Master General Control Register */
+ __IO uint32_t fifo_ctrl; /**< <tt>\b 0x000C:</tt> SPIM_FIFO_CTRL Register - SPI Master FIFO Control Register */
+ __IO uint32_t spcl_ctrl; /**< <tt>\b 0x0010:</tt> SPIM_SPCL_CTRL Register - SPI Master Special Mode Controls */
+ __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> SPIM_INTFL Register - SPI Master Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> SPIM_INTEN Register - SPI Master Interrupt Enable/Disable Settings */
+ __IO uint32_t simple_headers; /**< <tt>\b 0x001C:</tt> SPIM_SIMPLE_HEADERS Register - SPI Master Simple Mode Transaction Headers */
+} mxc_spim_regs_t;
+
+
+/**
+ * @ingroup spim_registers
+ * @defgroup spim_fifos SPIM TX and RX FIFOs
+ * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
+ * @{
+ */
+/**
+ * Structure type for the SPIM Transmit and Receive FIFOs.
+ */
+ typedef struct {
+ union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
+ __IO uint8_t trans_8[2048]; /**< 8-bit access to Transmit FIFO */
+ __IO uint16_t trans_16[1024]; /**< 16-bit access to Transmit FIFO */
+ __IO uint32_t trans_32[512]; /**< 32-bit access to Transmit FIFO */
+ };
+ union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
+ __IO uint8_t rslts_8[2048]; /**< 8-bit access to Receive FIFO */
+ __IO uint16_t rslts_16[1024]; /**< 16-bit access to Receive FIFO */
+ __IO uint32_t rslts_32[512]; /**< 32-bit access to Receive FIFO */
+ };
+} mxc_spim_fifo_regs_t;
+/**@} end of group spim_fifos */
+/**@} end of group spim_registers */
+
+
+/*
+ Register offsets for module SPIM.
+*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_Register_Offsets Register Offsets
+ * @brief SPI Master Register Offsets from the SPIM[n] Base Peripheral Address, where \c n \c = SPIM Instance Number.
+ * @{
+ */
+#define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0000</tt>*/
+#define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0004</tt>*/
+#define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0008</tt>*/
+#define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x000C</tt>*/
+#define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0010</tt>*/
+#define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0014</tt>*/
+#define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0018</tt>*/
+#define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x001C</tt>*/
+/**@} end of group SPIM_Register_Offsets*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_FIFO_Offsets FIFO Offsets
+ * @brief SPI Master FIFO Offsets from the SPIM[n] Base FIFO Address, where \c n \c = SPIM Instance Number.
+ * @{
+ */
+#define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0000</tt>*/
+#define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0800</tt>*/
+/**@} end of group SPIM_FIFO_Offsets*/
+
+/*
+ Field positions and masks for module SPIM.
+*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_MSTR_CFG_Register SPIM_MSTR_CFG
+ * @brief Field Positions and Bit Masks for the SPIM_MSTR_CFG register
+ * @{
+ */
+#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0 /**< SLAVE_SEL Position */
+#define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Mask */
+#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3 /**< THREE_WIRE_MODE Position */
+#define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS)) /**< THREE_WIRE_MODE Mask */
+#define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4 /**< SPI_MODE Position */
+#define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS)) /**< SPI_MODE Mask */
+#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6 /**< PAGE_SIZE Position */
+#define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)) /**< PAGE_SIZE Mask */
+#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8 /**< SCK_HI_CLK Position */
+#define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Mask */
+#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12 /**< SCK_LO_CLK Position */
+#define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Mask */
+#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Position */
+#define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Mask */
+#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Position */
+#define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Mask */
+#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20 /**< SDIO_SAMPLE_POINT Position */
+#define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Mask */
+
+#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL) /**< PAGE_SIZE_4B Field Value */
+#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL) /**< PAGE_SIZE_8B Field Value */
+#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL) /**< PAGE_SIZE_16B Field Value */
+#define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL) /**< PAGE_SIZE_32B Field Value */
+
+#define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_4B Shifted Field Value */
+#define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_8B Shifted Field Value */
+#define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_16B Shifted Field Value */
+#define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_32B Shifted Field Value */
+/**@} end of group SPIM_MSTR_CFG*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_SS_SR_POLARITY_Register SPIM_SS_SR_POLARITY
+ * @brief Field Positions and Bit Masks for the SPIM_SS_SR_POLARITY register
+ * @{
+ */
+#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0 /**< SS_POLARITY Position */
+#define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS)) /**< SS_POLARITY Mask */
+#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8 /**< FC_POLARITY Position */
+#define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS)) /**< FC_POLARITY Mask */
+/**@} end of group SPIM_SS_SR_POLARITY*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_GEN_CTRL_Register SPIM_GEN_CTRL
+ * @brief Field Positions and Bit Masks for the SPIM_GEN_CTRL register
+ * @{
+ */
+#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0 /**< SPI_MSTR_EN Position */
+#define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS)) /**< SPI_MSTR_EN Mask */
+#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
+#define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
+#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
+#define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
+#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3 /**< BIT_BANG_MODE Position */
+#define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS)) /**< BIT_BANG_MODE Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4 /**< BB_SS_IN_OUT Position */
+#define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS)) /**< BB_SS_IN_OUT Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5 /**< BB_SR_IN Position */
+#define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS)) /**< BB_SR_IN Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6 /**< BB_SCK_IN_OUT Position */
+#define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS)) /**< BB_SCK_IN_OUT Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8 /**< BB_SDIO_IN osition */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS)) /**< BB_SDIO_IN Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12 /**< BB_SDIO_OUT Position */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS)) /**< BB_SDIO_OUT Mask */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16 /**< BB_SDIO_DR_EN Position */
+#define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS)) /**< BB_SDIO_DR_EN Mask */
+#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20 /**< SIMPLE_MODE Position */
+#define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)) /**< SIMPLE_MODE Mask */
+#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21 /**< START_RX_ONLY Position */
+#define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS)) /**< START_RX_ONLY Mask */
+#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22 /**< DEASSERT_ACT_SS Position */
+#define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS)) /**< DEASSERT_ACT_SS Mask */
+#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24 /**< ENABLE_SCK_FB_MOD Position */
+#define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< ENABLE_SCK_FB_MOD Mask */
+#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25 /**< INVERT_SCK_FB_CLK Position */
+#define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS)) /**< INVERT_SCK_FB_CLK Mask */
+/**@} end of group SPIM_GEN_CTRL*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_FIFO_CTRL_Register SPIM_FIFO_CTRL
+ * @brief Field Positions and Bit Masks for the SPIM_FIFO_CTRL register
+ * @{
+ */
+#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
+#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
+#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8 /**< TX_FIFO_USED Position */
+#define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
+#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< RX_FIFO_AF_LVL Position */
+#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
+#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24 /**< RX_FIFO_USED Position */
+#define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
+/**@} end of group SPIM_FIFO_CTRL*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_SPCL_CTRL_Register SPIM_SPCL_CTRL
+ * @brief Field Positions and Bit Masks for the SPIM_SPCL_CTRL register
+ * @{
+ */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 /**< SS_SAMPLE_MODE Position */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS)) /**< SS_SAMPLE_MODE Mask */
+#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1 /**< MISO_FC_EN Position */
+#define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS)) /**< MISO_FC_EN Mask */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 /**< SS_SA_SDIO_OUT Position */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) /**< SS_SA_SDIO_OUT Mask */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 /**< SS_SA_SDIO_DR_EN Position */
+#define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) /**< SS_SA_SDIO_DR_EN Mask */
+
+#if (MXC_SPIM_REV == 0)
+#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16 /**< SPECIAL_MODE_3_EN Position */
+#define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS)) /**< SPECIAL_MODE_3_EN Mask */
+#else
+#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12 /**< RX_FIFO_MARGIN Position */
+#define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS)) /**< RX_FIFO_MARGIN Mask */
+#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16 /**< SCK_FB_DELAY Position */
+#define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS)) /**< SCK_FB_DELAY Mask */
+#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20 /**< SPARE_RESERVED Position */
+#define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS)) /**< SPARE_RESERVED Mask */
+#endif
+/**@} end of group SPIM_SPCL_CTRL*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_INTFL_Register SPIM_INTFL
+ * @brief Field Positions and Bit Masks for the SPIM_INTFL register
+ * @{
+ */
+#define MXC_F_SPIM_INTFL_TX_STALLED_POS 0 /**< TX_STALLED Position */
+#define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS)) /**< TX_STALLED Mask */
+#define MXC_F_SPIM_INTFL_RX_STALLED_POS 1 /**< RX_STALLED Position */
+#define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS)) /**< RX_STALLED Mask */
+#define MXC_F_SPIM_INTFL_TX_READY_POS 2 /**< TX_READY Position */
+#define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS)) /**< TX_READY Mask */
+#define MXC_F_SPIM_INTFL_RX_DONE_POS 3 /**< RX_DONE Position */
+#define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS)) /**< RX_DONE Mask */
+#define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
+#define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
+#define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
+#define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
+/**@} end of group SPIM_INTFL*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_INTEN_Register SPIM_INTEN
+ * @brief Field Positions and Bit Masks for the SPIM_INTEN register
+ * @{
+ */
+#define MXC_F_SPIM_INTEN_TX_STALLED_POS 0 /**< TX_STALLED Position */
+#define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS)) /**< TX_STALLED Mask */
+#define MXC_F_SPIM_INTEN_RX_STALLED_POS 1 /**< RX_STALLED Position */
+#define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS)) /**< RX_STALLED Mask */
+#define MXC_F_SPIM_INTEN_TX_READY_POS 2 /**< TX_READY Position */
+#define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS)) /**< TX_READY Mask */
+#define MXC_F_SPIM_INTEN_RX_DONE_POS 3 /**< RX_DONE Position */
+#define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS)) /**< RX_DONE Mask */
+#define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
+#define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
+#define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
+#define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
+/**@} end of group SPIM_INTEN*/
+/**
+ * @ingroup spim_registers
+ * @defgroup SPIM_SIMPLE_HEADERS_Register SPIM_SIMPLE_HEADERS
+ * @brief Field Positions and Bit Masks for the SPIM_SIMPLE_HEADERS register
+ * @{
+ */
+#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0 /**< TX_BIDIR_HEADER Position */
+#define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS)) /**< TX_BIDIR_HEADER Mask */
+#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16 /**< RX_ONLY_HEADER Position */
+#define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS)) /**< RX_ONLY_HEADER Mask */
+/**@} end of group SPIM_SIMPLE_HEADERS*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SPIM_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,224 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
+ * $Revision: 24859 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_SPIS_REGS_H_
+#define _MXC_SPIS_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup spis
+ * @defgroup spis_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
+ * @{
+ */
+
+/**
+ * Structure type to access the SPI Slave Peripheral Module Registers
+ */
+typedef struct {
+ __IO uint32_t gen_ctrl; /**< SPIS_GEN_CTRL Register - SPI Slave General Control Register */
+ __IO uint32_t fifo_ctrl; /**< SPIS_FIFO_CTRL Register - SPI Slave FIFO Control Register */
+ __IO uint32_t fifo_stat; /**< SPIS_FIFO_STAT Register - SPI Slave FIFO Status Register */
+ __IO uint32_t intfl; /**< SPIS_INTFL Register - SPI Slave Interrupt Flags */
+ __IO uint32_t inten; /**< SPIS_INTEN Register - SPI Slave Interrupt Enable/Disable Settings */
+} mxc_spis_regs_t;
+
+
+/**
+ * Structure type for the SPI Slave Transmit and Receive FIFOs.
+ */
+typedef struct {
+ union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
+ __IO uint8_t tx_8[2048]; /**< 8-bit access to Transmit FIFO */
+ __IO uint16_t tx_16[1024]; /**< 16-bit access to Transmit FIFO */
+ __IO uint32_t tx_32[512]; /**< 32-bit access to Transmit FIFO */
+ };
+ union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */
+ __IO uint8_t rx_8[2048]; /**< 8-bit access to Receive FIFO */
+ __IO uint16_t rx_16[1024]; /**< 16-bit access to Receive FIFO */
+ __IO uint32_t rx_32[512]; /**< 32-bit access to Receive FIFO */
+ };
+} mxc_spis_fifo_regs_t;
+/**@} end of group spis_registers */
+
+/*
+ Register offsets for module SPIS.
+*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_Register_Offsets Register Offsets
+ * @brief SPI Slave Register Offsets from the SPIS[n] Base Peripheral Address, where \c n \c = SPIS Instance Number.
+ * @{
+ */
+#define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0000</tt>*/
+#define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0004</tt>*/
+#define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0008</tt>*/
+#define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x000C</tt>*/
+#define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0010</tt>*/
+/**@} end of group SPIS_Register_Offsets*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_FIFO_Offsets FIFO Offsets
+ * @brief SPI Slave FIFO Offsets from the SPIS[n] Base FIFO Address, where \c n \c = SPIS Instance Number.
+ * @{
+ */
+#define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0000</tt> */
+#define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0800</tt> */
+/**@} end of group SPIS_FIFO_Offsets*/
+
+
+/*
+ Field positions and masks for module SPIS.
+*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_GEN_CTRL_Register SPIS_GEN_CTRL
+ * @brief Field Positions and Bit Masks for the SPIS_GEN_CTRL register
+ * @{
+ */
+#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 /**< SPI_SLAVE_EN Position */
+#define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) /**< SPI_SLAVE_EN Mask */
+#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
+#define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
+#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
+#define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
+#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 /**< DATA_WIDTH Position */
+#define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Mask */
+#define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 /**< SPI_MODE Position */
+#define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) /**< SPI_MODE Mask */
+#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 /**< TX_CLK_INVERT Position */
+#define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) /**< TX_CLK_INVERT Mask */
+/**@} end of group SPIS_GEN_CTRL*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_FIFO_CTRL_Register SPIS_FIFO_CTRL
+ * @brief Field Positions and Bit Masks for the SPIS_FIFO_CTRL register
+ * @{
+ */
+#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
+#define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
+#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 /**< RX_FIFO_AF_LVL Position */
+#define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
+/**@} end of group SPIS_FIFO_CTRL_Register*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_FIFO_STAT_Register SPIS_FIFO_STAT
+ * @brief Field Positions and Bit Masks for the SPIS_FIFO_STAT register
+ * @{
+ */
+#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 /**< TX_FIFO_USED Position */
+#define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
+#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 /**< RX_FIFO_USED Position */
+#define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
+/**@} end of group SPIS_FIFO_STAT_Register*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_INTFL_Register SPIS_INTFL
+ * @brief Field Positions and Bit Masks for the SPIS_INTFL register
+ * @{
+ */
+#define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
+#define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
+#define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
+#define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
+#define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
+#define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
+#define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
+#define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
+#define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
+#define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
+#define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
+#define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
+#define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
+#define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
+/**@} end of group SPIS_INTFL_Register*/
+/**
+ * @ingroup spis_registers
+ * @defgroup SPIS_INTEN_Register SPIS_INTEN
+ * @brief Field Positions and Bit Masks for the SPIS_INTEN register
+ * @{
+ */
+#define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
+#define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
+#define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
+#define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
+#define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
+#define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
+#define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
+#define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
+#define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
+#define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
+#define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
+#define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
+#define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
+#define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
+/**@} end of group SPIS_INTEN_Register*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SPIS_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/spix_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,309 @@
+/**
+ * @file
+ * @brief Registers, Fields, Field Positions, Masks and Values for the SPIX Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:45:43 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24673 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_SPIX_REGS_H_
+#define _MXC_SPIX_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup spix
+ * @defgroup spix_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the SPIX Peripheral Module.
+ */
+
+/**
+ * @ingroup spix_registers
+ * Structure type to access the SPIX Registers.
+ */
+ typedef struct {
+ __IO uint32_t master_cfg; /**< SPIX_MASTER_CFG Register. */
+ __IO uint32_t fetch_ctrl; /**< SPIX_FETCH_CTRL Register. */
+ __IO uint32_t mode_ctrl; /**< SPIX_MODE_CTRL Register. */
+ __IO uint32_t mode_data; /**< SPIX_MODE_DATA Register. */
+ __IO uint32_t sck_fb_ctrl; /**< SPIX_SCK_FB_CTRL Register. */
+} mxc_spix_regs_t;
+
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_Register_Offsets Register Offsets
+ * @brief SPIX Peripheral Register Offsets from the SPIX Base Peripheral Address, #MXC_BASE_SPIX.
+ * @{
+ */
+#define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x000</tt> */
+#define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x004</tt> */
+#define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x008</tt> */
+#define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x00C</tt> */
+#define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x010</tt> */
+/**@} end of SPIX_Register_Offsets */
+
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_Master_Cfg_Register SPIX_MASTER_CFG Register Fields
+ * @brief Register Fields and Shifted Field Masks for the SPIX_MASTER_CFG Register.
+ * @{
+ */
+#define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 /**< SPI_MODE Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SPI_MODE Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 /**< SS_ACT_LO Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< SS_ACT_LO Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 /**< ALT_TIMING_EN Field Position */
+#define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< ALT_TIMING_EN Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 /**< SLAVE_SEL Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8 /**< SCK_LO_CLK Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12 /**< SCK_HI_CLK Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Field Position */
+#define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Field Position */
+#define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20 /**< ALT_SCK_LO_CLK Field Position */
+#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) /**< ALT_SCK_LO_CLK Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24 /**< ALT_SCK_HI_CLK Field Position */
+#define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) /**< ALT_SCK_HI_CLK Shifted Field Mask */
+#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28 /**< SDIO_SAMPLE_POINT Field Position */
+#define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Shifted Field Mask */
+/**@}*/
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_Fetch_Ctrl_Register SPIX_FETCH_CTRL Register Fields
+ * @brief Register Fields and Shifted Masks for the SPIX_FETCH_CTRL Register.
+ * @{
+ */
+#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 /**< CMD_VALUE Field Position */
+#define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) /**< CMD_VALUE Shifted Field Mask */
+#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 /**< CMD_WIDTH Field Position */
+#define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< CMD_WIDTH Shifted Field Mask */
+#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< ADDR_WIDTH Field Position */
+#define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< ADDR_WIDTH Shifted Field Mask */
+#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 /**< DATA_WIDTH Field Position */
+#define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Shifted Field Mask */
+#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FOUR_BYTE_ADDR Field Position */
+#define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FOUR_BYTE_ADDRField Mask */
+/**@}*/
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_Mode_Ctrl_Register SPIX_MODE_CTRL Register Fields
+ * @brief Register Fields and Shifted Masks for the SPIX_MODE_CTRL Register.
+ * @{
+ */
+#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 /**< MODE_CLOCKS Field Position */
+#define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) /**< MODE_CLOCKS Shifted Field Mask */
+#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 /**< NO_CMD_MODE Field Position */
+#define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) /**< NO_CMD_MODE Shifted Field Mask */
+/**@}*/
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_Mode_Data_Register SPIX_MODE_DATA Register Fields
+ * @brief Register Fields and Shifted Masks for the SPIX_MODE_DATA Register.
+ * @{
+ */
+#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 /**< MODE_DATA_BITS Field Position */
+#define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) /**< MODE_DATA_BITS Shifted Field Mask */
+#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 /**< MODE_DATA_OE Field Position */
+#define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) /**< MODE_DATA_OE Shifted Field Mask */
+/**@}*/
+/**
+ * @ingroup spix_registers
+ * @defgroup SPIX_SCK_Fb_Ctrl_Register SPIX_SCK_FB_CTRL Register Fields
+ * @brief Register Fields and Shifted Masks for the SPIX_SCK_FB_CTRL Register.
+ * @{
+ */
+#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0 /**< Field Position */
+#define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< Field Mask */
+#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1 /**< Field Position */
+#define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS)) /**< Field Mask */
+
+#if(MXC_SPIX_REV == 0)
+#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4 /**< Field Position */
+#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)) /**< Field Mask */
+#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 /**< Field Position */
+#define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) /**< Field Mask */
+#endif
+/**@}*/
+
+
+/**
+ * @ingroup SPIX_Master_Cfg_Register
+ * @defgroup SPIX_Master_Cfg_SCK SCK Sampling Mode Field
+ * @brief Field values and shifted field values for setting the SPIX SCK Sampling Mode.
+ * @{
+ */
+#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) /**< Field value for setting the sampling of the SCK on the rising edge. */
+#define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) /**< Field value for setting the sampling of the SCK on the falling edge. */
+
+#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on rising edge Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on falling edge Field Shifted Value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Master_Cfg_Register
+ * @defgroup SPIX_Master_Cfg_SS Slave Select Polarity Field
+ * @brief Field values and shifted field values for setting the SPIX Slave Select Active High/Low Field.
+ * @{
+ */
+#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) /**< Slave Select Active High Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) /**< Slave Select Active Low Field selection value. */
+
+#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active High Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active Low Field Shifted Value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Master_Cfg_Register
+ * @defgroup SPIX_Master_Cfg_Alt Alternate Timing
+ * @brief Field values and shifted field values for setting the SPIX Alternate Timing Field.
+ * @{
+ */
+#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) /**< Alternate Timing Disabled (Default) Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) /**< Alternate Timing Enabled As Needed Field selection value. */
+
+#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Disabled Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Enabled As Needed Field Shifted Value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Master_Cfg_Register
+ * @defgroup SPIX_Master_Cfg_Act Active Delay Settings
+ * @brief Field values and shifted field values for setting the SPIX Activity Delay, the number of SPIX clocks between slave selection assert and active SPI clocking.
+ * @{
+ */
+#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Activity Delay Off Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
+
+#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< Activity Delay Off Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Master_Cfg_Register
+ * @defgroup SPIX_Master_Cfg_Inact Inactive Delay Settings
+ * @brief Field values and shifted field values for setting the SPIX Inactivity Delay, the number of SPIX clocks between the active SPI Clock and the Slave Select Deassertion.
+ * @{
+ */
+#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Inactivity Delay Off Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
+#define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
+
+#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< Inactivity Delay Off Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
+#define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Fetch_Ctrl_Register
+ * @defgroup SPIX_Fetch_ctrl_cmd_width Address Width Values and Shifted Values
+ * @brief Field values and shifted field values for selecting the SPIX Command Fetch Width
+ * @{
+ */
+#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 command width field value. */
+#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual command field value. */
+#define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad command field value. */
+
+#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x1 command width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x2 Dual command width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x4 Quad command width fetch shifted value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Fetch_Ctrl_Register
+ * @defgroup SPIX_Fetch_ctrl_addr_width Address Width Values and Shifted Values
+ * @brief Field values and shifted field values for selecting the SPIX Address Fetch Width
+ * @{
+ */
+#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 addr width field value. */
+#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual addr field value. */
+#define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad addr field value. */
+
+#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x1 addr width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x2 Dual addr width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x4 Quad addr width fetch shifted value. */
+/**@}*/
+/**
+ * @ingroup SPIX_Fetch_Ctrl_Register
+ * @defgroup SPIX_Fetch_ctrl_data_width Data Width Values and Shifted Values
+ * @brief Field values and shifted field values for selecting the SPIX Data Fetch Width
+ * @{
+ */
+#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< Value to select x1 data width fetch for SPIX Field selection value. */
+#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< Value to select x2 Dual Mode data width fetch for SPIX Field selection value. */
+#define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< Value to select x4 Quad Mode data width fetch for SPIX Field selection value. */
+
+#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x1 data width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x2 Dual data width fetch shifted value. */
+#define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x4 Quad data width fetch shifted value. */
+/**@}*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SPIX_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/sysman_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_SYSMAN_REGS_H_
+#define _MXC_SYSMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t pvt_monitor; /* 0x0000 System Clock Configuration */
+} mxc_sysman_regs_t;
+
+
+/*
+ Register offsets for module SYSMAN.
+*/
+
+#define MXC_R_SYSMAN_OFFS_PVT_MONITOR ((uint32_t)0x00000000UL)
+
+
+/*
+ Field positions and masks for module SYSMAN.
+*/
+
+#define MXC_F_SYSMAN_PVT_MONITOR_CODE_POS 0
+#define MXC_F_SYSMAN_PVT_MONITOR_CODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_SYSMAN_PVT_MONITOR_CODE_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SYSMAN_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,275 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-06-09 07:43:41 -0500 (Thu, 09 Jun 2016) $
+ * $Revision: 23255 $
+ *
+ ******************************************************************************/
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "max3263x.h"
+#include "clkman_regs.h"
+#include "adc_regs.h"
+#include "pwrseq_regs.h"
+#include "pwrman_regs.h"
+#include "icc_regs.h"
+#include "flc_regs.h"
+#include "rtc_regs.h"
+#include "trim_regs.h"
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000
+#endif
+
+#ifndef LP0_POST_HOOK
+#define LP0_POST_HOOK
+#endif
+
+// NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
+// be AFTER SystemInit() runs. This is required so the hal drivers will have
+// the correct value when the DATA sections are initialized.
+uint32_t SystemCoreClock = RO_FREQ;
+
+void SystemCoreClockUpdate(void)
+{
+#ifdef EMULATOR
+ SystemCoreClock = RO_FREQ;
+#else /* real hardware */
+ if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
+ /* 4 MHz source */
+ if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
+ SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
+ } else {
+ SystemCoreClock = 4000000;
+ }
+ } else {
+ /* 96 MHz source */
+ if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
+ SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
+ MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
+ } else {
+ SystemCoreClock = RO_FREQ;
+ }
+ }
+#endif
+}
+
+void CLKMAN_TrimRO(void)
+{
+ uint32_t running;
+ uint32_t trim;
+
+ /* Step 1: enable 32KHz RTC */
+ running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+
+ /* Wait for RTC warm-up */
+ while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
+
+ /* Step 2: enable RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 3: clear RO calibration complete interrupt */
+ MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
+
+ /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
+
+ /* Step 5: write initial trim to frequency calibration initial condition register */
+ trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
+ MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
+ ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
+
+ /* Step 6: load initial trim to active frequency trim register */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
+
+ /* Step 7: enable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+
+ /* Step 8: run frequency calibration in atomic mode */
+ MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
+
+ /* Step 9: waiting for ro_cal_done flag */
+ while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
+
+ /* Step 10: stop frequency calibration */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
+
+ /* Step 11: disable RO calibration complete interrupt */
+ MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
+
+ /* Step 12: read final frequency trim value */
+ trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
+
+ /* Step 13: write final trim to RO flash trim shadow register */
+ MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
+ ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
+
+ /* Step 14: restore RTC status */
+ if (!running) {
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+ }
+
+ /* Step 15: disable frequency loop to control RO trim */
+ MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
+}
+
+static void ICC_Enable(void)
+{
+ /* Invalidate cache and wait until ready */
+ MXC_ICC->invdt_all = 1;
+ while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+
+ /* Enable cache */
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* Must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+}
+
+/* This function is called before C runtime initialization and can be
+ * implemented by the application for early initializations. If a value other
+ * than '0' is returned, the C runtime initialization will be skipped.
+ *
+ * You may over-ride this function in your program by defining a custom
+ * PreInit(), but care should be taken to reproduce the initialization steps
+ * or a non-functional system may result.
+ */
+__weak int PreInit(void)
+{
+ /* Increase system clock to 96 MHz */
+ MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP0_POST_HOOK;
+
+ /* Enable cache here to reduce boot time */
+ ICC_Enable();
+
+ return 0;
+}
+
+/* Override this function for early platform initialization
+*/
+__weak void low_level_init(void) {}
+
+/* This function is called just before control is transferred to main().
+ */
+void SystemInit(void)
+{
+ /* Copy trim information from shadow registers into power manager registers */
+ /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
+ if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
+ (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
+ (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
+ MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
+ MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
+ } else {
+ /* No valid info block, use some reasonable defaults */
+ MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
+ MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
+ }
+
+ /* Improve flash access timing */
+ MXC_FLC->perform |= (MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS |
+ MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
+ MXC_F_FLC_PERFORM_AUTO_TACC |
+ MXC_F_FLC_PERFORM_AUTO_CLKDIV);
+
+ /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
+ MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
+ MXC_F_RTC_CTRL_AGGRESSIVE_RST);
+
+ /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
+ MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
+ MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
+ MXC_PWRSEQ->rtc_ctrl2 &= ~MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD;
+
+ /* Clear the GPIO WUD event if not waking up from LP0 */
+ /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
+ if ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) ||
+ !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
+ /* Clear GPIO WUD event and configuration registers, globally */
+ MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ } else {
+ /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
+ MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
+ /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
+ MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
+ }
+
+ /* Turn on retention regulator */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
+ MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
+
+ /* Adjust settings in the retention controller for fastest wake-up time */
+ MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
+ MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
+ MXC_PWRSEQ->retn_ctrl0 &= ~MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK;
+
+
+ /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
+ /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
+ MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
+ (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
+
+ /* Improve wake-up time by changing ROSEL to 140ns */
+ MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
+ (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
+ (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
+ MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
+
+ /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+ /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
+ MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
+
+#if (__FPU_PRESENT == 1)
+ /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
+ /* Grant full access, per "Table B3-24 CPACR bit assignments". */
+ /* DDI0403D "ARMv7-M Architecture Reference Manual" */
+ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+ __DSB();
+ __ISB();
+#endif
+
+ /* Early platform initialization */
+ low_level_init();
+
+ /* Perform an initial trim of the internal ring oscillator */
+ CLKMAN_TrimRO();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/system_max3263x.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,96 @@
+/**
+ * @file
+ * @brief MAX3263X System Clock Configuration and System Initialization.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
+ * $Revision: 24859 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/* Define to prevent redundant inclusion */
+#ifndef _SYSTEM_MAX3263X_H_
+#define _SYSTEM_MAX3263X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @ingroup max3263x
+ * @brief MAX3263X System File for CMSIS
+ * @{
+ */
+
+/* ****************************************************************************
+ Define clocks
+ *************************************************************************** */
+#ifndef HFXIN_FREQ
+/**
+ * @internal External HFXIN frequency.
+ */
+#define HFXIN_FREQ 8000000
+#endif
+
+#ifndef RO_FREQ
+#define RO_FREQ 96000000 /**< High Frequency Internal Relaxation Oscillator used as the default System Clock Source */
+#endif
+
+extern uint32_t SystemCoreClock; /*!< CMSIS System Clock Frequency (Core Clock) */
+
+/**
+ * Initializes the system.
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and set up the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable.
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from the device hardware.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_MAX3263X_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/tmr_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,307 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the Timer Peripheral
+ * Module.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24675 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_TMR_REGS_H_
+#define _MXC_TMR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup tmr
+ * @defgroup tmr_registers Timer Registers
+ * @brief Hardware interface definitions for the Timer Peripheral.
+ * @details Definitions for the Hardware Access Layer of the Timer
+ * Peripherals. Includes:
+ * - Registers
+ * - Fields
+ * - Positions
+ * - Values
+ * - Masks
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Structure type to access the Timer Registers, see #MXC_TMR_GET_TMR(i) to get a pointer to the Timer[i] register structure.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000</tt> - TMR_CTRL Register - Timer Control Register */
+ __IO uint32_t count32; /**< <tt>\b 0x0004</tt> - TMR_COUNT32 Register - Timer [32 bit] Current Count Value */
+ __IO uint32_t term_cnt32; /**< <tt>\b 0x0008</tt> - TMR_TERM_CNT32 Register - Timer [32 bit] Terminal Count Setting */
+ __IO uint32_t pwm_cap32; /**< <tt>\b 0x000C</tt> - TMR_PWM_CAP32 Register - Timer [32 bit] PWM Compare Setting or Capture/Measure Value */
+ __IO uint32_t count16_0; /**< <tt>\b 0x0010</tt> - TMR_COUNT16_0 Register - Timer [16 bit] Current Count Value, 16-bit Timer 0 */
+ __IO uint32_t term_cnt16_0; /**< <tt>\b 0x0014</tt> - TMR_TERM_CNT16_0 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 0 */
+ __IO uint32_t count16_1; /**< <tt>\b 0x0018</tt> - TMR_COUNT16_1 Register - Timer [16 bit] Current Count Value, 16-bit Timer 1 */
+ __IO uint32_t term_cnt16_1; /**< <tt>\b 0x001C</tt> - TMR_TERM_CNT16_1 Register - Timer [16 bit] Terminal Count Setting, 16-bit Timer 1 */
+ __IO uint32_t intfl; /**< <tt>\b 0x0020</tt> - TMR_INTFL Register - Timer Interrupt Flags */
+ __IO uint32_t inten; /**< <tt>\b 0x0024</tt> - TMR_INTEN Register - Timer Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+/**@} end of group tmr_registers. */
+
+
+/*
+ Register offsets for module TMR.
+*/
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_Register_Offsets Register Offsets
+ * @brief Timer Register Offsets from the Timer[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_TMR_INSTANCES for the \MXIM_Device. Use #MXC_TMR_GET_BASE(i) to get the base address for a specific timer number.
+ * @{
+ */
+#define MXC_R_TMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from TMR[n] Base Address: TMR_CTRL : <tt>\b 0x0x0000 </tt> */
+#define MXC_R_TMR_OFFS_COUNT32 ((uint32_t)0x00000004UL) /**< Offset from TMR[n] Base Address: TMR_COUNT32 : <tt>\b 0x0x0004 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT32 ((uint32_t)0x00000008UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT32 : <tt>\b 0x0x0008 </tt> */
+#define MXC_R_TMR_OFFS_PWM_CAP32 ((uint32_t)0x0000000CUL) /**< Offset from TMR[n] Base Address: TMR_PWM_CAP32 : <tt>\b 0x0x000C </tt> */
+#define MXC_R_TMR_OFFS_COUNT16_0 ((uint32_t)0x00000010UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_0 : <tt>\b 0x0x0010 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT16_0 ((uint32_t)0x00000014UL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_0 : <tt>\b 0x0x0014 </tt> */
+#define MXC_R_TMR_OFFS_COUNT16_1 ((uint32_t)0x00000018UL) /**< Offset from TMR[n] Base Address: TMR_COUNT16_1 : <tt>\b 0x0x0018 </tt> */
+#define MXC_R_TMR_OFFS_TERM_CNT16_1 ((uint32_t)0x0000001CUL) /**< Offset from TMR[n] Base Address: TMR_TERM_CNT16_1 : <tt>\b 0x0x001C </tt> */
+#define MXC_R_TMR_OFFS_INTFL ((uint32_t)0x00000020UL) /**< Offset from TMR[n] Base Address: TMR_INTFL : <tt>\b 0x0x0020 </tt> */
+#define MXC_R_TMR_OFFS_INTEN ((uint32_t)0x00000024UL) /**< Offset from TMR[n] Base Address: TMR_INTEN : <tt>\b 0x0x0024 </tt> */
+/**@} end of group TMR_Register_Offsets */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_CTRL_Register TMR_CTRL Register
+ * @brief Field Positions and Bit Masks for the TMR_CTRL register
+ * @{
+ */
+#define MXC_F_TMR_CTRL_MODE_POS 0 /**< MODE Field Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
+#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS)) /**< MODE Field Shifted Position for 32-bit timer if TMR2X16 Field is 0 (Default) */
+#define MXC_F_TMR_CTRL_TMR2X16_POS 3 /**< TMR2X16 Field Position */
+#define MXC_F_TMR_CTRL_TMR2X16 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS)) /**< TMR2X16 Field Shifted Position */
+#define MXC_F_TMR_CTRL_PRESCALE_POS 4 /**< PRESCALE Field Position */
+#define MXC_F_TMR_CTRL_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< PRESCALE Field Shifted Position */
+#define MXC_F_TMR_CTRL_POLARITY_POS 8 /**< POLARITY Field Position */
+#define MXC_F_TMR_CTRL_POLARITY ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS)) /**< POLARITY Field Shifted Position */
+#define MXC_F_TMR_CTRL_ENABLE0_POS 12 /**< ENABLE0 Field Position */
+#define MXC_F_TMR_CTRL_ENABLE0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS)) /**< ENABLE0 Field Shifted Position */
+#define MXC_F_TMR_CTRL_ENABLE1_POS 13 /**< ENABLE1 Field Position */
+#define MXC_F_TMR_CTRL_ENABLE1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS)) /**< ENABLE1 Field Shifted Position */
+/**@} end of group TMR_CTRL */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_COUNT16_0_Register TMR_COUNT16_0 Register
+ * @brief Field Positions and Bit Masks for the TMR_COUNT16_0 register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
+ * @{
+ */
+#define MXC_F_TMR_COUNT16_0_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_COUNT16_0_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_COUNT16_0 */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_TERM_CNT16_0_Register TMR_TERM_CNT16_0 Register
+ * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_0 register. This field indicates the termination count value for the <b> 16-bit Timer 0 </b> instance if the Timer is set to 2 16-bit Timers.
+ * @{
+ */
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 0 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_TERM_CNT16_0 */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_COUNT16_1__Register _TMR_COUNT16_1_ Register
+ * @brief Field Positions and Bit Masks for the _TMR_COUNT16_1_ register. This field indicates the current count value of the <b> 16-bit Timer 0 </b> instance.
+ * @{
+ */
+#define MXC_F_TMR_COUNT16_1_VALUE_POS 0 /**< VALUE Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_COUNT16_1_VALUE ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS)) /**< VALUE Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_COUNT16_1 */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_TERM_CNT16_1_Register TMR_TERM_CNT16_1 Register
+ * @brief Field Positions and Bit Masks for the TMR_TERM_CNT16_1 register. This field indicates the termination count value for the <b> 16-bit Timer 1 </b> instance if the Timer is set to 2 16-bit Timers.
+ * @{
+ */
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS 0 /**< TERM_COUNT Field Position for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS)) /**< TERM_COUNT Field Mask for the 16-bit timer 1 when the Timer is set to 2 16-bit timers, TMR2X16 is 1. */
+/**@} end of group TMR_TERM_CNT16_1 */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_INTFL_Register TMR_INTFL Register
+ * @brief Field Positions and Bit Masks for the TMR_INTFL register. This register includes the interrupt flags for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
+ * @{
+ */
+#define MXC_F_TMR_INTFL_TIMER0_POS 0 /**< TIMER0 Interrupt Flag Field Position */
+#define MXC_F_TMR_INTFL_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS)) /**< TIMER0 Interrupt Flag Shifted Field */
+#define MXC_F_TMR_INTFL_TIMER1_POS 1 /**< TIMER1 Interrupt Flag Field Position */
+#define MXC_F_TMR_INTFL_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS)) /**< TIMER1 Interrupt Flag Shifted Field */
+/**@} end of group TMR_INTFL */
+
+/**
+ * @ingroup tmr_registers
+ * @defgroup TMR_INTEN_Register TMR_INTEN Register
+ * @brief Field Positions and Bit Masks for the TMR_INTEN register. This register includes the interrupt enable bits for both <b> 16-bit Timer 0 and 16-bit Timer 1</b>.
+ * @{
+ */
+#define MXC_F_TMR_INTEN_TIMER0_POS 0 /**< TIMER0 Interrupt Enable Field Position */
+#define MXC_F_TMR_INTEN_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS)) /**< TIMER0 Interrupt Enable Shifted Field */
+#define MXC_F_TMR_INTEN_TIMER1_POS 1 /**< TIMER1 Interrupt Enable Field Position */
+#define MXC_F_TMR_INTEN_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS)) /**< TIMER1 Interrupt Enable Shifted Field */
+/**@} end of group TMR_INTEN */
+
+
+
+/*
+ Field values and shifted values for module TMR.
+*/
+/**
+ * @ingroup TMR_CTRL_Register
+ * @defgroup TMR_CTRL_field_values TMR_CTRL Field and Shifted Field Values
+ * @brief Field values and Shifted Field values for the TMR_CTRL register. Shifted field values are field values shifted to the loacation of the field in the register.
+ */
+/**
+ * @ingroup TMR_CTRL_field_values
+ * @defgroup TMR_CTRL_MODE_Field Mode Field for 32-bit Timer Operation.
+ * @brief This field is used to select the timer mode for a 32-bit timer.
+ * @details The mode field is used to set the 32-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
+ * @note If the 32-bit timer is set to operate as 2 16-bit timers, see @ref TMR_CTRL_MODE_16_Field.
+ * @{
+ */
+#define MXC_V_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(0x00000000UL)) /**< Field value to set a 32-bit Timer to 1-Shot Timer mode. */
+#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(0x00000001UL)) /**< Field value to set a 32-bit Timer to continuous mode. */
+#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)(0x00000002UL)) /**< Field value to set a 32-bit Timer to counter mode. */
+#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)(0x00000003UL)) /**< Field value to set a 32-bit Timer to pulse-width mode. */
+#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)(0x00000004UL)) /**< Field value to set a 32-bit Timer to capture mode. */
+#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)(0x00000005UL)) /**< Field value to set a 32-bit Timer to compare mode. */
+#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)(0x00000006UL)) /**< Field value to set a 32-bit Timer to gated mode. */
+#define MXC_V_TMR_CTRL_MODE_MEASURE ((uint32_t)(0x00000007UL)) /**< Field value to set a 32-bit Timer to measurement mode. */
+
+#define MXC_S_TMR_CTRL_MODE_ONE_SHOT ((uint32_t)(MXC_V_TMR_CTRL_MODE_ONE_SHOT << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to 1-Shot Timer mode. */
+#define MXC_S_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)(MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to continuous mode. */
+#define MXC_S_TMR_CTRL_MODE_COUNTER ((uint32_t)(MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to counter mode. */
+#define MXC_S_TMR_CTRL_MODE_PWM ((uint32_t)(MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to pulse-width mode. */
+#define MXC_S_TMR_CTRL_MODE_CAPTURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to capture mode. */
+#define MXC_S_TMR_CTRL_MODE_COMPARE ((uint32_t)(MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to compare mode. */
+#define MXC_S_TMR_CTRL_MODE_GATED ((uint32_t)(MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to gated mode. */
+#define MXC_S_TMR_CTRL_MODE_MEASURE ((uint32_t)(MXC_V_TMR_CTRL_MODE_MEASURE << MXC_F_TMR_CTRL_MODE_POS)) /**< Shifted Field value to set a 32-bit Timer to measurement mode. */
+/**@} end of group TMR_CTRL_MODE_Field */
+/**
+ * @ingroup TMR_CTRL_field_values
+ * @defgroup TMR_CTRL_MODE_16_Field 16-bit Timer Mode Field and Shifted Field Values.
+ * @brief This field is used to select the timer mode when the timer is set to a dual 16-bit timer. The mode field is used to set the 16-bit timer instance to one of the supported modes, e.g. 1-Shot, Continuous, etc.
+ * @{
+ */
+#define MXC_F_TMR_CTRL_MODE_16_0_POS 0
+#define MXC_F_TMR_CTRL_MODE_16_0 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_0_POS))
+
+#define MXC_F_TMR_CTRL_MODE_16_1_POS 1
+#define MXC_F_TMR_CTRL_MODE_16_1 ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_MODE_16_1_POS))
+/**@} end of group TMR_CTRL_MODE_16_Field */
+
+/**
+ * @ingroup TMR_CTRL_field_values
+ * @defgroup TMR_CTRL_PRESCALE_Field Prescale Divide Selection Field and Shifted Field Values.
+ * @brief Timer Clock Prescaler divide values and shifted values. The Prescale Divide field is used to scale the timer instance peripheral clock by the specified value.
+ * @{
+ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(0x00000000UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(0x00000001UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(0x00000002UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(0x00000003UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(0x00000004UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16\f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(0x00000005UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(0x00000006UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(0x00000007UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(0x00000008UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(0x00000009UL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(0x0000000AUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(0x0000000BUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
+#define MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(0x0000000CUL)) /**< Field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
+
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0}= 1 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1}= 2 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2}= 4 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_8 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3}= 8 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_16 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4}= 16 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_32 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5}= 32 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_64 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6}= 64 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_128 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7}= 128 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_256 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8}= 256 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_512 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9}= 512 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
+#define MXC_S_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 ((uint32_t)(MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096 << MXC_F_TMR_CTRL_PRESCALE_POS)) /**< Shifted field value to divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
+/**@} end of group TMR_CTRL_PRESCALE_Field */
+
+
+/*
+ * These two 1-bit fields replace the standard 3-bit mode field when the associated TMR module
+ * is in dual 16-bit timer mode.
+ */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TMR_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/tpu_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_TPU_REGS_H_
+#define _MXC_TPU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __RO uint32_t rsv000[4]; /* 0x0000-0x000C */
+ __IO uint32_t sks0; /* 0x0010 TPU Secure Key Storage Register 0 (Cleared on Tamper Detect) */
+ __IO uint32_t sks1; /* 0x0014 TPU Secure Key Storage Register 1 (Cleared on Tamper Detect) */
+ __IO uint32_t sks2; /* 0x0018 TPU Secure Key Storage Register 2 (Cleared on Tamper Detect) */
+ __IO uint32_t sks3; /* 0x001C TPU Secure Key Storage Register 3 (Cleared on Tamper Detect) */
+} mxc_tpu_tsr_regs_t;
+
+
+/*
+ Register offsets for module TPU.
+*/
+
+#define MXC_R_TPU_TSR_OFFS_SKS0 ((uint32_t)0x00000010UL)
+#define MXC_R_TPU_TSR_OFFS_SKS1 ((uint32_t)0x00000014UL)
+#define MXC_R_TPU_TSR_OFFS_SKS2 ((uint32_t)0x00000018UL)
+#define MXC_R_TPU_TSR_OFFS_SKS3 ((uint32_t)0x0000001CUL)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TPU_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/trim_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,131 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-05-02 16:15:59 -0500 (Mon, 02 May 2016) $
+ * $Revision: 22594 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_TRIM_REGS_H_
+#define _MXC_TRIM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __RO uint32_t rsv000[10]; /* 0x0000-0x0024 */
+ __IO uint32_t reg10_mem_size; /* 0x0028 Shadow Trim for Flash and SRAM Memory Size */
+ __IO uint32_t reg11_adc_trim0; /* 0x002C Shadow Trim for ADC R0 */
+ __IO uint32_t reg12_adc_trim1; /* 0x0030 Shadow Trim for ADC R1 */
+ __IO uint32_t for_pwr_reg5; /* 0x0034 Shadow Trim for PWRSEQ Register REG5 */
+ __IO uint32_t for_pwr_reg6; /* 0x0038 Shadow Trim for PWRSEQ Register REG6 */
+ __IO uint32_t for_pwr_reg7; /* 0x003C Shadow Trim for PWRSEQ Register REG7 */
+} mxc_trim_regs_t;
+
+
+/*
+ Register offsets for module TRIM.
+*/
+
+#define MXC_R_TRIM_OFFS_REG10_MEM_SIZE ((uint32_t)0x00000028UL)
+#define MXC_R_TRIM_OFFS_REG11_ADC_TRIM0 ((uint32_t)0x0000002CUL)
+#define MXC_R_TRIM_OFFS_REG12_ADC_TRIM1 ((uint32_t)0x00000030UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG5 ((uint32_t)0x00000034UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG6 ((uint32_t)0x00000038UL)
+#define MXC_R_TRIM_OFFS_FOR_PWR_REG7 ((uint32_t)0x0000003CUL)
+
+
+/*
+ Field positions and masks for module TRIM.
+*/
+
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS 0
+#define MXC_F_TRIM_REG10_MEM_SIZE_SRAM ((uint32_t)(0x00000003UL << MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS))
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS 2
+#define MXC_F_TRIM_REG10_MEM_SIZE_FLASH ((uint32_t)(0x00000007UL << MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS))
+
+#define MXC_V_TRIM_REG10_MEM_SRAM_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE ((uint32_t)(0x00000002UL))
+
+#define MXC_V_TRIM_REG10_MEM_FLASH_FULL_SIZE ((uint32_t)(0x00000000UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE ((uint32_t)(0x00000001UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE ((uint32_t)(0x00000002UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE ((uint32_t)(0x00000003UL))
+#define MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE ((uint32_t)(0x00000004UL))
+
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS 0
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X0R0_POS))
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS 16
+#define MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG11_ADC_TRIM0_ADCTRIM_X1R0_POS))
+
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS 0
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X0R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS 16
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1 ((uint32_t)(0x000003FFUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_X1R1_POS))
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS 28
+#define MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC ((uint32_t)(0x0000000FUL << MXC_F_TRIM_REG12_ADC_TRIM1_ADCTRIM_DC_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/uart_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,270 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-31 17:35:11 -0500 (Mon, 31 Oct 2016) $
+ * $Revision: 24860 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup uart_comm
+ * @defgroup uart_registers UART Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+
+/**
+ * Structure type for the UART peripheral registers allowing direct 32-bit access to each register.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART_CTRL Register - UART Control Register. */
+ __IO uint32_t baud; /**< <tt>\b 0x0004:</tt> UART_BAUD Register - UART Baud Control Register. */
+ __IO uint32_t tx_fifo_ctrl; /**< <tt>\b 0x0008:</tt> UART_TX_FIFO_CTRL Register - UART TX FIFO Control Register. */
+ __IO uint32_t rx_fifo_ctrl; /**< <tt>\b 0x000C:</tt> UART_RX_FIFO_CTRL Register - UART RX FIFO Control Register. */
+ __IO uint32_t md_ctrl; /**< <tt>\b 0x0010:</tt> UART_MD_CTRL Register - UART Multidrop Control Register. */
+ __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> UART_INTFL Register - UART Interrupt Flags. */
+ __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> UART_INTEN Register - UART Interrupt Enable/Disable Control. */
+#if (MXC_UART_REV > 0)
+ __RO uint32_t idle; /**< <tt>\b 0x001C:</tt> UART_IDLE Register - UART Idle Status */
+#endif
+} mxc_uart_regs_t;
+/**@} end of group uart_registers */
+
+/**
+ * @ingroup uart_registers
+ * @defgroup uart_fifos UART TX and RX FIFOs
+ * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
+ * @{
+ */
+/**
+ * Structure type for accessing the UART Transmit and Receive FIFOs.
+ */
+typedef struct {
+ union {
+ __IO uint8_t tx; /**< TX FIFO write point for data to transmit. */
+ __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO. */
+ __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO. */
+ __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO. */
+ };
+ union {
+ __IO uint8_t rx; /**< RX FIFO read point for received data. */
+ __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO. */
+ __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO. */
+ __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO. */
+ };
+} mxc_uart_fifo_regs_t;
+/**@} end of group uart_fifos */
+
+/*
+ Register offsets for module UART.
+*/
+
+#define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
+#define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
+#define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
+
+
+/*
+ Field positions and masks for module UART.
+*/
+
+#define MXC_F_UART_CTRL_UART_EN_POS 0
+#define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
+#define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
+#define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_UART_CTRL_DATA_SIZE_POS 4
+#define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
+#define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
+#define MXC_F_UART_CTRL_PARITY_POS 12
+#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_F_UART_CTRL_CTS_EN_POS 16
+#define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
+#define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
+#define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_EN_POS 18
+#define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
+#define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
+#define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
+#define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
+#define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
+
+#define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
+#define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
+#define MXC_F_UART_BAUD_BAUD_MODE_POS 8
+#define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
+
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
+#define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
+
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
+#define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
+
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
+#define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
+#define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
+#define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
+#define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
+
+/**
+ * @ingroup uart_registers
+ * @defgroup UART_INTFL_Register UART_INTFL
+ * @{
+ */
+#define MXC_F_UART_INTFL_TX_DONE_POS 0
+#define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
+#define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTFL_RX_STALLED_POS 4
+#define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
+/**@} end of group UART_INTFL_Register */
+
+#define MXC_F_UART_INTEN_TX_DONE_POS 0
+#define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
+#define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
+#define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
+#define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
+#define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
+#define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_UART_INTEN_RX_STALLED_POS 4
+#define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
+#define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
+#define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
+#define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
+#define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
+
+#if (MXC_UART_REV > 0)
+#define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
+#define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
+#define MXC_F_UART_IDLE_TX_IDLE_POS 1
+#define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
+#define MXC_F_UART_IDLE_RX_IDLE_POS 2
+#define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
+#endif
+
+/*
+ Field values and shifted values for module UART.
+*/
+
+#define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+#define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
+
+#define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
+#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
+#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
+#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
+
+#define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
+#define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_UART_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/usb_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,299 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
+ * $Revision: 21838 $
+ *
+ ******************************************************************************/
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+
+
+#define MXC_V_USB_EP_DIR_DISABLE ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+
+/* Offset Register Description
+ ============= ============================================================================ */
+typedef struct {
+ __IO uint32_t cn; /* 0x0000 USB Control Register */
+ __RO uint32_t rsv004[127]; /* 0x0004-0x01FC */
+ __IO uint32_t dev_addr; /* 0x0200 USB Device Address Register */
+ __IO uint32_t dev_cn; /* 0x0204 USB Device Control Register */
+ __IO uint32_t dev_intfl; /* 0x0208 USB Device Interrupt */
+ __IO uint32_t dev_inten; /* 0x020C USB Device Interrupt Enable */
+ __RO uint32_t rsv210[4]; /* 0x0210-0x021C */
+ __IO uint32_t ep_base; /* 0x0220 USB Endpoint Descriptor Table Base Address */
+ __IO uint32_t cur_buf; /* 0x0224 USB Current Endpoint Buffer Register */
+ __IO uint32_t in_owner; /* 0x0228 USB IN Endpoint Buffer Owner Register */
+ __IO uint32_t out_owner; /* 0x022C USB OUT Endpoint Buffer Owner Register */
+ __IO uint32_t in_int; /* 0x0230 USB IN Endpoint Buffer Available Interrupt */
+ __IO uint32_t out_int; /* 0x0234 USB OUT Endpoint Data Available Interrupt */
+ __IO uint32_t nak_int; /* 0x0238 USB IN Endpoint NAK Interrupt */
+ __IO uint32_t dma_err_int; /* 0x023C USB DMA Error Interrupt */
+ __IO uint32_t buf_ovr_int; /* 0x0240 USB Buffer Overflow Interrupt */
+ __RO uint32_t rsv244[7]; /* 0x0244-0x025C */
+ __IO uint32_t setup0; /* 0x0260 USB SETUP Packet Bytes 0 to 3 */
+ __IO uint32_t setup1; /* 0x0264 USB SETUP Packet Bytes 4 to 7 */
+ __RO uint32_t rsv268[6]; /* 0x0268-0x027C */
+ __IO uint32_t ep[8]; /* 0x0280-0x029C USB Endpoint[n] Control Register */
+} mxc_usb_regs_t;
+
+
+/*
+ Register offsets for module USB.
+*/
+
+#define MXC_R_USB_OFFS_CN ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0 ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1 ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0 ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1 ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2 ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3 ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4 ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5 ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6 ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7 ((uint32_t)0x0000029CUL)
+
+
+/*
+ Field positions and masks for module USB.
+*/
+
+#define MXC_F_USB_CN_USB_EN_POS 0
+#define MXC_F_USB_CN_USB_EN ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+#define MXC_F_USB_CN_HOST_POS 1
+#define MXC_F_USB_CN_HOST ((uint32_t)(0x00000001UL << MXC_F_USB_CN_HOST_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS 0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS 2
+#define MXC_F_USB_DEV_CN_SIGRWU ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS 3
+#define MXC_F_USB_DEV_CN_CONNECT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS 4
+#define MXC_F_USB_DEV_CN_ULPM ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS 5
+#define MXC_F_USB_DEV_CN_URST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS 6
+#define MXC_F_USB_DEV_CN_VBGATE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_OSCEN_POS 7
+#define MXC_F_USB_DEV_CN_OSCEN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_OSCEN_POS))
+#define MXC_F_USB_DEV_CN_BACT_OE_POS 8
+#define MXC_F_USB_DEV_CN_BACT_OE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_BACT_OE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS 9
+#define MXC_F_USB_DEV_CN_FIFO_MODE ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS 0
+#define MXC_F_USB_DEV_INTFL_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTFL_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS 2
+#define MXC_F_USB_DEV_INTFL_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS 3
+#define MXC_F_USB_DEV_INTFL_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS 4
+#define MXC_F_USB_DEV_INTFL_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS 6
+#define MXC_F_USB_DEV_INTFL_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTFL_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS 8
+#define MXC_F_USB_DEV_INTFL_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTFL_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTFL_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTFL_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS 16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS 0
+#define MXC_F_USB_DEV_INTEN_DPACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS 1
+#define MXC_F_USB_DEV_INTEN_RWU_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS 2
+#define MXC_F_USB_DEV_INTEN_BACT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS 3
+#define MXC_F_USB_DEV_INTEN_BRST ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS 4
+#define MXC_F_USB_DEV_INTEN_SUSP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS 5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS 6
+#define MXC_F_USB_DEV_INTEN_VBUS ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS 7
+#define MXC_F_USB_DEV_INTEN_BRST_DN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS 8
+#define MXC_F_USB_DEV_INTEN_SETUP ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS 9
+#define MXC_F_USB_DEV_INTEN_EP_IN ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS 10
+#define MXC_F_USB_DEV_INTEN_EP_OUT ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS 11
+#define MXC_F_USB_DEV_INTEN_EP_NAK ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS 12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS 13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS 9
+#define MXC_F_USB_EP_BASE_EP_BASE ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS 0
+#define MXC_F_USB_CUR_BUF_OUT_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS 16
+#define MXC_F_USB_CUR_BUF_IN_BUF ((uint32_t)(0x0000FFFFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS 0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS 16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER ((uint32_t)(0x0000FFFFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV_POS 0
+#define MXC_F_USB_IN_INT_INBAV ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_INT_INBAV_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV_POS 0
+#define MXC_F_USB_OUT_INT_OUTDAV ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_INT_OUTDAV_POS))
+
+#define MXC_F_USB_NAK_INT_NAK_POS 0
+#define MXC_F_USB_NAK_INT_NAK ((uint32_t)(0x000000FFUL << MXC_F_USB_NAK_INT_NAK_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS 0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR ((uint32_t)(0x000000FFUL << MXC_F_USB_DMA_ERR_INT_DMA_ERR_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS 0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR ((uint32_t)(0x000000FFUL << MXC_F_USB_BUF_OVR_INT_BUF_OVR_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS 0
+#define MXC_F_USB_SETUP0_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS 8
+#define MXC_F_USB_SETUP0_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS 16
+#define MXC_F_USB_SETUP0_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS 24
+#define MXC_F_USB_SETUP0_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE0_POS 0
+#define MXC_F_USB_SETUP1_BYTE0 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE0_POS))
+#define MXC_F_USB_SETUP1_BYTE1_POS 8
+#define MXC_F_USB_SETUP1_BYTE1 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE1_POS))
+#define MXC_F_USB_SETUP1_BYTE2_POS 16
+#define MXC_F_USB_SETUP1_BYTE2 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE2_POS))
+#define MXC_F_USB_SETUP1_BYTE3_POS 24
+#define MXC_F_USB_SETUP1_BYTE3 ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE3_POS))
+
+#define MXC_F_USB_EP_DIR_POS 0
+#define MXC_F_USB_EP_DIR ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+#define MXC_F_USB_EP_BUF2_POS 3
+#define MXC_F_USB_EP_BUF2 ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INT_EN_POS 4
+#define MXC_F_USB_EP_INT_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INT_EN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS 5
+#define MXC_F_USB_EP_NAK_EN ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS 6
+#define MXC_F_USB_EP_DT ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS 8
+#define MXC_F_USB_EP_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS 9
+#define MXC_F_USB_EP_ST_STALL ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS 10
+#define MXC_F_USB_EP_ST_ACK ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_USB_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt2_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,320 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the WDT2 Peripheral Module.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24678 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_WDT2_REGS_H_
+#define _MXC_WDT2_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup wdt2
+ * @defgroup wdt2_registers WDT2 Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+/**
+ * Structure type to access the WDT2 Registers, see #MXC_WDT2 to get a pointer to the WDT2 register structure.
+ * @note This is an always-on watchdog timer, it operates in all modes of operation.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< WDT2_CTRL Register - WDT Control Register */
+ __IO uint32_t clear; /**< WDT2_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
+ __IO uint32_t flags; /**< WDT2_FLAGS Register - WDT Interrupt and Reset Flags */
+ __IO uint32_t enable; /**< WDT2_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
+ __RO uint32_t rsv010; /**< <em><b>RESERVED, DO NOT MODIFY</b></em>. */
+ __IO uint32_t lock_ctrl; /**< WDT2_LOCK_CTRL Register - Lock for Control Register */
+} mxc_wdt2_regs_t;
+/**@} end of group wdt2_registers.*/
+
+
+/*
+ Register offsets for module WDT2.
+*/
+/**
+ * @ingroup wdt2_registers
+ * @defgroup WDT2_Register_Offsets Register Offsets
+ * @brief Watchdog Timer 2 Register Offsets from the WDT2 Base Peripheral Address.
+ * @details Use #MXC_WDT2 for the WDT2 Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL) /**< WDT2_CTRL Offset: <tt>0x0000</tt> */
+#define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< WDT2_CLEAR Offset: <tt>0x0004</tt> */
+#define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< WDT2_FLAGS Offset: <tt>0x0008</tt> */
+#define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< WDT2_ENABLE Offset: <tt>0x000C</tt> */
+#define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< WDT2_LOCK_CTRL Offset: <tt>0x0014</tt> */
+/**@} end of group WDT2_Register_Offsets */
+
+
+/*
+ Field positions and masks for module WDT2.
+*/
+/**
+ * @ingroup wdt2_registers
+ * @defgroup WDT2_CTRL_Register WDT2_CTRL Register
+ * @brief Field Positions and Bit Masks for the WDT2_CTRL register
+ * @{
+ */
+#define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
+#define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
+#define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
+#define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
+ * interrupt period has expired before the device resets. If the
+ * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
+ * the device will not reset. */
+#define MXC_F_WDT2_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
+#define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
+#define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
+#define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
+#define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10 /**< WAIT_PERIOD Field Position */
+#define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS)) /**< WAIT_PERIOD Field Mask */
+/**@} end of group WDT2_CTRL */
+/**
+ * @ingroup wdt2_registers
+ * @defgroup WDT2_FLAGS_Register WDT2_FLAGS Register
+ * @brief Field Positions and Bit Masks for the WDT2_FLAGS register. Watchdog Timer 2 Flags for Interrupts and Reset.
+ * @{
+ */
+#define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
+#define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer 2 timed out. */
+#define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
+#define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
+/**@} end of group WDT2_FLAGS */
+
+/**
+ * @ingroup wdt2_registers
+ * @defgroup WDT2_ENABLE_Register WDT2_ENABLE Register
+ * @brief Field Positions and Bit Masks for the WDT2_ENABLE register.
+ * @{
+ */
+#define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
+#define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
+#define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
+#define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
+/**@} end of group WDT2_ENABLE */
+
+/**
+ * @ingroup wdt2_registers
+ * @defgroup WDT2_LOCK_CTRL_Register WDT2_LOCK_CTRL Register
+ * @brief The WDT2_LOCK_CTRL register controls read/write access to the \ref WDT2_CTRL_Register.
+ * @{
+ */
+#define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT2_LOCK_CTRL register. */
+#define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT2_LOCK_CTRL register. Reading a value of */
+/**@} end of group WDT2_ENABLE */
+
+
+
+/*
+ Field values and shifted values for module WDT2.
+*/
+/**
+ * @ingroup WDT2_CTRL_Register
+ * @defgroup WDT2_CTRL_field_values WDT2_CTRL Register Field and Shifted Field Values
+ * @brief Field values and Shifted Field values for the WDT2_CTRL register.
+ * @details Shifted field values are field values shifted to the loacation of the field in the register.
+ */
+/**
+ * @ingroup WDT2_CTRL_field_values
+ * @defgroup WDT2_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
+ * @brief Sets the duration of the watchdog interrupt period.
+ * @details The INT_PERIOD field sets the duration of the watchdog interrupt
+ * period, which is the time period from the WDT2 being
+ * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_FLAGS_TIMEOUT, is
+ * set.
+ * The values defined are in the number of watchdog clock cycles.
+ * @{
+ */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{15} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{14} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{13} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{12} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{11} \f$ WDT2 CLK Cycles */
+#define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{10} \f$ WDT2 CLK Cycles */
+/**@} end of group WDT2_CTRL_INT_PERIOD_Value */
+
+/**
+ * @ingroup WDT2_CTRL_field_values
+ * @defgroup WDT2_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
+ * @brief Shifted values for the \ref WDT2_CTRL_INT_PERIOD_Value
+ * @details The shifted value is
+ * shifted to align with the fields location in the WDT2_CTRL register.
+ * @{
+ */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS */
+/**@} end of group WDT2_CTRL_INT_PERIOD_Shifted */
+/**
+ * @ingroup WDT2_CTRL_field_values
+ * @defgroup WDT2_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
+ * @brief Sets the duration of the watchdog reset period.
+ * @details The RST_PERIOD field sets the duration of the watchdog reset
+ * period, which is the time period from the WDT being
+ * enabled/cleared until the WDT2 flag, #MXC_F_WDT2_CTRL_RST_PERIOD is
+ * set.
+ * The values defined are in the number of watchdog clock cycles.
+ * @{
+ */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{21} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{20} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{19} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{18} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{17} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{16} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{15} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{14} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{13} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{12} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{11} \f$ WDT2 CLK CYCLES */
+#define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{10} \f$ WDT2 CLK CYCLES */
+/**@} end of group WDT2_CTRL_RST_PERIOD_Value */
+
+/**
+ * @ingroup WDT2_CTRL_field_values
+ * @defgroup WDT2_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
+ * @brief Shifted values for the \ref WDT2_CTRL_RST_PERIOD_Value
+ * @details These values are shifted to align with the field's location in the WDT2_CTRL register.
+ * @{
+ */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS */
+#define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS */
+/**@} end of group WDT2_CTRL_RST_PERIOD_Shifted */
+/**
+ * @ingroup WDT2_LOCK_CTRL_Register
+ * @defgroup WDT2_LOCK_field_values Watchdog Timer WDT2_LOCK field values
+ * @brief Lock/Unlock values for the watchdog timer \ref WDT2_CTRL_Register.
+ * @{
+ */
+#define MXC_V_WDT2_LOCK_KEY 0x24 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b locks the \ref WDT2_CTRL_Register making it read only. */
+#define MXC_V_WDT2_UNLOCK_KEY 0x42 /**< Writing this value to the WDT2_LOCK field of the \ref WDT2_LOCK_CTRL_Register \b unlocks the \ref WDT2_CTRL_Register making it read/write. */
+/**@} end of group WDT2_LOCK_field_values */
+///@cond
+/**
+ * @internal
+ * @ingroup WDT2_CLEAR_Register
+ * @defgroup WDT2_CLEAR_field_values Watchdog Timer Clear Sequence Values
+ * @brief Writing the sequence of #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 to the \ref WDT2_CLEAR_Register will clear/reset the watchdog timer count.
+ * @note The values #MXC_V_WDT2_RESET_KEY_0, #MXC_V_WDT2_RESET_KEY_1 must be written sequentially to the \ref WDT2_CLEAR_Register to clear the watchdog counter.
+ * @{
+ */
+#define MXC_V_WDT2_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */
+#define MXC_V_WDT2_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT2_CLEAR_Register to perform a WDT2 clear. */
+/**
+ * @} end of group WDT2_CLEAR_field_values
+ * @endinternal
+ */
+///@endcond
+/**@} wdt2_registers*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_WDT2_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/wdt_regs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,380 @@
+/**
+ * @file
+ * @brief Type definitions for the Watchdog Timer Peripheral
+ *
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24677 $
+ *
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_WDT_REGS_H_
+#define _MXC_WDT_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+///@cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __RO
+#define __RO volatile const
+#endif
+///@endcond
+
+/**
+ * @ingroup wdt0
+ * @defgroup wdt_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions
+ * @{
+ */
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ access to each register in module.
+*/
+/**
+ * Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure.
+ * @note For the Always-On Watch Dog Timer, see \ref wdt2.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> WDT_CTRL Register - WDT Control Register */
+ __IO uint32_t clear; /**< <tt>\b 0x0004:</tt> WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */
+ __IO uint32_t flags; /**< <tt>\b 0x0008:</tt> WDT_FLAGS Register - WDT Interrupt and Reset Flags */
+ __IO uint32_t enable; /**< <tt>\b 0x000C:</tt> WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */
+ __RO uint32_t rsv010; /**< <tt>\b 0x0010:</tt> RESERVED, DO NOT MODIFY. */
+ __IO uint32_t lock_ctrl; /**< <tt>\b 0x0014:</tt> WDT_LOCK_CTRL Register - Lock for Control Register */
+} mxc_wdt_regs_t;
+/**@} end of group wdt_registers.*/
+
+/*
+ Register offsets for module WDT.
+*/
+/**
+ * @ingroup wdt_registers
+ * @defgroup WDT_Register_Offsets Register Offsets
+ * @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device.
+ * @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance.
+ * @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver.
+ * @{
+ */
+#define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : <tt>\b 0x0000 </tt> */
+#define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : <tt>\b 0x0004 </tt> */
+#define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : <tt>\b 0x0008 </tt> */
+#define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : <tt>\b 0x000C </tt> */
+#define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : <tt>\b 0x0014 </tt> */
+/**@} end of group WDT_Register_Offsets */
+
+/*
+ Field positions and masks for module WDT.
+*/
+/**
+ * @ingroup wdt_registers
+ * @defgroup WDT_CTRL_Register WDT_CTRL Register
+ * @brief Field Positions and Bit Masks for the WDT_CTRL register
+ * @{
+ */
+#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */
+#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */
+#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */
+#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an
+ * interrupt period has expired before the device resets. If the
+ * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration,
+ * the device will not reset. */
+#define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */
+#define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */
+#define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */
+#define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */
+#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */
+#define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */
+/**@} end of group WDT_CTRL */
+/**
+ * @ingroup wdt_registers
+ * @defgroup WDT_FLAGS_Register WDT_FLAGS Register
+ * @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset.
+ * @{
+ */
+#define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */
+#define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */
+#define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */
+#define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register <b><em> during the pre-window period</em></b>. */
+#define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */
+#define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */
+/**@} end of group WDT_FLAGS */
+
+/**
+ * @ingroup wdt_registers
+ * @defgroup WDT_ENABLE_Register WDT_ENABLE Register
+ * @brief Field Positions and Bit Masks for the WDT_ENABLE register.
+ * @{
+ */
+#define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */
+#define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */
+#define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */
+#define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */
+#define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */
+#define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */
+/**@} end of group WDT_ENABLE */
+
+/**
+ * @ingroup wdt_registers
+ * @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register
+ * @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register.
+ * @{
+ */
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */
+/**@} end of group WDT_ENABLE */
+
+
+
+/*
+ Field values and shifted values for module WDT.
+*/
+/**
+ * @ingroup WDT_CTRL_Register
+ * @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values
+ * @brief Field values and Shifted Field values for the WDT_CTRL register.
+ * @details Shifted field values are field values shifted to the loacation of the field in the register.
+ */
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period
+ * @brief Sets the duration of the watchdog interrupt period.
+ * @details The INT_PERIOD field sets the duration of the watchdog interrupt
+ * period, which is the time period from the WDT being
+ * enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is
+ * set.
+ * The values defined are in the number of watchdog clock cycles.
+ * @{
+ */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */
+#define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */
+/**@} end of group WDT_CTRL_INT_PERIOD_Value */
+
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values
+ * @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value
+ * @details The shifted value is
+ * shifted to align with the fields location in the WDT_CTRL register.
+ * @{
+ */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */
+#define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */
+/**@} end of group WDT_CTRL_INT_PERIOD_Shifted */
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period
+ * @brief Sets the duration of the watchdog reset period.
+ * @details The RST_PERIOD field sets the duration of the watchdog reset
+ * period, which is the time period from the WDT being
+ * enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is
+ * set.
+ * The values defined are in the number of watchdog clock cycles.
+ * @{
+ */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
+/**@} end of group WDT_CTRL_RST_PERIOD_Value */
+
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values
+ * @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value
+ * @details These values are shifted to align with the field's location in the WDT_CTRL register.
+ * @{
+ */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */
+#define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */
+/**@} end of group WDT_CTRL_RST_PERIOD_Shifted */
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period
+ * @brief Sets the duration of the watchdog wait window period.
+ * @details The WAIT_PERIOD field sets the duration of the watchdog pre-window
+ * period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur.
+ * This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting
+ * overclocking or an invalid clock.
+ * The values defined are in the number of watchdog clock cycles.
+ * @{
+ */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */
+#define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */
+/**@} end of group WDT_CTRL_WAIT_PERIOD_Value */
+
+/**
+ * @ingroup WDT_CTRL_field_values
+ * @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values
+ * @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value
+ * @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register.
+ * @{
+ */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */
+#define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */
+/**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */
+
+/**
+ * @ingroup WDT_LOCK_CTRL_Register
+ * @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values
+ * @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register.
+ * @{
+ */
+#define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */
+#define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */
+/**@} end of group WDT_LOCK_field_values */
+///@cond
+/*
+ * @internal
+ * @ingroup WDT_CLEAR_Register
+ * @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values
+ * @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count.
+ * @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter.
+ * @{
+ */
+#define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
+#define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */
+/**
+ * @} end of group WDT_CLEAR_field_values
+ * @endinternal
+ */
+///@endcond
+/**@} wdt_registers*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_WDT_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,128 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "gpio_regs.h"
+#include "clkman_regs.h"
+
+uint32_t gpio_set(PinName name)
+{
+ MBED_ASSERT(name != (PinName)NC);
+ pin_function(name, 0);
+ return 1 << PINNAME_TO_PIN(name);
+}
+
+void gpio_init(gpio_t *obj, PinName name)
+{
+ obj->name = name;
+ if (name == (PinName)NC) {
+ return;
+ }
+
+ unsigned int port = PINNAME_TO_PORT(name);
+ unsigned int pin = PINNAME_TO_PIN(name);
+
+ obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin);
+ obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin);
+ obj->mode = PullDefault;
+
+ /* Ensure that the GPIO clock is enabled */
+ MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER;
+
+ /* Ensure that the GPIO clock is enabled */
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+ obj->mode = mode;
+ pin_mode(obj->name, mode);
+}
+
+void pin_dir_mode(PinName name, PinDirection direction, PinMode mode)
+{
+ MBED_ASSERT(name != (PinName)NC);
+
+ unsigned int port = PINNAME_TO_PORT(name);
+ unsigned int pin = PINNAME_TO_PIN(name);
+
+ /* Set function; Firmware Control (GPIO mode) */
+ MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin));
+
+ /* Normal input is always enabled */
+ MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin));
+
+ uint32_t new_mode;
+ if (direction == PIN_OUTPUT) {
+ // PullUp = not valid,
+ // PullDown = not valid,
+ // OpenDrain = MXC_V_GPIO_OUT_MODE_OD,
+ // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL,
+ if (mode == OpenDrain) {
+ new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN;
+ } else {
+ new_mode = MXC_V_GPIO_OUT_MODE_NORMAL;
+ }
+ } else {
+ // PullUp = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP
+ // PullDown = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN
+ // OpenDrain = MXC_V_GPIO_OUT_MODE_OD
+ // PullNone = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z
+ if (mode == PullUp) {
+ new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP;
+ MXC_GPIO->out_val[port] |= 1 << pin;
+ } else if (mode == PullDown) {
+ new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN;
+ MXC_GPIO->out_val[port] &= ~(1 << pin);
+ } else if (mode == OpenDrain) {
+ new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN;
+ MXC_GPIO->out_val[port] |= 1 << pin;
+ } else {
+ new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z;
+ MXC_GPIO->out_val[port] &= ~(1 << pin);
+ }
+ }
+
+ /* Set new mode */
+ uint32_t out_mode = MXC_GPIO->out_mode[port];
+ out_mode &= ~(0xF << (pin * 4));
+ out_mode |= (new_mode << (pin * 4));
+ MXC_GPIO->out_mode[port] = out_mode;
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+ pin_dir_mode(obj->name, direction, obj->mode);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,183 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+
+static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
+static gpio_irq_handler irq_handler;
+
+static void handle_irq(unsigned int port)
+{
+ uint32_t intfl, in_val;
+ uint32_t mask;
+ unsigned int pin;
+
+ /* Read pin state */
+ in_val = MXC_GPIO->in_val[port];
+
+ /* Read interrupts */
+ intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
+
+ mask = 1;
+
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if (intfl & mask) {
+ MXC_GPIO->intfl[port] = mask; /* clear interrupt */
+ gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
+ gpio_irq_t *obj = objs[port][pin];
+ if (obj && obj->id) {
+ if ((event == IRQ_RISE) && obj->rise_en) {
+ irq_handler(obj->id, IRQ_RISE);
+ } else if ((event == IRQ_FALL) && obj->fall_en) {
+ irq_handler(obj->id, IRQ_FALL);
+ }
+ }
+ }
+ mask <<= 1;
+ }
+}
+
+void gpio_irq_0(void) { handle_irq(0); }
+void gpio_irq_1(void) { handle_irq(1); }
+void gpio_irq_2(void) { handle_irq(2); }
+void gpio_irq_3(void) { handle_irq(3); }
+void gpio_irq_4(void) { handle_irq(4); }
+void gpio_irq_5(void) { handle_irq(5); }
+void gpio_irq_6(void) { handle_irq(6); }
+void gpio_irq_7(void) { handle_irq(7); }
+void gpio_irq_8(void) { handle_irq(8); }
+
+int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
+{
+ if (name == NC) {
+ return -1;
+ }
+
+ uint8_t port = PINNAME_TO_PORT(name);
+ uint8_t pin = PINNAME_TO_PIN(name);
+
+ if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
+ return 1;
+ }
+
+ obj->port = port;
+ obj->pin = pin;
+ obj->id = id;
+ objs[port][pin] = obj;
+
+ /* register handlers */
+ irq_handler = handler;
+ NVIC_SetVector(GPIO_P0_IRQn, gpio_irq_0);
+ NVIC_SetVector(GPIO_P1_IRQn, gpio_irq_1);
+ NVIC_SetVector(GPIO_P2_IRQn, gpio_irq_2);
+ NVIC_SetVector(GPIO_P3_IRQn, gpio_irq_3);
+ NVIC_SetVector(GPIO_P4_IRQn, gpio_irq_4);
+ NVIC_SetVector(GPIO_P5_IRQn, gpio_irq_5);
+ NVIC_SetVector(GPIO_P6_IRQn, gpio_irq_6);
+ NVIC_SetVector(GPIO_P7_IRQn, gpio_irq_7);
+ NVIC_SetVector(GPIO_P8_IRQn, gpio_irq_8);
+
+ /* disable the interrupt locally */
+ MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
+
+ /* clear a pending request */
+ MXC_GPIO->intfl[port] = 1 << pin;
+
+ /* enable the requested interrupt */
+ MXC_GPIO->inten[port] |= (1 << pin);
+ NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+ /* disable interrupt */
+ MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
+ MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
+ objs[obj->port][obj->pin] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+ if (event == IRQ_FALL) {
+ obj->fall_en = enable;
+ } else if (event == IRQ_RISE) {
+ obj->rise_en = enable;
+ }
+
+ if (obj->fall_en && obj->rise_en) {
+ MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
+ } else if (obj->fall_en) {
+ uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
+ int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
+ int_mode |= (MXC_V_GPIO_INT_MODE_FALLING_EDGE << (obj->pin*4));
+ MXC_GPIO->int_mode[obj->port] = int_mode;
+ } else if (obj->rise_en) {
+ uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
+ int_mode &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
+ int_mode |= (MXC_V_GPIO_INT_MODE_RISING_EDGE << (obj->pin*4));
+ MXC_GPIO->int_mode[obj->port] = int_mode;
+ } else {
+ MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
+ }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+ MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+ MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
+}
+
+gpio_irq_t *gpio_irq_get_obj(PinName name)
+{
+ if (name == NC) {
+ return NULL;
+ }
+
+ unsigned int port = PINNAME_TO_PORT(name);
+ unsigned int pin = PINNAME_TO_PIN(name);
+
+ if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
+ return NULL;
+ }
+
+ return objs[port][pin];
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_object.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName name;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PinMode mode;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->name != (PinName)NC);
+ *obj->reg_out = !!value;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->name != (PinName)NC);
+ return *obj->reg_in;
+}
+
+void pin_dir_mode(PinName name, PinDirection direction, PinMode mode);
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->name != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,213 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "i2cm_regs.h"
+#include "i2cm.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+#ifndef MXC_I2CM_RX_TIMEOUT
+#define MXC_I2CM_RX_TIMEOUT 0x5000
+#endif
+
+#define MBED_NAK 0
+#define MBED_ACK 1
+#define MBED_TIMEOUT 2
+
+//******************************************************************************
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+ // SDA and SCL must map to same peripheral instance
+ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+ I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+ mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
+ MBED_ASSERT((int)i2c != NC);
+
+ obj->i2c = i2c;
+ obj->fifo = MXC_I2CM_GET_FIFO(MXC_I2CM_GET_IDX(i2c));
+ obj->start_pending = 0;
+
+ // Merge pin function requests for use with CMSIS init func
+ ioman_req_t io_req;
+ pin_function_t *pin_func;
+ pin_func = (pin_function_t *)pinmap_find_function(sda, PinMap_I2C_SDA);
+ io_req.value = pin_func->req_val;
+ pin_func = (pin_function_t *)pinmap_find_function(scl, PinMap_I2C_SCL);
+ io_req.value |= pin_func->req_val;
+
+ obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req;
+ obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack;
+ obj->sys_cfg.io_cfg.req_val = io_req;
+ obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_1;
+
+ I2CM_Init(obj->i2c, &obj->sys_cfg, I2CM_SPEED_400KHZ);
+}
+
+//******************************************************************************
+void i2c_frequency(i2c_t *obj, int hz)
+{
+ I2CM_Init(obj->i2c, &obj->sys_cfg, hz);
+}
+
+//******************************************************************************
+int i2c_start(i2c_t *obj)
+{
+ obj->start_pending = 1;
+ return 0;
+}
+
+//******************************************************************************
+int i2c_stop(i2c_t *obj)
+{
+ obj->start_pending = 0;
+ I2CM_WriteTxFifo(obj->i2c, obj->fifo, MXC_S_I2CM_TRANS_TAG_STOP);
+ I2CM_TxInProgress(obj->i2c);
+ return 0;
+}
+
+//******************************************************************************
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+ MBED_ASSERT(stop != 0);
+ return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length);
+}
+
+//******************************************************************************
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+ mxc_i2cm_regs_t *i2cm = obj->i2c;
+ mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
+
+ if (stop) {
+ return I2CM_Write(i2cm, address >> 1, NULL, 0, (uint8_t *)data, length);
+ }
+
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+ if (I2CM_Tx(i2cm, fifo, address >> 1, (uint8_t *)data, length, 0) == E_NO_ERROR) {
+ return length;
+ } else {
+ return -1;
+ }
+}
+
+//******************************************************************************
+void i2c_reset(i2c_t *obj)
+{
+ I2CM_Recover(obj->i2c);
+}
+
+//******************************************************************************
+int i2c_byte_read(i2c_t *obj, int last)
+{
+ mxc_i2cm_regs_t *i2cm = obj->i2c;
+ mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
+ int tmp;
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+
+ if (last) {
+ // NACK the last read byte
+ if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) {
+ goto byte_read_err;
+ }
+
+ // Send the stop condition
+ if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) {
+ goto byte_read_err;
+ }
+ } else {
+ if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) {
+ goto byte_read_err;
+ }
+ }
+
+ do {
+ // Wait for data in RX FIFO
+ int timeout = MXC_I2CM_RX_TIMEOUT;
+ while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
+ ((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) {
+
+ if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) {
+ goto byte_read_err;
+ }
+
+ if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) {
+ goto byte_read_err;
+ }
+ }
+ i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
+
+ } while ((tmp = fifo->rx) & MXC_S_I2CM_RSTLS_TAG_EMPTY);
+
+ return (uint8_t)tmp;
+
+byte_read_err:
+ i2c_reset(obj);
+ return -1;
+}
+
+//******************************************************************************
+int i2c_byte_write(i2c_t *obj, int data)
+{
+ mxc_i2cm_regs_t *i2cm = obj->i2c;
+ mxc_i2cm_fifo_regs_t *fifo = obj->fifo;
+ int result;
+
+ if (obj->start_pending) {
+ obj->start_pending = 0;
+ data |= MXC_S_I2CM_TRANS_TAG_START;
+ } else {
+ data |= MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
+ }
+
+ if ((result = I2CM_WriteTxFifo(i2cm, fifo, data)) != E_NO_ERROR) {
+ i2c_reset(obj);
+ if (result == E_COMM_ERR) {
+ return MBED_NAK;
+ }
+ return MBED_TIMEOUT;
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+
+ return MBED_ACK;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,180 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the Analog to
+ * Digital Converter (ADC) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 12:50:50 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24349 $
+ *
+ *************************************************************************** */
+
+/**
+ * @ingroup adc
+ * @{
+ */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "adc.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+int ADC_Init(void)
+{
+ int err;
+
+ if ((err = SYS_ADC_Init()) != E_NO_ERROR) {
+ return err;
+ }
+
+ /* Wipe previous configuration */
+ MXC_ADC->intr = 0;
+
+ /* Clear all ADC interrupt flags (W1C) */
+ MXC_ADC->intr = MXC_ADC->intr;
+
+ /* Enable done interrupt */
+ MXC_ADC->intr = MXC_F_ADC_INTR_ADC_DONE_IE;
+
+ /* Power up the ADC */
+ MXC_ADC->ctrl = (MXC_F_ADC_CTRL_ADC_PU |
+ MXC_F_ADC_CTRL_ADC_CLK_EN |
+ MXC_F_ADC_CTRL_BUF_PU |
+ MXC_F_ADC_CTRL_ADC_REFBUF_PU |
+ MXC_F_ADC_CTRL_ADC_CHGPUMP_PU);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass)
+{
+ uint32_t ctrl_tmp;
+
+ /* Clear the ADC done flag */
+ ADC_ClearFlags(MXC_F_ADC_INTR_ADC_DONE_IF);
+
+ /* Insert channel selection */
+ ctrl_tmp = MXC_ADC->ctrl;
+ ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_CHSEL);
+ ctrl_tmp |= ((channel << MXC_F_ADC_CTRL_ADC_CHSEL_POS) & MXC_F_ADC_CTRL_ADC_CHSEL);
+
+ /* Clear channel configuration */
+ ctrl_tmp &= ~(MXC_F_ADC_CTRL_ADC_REFSCL | MXC_F_ADC_CTRL_ADC_SCALE | MXC_F_ADC_CTRL_BUF_BYPASS);
+
+ /* ADC reference scaling must be set for all channels but two*/
+ if ((channel != ADC_CH_VDD18) && (channel != ADC_CH_VDD12)) {
+ ctrl_tmp |= MXC_F_ADC_CTRL_ADC_REFSCL;
+ }
+
+ /* Finalize user-requested channel configuration */
+ if (adc_scale || channel > ADC_CH_3) {
+ ctrl_tmp |= MXC_F_ADC_CTRL_ADC_SCALE;
+ }
+ if (bypass) {
+ ctrl_tmp |= MXC_F_ADC_CTRL_BUF_BYPASS;
+ }
+
+ /* Write this configuration */
+ MXC_ADC->ctrl = ctrl_tmp;
+
+ /* Start conversion */
+ MXC_ADC->ctrl |= MXC_F_ADC_CTRL_CPU_ADC_START;
+
+}
+
+/* ************************************************************************* */
+int ADC_GetData(uint16_t *outdata)
+{
+ /* See if a conversion is in process */
+ if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_ACTIVE) {
+ /* Wait for conversion to complete */
+ while ((MXC_ADC->intr & MXC_F_ADC_INTR_ADC_DONE_IF) == 0);
+ }
+
+ /* Read 32-bit value and truncate to 16-bit for output depending on data align bit*/
+ if((MXC_ADC->ctrl & MXC_F_ADC_CTRL_ADC_DATAALIGN) == 0)
+ *outdata = (uint16_t)(MXC_ADC->data); /* LSB justified */
+ else
+ *outdata = (uint16_t)(MXC_ADC->data >> 6); /* MSB justified */
+
+ /* Check for overflow */
+ if (MXC_ADC->status & MXC_F_ADC_STATUS_ADC_OVERFLOW) {
+ return E_OVERFLOW;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel,
+ unsigned int low_enable, unsigned int low_limit,
+ unsigned int high_enable, unsigned int high_limit)
+{
+ /* Check args */
+ if ((unit >= ADC_LIMIT_MAX) || (channel >= ADC_CH_MAX))
+ return E_BAD_PARAM;
+
+ /* set channel using the limit */
+ MXC_ADC->limit[unit] = ((channel << MXC_F_ADC_LIMIT0_CH_SEL_POS) & MXC_F_ADC_LIMIT0_CH_SEL);
+
+ /* enable/disable the limit*/
+ if (low_enable) {
+ MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN |
+ ((low_limit << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_LO_LIMIT);
+ }
+ else{
+ MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN;
+ }
+
+ if (high_enable) {
+ MXC_ADC->limit[unit] |= MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN |
+ ((high_limit << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS) & MXC_F_ADC_LIMIT0_CH_HI_LIMIT);
+ }
+ else{
+ MXC_ADC->limit[unit] &= ~MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN;
+ }
+
+ return E_NO_ERROR;
+}
+
+/**@} end of group adc */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/adc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,217 @@
+/**
+ * @file
+ * @brief Analog to Digital Converter function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-07 14:53:52 -0500 (Fri, 07 Oct 2016) $
+ * $Revision: 24632 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ADC_H
+#define _ADC_H
+
+/* **** Includes **** */
+#include <stdint.h>
+
+/* Doxy group definition for this peripheral module */
+
+/**
+ * @ingroup periphlibs
+ * @defgroup adc Analog to Digital Converter (ADC)
+ * @{
+ */
+
+#include "adc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type for ADC Channel Selection. See \ref ADC_CHSEL_values "ADC Channel Select Values" for additional information.
+ */
+typedef enum {
+ ADC_CH_0 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0, /**< Channel 0 Select */
+ ADC_CH_1 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1, /**< Channel 1 Select */
+ ADC_CH_2 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN2, /**< Channel 2 Select */
+ ADC_CH_3 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN3, /**< Channel 3 Select */
+ ADC_CH_0_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5, /**< Channel 0 divided by 5 */
+ ADC_CH_1_DIV_5 = MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5, /**< Channel 1 divided by 5 */
+ ADC_CH_VDDB_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4, /**< VDDB divided by 4 */
+ ADC_CH_VDD18 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD18, /**< VDD18 input select */
+ ADC_CH_VDD12 = MXC_V_ADC_CTRL_ADC_CHSEL_VDD12, /**< VDD12 input select */
+ ADC_CH_VRTC_DIV_2 = MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2, /**< VRTC divided by 2 */
+ ADC_CH_TMON = MXC_V_ADC_CTRL_ADC_CHSEL_TMON, /**< TMON input select */
+#if (MXC_ADC_REV > 0)
+ ADC_CH_VDDIO_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4, /**< VDDIO divided by 4 select */
+ ADC_CH_VDDIOH_DIV_4 = MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4, /**< VDDIOH divided by 4 select */
+#endif
+ ADC_CH_MAX /**< Max enum value for channel selection */
+} mxc_adc_chsel_t;
+
+/**
+ * Enumeration type for the ADC limit register to set
+ */
+typedef enum {
+ ADC_LIMIT_0 = 0, /**< ADC Limit Register 0 */
+ ADC_LIMIT_1 = 1, /**< ADC Limit Register 1 */
+ ADC_LIMIT_2 = 2, /**< ADC Limit Register 2 */
+ ADC_LIMIT_3 = 3, /**< ADC Limit Register 3 */
+ ADC_LIMIT_MAX /**< Number of Limit registers */
+} mxc_adc_limitsel_t;
+
+///@cond
+/**
+ * Mask for all Interrupt Flag Fields
+ */
+#define ADC_IF_MASK (0xffffffffUL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)
+
+/**
+ * Mask for all Interrupt Enable Fields
+ */
+#define ADC_IE_MASK (0xffffffffUL >> MXC_F_ADC_INTR_ADC_DONE_IF_POS)
+///@endcond
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize the ADC hardware
+ *
+ * @return #E_NO_ERROR if successful
+ */
+int ADC_Init(void);
+
+/**
+ * @brief Start ADC conversion on the selected channel
+ *
+ * @param channel Channel select from #mxc_adc_chsel_t
+ * @param adc_scale Enable the ADC input scaling mode if non-zero
+ * @param bypass Bypass input buffer stage if non-zero
+ */
+void ADC_StartConvert(mxc_adc_chsel_t channel, unsigned int adc_scale, unsigned int bypass);
+
+/**
+ * @brief Gets the result from the previous ADC conversion
+ *
+ * @param outdata Pointer to store the ADC data conversion
+ * result.
+ * @return #E_OVERFLOW ADC overflow error
+ * @return #E_NO_ERROR Data returned in outdata parameter
+ */
+int ADC_GetData(uint16_t *outdata);
+
+/**
+ * @brief Set the data limits for an ADC channel monitor
+ *
+ * @param unit Which data limit unit to configure
+ * @param channel Channel select from mxc_adc_chsel_t
+ * @param low_enable Enable the lower limit on this monitor
+ * @param low_limit Value for lower limit monitor
+ * @param high_enable Enable the upper limit on this monitor
+ * @param high_limit Value for upper limit monitor
+ *
+ * @return #E_BAD_PARAM ADC limit or channel greater than supported
+ * @return #E_NO_ERROR ADC limit set successfully
+ */
+int ADC_SetLimit(mxc_adc_limitsel_t unit, mxc_adc_chsel_t channel,
+ unsigned int low_enable, unsigned int low_limit,
+ unsigned int high_enable, unsigned int high_limit);
+
+/**
+ * @brief Get interrupt flags
+ *
+ * @return ADC Interrupt flags bit mask. See the @ref ADC_INTR_IF_Register
+ * "ADC_INTR Register" for the interrupt flag masks.
+ */
+__STATIC_INLINE uint32_t ADC_GetFlags()
+{
+ return (MXC_ADC->intr & ADC_IF_MASK);
+}
+
+/**
+ * @brief Clear interrupt flag(s) using the mask parameter. All bits set in
+ * the parameter will be cleared.
+ *
+ * @param mask Interrupt flags to clear. See the @ref ADC_INTR_IF_Register
+ * "ADC_INTR Register" for the interrupt flag masks.
+ */
+__STATIC_INLINE void ADC_ClearFlags(uint32_t mask)
+{
+ MXC_ADC->intr = ((MXC_ADC->intr & ADC_IF_MASK) | mask);
+}
+
+/**
+ * @brief Get the Status of the ADC
+ *
+ * @return ADC status register. See @ref ADC_STATUS_Register "ADC_STATUS
+ * Register" for details.
+ */
+__STATIC_INLINE uint32_t ADC_GetStatus()
+{
+ return (MXC_ADC->status);
+}
+
+/**
+ * @brief Enables the ADC interrupts specified by the mask parameter
+ *
+ * @param mask ADC interrupts to enable. See @ref ADC_INTR_IE_Register
+ * "ADC_INTR Register" for the interrupt enable bit masks.
+ */
+__STATIC_INLINE void ADC_EnableINT(uint32_t mask)
+{
+ MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) | mask);
+}
+
+/**
+ * @brief Disable ADC interrupts based on mask
+ *
+ * @param mask ADC interrupts to disable. See @ref ADC_INTR_IE_Register
+ * "ADC_INTR Register" for the interrupt enable bit masks.
+ */
+__STATIC_INLINE void ADC_DisableINT(uint32_t mask)
+{
+ MXC_ADC->intr = ((MXC_ADC->intr & ADC_IE_MASK) & ~mask);
+}
+
+/**@} end of group adc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ADC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,214 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the Advanced
+ * Encryption Standard (AES) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 12:50:17 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24348 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h> /* Included for memcpy() & #includes stddef for NULL */
+
+#include "mxc_config.h"
+#include "aes.h"
+#include "nvic_table.h"
+
+/**
+ * @ingroup aes
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Local Function Prototypes **** */
+static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count);
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode)
+{
+ unsigned int len;
+
+ /* Erase any existing key */
+ MXC_AES_MEM->key[7] = MXC_AES_MEM->key[6] = MXC_AES_MEM->key[5] = MXC_AES_MEM->key[4] \
+ = MXC_AES_MEM->key[3] = MXC_AES_MEM->key[2] = MXC_AES_MEM->key[1] = MXC_AES_MEM->key[0] \
+ = 0x00000000;
+
+ /* Determine length of key */
+ if (mode == MXC_E_AES_MODE_256) {
+ len = MXC_AES_KEY_256_LEN;
+ } else if (mode == MXC_E_AES_MODE_192) {
+ len = MXC_AES_KEY_192_LEN;
+ } else if (mode == MXC_E_AES_MODE_128) {
+ len = MXC_AES_KEY_128_LEN;
+ } else {
+ return E_BAD_PARAM;
+ }
+
+ /* Load new key, based on key mode */
+ if (aes_memcpy32((uint32_t *)MXC_AES_MEM->key, (uint32_t *)key, len / sizeof(uint32_t)) < 0) {
+ return E_NULL_PTR;
+ }
+
+ return E_SUCCESS;
+}
+
+/* ************************************************************************* */
+int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir)
+{
+ /* Output array can't be a NULL, unless we are in _ASYNC mode */
+ if ((out == NULL)
+ && ((dir != MXC_E_AES_ENCRYPT_ASYNC) && (dir != MXC_E_AES_DECRYPT_ASYNC))) {
+ return E_NULL_PTR;
+ }
+
+ /* Another encryption is already in progress */
+ if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
+ return E_BUSY;
+ }
+
+ /* Clear interrupt flag and any existing configuration*/
+ MXC_AES->ctrl = MXC_F_AES_CTRL_INTFL;
+
+ /* Select key size & direction
+ *
+ * Note: This is done first to detect argument errors, before sensitive data
+ * is loaded into AES_MEM block
+ *
+ */
+ switch (mode) {
+ case MXC_E_AES_MODE_128:
+ MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_128;
+ break;
+
+ case MXC_E_AES_MODE_192:
+ MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_192;
+ break;
+
+ case MXC_E_AES_MODE_256:
+ MXC_AES->ctrl |= MXC_S_AES_CTRL_KEY_SIZE_256;
+ break;
+
+ default:
+ return E_BAD_PARAM;
+ }
+
+ switch (dir) {
+ case MXC_E_AES_ENCRYPT:
+ case MXC_E_AES_ENCRYPT_ASYNC:
+ MXC_AES->ctrl |= MXC_S_AES_CTRL_ENCRYPT_MODE;
+ break;
+
+ case MXC_E_AES_DECRYPT:
+ case MXC_E_AES_DECRYPT_ASYNC:
+ MXC_AES->ctrl |= MXC_S_AES_CTRL_DECRYPT_MODE;
+ break;
+
+ default:
+ return E_BAD_PARAM;
+ }
+
+ /* If non-blocking mode has been selected, interrupts are automatically enabled */
+ if ((dir == MXC_E_AES_ENCRYPT_ASYNC) ||
+ (dir == MXC_E_AES_DECRYPT_ASYNC)) {
+ MXC_AES->ctrl |= MXC_F_AES_CTRL_INTEN;
+ }
+
+ /* Load input into engine */
+ if (aes_memcpy32((uint32_t *)MXC_AES_MEM->inp, (uint32_t *)in, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) {
+ return E_NULL_PTR;
+ }
+
+ /* Start operation */
+ MXC_AES->ctrl |= MXC_F_AES_CTRL_START;
+
+ /* Block, waiting on engine to complete, or fall through if non-blocking */
+ if ((dir != MXC_E_AES_ENCRYPT_ASYNC) &&
+ (dir != MXC_E_AES_DECRYPT_ASYNC)) {
+ while (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
+ /* Ensure that this wait loop is not optimized out */
+ __NOP();
+ }
+
+ /* Get output from engine */
+ return AES_GetOutput(out);
+ }
+
+ return E_SUCCESS;
+}
+
+/* ************************************************************************* */
+int AES_GetOutput(uint8_t *out)
+{
+ /* Don't read it out of the AES memory unless engine is idle */
+ if (MXC_AES->ctrl & MXC_F_AES_CTRL_START) {
+ return E_BUSY;
+ }
+
+ /* Pull out result */
+ if (aes_memcpy32((uint32_t *)out, (uint32_t *)MXC_AES_MEM->out, MXC_AES_DATA_LEN / sizeof(uint32_t)) < 0) {
+ return E_NULL_PTR;
+ }
+
+ /* Clear interrupt flag, write 1 to clear */
+ MXC_AES->ctrl |= MXC_F_AES_CTRL_INTFL;
+
+ return E_SUCCESS;
+}
+
+/**
+ * @internal This memory copy is used only by the AES module to avoid data leakage by the standard C library.
+ * Copy count number of 32-bit locations from in to out
+ */
+static int aes_memcpy32(uint32_t *out, uint32_t *in, unsigned int count)
+{
+ if ((out == NULL) || (in == NULL)) {
+ /* Invalid arguments, but is internal-only so don't use error codes */
+ return -1;
+ }
+
+ while (count--) {
+ *out++ = *in++;
+ }
+
+ return 0;
+}
+
+/**@} end of group aes */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,206 @@
+/**
+ * @file
+ * @brief Advanced Encryption Standard (AES) function prototypes and data
+ * types.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24655 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _AES_H
+#define _AES_H
+/* **** Includes **** */
+#include <stdint.h>
+#include "aes_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup aes Advanced Encryption Standard (AES)
+ * @brief High-level API for AES encryption engine
+ */
+
+/**
+ * @ingroup aes
+ * @defgroup aes_overview Overview and Usage
+ * @brief Advanced Encryption Standard API public include file.
+ * @details
+ * <b>Key/data format in memory</b>
+ * The API functions require that key and plain/ciphertext will be stored as a
+ * byte array in LSB .. MSB format.
+ * @par
+ * As an example, given the key @a 0x139A35422F1D61DE3C91787FE0507AFD, the proper storage order is:
+ * ~~~~~
+ * uint8_t key[16] = { 0xFD, 0x7A, 0x50, 0xE0,
+ * 0x7F, 0x78, 0x91, 0x3C,
+ * 0xDE, 0x61, 0x1D, 0x2F,
+ * 0x42, 0x35, 0x9A, 0x13 };
+ * ~~~~~
+ * This is the same order expected by the underlying hardware.
+ */
+
+/* **** Definitions **** */
+/**
+ * @ingroup aes
+ * @{
+ */
+#define MXC_AES_DATA_LEN (128 / 8) /**< Number of bytes in an AES plaintext or cyphertext block, which are always 128-bits long. */
+#define MXC_AES_KEY_128_LEN (128 / 8) /**< Number of bytes in a AES-128 key. */
+#define MXC_AES_KEY_192_LEN (192 / 8) /**< Number of bytes in a AES-192 key. */
+#define MXC_AES_KEY_256_LEN (256 / 8) /**< Number of bytes in a AES-256 key. */
+
+/**
+ * Enumeration type for AES key size selection (bits).
+ */
+typedef enum {
+ MXC_E_AES_MODE_128 = MXC_V_AES_CTRL_KEY_SIZE_128, /**< 128-bit key. */
+ MXC_E_AES_MODE_192 = MXC_V_AES_CTRL_KEY_SIZE_192, /**< 192-bit key. */
+ MXC_E_AES_MODE_256 = MXC_V_AES_CTRL_KEY_SIZE_256 /**< 256-bit key. */
+} mxc_aes_mode_t;
+
+/**
+ * Enumeration type for specifying encryption/decrytion and asynchronous or blocking behavior.
+ */
+typedef enum {
+ MXC_E_AES_ENCRYPT = 0, /**< Encrypt (synchronous/blocking). */
+ MXC_E_AES_ENCRYPT_ASYNC = 1, /**< Encrypt (aynchronous/interrupt-driven). */
+ MXC_E_AES_DECRYPT = 2, /**< Decrypt (synchronous/blocking). */
+ MXC_E_AES_DECRYPT_ASYNC = 3 /**< Decrypt (aynchronous/interrupt-driven). */
+} mxc_aes_dir_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Configure AES block with keying material
+ *
+ * @param key 128, 192, or 256 bit keying material
+ * @param mode The key length, see #mxc_aes_mode_t for supported lengths.
+ *
+ * @return #E_BAD_PARAM Specified @a mode is invalid, see #mxc_aes_mode_t.
+ * @return #E_NULL_PTR Invalid/Null pointer for parameter @a key.
+ * @return #E_SUCCESS Key and mode set up correctly.
+ */
+int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode);
+
+
+/**
+ * @brief Encrypt/decrypt an input block with the loaded AES key.
+ * @note The parameters @a in and @a out must be 16 bytes.
+ *
+ * @param in Pointer to input array of 16 bytes.
+ * @param out Pointer to output array of 16 bytes.
+ * @param mode AES key size to use for the transaction, see #mxc_aes_mode_t for supported key sizes.
+ * @param dir Operation to perform, see #mxc_aes_dir_t for supported operations.
+ *
+ * @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out.
+ * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured.
+ */
+int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir);
+
+/**
+ * @brief Read the AES output memory, used for asynchronous encryption, and
+ * clears interrupt flag.
+ * @note The parameter @a out must always be 16 bytes.
+ *
+ * @param out Pointer to a 16-byte array to store the output from the AES operation.
+ *
+ * @return #E_SUCCESS Output data was written to the location pointed
+ * to by @a *out.
+ * @return A @ref MXC_Error_Codes "Error Code" indicating the error that
+ * occured.
+ */
+int AES_GetOutput(uint8_t *out);
+
+/**
+ * @def AES_ECBEncrypt(ptxt, ctxt, mode)
+ * @brief Encrypt a block of plaintext with the loaded AES key, blocks
+ * until complete.
+ * @hideinitializer
+ *
+ * @param ptxt Pointer to plaintext input array (always 16 bytes)
+ * @param ctxt Pointer to ciphertext output array (always 16 bytes)
+ * @param mode Selects key length, valid modes found in mxc_aes_mode_t
+ */
+#define AES_ECBEncrypt(ptxt, ctxt, mode) AES_ECBOp(ptxt, ctxt, mode, MXC_E_AES_ENCRYPT)
+
+
+/**
+ * @def AES_ECBDecrypt(ctxt, ptxt, mode)
+ * @hideinitializer
+ * @brief Decrypt a block of ciphertext with the loaded AES key, blocks
+ * until complete.
+ *
+ * @param ctxt Pointer to ciphertext output array (always 16 bytes)
+ * @param ptxt Pointer to plaintext input array (always 16 bytes)
+ * @param mode Selects key length, valid modes found in mxc_aes_mode_t
+ */
+#define AES_ECBDecrypt(ctxt, ptxt, mode) AES_ECBOp(ctxt, ptxt, mode, MXC_E_AES_DECRYPT)
+
+/**
+ * @def AES_ECBEncryptAsync(ptxt, mode)
+ * @hideinitializer
+ * @brief Starts encryption of a block, enables interrupt, and returns
+ * immediately. Use AES_GetOuput() to retrieve result after
+ * interrupt fires
+ *
+ *
+ * @param ptxt Pointer to plaintext input array (always 16 bytes)
+ * @param mode Selects key length, valid modes found in mxc_aes_mode_t
+ */
+#define AES_ECBEncryptAsync(ptxt, mode) AES_ECBOp(ptxt, NULL, mode, MXC_E_AES_ENCRYPT_ASYNC)
+
+/**
+ * @def AES_ECBDecryptAsync(ctxt, mode)
+ * @hideinitializer
+ * @brief Starts encryption of a block, enables interrupt, and returns
+ * immediately. Use AES_GetOuput() to retrieve result after
+ * interrupt fires
+ *
+ * @param ctxt Pointer to ciphertext output array (always 16 bytes)
+ * @param mode Selects key length, valid modes found in mxc_aes_mode_t
+ */
+#define AES_ECBDecryptAsync(ctxt, mode) AES_ECBOp(ctxt, NULL, mode, MXC_E_AES_DECRYPT_ASYNC)
+
+/**@} end of group aes*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,185 @@
+/**
+ * @file
+ * @brief System Clock Management (CLKMAN) Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
+ * $Revision: 24058 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "clkman.h"
+#include "pwrseq_regs.h"
+
+ /**
+ * @ingroup clkman
+ * @{
+ */
+
+/* ************************************************************************* */
+void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale)
+{
+ MXC_CLKMAN->clk_ctrl = ((MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) |
+ (MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO));
+
+ switch(select) {
+ case CLKMAN_SYSTEM_SOURCE_96MHZ:
+ default:
+ // Enable and select the 96MHz oscillator
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN);
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT);
+
+ // Disable the 4MHz oscillator
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN;
+
+ // Divide the system clock by the scale
+ MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RO_DIV) |
+ (scale << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS));
+
+ break;
+ case CLKMAN_SYSTEM_SOURCE_4MHZ:
+ // Enable and select the 4MHz oscillator
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN);
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT);
+
+ // Disable the 96MHz oscillator
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN;
+
+ // 4MHz System source can only be divided down by a maximum factor of 8
+ MXC_ASSERT(scale <= CLKMAN_SYSTEM_SCALE_DIV_8);
+
+ // Divide the system clock by the scale
+ MXC_PWRSEQ->reg3 = ((MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_RC_DIV) |
+ (scale << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS));
+ break;
+ }
+
+ SystemCoreClockUpdate();
+}
+
+/* ************************************************************************* */
+void CLKMAN_CryptoClockEnable(int enable)
+{
+ if (enable) {
+ /* Enable oscillator */
+ MXC_CLKMAN->clk_config |= MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE;
+ /* Un-gate clock to TPU modules */
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE;
+ } else {
+ /* Gate clock off */
+ MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE;
+ /* Disable oscillator */
+ MXC_CLKMAN->clk_config &= ~MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE;
+ }
+}
+
+/* ************************************************************************* */
+void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale)
+{
+ volatile uint32_t *clk_ctrl_reg;
+
+ MXC_ASSERT(clk <= CLKMAN_CLK_MAX);
+ MXC_ASSERT(scale != CLKMAN_SCALE_AUTO);
+
+ if (clk < CLKMAN_CRYPTO_CLK_AES) {
+ clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk;
+ } else {
+ clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES);
+ }
+
+ *clk_ctrl_reg = scale;
+}
+
+/* ************************************************************************* */
+clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk)
+{
+ volatile uint32_t *clk_ctrl_reg;
+ MXC_ASSERT(clk <= CLKMAN_CLK_MAX);
+
+ if (clk < CLKMAN_CRYPTO_CLK_AES) {
+ clk_ctrl_reg = &MXC_CLKMAN->sys_clk_ctrl_0_cm4 + clk;
+ } else {
+ clk_ctrl_reg = &MXC_CLKMAN->crypt_clk_ctrl_0_aes + (clk - CLKMAN_CRYPTO_CLK_AES);
+ }
+
+ return (clkman_scale_t)*clk_ctrl_reg;
+}
+
+/* ************************************************************************* */
+void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable)
+{
+ if (enable) {
+ MXC_CLKMAN->clk_ctrl |= clk;
+ } else {
+ MXC_CLKMAN->clk_ctrl &= ~clk;
+ }
+}
+
+/* ************************************************************************ */
+int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select)
+{
+ MXC_ASSERT(idx < MXC_CFG_WDT_INSTANCES);
+
+ if (select == CLKMAN_WDT_SELECT_DISABLED) {
+ if (idx == 0) {
+ MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE;
+ } else if (idx == 1) {
+ MXC_CLKMAN->clk_ctrl &= ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE;
+ } else {
+ return E_BAD_PARAM;
+ }
+ } else {
+ if (idx == 0) {
+ MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT) |
+ MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE |
+ ((select << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT);
+ } else if (idx == 1) {
+ MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT) |
+ MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE |
+ ((select << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS) & MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT);
+ } else {
+ return E_BAD_PARAM;
+ }
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+/* NOTE: CLKMAN_TrimRO() is implemented in system_max32XXX.c */
+/* ************************************************************************* */
+
+/**@} end of group clkman */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/clkman.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,271 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the System Clock
+ * Management (CLKMAN) module.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
+ * $Revision: 24058 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _CLKMAN_H_
+#define _CLKMAN_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "clkman_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup clkman Clock Management
+ * @ingroup sysconfig
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type specifying the System Clock Rate. @see CLKMAN_SYSTEM_SOURCE_values
+ */
+typedef enum {
+ CLKMAN_SYSTEM_SOURCE_96MHZ = 0, /**< Clock select for 96MHz oscillator.*/
+ CLKMAN_SYSTEM_SOURCE_4MHZ = 1 /**< Clock select for 4MHz oscillator. */
+}
+clkman_system_source_select_t;
+
+/**
+ * Enumeration type for setting the system clock divider.
+ * @note 4MHz System source can only be divided down by a maximum factor of 8.
+ */
+typedef enum {
+ CLKMAN_SYSTEM_SCALE_DIV_1 = 0, /**< Clock scale for dividing system by 1. */
+ CLKMAN_SYSTEM_SCALE_DIV_2 = 1, /**< Clock scale for dividing system by 2. */
+ CLKMAN_SYSTEM_SCALE_DIV_4 = 2, /**< Clock scale for dividing system by 4. */
+ CLKMAN_SYSTEM_SCALE_DIV_8 = 3, /**< Clock scale for dividing system by 8. */
+ CLKMAN_SYSTEM_SCALE_DIV_16 = 4 /**< Clock scale for dividing system by 16. */
+} clkman_system_scale_t;
+
+/**
+ * Enumeration type for selecting a peripheral module for setting and getting it's clock scale.
+ */
+typedef enum {
+ CLKMAN_CLK_CPU = 0, /**< CPU clock. */
+ CLKMAN_CLK_SYNC = 1, /**< Synchronizer clock. */
+ CLKMAN_CLK_SPIX = 2, /**< SPI XIP module clock. */
+ CLKMAN_CLK_PRNG = 3, /**< PRNG module clock. */
+ CLKMAN_CLK_WDT0 = 4, /**< Watchdog Timer 0 clock. */
+ CLKMAN_CLK_WDT1 = 5, /**< Watchdog Timer 1 clock. */
+ CLKMAN_CLK_GPIO = 6, /**< GPIO module clock. */
+ CLKMAN_CLK_PT = 7, /**< Pulse Train engine clock. */
+ CLKMAN_CLK_UART = 8, /**< UART clock. */
+ CLKMAN_CLK_I2CM = 9, /**< I2C Master module clock (for all instances). */
+ CLKMAN_CLK_I2CS = 10, /**< I2C Slave module clock. */
+ CLKMAN_CLK_SPIM0 = 11, /**< SPI Master instance 0 module clock. */
+ CLKMAN_CLK_SPIM1 = 12, /**< SPI Master instance 1 module clock. */
+ CLKMAN_CLK_SPIM2 = 13, /**< SPI Master instance 2 module clock. */
+ CLKMAN_CLK_SPIB = 14, /**< SPI Bridge module clock. */
+ CLKMAN_CLK_OWM = 15, /**< OWM module clock. */
+ CLKMAN_CLK_SPIS = 16, /**< SPI Slave module clock. */
+ CLKMAN_CRYPTO_CLK_AES = 17, /**< AES engine clock. */
+ CLKMAN_CRYPTO_CLK_MAA = 18, /**< Modular Arithmetic Accelerator (MAA) clock. */
+ CLKMAN_CRYPTO_CLK_PRNG = 19, /**< Pseudo-random number Generator (PRNG) clock. */
+ CLKMAN_CLK_MAX /**< Maximum value of enum for limit checking. */
+} clkman_clk_t;
+
+/**
+ * Enumeration type for selecting a peripheral module (USB, Cryto, ADC, WDT0, WDT1 and RTC/RTOS)
+ * to enable/disable clock gating.
+ */
+typedef enum {
+ CLKMAN_USB_CLOCK = MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE, /**< Enable/Disable mask for USB. */
+ CLKMAN_CRYPTO_CLOCK = MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE, /**< Enable/Disable mask for Crypto Clock. */
+ CLKMAN_ADC_CLOCK = MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE, /**< Enable/Disable mask for ADC. */
+ CLKMAN_WDT0_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 0. */
+ CLKMAN_WDT1_CLOCK = MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE, /**< Enable/Disable mask for Watch Dog Timer 1. */
+ CLKMAN_RTOS_MODE = MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE /**< Enable/Disable mask for 32kHz clock in LP1
+ * required to use JTAG for debug.
+ */
+} clkman_enable_clk_t;
+
+/**
+ * Enumeration type for selecting the clock scale for the system or peripheral module.
+ */
+typedef enum {
+ CLKMAN_SCALE_DISABLED = MXC_V_CLKMAN_CLK_SCALE_DISABLED, /**< Clock disabled. */
+ CLKMAN_SCALE_DIV_1 = MXC_V_CLKMAN_CLK_SCALE_DIV_1, /**< Clock scale for dividing by 1. */
+ CLKMAN_SCALE_DIV_2 = MXC_V_CLKMAN_CLK_SCALE_DIV_2, /**< Clock scale for dividing by 2. */
+ CLKMAN_SCALE_DIV_4 = MXC_V_CLKMAN_CLK_SCALE_DIV_4, /**< Clock scale for dividing by 4. */
+ CLKMAN_SCALE_DIV_8 = MXC_V_CLKMAN_CLK_SCALE_DIV_8, /**< Clock scale for dividing by 8. */
+ CLKMAN_SCALE_DIV_16 = MXC_V_CLKMAN_CLK_SCALE_DIV_16, /**< Clock scale for dividing by 16. */
+ CLKMAN_SCALE_DIV_32 = MXC_V_CLKMAN_CLK_SCALE_DIV_32, /**< Clock scale for dividing by 32. */
+ CLKMAN_SCALE_DIV_64 = MXC_V_CLKMAN_CLK_SCALE_DIV_64, /**< Clock scale for dividing by 64. */
+ CLKMAN_SCALE_DIV_128 = MXC_V_CLKMAN_CLK_SCALE_DIV_128, /**< Clock scale for dividing by 128. */
+ CLKMAN_SCALE_DIV_256 = MXC_V_CLKMAN_CLK_SCALE_DIV_256, /**< Clock scale for dividing by 256. */
+ CLKMAN_SCALE_AUTO /**< Clock scale to auto select divider. */
+} clkman_scale_t;
+
+/*
+ * Enumeration type for selecting the source clock for the Watch Dog Timers.
+ * | Enumeration Selection | Value | WDT Clock Source |
+ * | :--------------------------------------: | :---: | :-------------------------- |
+ * | CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL | 0 | Scaled System Clock |
+ * | CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR | 1 | 32 kHz Real-Time Clock |
+ * | CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR | 2 | 96 MHz Oscillator unscaled |
+ * | CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR | 3 | Nano-ring clock |
+ * | CLKMAN_WDT_SELECT_DISABLED | 4 | WDT0 Clock is disabled |
+ */
+typedef enum {
+ CLKMAN_WDT_SELECT_SCALED_SYS_CLK_CTRL = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0, /**< Use scaled system clock for Watchdog Timer 0. */
+ CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR, /**< Use 32kHz oscillator for Watchdog Timer 0. */
+ CLKMAN_WDT_SELECT_96MHZ_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR, /**< Use 96MHz clock for Watchdog Timer 0. */
+ CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR = MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR, /**< Use Nano-Ring Oscillator (8kHz) for Watchdog Timer 0 clock.*/
+ CLKMAN_WDT_SELECT_DISABLED /**< Watchdog Timer 0 clock disabled. */
+} clkman_wdt_clk_select_t;
+
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Selects the system clock source,
+ * @note 4MHz System source can only be divided down by a maximum factor
+ * of 8.
+ *
+ * @param select System clock source.
+ * @param scale System clock scaler.
+ */
+void CLKMAN_SetSystemClock(clkman_system_source_select_t select, clkman_system_scale_t scale);
+
+/**
+ * @brief Enables/disables the Crypto/TPU relaxation oscillator
+ *
+ * @param enable |:------- | :---: |
+ * | Enable | 1 |
+ * | Disable | 0 |
+ */
+void CLKMAN_CryptoClockEnable(int enable);
+
+/**
+ * @brief Enables/Disables clock gating for the specified peripheral
+ * module.
+ *
+ * @param clk Peripheral module to enable/disable clock gating.
+ * @param enable Enable (1) or Disable (0).
+ */
+void CLKMAN_ClockGate(clkman_enable_clk_t clk, int enable);
+
+/**
+ * @brief Sets the specified clock scaler value.
+ *
+ * @param clk Peripheral module to set the desired clock scale.
+ * @param scale Clock scale/divisor for the specified peripheral module.
+ */
+void CLKMAN_SetClkScale(clkman_clk_t clk, clkman_scale_t scale);
+
+/**
+ * @brief Get the clock scaler/divisor value for the specified peripheral
+ * module.
+ *
+ * @param clk The peripheral module to get the current clock scale setting, see #clkman_clk_t.
+ * @return A value indicating the clock divisor/scale of the requested
+ * peripheral module.
+ */
+clkman_scale_t CLKMAN_GetClkScale(clkman_clk_t clk);
+
+/**
+ * @brief Selects the clock source for the specified watchdog timer.
+ *
+ * @param idx Value indicating the WDT to set the clock source on.
+ * @param select Value of the desired clock source for the WDT.
+ */
+int CLKMAN_WdtClkSelect(unsigned int idx, clkman_wdt_clk_select_t select);
+
+/**
+ * @brief Get the interrupt flags for the CLKMAN module.
+ *
+ * @return The current interrupt flags.
+ */
+__STATIC_INLINE uint32_t CLKMAN_GetFlags(void)
+{
+ return MXC_CLKMAN->intfl;
+}
+
+/**
+ * @brief Clear the specified interrupt flags
+ *
+ * @param mask mask of clock management interrupt flags to clear
+ */
+__STATIC_INLINE void CLKMAN_ClrFlags(uint32_t mask)
+{
+ MXC_CLKMAN->intfl = mask;
+}
+
+/**
+ * @brief Enable the interrupts specified in the mask parameter.
+ *
+ * @param mask Mask of clock management interrupts to enable, 1 to enable
+ * a specific interrupt.
+ */
+__STATIC_INLINE void CLKMAN_EnableInt(uint32_t mask)
+{
+ MXC_CLKMAN->inten |= mask;
+}
+
+/**
+ * @brief Disable the specified interrupts
+ *
+ * @param mask Mask of CLKMAN interrupts to disable, 1 to disable a
+ * specific interrupt.
+ */
+__STATIC_INLINE void CLKMAN_DisableInt(uint32_t mask)
+{
+ MXC_CLKMAN->inten &= ~mask;
+}
+
+/**
+ * @brief Trim the ring oscillator.
+ * @note CLKMAN_TrimRO() is implemented in system_max32XXX.c
+ */
+void CLKMAN_TrimRO(void);
+
+/**@} end of group clkman */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CLKMAN_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,108 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the Cyclic
+ * Redundency Check (CRC) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 11:49:04 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24339 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "crc.h"
+
+/**
+ * @ingroup crc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian)
+{
+ if(CCITT_TRUE)
+ MXC_CRC->reseed |= MXC_F_CRC_RESEED_CCITT_MODE;
+ else
+ MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_CCITT_MODE;
+
+ if(lilEndian)
+ MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN16;
+ else
+ MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN16;
+}
+
+/* ************************************************************************* */
+void CRC32_Init(uint8_t lilEndian)
+{
+ if(lilEndian)
+ MXC_CRC->reseed |= MXC_F_CRC_RESEED_REV_ENDIAN32;
+ else
+ MXC_CRC->reseed &= ~MXC_F_CRC_RESEED_REV_ENDIAN32;
+}
+
+/* ************************************************************************* */
+
+void CRC16_Reseed(uint16_t initData)
+{
+ //set initial value
+ MXC_CRC->seed16 = initData;
+
+ //reseed the CRC16 generator
+ MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC16;
+
+ //wait for reseed to clear itself
+ while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC16);
+
+}
+
+/* ************************************************************************* */
+void CRC32_Reseed(uint32_t initData)
+{
+ //set initial value
+ MXC_CRC->seed32 = initData;
+
+ //reseed the CRC16 generator
+ MXC_CRC->reseed |= MXC_F_CRC_RESEED_CRC32;
+
+ //wait for reseed to clear itself
+ while(MXC_CRC->reseed & MXC_F_CRC_RESEED_CRC32);
+}
+
+/**@} end of group crc */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/crc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,191 @@
+/**
+ * @file
+ * @brief CRC peripheral module function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 16:57:56 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24657 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _CRC_H_
+#define _CRC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup crc Cyclic Redundancy Check (CRC)
+ * @brief High-level API for CRC Peripheral Module
+ * @{
+ */
+
+/**
+ * @page crc_overview Overview and Usage
+ * @parblock
+ * - Initialize the CRC for usage by calling either the CRC16_Init() function or the CRC32_Init() funciton
+ * + For CRC16, CCITT mode is enabled if the parameter is set
+ * + Select the Endian of the data for calculation
+ * - passing a 1 sets the module to little endian
+ * - passing a 0 sets the module to big endian
+ * - Set the intial CRC seed by calling CRC16_Reseed() or CRC32_Reseed()
+ * + This is the initial value of the CRC remainder to be used when the data is passed to the module
+ * - Pass data to the CRC engine using the methods:
+ * + CRC16_AddData()
+ * + CRC16_AddDataArray()
+ * + CRC32_AddData()
+ * + CRC32_AddDataArray()
+ * @note any data passed to the add methods of the peripheral is padded with zeros if it is less than
+ * 32-bits.
+ * @endparblock
+*/
+
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include <string.h>
+#include "crc_regs.h"
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize CRC clock and select CRC16 mode and byte order.
+ *
+ * @param CCITT_TRUE CRC16-CCITT-TRUE = 1, CRC16-CCITT-FALSE = 0
+ * @param lilEndian byte order, little endian = 1, big endian = 0
+ */
+void CRC16_Init(uint8_t CCITT_TRUE, uint8_t lilEndian);
+
+/**
+ * @brief Initialize CRC clock and select byte order for CRC32.
+ *
+ * @param lilEndian byte order, little endian = 1, big endian = 0
+ */
+void CRC32_Init(uint8_t lilEndian);
+
+/**
+ * @brief Initialize CRC16 calculation.
+ *
+ * @param initData intial remainder to start the CRC16 calculation with
+ */
+void CRC16_Reseed(uint16_t initData);
+
+/**
+ * @brief Initialize CRC32 calculation.
+ *
+ * @param initData intial remainder to start the CRC32 calculation with
+ */
+void CRC32_Reseed(uint32_t initData);
+
+/**
+ * @brief Add data to the CRC16 calculation.
+ *
+ * @param data data to add to the CRC16 calculation
+ * @note data is padded with zeros if less than 32bits.
+ */
+__STATIC_INLINE void CRC16_AddData(uint32_t data)
+{
+ MXC_CRC_DATA->value16[0] = data;
+}
+
+/**
+ * @brief Add data to the CRC32 calculation
+ *
+ * @param data data to add to the CRC32 calculation
+ * @note data is padded with zeros if less than 32bits
+ */
+__STATIC_INLINE void CRC32_AddData(uint32_t data)
+{
+ MXC_CRC_DATA->value32[0] = data;
+}
+
+/**
+ * @brief Add an array of data to the CRC16 calculation
+ *
+ * @param data pointer to array of data
+ * @note data is padded with zeros if less than 32bits
+ *
+ * @param arrayLength number of elements in array
+ */
+__STATIC_INLINE void CRC16_AddDataArray(uint32_t *data, uint32_t arrayLength)
+{
+ memcpy((void *)(&(MXC_CRC_DATA->value16)), (void *)data, arrayLength * sizeof(data[0]));
+}
+
+/**
+ * @brief Add an array of data to the CRC32 calculation
+ *
+ * @param data pointer to array of data
+ * @note data is padded with zeros if less than 32bits
+ * @param arrayLength number of elements in array
+ */
+__STATIC_INLINE void CRC32_AddDataArray(uint32_t *data, uint32_t arrayLength)
+{
+ memcpy((void *)(&(MXC_CRC_DATA->value32)), (void *)data, arrayLength * sizeof(data[0]));
+}
+
+/**
+ * @brief Get the calculated CRC16 value
+ *
+ * @return CRC16 value
+ */
+__STATIC_INLINE uint32_t CRC16_GetCRC()
+{
+ return MXC_CRC_DATA->value16[0];
+}
+
+/**
+ * @brief Get the calculated CRC32 value
+ *
+ * @return CRC32 value
+ */
+__STATIC_INLINE uint32_t CRC32_GetCRC()
+{
+ return MXC_CRC_DATA->value32[0];
+}
+
+/**@} end of crc group */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CRC_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,260 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the Flash
+ * Controller (FLC) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 11:48:21 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24338 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "flc.h"
+
+
+/**
+ * @ingroup flc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+#if defined ( __GNUC__ )
+#undef IAR_PRAGMAS //Make sure this is not defined for GCC
+#endif
+
+#if IAR_PRAGMAS
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+/**
+ * @brief Return the status of the busy state of the flash controller.
+ *
+ * @return 0 Flash Controller is idle.
+ * @return Non-zero indicates the flash controller is performing an
+ * erase or write request.
+ */
+__STATIC_INLINE int FLC_Busy(void)
+{
+ return (MXC_FLC->ctrl & (MXC_F_FLC_CTRL_WRITE | MXC_F_FLC_CTRL_MASS_ERASE | MXC_F_FLC_CTRL_PAGE_ERASE));
+}
+
+/* ************************************************************************* */
+#if IAR_PRAGMAS
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Init(void)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return E_BUSY;
+ }
+
+ /* Enable automatic calculation of the clock divider to generate a 1MHz clock from the APB clock */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_AUTO_CLKDIV;
+
+ /* The flash controller will stall any reads while flash operations are in
+ * progress. Disable the legacy failure detection logic that would flag reads
+ * during flash operations as errors.
+ */
+ MXC_FLC->perform |= MXC_F_FLC_PERFORM_EN_PREVENT_FAIL;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+#if IAR_PRAGMAS
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return E_BUSY;
+ }
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
+ ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
+
+ /* Write the Erase Code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) |
+ ((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Erase the request page */
+ MXC_FLC->faddr = address;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_PAGE_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return E_UNKNOWN;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+#if IAR_PRAGMAS
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key)
+{
+ uint32_t *ptr = (uint32_t*)data;
+
+ /* Can only write in full word units */
+ if ((address & 3) || (length & 3)) {
+ return E_BAD_PARAM;
+ }
+
+ if (length == 0) {
+ /* Nothing to do */
+ return E_NO_ERROR;
+ }
+
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return E_BUSY;
+ }
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
+ ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
+
+ /* Set the address to write and enable auto increment */
+ MXC_FLC->faddr = address;
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_AUTO_INCRE_MODE;
+ uint32_t write_cmd = MXC_FLC->ctrl | MXC_F_FLC_CTRL_WRITE;
+
+ for (; length > 0; length -= 4) {
+ /* Perform the write */
+ MXC_FLC->fdata = *ptr++;
+ MXC_FLC->ctrl = write_cmd;
+ while (FLC_Busy());
+ }
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~MXC_F_FLC_CTRL_FLSH_UNLOCK;
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return E_UNKNOWN;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+#if IAR_PRAGMAS
+// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
+#pragma section=".flashprog"
+#endif
+#if defined ( __GNUC__ )
+__attribute__ ((section(".flashprog")))
+#endif
+int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key)
+{
+ /* Check if the flash controller is busy */
+ if (FLC_Busy()) {
+ return E_BUSY;
+ }
+
+ /* Clear stale errors. Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+
+ /* Unlock flash */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_FLSH_UNLOCK) |
+ ((unlock_key << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS) & MXC_F_FLC_CTRL_FLSH_UNLOCK);
+
+ /* Write the Erase Code */
+ MXC_FLC->ctrl = (MXC_FLC->ctrl & ~MXC_F_FLC_CTRL_ERASE_CODE) |
+ ((erase_code << MXC_F_FLC_CTRL_ERASE_CODE_POS) & MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Start the mass erase */
+ MXC_FLC->ctrl |= MXC_F_FLC_CTRL_MASS_ERASE;
+
+ /* Wait until flash operation is complete */
+ while (FLC_Busy());
+
+ /* Lock flash */
+ MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_FLSH_UNLOCK | MXC_F_FLC_CTRL_ERASE_CODE);
+
+ /* Check for failures */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_FAILED_IF) {
+ /* Interrupt flags can only be written to zero, so this is safe */
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_FAILED_IF;
+ return E_UNKNOWN;
+ }
+
+ return E_NO_ERROR;
+}
+
+/**@} end of group flc */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/flc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,117 @@
+/**
+ * @file
+ * @brief Flash Controller (FLC) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:54:04 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24658 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _FLC_H_
+#define _FLC_H_
+
+/* **** Includes **** */
+#include "flc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup sysconfig
+ * @defgroup flc Flash Controller (FLC)
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Prepares the Flash Controller for in-application flash operations. This function
+ * only needs to be called one time after a reset event.
+ *
+ * @return #E_NO_ERROR if flash controller initialized correctly, error if
+ * unsuccessful.
+ */
+int FLC_Init(void);
+
+/**
+ * @brief This function will erase a single page of flash.
+ *
+ * @param address Address of the page to be erased.
+ * @param erase_code Flash erase code; defined as
+ * #MXC_V_FLC_ERASE_CODE_PAGE_ERASE for page erase
+ * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
+ *
+ * @returns #E_NO_ERROR if page erase successful, error if unsuccessful.
+ */
+int FLC_PageErase(uint32_t address, uint8_t erase_code, uint8_t unlock_key);
+
+/**
+ * @brief This function writes data to the flash device through the flash
+ * controller interface
+ *
+ * @param address Start address for desired write. @note This address
+ * must be 32-bit word aligned
+ * @param data A pointer to the buffer containing the data to write.
+ * @param length Size of the data to write in bytes. @note The length
+ * must be in 32-bit multiples.
+ * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
+ *
+ * @returns #E_NO_ERROR if data written successfully, error if unsuccessful.
+ */
+int FLC_Write(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key);
+
+/**
+ * @brief This function will mass erase the flash.
+ *
+ * @param erase_code Flash erase code, #MXC_V_FLC_ERASE_CODE_MASS_ERASE.
+ * @param unlock_key Unlock key, #MXC_V_FLC_FLSH_UNLOCK_KEY.
+ *
+ * @returns #E_NO_ERROR if device mass erase successful, error if unsuccessful.
+ */
+int FLC_MassErase(uint8_t erase_code, uint8_t unlock_key);
+
+/**@} end of group flc */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,186 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the
+ * General-Purpose Input/Output (GPIO) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 11:41:02 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24337 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "gpio.h"
+#include "clkman_regs.h"
+
+/**
+ * @ingroup gpio
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* ************************************************************************* */
+static void (*callbacks[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT])(void *);
+static void *cbparam[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT];
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+static int PinConfig(unsigned int port, unsigned int pin, gpio_func_t func, gpio_pad_t pad)
+{
+ /* Check if available */
+ if (!(MXC_GPIO->free[port] & (1 << pin))) {
+ return E_BUSY;
+ }
+
+ /* Set function */
+ uint32_t func_sel = MXC_GPIO->func_sel[port];
+ func_sel &= ~(0xF << (4 * pin));
+ func_sel |= (func << (4 * pin));
+ MXC_GPIO->func_sel[port] = func_sel;
+
+ /* Normal input is always enabled */
+ MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin));
+
+ /* Set requested output mode */
+ uint32_t out_mode = MXC_GPIO->out_mode[port];
+ out_mode &= ~(0xF << (4 * pin));
+ out_mode |= (pad << (4 * pin));
+ MXC_GPIO->out_mode[port] = out_mode;
+
+ /* Enable the pull up/down if necessary */
+ if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) {
+ MXC_GPIO->out_val[port] |= (1 << pin);
+ } else if (pad == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) {
+ MXC_GPIO->out_val[port] &= ~(1 << pin);
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int GPIO_Config(const gpio_cfg_t *cfg)
+{
+ unsigned int pin;
+ int err = E_NO_ERROR;
+
+ MXC_ASSERT(cfg);
+ MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
+
+ // Set system level configurations
+ if ((err = SYS_GPIO_Init()) != E_NO_ERROR) {
+ return err;
+ }
+
+ // Configure each pin in the mask
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if (cfg->mask & (1 << pin)) {
+ if (PinConfig(cfg->port, pin, cfg->func, cfg->pad) != E_NO_ERROR) {
+ err = E_BUSY;
+ }
+ }
+ }
+
+ return err;
+}
+
+/* ************************************************************************* */
+static void IntConfig(unsigned int port, unsigned int pin, gpio_int_mode_t mode)
+{
+ uint32_t int_mode = MXC_GPIO->int_mode[port];
+ int_mode &= ~(0xF << (pin*4));
+ int_mode |= (mode << (pin*4));
+ MXC_GPIO->int_mode[port] = int_mode;
+}
+
+/* ************************************************************************* */
+void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode)
+{
+ unsigned int pin;
+
+ MXC_ASSERT(cfg);
+ MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
+
+ // Configure each pin in the mask
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if (cfg->mask & (1 << pin)) {
+ IntConfig(cfg->port, pin, mode);
+ }
+ }
+}
+
+/* ************************************************************************* */
+void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata)
+{
+ unsigned int pin;
+
+ MXC_ASSERT(cfg);
+ MXC_ASSERT(cfg->port < MXC_GPIO_NUM_PORTS);
+
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if (cfg->mask & (1 << pin)) {
+ callbacks[cfg->port][pin] = func;
+ cbparam[cfg->port][pin] = cbdata;
+ }
+ }
+}
+
+/* ************************************************************************* */
+void GPIO_Handler(unsigned int port)
+{
+ uint8_t intfl;
+ unsigned int pin;
+
+ MXC_ASSERT(port < MXC_GPIO_NUM_PORTS);
+
+ // Read and clear enabled interrupts.
+ intfl = MXC_GPIO->intfl[port];
+ intfl &= MXC_GPIO->inten[port];
+ MXC_GPIO->intfl[port] = intfl;
+
+ // Process each pins' interrupt
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if ((intfl & (1 << pin)) && callbacks[port][pin]) {
+ callbacks[port][pin](cbparam[port][pin]);
+ }
+ }
+}
+
+/**@} end of group gpio */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,315 @@
+/**
+ * @file
+ * @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24659 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Doxy group definition for this peripheral module
+/**
+ * @ingroup periphlibs
+ * @defgroup gpio General-Purpose Input/Output (GPIO)
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * @defgroup gpio_port_pin Port and Pin Definitions
+ * @ingroup gpio
+ * @{
+ * @defgroup gpio_port Port Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PORT_0 (0) /**< Port 0 Define*/
+#define PORT_1 (1) /**< Port 1 Define*/
+#define PORT_2 (2) /**< Port 2 Define*/
+#define PORT_3 (3) /**< Port 3 Define*/
+#define PORT_4 (4) /**< Port 4 Define*/
+#define PORT_5 (5) /**< Port 5 Define*/
+#define PORT_6 (6) /**< Port 6 Define*/
+#define PORT_7 (7) /**< Port 7 Define*/
+#define PORT_8 (8) /**< Port 8 Define*/
+#define PORT_9 (9) /**< Port 9 Define*/
+#define PORT_10 (10) /**< Port 10 Define*/
+#define PORT_11 (11) /**< Port 11 Define*/
+#define PORT_12 (12) /**< Port 12 Define*/
+#define PORT_13 (13) /**< Port 13 Define*/
+#define PORT_14 (14) /**< Port 14 Define*/
+#define PORT_15 (15) /**< Port 15 Define*/
+/**@} end of gpio_port group*/
+/**
+ * @defgroup gpio_pin Pin Definitions
+ * @ingroup gpio_port_pin
+ * @{
+ */
+#define PIN_0 (1 << 0) /**< Pin 0 Define */
+#define PIN_1 (1 << 1) /**< Pin 1 Define */
+#define PIN_2 (1 << 2) /**< Pin 2 Define */
+#define PIN_3 (1 << 3) /**< Pin 3 Define */
+#define PIN_4 (1 << 4) /**< Pin 4 Define */
+#define PIN_5 (1 << 5) /**< Pin 5 Define */
+#define PIN_6 (1 << 6) /**< Pin 6 Define */
+#define PIN_7 (1 << 7) /**< Pin 7 Define */
+/**@} end of gpio_pin group */
+/**@} end of gpio_port_pin group */
+
+/**
+ * Enumeration type for the GPIO Function Type
+ */
+typedef enum {
+ GPIO_FUNC_GPIO = MXC_V_GPIO_FUNC_SEL_MODE_GPIO, /**< GPIO Function Selection */
+ GPIO_FUNC_PT = MXC_V_GPIO_FUNC_SEL_MODE_PT, /**< Pulse Train Function Selection */
+ GPIO_FUNC_TMR = MXC_V_GPIO_FUNC_SEL_MODE_TMR /**< Timer Function Selection */
+}
+gpio_func_t;
+
+/**
+ * Enumeration type for the type of GPIO pad on a given pin.
+ */
+typedef enum {
+ GPIO_PAD_INPUT_PULLUP = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP, /**< Set pad to high impedance, weak pull-up */
+ GPIO_PAD_OPEN_DRAIN = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN, /**< Set pad to open-drain with high impedance with input buffer */
+ GPIO_PAD_OPEN_DRAIN_PULLUP = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP, /**< Set pad to open-drain with weak pull-up */
+ GPIO_PAD_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, /**< Set pad to high impednace, input buffer enabled */
+ GPIO_PAD_NORMAL = MXC_V_GPIO_OUT_MODE_NORMAL, /**< Set pad to normal drive mode for high an low output */
+ GPIO_PAD_SLOW = MXC_V_GPIO_OUT_MODE_SLOW_DRIVE, /**< Set pad to slow drive mode, which is normal mode with negative feedback to slow edge transitions */
+ GPIO_PAD_FAST = MXC_V_GPIO_OUT_MODE_FAST_DRIVE, /**< Set pad to fash drive mode, which is normal mode with a transistor drive to drive fast high and low */
+ GPIO_PAD_INPUT_PULLDOWN = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN, /**< Set pad to weak pulldown mode */
+ GPIO_PAD_OPEN_SOURCE = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE, /**< Set pad to open source mode, transistor drive to high */
+ GPIO_PAD_OPEN_SOURCE_PULLDOWN = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN /**< Set pad to open source with weak pulldown mode, transistor drive to high, weak pulldown to GND for low */
+} gpio_pad_t;
+
+/**
+ * Structure type for configuring a GPIO port.
+ */
+typedef struct {
+ uint32_t port; /// Index of GPIO port
+ uint32_t mask; /// Pin mask. Multiple bits can be set.
+ gpio_func_t func; /// Function type
+ gpio_pad_t pad; /// Pad type
+} gpio_cfg_t;
+
+/**
+ * Enumeration type for the interrupt type on a GPIO port.
+ */
+typedef enum {
+ GPIO_INT_DISABLE = MXC_V_GPIO_INT_MODE_DISABLE, /**< Disable interrupts */
+ GPIO_INT_FALLING_EDGE = MXC_V_GPIO_INT_MODE_FALLING_EDGE, /**< Interrupt on Falling Edge */
+ GPIO_INT_RISING_EDGE = MXC_V_GPIO_INT_MODE_RISING_EDGE, /**< Interrupt on Rising Edge */
+ GPIO_INT_ANY_EDGE = MXC_V_GPIO_INT_MODE_ANY_EDGE, /**< Interrupt on Falling or Rising Edge */
+ GPIO_INT_LOW_LEVEL = MXC_V_GPIO_INT_MODE_LOW_LVL, /**< Interrupt on a low level input detection */
+ GPIO_INT_HIGH_LEVEL = MXC_V_GPIO_INT_MODE_HIGH_LVL /**< Interrupt on a high level input detection */
+} gpio_int_mode_t;
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Configure GPIO pin(s).
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ * @return #E_NO_ERROR if everything is successful.
+ *
+ */
+int GPIO_Config(const gpio_cfg_t *cfg);
+
+/**
+ * @brief Gets the pin(s) input state.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ * @return The requested pin state.
+ *
+ */
+__STATIC_INLINE uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
+{
+ return (MXC_GPIO->in_val[cfg->port] & cfg->mask);
+}
+
+/**
+ * @brief Sets the pin(s) to a high level output.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ */
+__STATIC_INLINE void GPIO_OutSet(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->out_val[cfg->port] |= cfg->mask;
+}
+
+/**
+ * @brief Clears the pin(s) to a low level output.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ */
+__STATIC_INLINE void GPIO_OutClr(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->out_val[cfg->port] &= ~(cfg->mask);
+}
+
+/**
+ * @brief Gets the pin(s) output state.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ * @return The state of the requested pin.
+ *
+ */
+__STATIC_INLINE uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
+{
+ return (MXC_GPIO->out_val[cfg->port] & cfg->mask);
+}
+
+/**
+ * @brief Write the pin(s) to a desired output level.
+ * @param cfg Pointer to configuration structure describing the pin.
+ * @param val Desired output level of the pin(s). This will be masked
+ * with the configuration mask.
+ *
+ */
+__STATIC_INLINE void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
+{
+ MXC_GPIO->out_val[cfg->port] = (MXC_GPIO->out_val[cfg->port] & ~cfg->mask) | (val & cfg->mask);
+}
+
+/**
+ * @brief Toggles the the pin(s) output level.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ */
+__STATIC_INLINE void GPIO_OutToggle(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->out_val[cfg->port] ^= cfg->mask;
+}
+
+/**
+ * @brief Configure GPIO interrupt(s)
+ * @param cfg Pointer to configuration structure describing the pin.
+ * @param mode Requested interrupt mode.
+ *
+ */
+void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode);
+
+/**
+ * @brief Enables the specified GPIO interrupt
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ */
+__STATIC_INLINE void GPIO_IntEnable(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->inten[cfg->port] |= cfg->mask;
+}
+
+/**
+ * @brief Disables the specified GPIO interrupt.
+ * @param cfg Pointer to configuration structure describing the pin.
+ *
+ */
+__STATIC_INLINE void GPIO_IntDisable(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->inten[cfg->port] &= ~cfg->mask;
+}
+
+/**
+ * @brief Gets the interrupt(s) status on a GPIO pin.
+ * @param cfg Pointer to configuration structure describing the pin
+ * for which the status is being requested.
+ *
+ * @return The requested interrupt status.
+ *
+ */
+__STATIC_INLINE uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
+{
+ return (MXC_GPIO->intfl[cfg->port] & cfg->mask);
+}
+
+/**
+ * @brief Clears the interrupt(s) status on a GPIO pin.
+ * @param cfg Pointer to configuration structure describing the pin
+ * to clear the interrupt state of.
+ *
+ */
+__STATIC_INLINE void GPIO_IntClr(const gpio_cfg_t *cfg)
+{
+ MXC_GPIO->intfl[cfg->port] = cfg->mask;
+}
+
+/**
+ * @brief Type alias for a GPIO callback function with prototype:
+ * @code
+ * void callback_fn(void *cbdata);
+ * @endcode
+ * @param cbdata A void pointer to the data type as registered when
+ * @c GPIO_RegisterCallback() was called.
+ *
+ */
+typedef void (*gpio_callback_fn)(void *cbdata);
+
+/**
+ * @brief Registers a callback for the interrupt on a given port and pin.
+ * @param cfg Pointer to configuration structure describing the pin
+ * @param callback A pointer to a function of type #gpio_callback_fn.
+ * @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
+ *
+ */
+void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
+
+/**
+ * @brief GPIO IRQ Handler. @note If a callback is registered for a given
+ * interrupt, the callback function will be called.
+ *
+ * @param port number of the port that generated the interrupt service routine.
+ *
+ */
+void GPIO_Handler(unsigned int port);
+
+/**@} end of group gpio */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,924 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the I2CM
+ * (Inter-Integrated Circuit Master) peripheral module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 11:40:02 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24336 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_errors.h"
+#include "mxc_sys.h"
+#include "i2cm.h"
+
+
+/**
+ * @ingroup i2cm
+ * @{
+ */
+
+///@cond
+// No Doxygen documentation for the items between here and endcond.
+/* **** Definitions **** */
+#ifndef MXC_I2CM_TX_TIMEOUT
+#define MXC_I2CM_TX_TIMEOUT 0x5000 /**< Master Transmit Timeout in number of repetitive attempts to receive an ACK/NACK or for a transmission to occur */
+#endif
+
+#ifndef MXC_I2CM_RX_TIMEOUT
+#define MXC_I2CM_RX_TIMEOUT 0x5000 /**< Master Receive Timeout in number of attempts to check FIFO for received data from a slave */
+#endif
+
+#define I2CM_READ_BIT 0x0001 /**< Bit location to specify a read for the I2C protocol */
+///@cond
+#define I2CM_FIFO_DEPTH_3Q ((3 * MXC_I2CM_FIFO_DEPTH) / 4)
+#define I2CM_FIFO_DEPTH_2Q (MXC_I2CM_FIFO_DEPTH / 2)
+
+//
+/* **** Globals **** */
+
+/* Clock divider lookup table */
+static const uint32_t clk_div_table[3][8] = {
+ /* I2CM_SPEED_100KHZ */
+ {
+ // 12000000
+ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 24000000
+ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 36000000 NOT SUPPORTED
+ 0,
+ // 48000000
+ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 60000000 NOT SUPPORTED
+ 0,
+ // 72000000 NOT SUPPORTED
+ 0,
+ // 84000000 NOT SUPPORTED
+ 0,
+ // 96000000
+ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ },
+ /* I2CM_SPEED_400KHZ */
+ {
+ // 12000000
+ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 24000000
+ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 36000000 NOT SUPPORTED
+ 0,
+ // 48000000
+ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ // 60000000 NOT SUPPORTED
+ 0,
+ // 72000000 NOT SUPPORTED
+ 0,
+ // 84000000 NOT SUPPORTED
+ 0,
+ // 96000000
+ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
+ (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
+ (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
+ },
+};
+
+// Saves the state of the non-blocking requests
+typedef enum {
+ I2CM_STATE_READING = 0,
+ I2CM_STATE_WRITING = 1
+} i2cm_state_t;
+
+typedef struct {
+ i2cm_req_t *req;
+ i2cm_state_t state;
+} i2cm_req_state_t;
+static i2cm_req_state_t states[MXC_CFG_I2CM_INSTANCES];
+
+/* **** Local Function Prototypes **** */
+
+static void I2CM_FreeCallback(int i2cm_num, int error);
+
+static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
+ uint8_t *data, uint32_t len);
+
+static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req);
+static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num);
+static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num);
+///@endcond
+//
+/* ************************************************************************* */
+int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed)
+{
+ int err, clki;
+
+ // Check the base pointer
+ MXC_ASSERT(MXC_I2CM_GET_IDX(i2cm) >= 0);
+
+ // Set system level configurations
+ if ((err = SYS_I2CM_Init(i2cm, sys_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ // Compute clock array index
+ clki = ((SYS_I2CM_GetFreq(i2cm) / 12000000) - 1);
+
+ // Get clock divider settings from lookup table
+ if ((speed == I2CM_SPEED_100KHZ) && (clk_div_table[I2CM_SPEED_100KHZ][clki] > 0)) {
+ i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_100KHZ][clki];
+
+ } else if ((speed == I2CM_SPEED_400KHZ) && (clk_div_table[I2CM_SPEED_400KHZ][clki] > 0)) {
+ i2cm->fs_clk_div = clk_div_table[I2CM_SPEED_400KHZ][clki];
+
+ } else {
+ // Requested speed is not achievable with the current clock setup
+ return E_NOT_SUPPORTED;
+ }
+
+ // Reset module
+ i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
+ i2cm->ctrl = 0;
+
+ // Set timeout to 255 ms and turn on the auto-stop option
+ i2cm->timeout = (MXC_F_I2CM_TIMEOUT_TX_TIMEOUT | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN);
+
+ // Enable tx_fifo and rx_fifo
+ i2cm->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm)
+{
+ int i2cm_num, err;
+
+ // Check the base pointer
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+ MXC_ASSERT(i2cm_num >= 0);
+
+ // Disable and clear interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+
+ // Call all of the pending callbacks for this I2CM
+ if(states[i2cm_num].req != NULL) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, E_SHUTDOWN);
+ }
+
+ // Clears system level configurations
+ if ((err = SYS_I2CM_Shutdown(i2cm)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+
+/* ************************************************************************* */
+int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
+ uint32_t cmd_len, uint8_t* data, uint32_t len)
+{
+ int i2cm_num;
+ int error = E_NO_ERROR;
+ int retval = E_NO_ERROR;
+ mxc_i2cm_fifo_regs_t *fifo;
+
+ if(data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the I2CM has been initialized
+ if(i2cm->ctrl == 0) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Lock this I2CM
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+ while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {}
+
+ // Get the FIFO pointer for this I2CM
+ fifo = MXC_I2CM_GET_FIFO(i2cm_num);
+
+ // Disable and clear the interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+
+ // Transmit the command if there is command data and length
+ if((cmd_data != NULL) && (cmd_len > 0)) {
+ retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0);
+ }
+
+ // Read data from the slave if we don't have any errors
+ if(retval == E_NO_ERROR) {
+ retval = I2CM_Rx(i2cm, fifo, addr, data, len);
+ }
+
+ // Wait for the transaction to complete
+ if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) {
+ retval = error;
+ }
+
+ // Unlock this I2CM
+ mxc_free_lock((uint32_t*)&states[i2cm_num].req);
+
+ if(retval != E_NO_ERROR) {
+ return retval;
+ }
+
+ return len;
+}
+
+/* ************************************************************************* */
+int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
+ uint32_t cmd_len, uint8_t* data, uint32_t len)
+{
+ int i2cm_num;
+ int error = E_NO_ERROR;
+ int retval = E_NO_ERROR;
+ mxc_i2cm_fifo_regs_t *fifo;
+
+ if(data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the I2CM has been initialized
+ if(i2cm->ctrl == 0) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Lock this I2CM
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+ while(mxc_get_lock((uint32_t*)&states[i2cm_num].req,1) != E_NO_ERROR) {}
+
+ // Get the FIFO pointer for this I2CM
+ fifo = MXC_I2CM_GET_FIFO(i2cm_num);
+
+ // Disable and clear the interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+
+ // Transmit the command if there is command data and length, don't send stop bit
+ if((cmd_data != NULL) && (cmd_len > 0)) {
+ retval = I2CM_Tx(i2cm, fifo, addr, cmd_data, cmd_len, 0);
+ }
+
+ // Write data to the slave, send the stop bit
+ if(retval == E_NO_ERROR) {
+ retval = I2CM_Tx(i2cm, fifo, addr, data, len, 1);
+ }
+
+ // Wait for the transaction to complete
+ if((error = I2CM_TxInProgress(i2cm)) != E_NO_ERROR) {
+ retval = error;
+ }
+
+ // Unlock this I2CM
+ mxc_free_lock((uint32_t*)&states[i2cm_num].req);
+
+ if(retval != E_NO_ERROR) {
+ return retval;
+ }
+
+ return len;
+}
+
+/* ************************************************************************* */
+int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req)
+{
+ int i2cm_num, error;
+
+ if(req->data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the I2CM has been initialized
+ if(i2cm->ctrl == 0) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(req->data_len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+
+ // Attempt to register this request
+ if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ states[i2cm_num].state = I2CM_STATE_READING;
+
+ // Clear the number of bytes counter
+ req->cmd_num = 0;
+ req->data_num = 0;
+
+ // Disable and clear the interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+
+ // Start the read
+ if((error = I2CM_ReadHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, error);
+ return error;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req)
+{
+ int i2cm_num, error;
+
+ if(req->data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the I2CM has been initialized
+ if(i2cm->ctrl == 0) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(req->data_len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+
+ // Attempt to register this request
+ if(mxc_get_lock((uint32_t*)&states[i2cm_num].req, (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ states[i2cm_num].state = I2CM_STATE_WRITING;
+
+ // Clear the number of bytes counter
+ req->cmd_num = 0;
+ req->data_num = 0;
+
+ // Disable and clear the interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+
+ // Start the Write
+ if((error = I2CM_WriteHandler(i2cm, req, i2cm_num)) != E_NO_ERROR) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, error);
+ return error;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_AbortAsync(i2cm_req_t *req)
+{
+ int i2cm_num;
+ mxc_i2cm_regs_t *i2cm;
+
+ // Find the request, set to NULL
+ for(i2cm_num = 0; i2cm_num < MXC_CFG_I2CM_INSTANCES; i2cm_num++)
+ {
+ if(req == states[i2cm_num].req) {
+
+ i2cm = MXC_I2CM_GET_I2CM(i2cm_num);
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, E_ABORT);
+
+ return E_NO_ERROR;
+ }
+ }
+
+ return E_BAD_PARAM;
+}
+
+/* ************************************************************************* */
+void I2CM_Handler(mxc_i2cm_regs_t *i2cm)
+{
+ uint32_t intfl;
+ int i2cm_num, error;
+
+ // Save and clear the interrupts
+ intfl = i2cm->intfl;
+ i2cm->intfl = intfl;
+
+ // Mask the disabled interrupts
+ intfl &= i2cm->inten;
+
+ i2cm_num = MXC_I2CM_GET_IDX(i2cm);
+
+ // Check for errors
+ if ((intfl & MXC_F_I2CM_INTFL_TX_NACKED) || (intfl & MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, E_COMM_ERR);
+ return;
+ }
+
+ if(intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, E_TIME_OUT);
+ return;
+ }
+
+ // Read or write
+ if(states[i2cm_num].state == I2CM_STATE_READING) {
+ if((error = I2CM_ReadHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, error);
+ return;
+ }
+
+ } else if(states[i2cm_num].state == I2CM_STATE_WRITING) {
+ if((error = I2CM_WriteHandler(i2cm, states[i2cm_num].req, i2cm_num)) != E_NO_ERROR) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, error);
+ return;
+ }
+ }
+
+ // Done with the transaction
+ if(intfl & MXC_F_I2CM_INTFL_TX_DONE) {
+ I2CM_Recover(i2cm);
+ I2CM_FreeCallback(i2cm_num, E_NO_ERROR);
+ }
+
+}
+
+/* ************************************************************************* */
+int I2CM_Busy(mxc_i2cm_regs_t *i2cm)
+{
+ // Check to see if there are any ongoing transactions
+ if((states[MXC_I2CM_GET_IDX(i2cm)].req == NULL) &&
+ !(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+
+ return E_NO_ERROR;
+ }
+
+ return E_BUSY;
+}
+
+/* ************************************************************************* */
+int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm)
+{
+ if(I2CM_Busy(i2cm) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Disable interrupts
+ i2cm->inten = 0;
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm)
+{
+ // If SCL is low, we don't have the bus
+ if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SCL_IN_VAL)) {
+ return E_BUSY;
+ }
+
+ // If SDA is low, we don't have the bus
+ if(!(i2cm->bb & MXC_F_I2CM_BB_BB_SDA_IN_VAL)) {
+ return E_BUSY;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static void I2CM_FreeCallback(int i2cm_num, int error)
+{
+ // Save the request
+ i2cm_req_t *temp_req = states[i2cm_num].req;
+
+ // Unlock this UART to write
+ mxc_free_lock((uint32_t*)&states[i2cm_num].req);
+
+ // Callback if not NULL
+ if(temp_req->callback != NULL) {
+ temp_req->callback(temp_req, error);
+ }
+}
+
+/* ************************************************************************* */
+void I2CM_Recover(mxc_i2cm_regs_t *i2cm)
+{
+ // Disable and clear interrupts
+ i2cm->inten = 0;
+ i2cm->intfl = i2cm->intfl;
+ i2cm->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
+ i2cm->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
+}
+
+/* ************************************************************************* */
+int I2CM_WriteTxFifo(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data)
+{
+ int32_t timeout = MXC_I2CM_TX_TIMEOUT;
+
+ // Read the TX FIFO to determine if it's full
+ do {
+
+ // Wait for the TX FIFO to have room and check for errors
+ if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED |
+ MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
+
+ return E_COMM_ERR;
+ }
+
+ if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) || !timeout--) {
+ return E_TIME_OUT;
+ }
+
+ } while (fifo->tx);
+
+ fifo->tx = data;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm)
+{
+ int32_t timeout = MXC_I2CM_TX_TIMEOUT;
+
+ while ((i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
+
+ if (i2cm->intfl & (MXC_F_I2CM_INTFL_TX_NACKED |
+ MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
+
+ I2CM_Recover(i2cm);
+ return E_COMM_ERR;
+ }
+
+ if((i2cm->intfl & MXC_F_I2CM_INTFL_TX_TIMEOUT) && !timeout--) {
+ I2CM_Recover(i2cm);
+ return E_TIME_OUT;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
+ const uint8_t *data, uint32_t len, uint8_t stop)
+{
+ uint32_t i;
+ int error;
+
+ // Write the address to the TXFIFO
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (addr << 1)))) != E_NO_ERROR) {
+ return error;
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+
+ // Fill the FIFO
+ for (i = 0; i < len; i++) {
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != E_NO_ERROR) {
+ return error;
+ }
+ }
+
+ // Send the stop condition
+ if(stop) {
+ if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
+ return error;
+ }
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static int I2CM_Rx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr,
+ uint8_t *data, uint32_t len)
+{
+ uint32_t i = len;
+ int32_t timeout;
+ uint16_t temp;
+ int error;
+
+ // Write the address to the TXFIFO
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
+ (addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) {
+
+ return error;
+ }
+
+ // Write to the TXFIFO the number of bytes we want to read
+ while(i > 256) {
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) {
+ return error;
+ }
+
+ i -= 256;
+ }
+
+ if(i > 1) {
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i-2)))) != E_NO_ERROR) {
+ return error;
+ }
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+
+
+ // NACK the last read byte
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) {
+ return error;
+ }
+
+ // Send the stop condition
+ if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
+ return error;
+ }
+
+ // Get the data from the RX FIFO
+ i = 0;
+ while (i < len) {
+
+ // Wait for there to be data in the RX FIFO
+ timeout = MXC_I2CM_RX_TIMEOUT;
+ while (!(i2cm->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
+ ((i2cm->bb & MXC_F_I2CM_BB_RX_FIFO_CNT) == 0)) {
+
+ if((timeout-- < 0) || (i2cm->trans & MXC_F_I2CM_TRANS_TX_TIMEOUT)) {
+ return E_TIME_OUT;
+ }
+
+ if (i2cm->trans & (MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED)) {
+ return E_COMM_ERR;
+ }
+ }
+ i2cm->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
+
+ // Save the data from the RX FIFO
+ temp = fifo->rx;
+ if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
+ continue;
+ }
+ data[i++] = (uint8_t)temp;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static int I2CM_CmdHandler(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, i2cm_req_t *req)
+{
+ int error;
+
+ // Start of the command
+ if(req->cmd_num == 0) {
+
+ // Write the address to the TXFIFO
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START | (req->addr << 1)))) != E_NO_ERROR) {
+ return error;
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+ }
+
+ // Write to the FIFO until it is full or we run out of command bytes
+ while((req->cmd_num < req->cmd_len) && (!fifo->tx)) {
+ fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->cmd_data[req->cmd_num++];
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static int I2CM_ReadHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num)
+{
+ int error, cmd_remain, data_remain;
+ uint16_t data;
+ uint32_t temp_len, inten;
+ mxc_i2cm_fifo_regs_t *fifo;
+
+ // Get the FIFO pointer for this I2CM
+ fifo = MXC_I2CM_GET_FIFO(i2cm_num);
+
+ cmd_remain = req->cmd_len - req->cmd_num;
+ data_remain = req->data_len - req->data_num;
+
+ // Process the command portion
+ if((cmd_remain) && (req->cmd_data != NULL)) {
+ if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) {
+ return error;
+ }
+
+ cmd_remain = req->cmd_len - req->cmd_num;
+ }
+
+ // Process the data portion
+ if((cmd_remain == 0) && (data_remain)) {
+
+ // Save the data from the RXFIFO
+ data = fifo->rx;
+ while((req->data_num < req->data_len) && !(data & MXC_S_I2CM_RSTLS_TAG_EMPTY)) {
+ req->data[req->data_num++] = data;
+ data = fifo->rx;
+ }
+
+ // Start of the data portion
+ if(req->data_num == 0) {
+
+ temp_len = req->data_len;
+
+ // Write the address to the TXFIFO
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
+ (req->addr << 1) | I2CM_READ_BIT))) != E_NO_ERROR) {
+
+ return error;
+ }
+
+ // Write to the TXFIFO the number of bytes we want to read
+ while(temp_len > 256) {
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != E_NO_ERROR) {
+ return error;
+ }
+
+ temp_len -= 256;
+ }
+
+ if(temp_len > 1) {
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (temp_len-2)))) != E_NO_ERROR) {
+ return error;
+ }
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+
+ // NACK the last read byte
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_RXDATA_NACK))) != E_NO_ERROR) {
+ return error;
+ }
+
+ // Send the stop condition
+ if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
+ return error;
+ }
+ }
+ }
+
+ // Enable the required interrupts
+ inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED |
+ MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT;
+
+ if (cmd_remain) {
+ inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY);
+ }
+
+ data_remain = req->data_len - req->data_num;
+ if (data_remain > I2CM_FIFO_DEPTH_3Q) {
+ inten |= MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL;
+
+ } else if (data_remain > I2CM_FIFO_DEPTH_2Q) {
+ inten |= MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL;
+
+ } else if (data_remain > 0) {
+ inten |= MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY;
+ }
+
+ i2cm->inten = inten;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static int I2CM_WriteHandler(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req, int i2cm_num)
+{
+ int error, cmd_remain, data_remain;
+ uint32_t inten;
+ mxc_i2cm_fifo_regs_t *fifo;
+
+ // Get the FIFO pointer for this I2CM
+ fifo = MXC_I2CM_GET_FIFO(i2cm_num);
+
+ cmd_remain = req->cmd_len - req->cmd_num;
+ data_remain = req->data_len - req->data_num;
+
+ // Process the command portion
+ if((cmd_remain) && (req->cmd_data != NULL)) {
+ if((error = I2CM_CmdHandler(i2cm, fifo, req)) != E_NO_ERROR) {
+ return error;
+ }
+
+ cmd_remain = req->cmd_len - req->cmd_num;
+ }
+
+ // Process the data portion
+ if((cmd_remain == 0) && (data_remain)) {
+
+ // Start of the data portion
+ if(req->data_num == 0) {
+
+ // Write the address to the TXFIFO
+ if((error = I2CM_WriteTxFifo(i2cm, fifo, (MXC_S_I2CM_TRANS_TAG_START |
+ (req->addr << 1)))) != E_NO_ERROR) {
+
+ return error;
+ }
+
+ // Start the transaction if it is not currently ongoing
+ if (!(i2cm->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+ i2cm->trans |= MXC_F_I2CM_TRANS_TX_START;
+ }
+ }
+
+ // Write bytes to the FIFO until it's full or we run out of bytes
+ while(req->data_num < req->data_len) {
+ fifo->tx = MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | req->data[req->data_num++];
+ }
+
+ // Send the stop condition
+ if ((error = I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP)) != E_NO_ERROR) {
+ return error;
+ }
+ }
+
+ // Enable the required interrupts
+ data_remain = req->data_len - req->data_num;
+ inten = MXC_F_I2CM_INTEN_TX_DONE | MXC_F_I2CM_INTEN_TX_NACKED |
+ MXC_F_I2CM_INTEN_TX_LOST_ARBITR | MXC_F_I2CM_INTEN_TX_TIMEOUT;
+
+ if(data_remain || cmd_remain) {
+ inten |= (MXC_F_I2CM_INTEN_TX_FIFO_EMPTY | MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY);
+ }
+ i2cm->inten = inten;
+
+ return E_NO_ERROR;
+}
+/**@} end of group i2cm */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cm.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,340 @@
+/**
+ * @file
+ * @brief I2CM (Inter-Integrated Circuit Master) function prototypes and
+ * data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24660 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _I2CM_H_
+#define _I2CM_H_
+
+/***** Includes *****/
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "i2cm_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @ingroup commperipherals
+ * @defgroup i2c_master_slave I2C
+ * @brief I2C Master and Slave Communications
+ */
+/**
+ * @ingroup i2c_master_slave
+ * @defgroup i2cm I2C Master
+ * @brief I2C Master
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type to select supported I2CM frequencies.
+ */
+typedef enum {
+ I2CM_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */
+ I2CM_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */
+} i2cm_speed_t;
+
+/**
+ * Structure type for an I2CM Transaction request.
+ */
+typedef struct i2cm_req i2cm_req_t;
+
+/**
+ * Function type for the I2C Master callback. The function declaration for the
+ * I2CM callback is:
+ * @code
+ * void callback(i2cm_req_t * req, int error_code);
+ * @endcode | | | | -----: |
+ * :----------------------------------------- | | @p req | Pointer to an
+ * #i2cm_req object representing the I2CM active transaction. | | @p error_code
+ * | An error code if the active transaction had a failure or #E_NO_ERROR if
+ * successful. |
+ *
+ * @addtogroup i2cm_async
+ * @{
+ */
+typedef void (*i2cm_callback_fn)(i2cm_req_t * req, int error_code);
+/**@}*/
+
+
+/**
+ * I2CM Transaction request structure.
+ * @note Only supports 7-bit addressing. Driver will shift the address and
+ * add the read bit when necessary.
+ */
+struct i2cm_req {
+ uint8_t addr; /**< 7-Bit unshifted address of the slave for communication. */
+ const uint8_t *cmd_data; /**< Pointer to a command data buffer to send to the slave before either a read or write transaction. */
+ uint32_t cmd_len; /**< Number of bytes in command. */
+ uint8_t *data; /**< Data to write or read. */
+ uint32_t data_len; /**< Length of data. */
+ uint32_t cmd_num; /**< Number of command bytes sent. */
+ uint32_t data_num; /**< Number of data bytes sent. */
+ i2cm_callback_fn callback; /**< Function pointer to a callback function. */
+};
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize the I2CM peripheral module.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ * @param sys_cfg Pointer to an I2CM configuration structure of type
+ * #sys_cfg_i2cm_t.
+ * @param speed I2CM bus speed, see #i2cm_speed_t.
+ *
+ * @return #E_NO_ERROR if initialized successfully, error if unsuccessful.
+ */
+int I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *sys_cfg, i2cm_speed_t speed);
+
+/**
+ * @brief Shutdown I2CM module.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ *
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ *
+ */
+int I2CM_Shutdown(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @defgroup i2cm_blocking I2CM Blocking Functions
+ * @{
+ */
+
+/**
+ * @brief Read I2CM data. Will block until transaction is complete.
+ *
+ * @note Command is an optional feature where the master will write the @c
+ * cmd_data before reading from the slave. If command is undesired,
+ * set the @c *cmd_data parameter to NULL and pass 0 for the @c
+ * cmd_len parameter.
+ * @note If there is a command, the master will send a repeated start
+ * sequence before attempting to read from the slave.
+ * @note This function blocks until the transaction has completed.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ * @param addr I2C address of the slave.
+ * @param cmd_data Data to write before reading.
+ * @param cmd_len Number of bytes to write before reading.
+ * @param data Where to store the data read.
+ * @param len Number of bytes to read.
+ *
+ * @return Number of bytes read if successful, error code if unsuccessful.
+ */
+int I2CM_Read(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
+ uint32_t cmd_len, uint8_t* data, uint32_t len);
+
+/**
+ * @brief Write data to a slave device.
+ *
+ * @note Command is an optional feature where the master will write the @c
+ * cmd_data before writing the @c data to the slave. If command is
+ * not needed, set the @c cmd_data to @c NULL and set @c cmd_len to
+ * 0. If there is a command, the master will send a repeated start
+ * sequence before attempting to read from the slave.
+ * @note This function blocks until the transaction has completed.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ * @param addr I2C address of the slave.
+ * @param cmd_data Data to write before writing data.
+ * @param cmd_len Number of bytes to write before writing data.
+ * @param data Data to be written.
+ * @param len Number of bytes to Write.
+ *
+ * @return Number of bytes writen if successful or an @ref MXC_Error_Codes
+ * "Error Code" if unsuccessful.
+ */
+int I2CM_Write(mxc_i2cm_regs_t *i2cm, uint8_t addr, const uint8_t *cmd_data,
+ uint32_t cmd_len, uint8_t* data, uint32_t len);
+/**@} end of i2cm_blocking functions */
+
+/**
+ * @defgroup i2cm_async I2CM Asynchrous Functions
+ * @{
+ */
+
+/**
+ * @brief Asynchronously read I2CM data.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ * @param req Pointer to an I2CM transaction request structure, see
+ * #i2cm_req.
+ *
+ * @return #E_NO_ERROR if everything is successful or an @ref
+ * MXC_Error_Codes "Error Code" if unsuccessful.
+ */
+int I2CM_ReadAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
+
+/**
+ * @brief Asynchronously write I2CM data.
+ *
+ * @param i2cm Pointer to the I2CM registers, see #mxc_i2cm_regs_t.
+ * @param req Pointer to an I2CM transaction request structure, see
+ * #i2cm_req.
+ *
+ * @return #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int I2CM_WriteAsync(mxc_i2cm_regs_t *i2cm, i2cm_req_t *req);
+
+/**
+ * @brief Abort asynchronous request.
+ * @param req Pointer to request for an I2CM transaction.
+ * @note Will call the callback for the request.
+ *
+ * @return #E_NO_ERROR if request aborted, error if unsuccessful.
+ */
+int I2CM_AbortAsync(i2cm_req_t *req);
+
+/**
+ * @brief I2CM interrupt handler.
+ *
+ * @details This function is an IRQ handler and will be called by the core if
+ * I2CM interrupts are enabled. Alternately, if the application is
+ * using asynchronous methods, this function can be periodically
+ * called by the application if the I2CM interrupts are disabled.
+ *
+ * @param i2cm Base address of the I2CM module.
+ */
+void I2CM_Handler(mxc_i2cm_regs_t *i2cm);
+/**@} end of i2cm_async */
+
+/**
+ * @brief Returns the status of the I2CM peripheral module.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ *
+ * @return #E_NO_ERROR if idle.
+ * @return #E_BUSY if in use.
+ */
+int I2CM_Busy(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @brief Attempt to prepare the I2CM for sleep.
+ * @details Checks for any ongoing transactions. Disables interrupts if the
+ * I2CM is idle.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ *
+ * @return #E_NO_ERROR if ready to sleep.
+ * @return #E_BUSY if the bus is not ready for sleep.
+ */
+int I2CM_PrepForSleep(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @brief Check the I2C bus to determine if any other masters are using the
+ * bus.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ *
+ * @return #E_NO_ERROR if SCL and SDA are high,
+ * @return #E_BUSY otherwise.
+ */
+int I2CM_BusCheck(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @brief Drain/Empty all of the data in the I2CM Receive FIFO.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ */
+__STATIC_INLINE void I2CM_DrainRX(mxc_i2cm_regs_t *i2cm)
+{
+ i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_RX_FIFO_EN);
+ i2cm->ctrl |= MXC_F_I2CM_CTRL_RX_FIFO_EN;
+}
+
+/**
+ * @brief Drain/Empty any data in the I2CM Transmit FIFO.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ */
+__STATIC_INLINE void I2CM_DrainTX(mxc_i2cm_regs_t *i2cm)
+{
+ i2cm->ctrl &= ~(MXC_F_I2CM_CTRL_TX_FIFO_EN);
+ i2cm->ctrl |= MXC_F_I2CM_CTRL_TX_FIFO_EN;
+}
+
+/**
+ * @brief Clear interrupt flags.
+ *
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ * @param mask Mask of I2CM interrupts to clear (1 to clear),
+ * @see I2CM_INTFL_Register for the interrupt flag masks.
+ */
+__STATIC_INLINE void I2CM_ClearFlags(mxc_i2cm_regs_t *i2cm, uint32_t mask)
+{
+ i2cm->intfl = mask;
+}
+
+/**
+ * @brief Gets the current I2CM interrupt flags.
+ * @param i2cm Pointer to the I2CM register structure, see
+ * #mxc_i2cm_regs_t.
+ *
+ * @return The currently set interrupt flags, @see I2CM_INTFL_Register
+ * for the interrupt flag masks.
+ */
+__STATIC_INLINE unsigned I2CM_GetFlags(mxc_i2cm_regs_t *i2cm)
+{
+ return(i2cm->intfl);
+}
+/**@} end of group i2cm */
+
+void I2CM_Recover(mxc_i2cm_regs_t *i2cm);
+int I2CM_WriteTxFifo(mxc_i2cm_regs_t *regs, mxc_i2cm_fifo_regs_t *fifo, const uint16_t data);
+int I2CM_TxInProgress(mxc_i2cm_regs_t *i2cm);
+int I2CM_Tx(mxc_i2cm_regs_t *i2cm, mxc_i2cm_fifo_regs_t *fifo, uint8_t addr, const uint8_t *data, uint32_t len, uint8_t stop);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2CM_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,209 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the I2CS
+ * (Inter-Integrated Circuit Slave) peripheral module.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 18:05:59 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24332 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_assert.h"
+#include "mxc_errors.h"
+#include "mxc_sys.h"
+#include "i2cs.h"
+
+/**
+ * @ingroup i2cs
+ * @{
+ */
+/* **** Definitions **** */
+
+/* **** Globals ***** */
+
+
+// No Doxygen documentation for the items between here and endcond.
+/* Clock divider lookup table */
+static const uint32_t clk_div_table[2][8] = {
+ /* I2CS_SPEED_100KHZ */
+ {
+ // 12000000
+ (6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 24000000
+ (12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 36000000 NOT SUPPORTED
+ 0,
+ // 48000000
+ (24 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 60000000 NOT SUPPORTED
+ 0,
+ // 72000000 NOT SUPPORTED
+ 0,
+ // 84000000 NOT SUPPORTED
+ 0,
+ // 96000000
+ (48 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)
+ },
+ /* I2CS_SPEED_400KHZ */
+ {
+ // 12000000
+ (2 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 24000000
+ (3 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 36000000 NOT SUPPORTED
+ 0,
+ // 48000000
+ (6 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS),
+ // 60000000 NOT SUPPORTED
+ 0,
+ // 72000000 NOT SUPPORTED
+ 0,
+ // 84000000 NOT SUPPORTED
+ 0,
+ // 96000000
+ (12 << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)
+ },
+};
+
+
+static void (*callbacks[MXC_CFG_I2CS_INSTANCES][MXC_CFG_I2CS_BUFFER_SIZE])(uint8_t);
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed,
+ uint16_t address, i2cs_addr_t addr_len)
+{
+ int err, i, i2cs_index;
+
+ i2cs_index = MXC_I2CS_GET_IDX(i2cs);
+ MXC_ASSERT(i2cs_index >= 0);
+
+ // Set system level configurations
+ if ((err = SYS_I2CS_Init(i2cs, sys_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ // Compute clock array index
+ int clki = ((SYS_I2CS_GetFreq(i2cs) / 12000000) - 1);
+
+ // Get clock divider settings from lookup table
+ if ((speed == I2CS_SPEED_100KHZ) && (clk_div_table[I2CS_SPEED_100KHZ][clki] > 0)) {
+ i2cs->clk_div = clk_div_table[I2CS_SPEED_100KHZ][clki];
+ } else if ((speed == I2CS_SPEED_400KHZ) && (clk_div_table[I2CS_SPEED_400KHZ][clki] > 0)) {
+ i2cs->clk_div = clk_div_table[I2CS_SPEED_400KHZ][clki];
+ } else {
+ MXC_ASSERT_FAIL();
+ }
+
+ // Clear the interrupt callbacks
+ for(i = 0; i < MXC_CFG_I2CS_BUFFER_SIZE; i++) {
+ callbacks[i2cs_index][i] = NULL;
+ }
+
+ // Reset module
+ i2cs->dev_id = MXC_F_I2CS_DEV_ID_SLAVE_RESET;
+ i2cs->dev_id = ((((address >> 0) << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)
+ & MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID) | addr_len);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs)
+{
+ int err;
+
+ // Disable and clear interrupts
+ i2cs->inten = 0;
+ i2cs->intfl = i2cs->intfl;
+
+ // clears system level configurations
+ if ((err = SYS_I2CS_Shutdown(i2cs)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void I2CS_Handler(mxc_i2cs_regs_t *i2cs)
+{
+ uint32_t intfl;
+ uint8_t i;
+ int i2cs_index = MXC_I2CS_GET_IDX(i2cs);
+
+ // Save and clear the interrupt flags
+ intfl = i2cs->intfl;
+ i2cs->intfl = intfl;
+
+ // Process each interrupt
+ for(i = 0; i < 32; i++) {
+ if(intfl & (0x1 << i)) {
+ if(callbacks[i2cs_index][i] != NULL) {
+ callbacks[i2cs_index][i](i);
+ }
+ }
+ }
+
+}
+
+/* ************************************************************************* */
+void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback)
+{
+ int i2cs_index = MXC_I2CS_GET_IDX(i2cs);
+
+ // Make sure we don't overflow
+ MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
+
+ if(callback != NULL) {
+ // Save the callback address
+ callbacks[i2cs_index][addr] = callback;
+
+ // Clear and Enable the interrupt for the given byte
+ i2cs->intfl = (0x1 << addr);
+ i2cs->inten |= (0x1 << addr);
+ } else {
+ // Disable and clear the interrupt
+ i2cs->inten &= ~(0x1 << addr);
+ i2cs->intfl = (0x1 << addr);
+
+ // Clear the callback address
+ callbacks[i2cs_index][addr] = NULL;
+ }
+}
+
+/**@} end of group i2cs*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/i2cs.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,215 @@
+/**
+ * @file
+ * @brief I2CS (Inter-Integrated Circuit Slave) function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24661 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _I2CS_H_
+#define _I2CS_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "mxc_assert.h"
+#include "i2cs_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup i2c_master_slave
+ * @defgroup i2cs I2C Slave
+ * @brief I2C Slave (I2CS) API
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * Internal buffer size for storing I2C Slave Messages
+ */
+#define I2CS_BUFFER_SIZE 32
+
+/**
+ * Enumeration type to select supported I2CS frequencies.
+ */
+typedef enum {
+ I2CS_SPEED_100KHZ = 0, /**< Use to select a bus communication speed of 100 kHz. */
+ I2CS_SPEED_400KHZ = 1 /**< Use to select a bus communication speed of 400 kHz. */
+} i2cs_speed_t;
+
+/**
+ * Enumeration type to select the I2CS addressing mode.
+ */
+typedef enum {
+ I2CS_ADDR_8 = 0, /**< Sets the slave address mode to 8-bits (7-bits address plus read/write bit). */
+ I2CS_ADDR_10 = MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE /**< Sets the slave address mode to 10-bits. */
+} i2cs_addr_t;
+
+/**
+ * Type alias for an I2CS callback function that will be called when a given byte is updated by the Master, see I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback).
+ * @details The function prototype for implementing callback_fn is:
+ * @code
+ * void func(uint8_t addr);
+ * @endcode
+ */
+typedef void (*i2cs_callback_fn)(uint8_t error_code);
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize I2CS module.
+ * @param i2cs Pointer to I2CS regs.
+ * @param sys_cfg Pointer to I2CS system configuration, see
+ * #sys_cfg_i2cs_t.
+ * @param speed I2CS frequency.
+ * @param address I2CS address.
+ * @param addr_len I2CS address length.
+ * @return #E_NO_ERROR if everything is successful or an
+ * @ref MXC_Error_Codes "error code" if unsuccessful.
+ *
+ */
+int I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *sys_cfg, i2cs_speed_t speed, uint16_t address, i2cs_addr_t addr_len);
+
+/**
+ * @brief Shutdown I2CS module.
+ * @param i2cs Pointer to I2CS regs.
+ * @return #E_NO_ERROR if everything is successful or an
+ * @ref MXC_Error_Codes "error code" if unsuccessful.
+ */
+int I2CS_Shutdown(mxc_i2cs_regs_t *i2cs);
+
+/**
+ * @brief I2CS interrupt handler.
+ * @details This function should be called by the application from the
+ * interrupt handler if I2CS interrupts are enabled. Alternately,
+ * this function can be periodically called by the application if
+ * I2CS interrupts are disabled.
+ *
+ * @param i2cs Pointer to I2CS regs.
+ */
+void I2CS_Handler(mxc_i2cs_regs_t *i2cs);
+
+/**
+ * @brief Register a callback that is triggered by an update of a specified
+ * byte.
+ * @details Registering a callback causes the slave to interrupt when the
+ * master has updated a specified byte.
+ *
+ * @param i2cs Pointer to the I2CS register structure, see
+ * #mxc_i2cs_regs_t.
+ * @param addr Index to trigger a call to the #i2cs_callback_fn.
+ * @param callback callback function of type #i2cs_callback_fn to be called
+ * when the addr being written by the master matches \c addr.
+ */
+void I2CS_RegisterCallback(mxc_i2cs_regs_t *i2cs, uint8_t addr, i2cs_callback_fn callback);
+
+/**
+ * @brief Write I2CS data to a given byte.
+ * @details The slave has a buffer of registers that the external master can
+ * read. Use this function to write data into a specified
+ * address/index.
+ *
+ * @param i2cs Pointer to I2CS regs.
+ * @param addr Address/Index to write.
+ * @param data Data to be written.
+ */
+__STATIC_INLINE void I2CS_Write(mxc_i2cs_regs_t *i2cs, uint8_t addr, uint8_t data)
+{
+ // Make sure we don't overflow
+ MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
+ i2cs->data_byte[addr] = ((i2cs->data_byte[addr] & ~MXC_F_I2CS_DATA_BYTE_DATA_FIELD) |
+ (data << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS));
+}
+
+/**
+ * @brief Read I2CS data from a given address .
+ * @details The slave has a buffer of registers that the external master can
+ * read. Use this function to read the data from the registers.
+ *
+ * @param i2cs Pointer to I2CS regs.
+ * @param addr Address/Index to read from.
+ *
+ * @return Data contained in requested @c addr register.
+ */
+__STATIC_INLINE uint8_t I2CS_Read(mxc_i2cs_regs_t *i2cs, uint8_t addr)
+{
+ // Make sure we don't overflow
+ MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
+ return ((i2cs->data_byte[addr] & MXC_F_I2CS_DATA_BYTE_DATA_FIELD) >>
+ MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS);
+}
+
+/**
+ * @brief Set the given index to read only (RO).
+ * @details This index will be flagged as read only. The slave will NACK the
+ * master if it attempts to write this location. Multiple calls with
+ * different index/address values will yield multiple read-only
+ * locations within the slave register set.
+ *
+ * @param i2cs Pointer to I2CS regs.
+ * @param addr Address/Index of the byte to set to RO.
+ */
+__STATIC_INLINE void I2CS_SetRO(mxc_i2cs_regs_t *i2cs, uint8_t addr)
+{
+ // Make sure we don't overflow
+ MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
+ i2cs->data_byte[addr] |= MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL;
+}
+
+/**
+ * @brief Sets the given address to R/W.
+ * @param i2cs Pointer to I2CS regs.
+ * @param addr Index to start clearing RO flag.
+ */
+__STATIC_INLINE void I2CS_ClearRO(mxc_i2cs_regs_t *i2cs, uint8_t addr)
+{
+ // Make sure we don't overflow
+ MXC_ASSERT(addr < MXC_CFG_I2CS_BUFFER_SIZE);
+ i2cs->data_byte[addr] &= ~MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL;
+}
+
+/**@} end of group i2cs */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _I2CS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,77 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the
+ * Instruction Cache Controller.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:45:25 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24331 $
+ *
+ *************************************************************************** */
+
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "icc.h"
+/**
+ * @ingroup icc
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+void ICC_Enable(void)
+{
+ /* Invalidate cache and wait until ready */
+ MXC_ICC->invdt_all = 1;
+ while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+
+ /* Enable cache */
+ MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+ /* Must invalidate a second time for proper use */
+ MXC_ICC->invdt_all = 1;
+}
+
+/* ************************************************************************* */
+void ICC_Disable(void)
+{
+ MXC_ICC->ctrl_stat &= ~MXC_F_ICC_CTRL_STAT_ENABLE;
+}
+/**@} end of group icc */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/icc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,83 @@
+/**
+ * @file
+ * @brief Instruction Cache Controller function prototypes and data types.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:01:16 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24662 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ICC_H_
+#define _ICC_H_
+
+/* **** Includes **** */
+#include "icc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Doxy group definition for this peripheral module */
+
+/**
+ * @ingroup sysconfig
+ * @defgroup icc Instruction Cache Controller (ICC)
+ * @{
+ */
+/**
+ * @brief Enable and flush the instruction cache controller.
+ */
+void ICC_Enable(void);
+
+/**
+ * @brief Disable the instruction cache controller.
+ */
+void ICC_Disable(void);
+
+/**
+ * @brief Flush the instruction cache controller.
+ */
+__STATIC_INLINE void ICC_Flush()
+{
+ ICC_Disable();
+ ICC_Enable();
+}
+/**@} end of group icc */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICC_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,59 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $
+ * $Revision: 22543 $
+ *
+ ******************************************************************************/
+
+#include <stddef.h>
+#include "mxc_config.h"
+#include "ioman.h"
+
+/******************************************************************************/
+int IOMAN_Config(const ioman_cfg_t *cfg)
+{
+ if(cfg == NULL) {
+ return E_NULL_PTR;
+ }
+
+ if (*cfg->ack_reg != cfg->req_val.value) {
+ /* Request pin mapping */
+ *cfg->req_reg = cfg->req_val.value;
+
+ /* Check for acknowledgment */
+ if (*cfg->ack_reg != cfg->req_val.value) {
+ return E_BUSY;
+ }
+ }
+
+ return E_NO_ERROR;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/ioman.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,323 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-04-27 15:26:08 -0500 (Wed, 27 Apr 2016) $
+ * $Revision: 22543 $
+ *
+ ******************************************************************************/
+
+/**
+ * @file ioman.h
+ * @brief IOMAN provides IO Management to the device. The functions in this
+ * API enable requesting port pin assignment and release for all peripherals
+ * with external I/O. Port pin mapping support is included for peripherals
+ * that can support more than one pin mapping in a package.
+ */
+
+#ifndef _IOMAN_H_
+#define _IOMAN_H_
+
+#include "mxc_config.h"
+#include "ioman_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***** Definitions *****/
+
+/** @brief Aliases for IOMAN package mapping field values. Refer to the
+ * User's Guide for pinouts for each mapping.
+ */
+typedef enum {
+ IOMAN_MAP_UNUSED = 0, /**< Pin is not used */
+ IOMAN_MAP_A = 0, /**< Pin Mapping A */
+ IOMAN_MAP_B = 1, /**< Pin Mapping B */
+ IOMAN_MAP_C = 2, /**< Pin Mapping C */
+ IOMAN_MAP_D = 3, /**< Pin Mapping D */
+ IOMAN_MAP_E = 4, /**< Pin Mapping E */
+ IOMAN_MAP_F = 5, /**< Pin Mapping F */
+ IOMAN_MAP_G = 6 /**< Pin Mapping G */
+}
+ioman_map_t;
+
+/** @brief Typing of IOMAN Request and Acknowledge register fields */
+typedef union {
+ uint32_t value;
+ mxc_ioman_spix_req_t spix; /**< SPIX IOMAN configuration struct */
+ mxc_ioman_uart0_req_t uart; /**< UART IOMAN configuration struct, see mxc_ioman_uart0_req_t */
+ mxc_ioman_i2cm0_req_t i2cm0; /**< I<sup>2</sup>C Master 0 IOMAN configuration struct, see mxc_ioman_i2cm0_req_t */
+ mxc_ioman_i2cm1_req_t i2cm1; /**< I<sup>2</sup>C Master 1 IOMAN configuration struct, see mxc_ioman_i2cm1_req_t */
+ mxc_ioman_i2cm2_req_t i2cm2; /**< I<sup>2</sup>C Master 2 IOMAN configuration struct, see mxc_ioman_i2cm2_req_t */
+ mxc_ioman_i2cs_req_t i2cs; /**< I<sup>2</sup>C Slave IOMAN configuration struct, see mxc_ioman_i2cs_req_t */
+ mxc_ioman_spim0_req_t spim0; /**< SPI Master 0 IOMAN configuration struct, see mxc_ioman_spim0_req_t */
+ mxc_ioman_spim1_req_t spim1; /**< SPI Master 1 IOMAN configuration struct, see mxc_ioman_spim1_req_t */
+ mxc_ioman_spim2_req_t spim2; /**< SPI Master 2 IOMAN configuration struct, see mxc_ioman_spim1_req_t */
+ mxc_ioman_spib_req_t spib; /**< SPI Bridge IOMAN configuration struct, see mxc_ioman_spib_req_t */
+ mxc_ioman_owm_req_t owm; /**< 1-Wire Master IOMAN configuration struct, see mxc_ioman_owm_req_t */
+} ioman_req_t;
+
+/** @brief IOMAN configuration object */
+typedef struct {
+ volatile uint32_t *req_reg; /** Pointer to an IOMAN request register */
+ volatile uint32_t *ack_reg; /** Pointer to an IOMAN acknowledge register */
+ ioman_req_t req_val; /** IOMAN request register value, see ioman_req_t */
+} ioman_cfg_t;
+
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief Configure the IO Manager using the specified configuration object.
+ * @param cfg IOMAN configuration object
+ * @returns E_NO_ERROR Configuration successful
+ */
+int IOMAN_Config(const ioman_cfg_t *cfg);
+
+/**
+ * @brief Create an IOMAN configuration object for the SPI XIP module. Call IOMAN_Config with this object.
+ * @param core Request (1) or release (0) SPIX core external pins
+ * @param ss0 Request (1) or release (0) slave select 0 active out
+ * @param ss1 Request (1) or release (0) slave select 1 active out
+ * @param ss2 Request (1) or release (0) slave select 2 active out
+ * @param quad Request (1) or release (0) quad IO
+ * @param fast Request (1) or release (0) fast mode
+ * @returns io_man_cfg_t IOMAN configuration object for the SPI XIP module.
+ */
+ioman_cfg_t IOMAN_SPIX(int core, int ss0, int ss1, int ss2, int quad, int fast);
+
+/**
+ * @brief Create an IOMAN configuration object for a UART module. Call IOMAN_Config with this object.
+ * @param idx Index of the UART module
+ * @param io_map Set the pin mapping for RX/TX pins, see ioman_map_t
+ * @param cts_map Set the pin mapping for CTS pin, see ioman_map_t
+ * @param rts_map Set the pin mapping for RTS pin, see ioman_map_t
+ * @param io_en Request (1) or release (0) RX and TX pins
+ * @param cts_en Request (1) or release (0) CTS pin
+ * @param rts_en Request (1) or release (0) RTS pin
+ * @returns ioman_cfg_t IOMAN configuration object for the UART module
+ */
+ioman_cfg_t IOMAN_UART(int idx, ioman_map_t io_map, ioman_map_t cts_map, ioman_map_t rts_map, int io_en, int cts_en, int rts_en);
+
+/**
+ * @brief Create an IOMAN configuration object for the I2CM0 module. Call IOMAN_Config with this object.
+ * @param map Set the pin mapping for I2CM1 module, see ioman_map_t
+ * @param io_en Request (1) or release (0) the I/O for the I2CM0 module
+ * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
+ */
+ioman_cfg_t IOMAN_I2CM0(ioman_map_t map, int io_en);
+
+/**
+ * @brief Create an IOMAN configuration object for the I2CM1 module. Call IOMAN_Config with this object.
+ * @param map Set the pin mapping for I2CM1 module, see ioman_map_t
+ * @param io_en Request (1) or release (0) the I/O for the I2CM1 module
+ * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
+ */
+ioman_cfg_t IOMAN_I2CM1(ioman_map_t map, int io_en);
+
+/**
+ * @brief Create an IOMAN configuration object for the I2CM2 module. Call IOMAN_Config with this object.
+ * @param map Set the pin mapping for I2CM2 module, see ioman_map_t
+ * @param io_en Request (1) or release (0) the I/O for the I2CM2 module
+ * @returns ioman_cfg_t IOMAN configuration object for the I2CM0 module.
+ */
+ioman_cfg_t IOMAN_I2CM2(ioman_map_t map, int io_en);
+
+/**
+ * @brief Create an IOMAN configuration object for an I2C slave module. Call IOMAN_Config with this object.
+ * @param map Select the pin mapping for all configured pins, see ioman_map_t
+ * @param io_en Request (1) or release (0) the I/O for this module
+ * @returns ioman_cfg_t IOMAN configuration object for the I2CS module
+ */
+ioman_cfg_t IOMAN_I2CS(ioman_map_t map, int io_en);
+
+/**
+ * @brief Create an IOMAN configuration object for a SPI Master (SPIM) module. Call IOMAN_Config with this object.
+ * @param io_en Request (1) or release (0) the core IO for the module
+ * @param ss0 Request (1) or release (0) slave select 0
+ * @param ss1 Request (1) or release (0) slave select 1
+ * @param ss2 Request (1) or release (0) slave select 2
+ * @param ss3 Request (1) or release (0) slave select 3
+ * @param ss4 Request (1) or release (0) slave select 4
+ * @param quad Request (1) or release (0) quad IO
+ * @param fast Request (1) or release (0) fast mode
+ * @returns ioman_cfg_t IOMAN configuration object for an SPIM0 module
+ */
+ioman_cfg_t IOMAN_SPIM0(int io_en, int ss0, int ss1, int ss2, int ss3, int ss4, int quad, int fast);
+
+/**
+ * @brief Create an IOMAN configuration object for a SPIM module. Call IOMAN_Config with this object.
+ * @param io_en Request (1) or release (0) the core IO for the module
+ * @param ss0 Request (1) or release (0) slave select 0
+ * @param ss1 Request (1) or release (0) slave select 1
+ * @param ss2 Request (1) or release (0) slave select 2
+ * @param quad Request (1) or release (0) quad IO
+ * @param fast Request (1) or release (0) fast mode
+ * @returns ioman_cfg_t IOMAN configuration object for the SPIM1 module.
+ */
+ioman_cfg_t IOMAN_SPIM1(int io_en, int ss0, int ss1, int ss2, int quad, int fast);
+
+/**
+ * @brief Create an IOMAN configuration object for a SPI module. Call IOMAN_Config with this object.
+ * @param map Select the pin mapping, see ioman_map_t
+ * @param io_en Request (1) or release (0) the core IO for the module
+ * @param ss0 Request (1) or release (0) slave select 0
+ * @param ss1 Request (1) or release (0) slave select 1
+ * @param ss2 Request (1) or release (0) slave select 2
+ * @param sr0 Request (1) or release (0) slave ready 0
+ * @param sr1 Request (1) or release (0) slave ready 1
+ * @param quad Request (1) or release (0) quad IO
+ * @param fast Request (1) or release (0) fast mode
+ * @returns ioman_cfg_t IOMAN configuration object for the SPIM2 module
+ */
+ioman_cfg_t IOMAN_SPIM2(ioman_map_t map, int io_en, int ss0, int ss1, int ss2, int sr0, int sr1, int quad, int fast);
+
+/**
+ * @brief Create an IOMAN configuration object for the SPI Bridge module. Call IOMAN_Config with this object.
+ * @param io_en Request (1) or release (0) the core IO for the module
+ * @param quad Request (1) or release (0) quad IO
+ * @param fast Request (1) or release (0) fast mode
+ * @returns ioman_cfg_t IOMAN configuration object for the SPIB module
+ */
+ioman_cfg_t IOMAN_SPIB(int io_en, int quad, int fast);
+
+/**
+ * @brief Create an IOMAN configuration object for the 1-Wire Master module. Call IOMAN_Config with this object.
+ * @param io_en Request (1) or release (0) the core IO for the module
+ * @param epu Request (1) or release (0) external pullup
+ * @returns ioman_cfg_t IOMAN configuration object for the OWM module
+ */
+ioman_cfg_t IOMAN_OWM(int io_en, int epu);
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* All the function prototypes above are implemented as macros below. The
+ * above prototypes are for simplicity in doxygen.
+ */
+#define IOMAN_SPIX(c, ss0, ss1, ss2, q, f) { \
+ .req_reg = &MXC_IOMAN->spix_req, \
+ .ack_reg = &MXC_IOMAN->spix_ack, \
+ .req_val.spix = { .core_io_req = c, \
+ .ss0_io_req = ss0, \
+ .ss1_io_req = ss1, \
+ .ss2_io_req = ss2, \
+ .quad_io_req = q, \
+ .fast_mode = f } }
+
+#define IOMAN_UART(i, im, cm, rm, ien, cen, ren) { \
+ .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_req) + (i * 2*sizeof(uint32_t))), \
+ .ack_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->uart0_ack) + (i * 2*sizeof(uint32_t))), \
+ .req_val.uart = { .io_map = im, \
+ .cts_map = cm, \
+ .rts_map = rm, \
+ .io_req = ien, \
+ .cts_io_req = cen, \
+ .rts_io_req = ren } }
+
+#define IOMAN_I2CM0(m, ien ) { \
+ .req_reg = ((&MXC_IOMAN->i2cm0_req)), \
+ .ack_reg = ((&MXC_IOMAN->i2cm0_ack)), \
+ .req_val.i2cm0 = { .mapping_req = ien } }
+
+#define IOMAN_I2CM1(m, ien) { \
+ .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm1_req)), \
+ .ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm1_ack)), \
+ .req_val.i2cm1 = { .io_sel = m, \
+ .mapping_req = ien } }
+
+#define IOMAN_I2CM2(m, ien) { \
+ .req_reg = (uint32_t*)((unsigned int)(&MXC_IOMAN->i2cm2_req)), \
+ .ack_reg = (uint32_t*)((unsigned int) (&MXC_IOMAN->i2cm2_ack)), \
+ .req_val.i2cm2 = { .io_sel = m, \
+ .mapping_req = ien } }
+
+#define IOMAN_I2CS(m, ien) { \
+ .req_reg = &MXC_IOMAN->i2cs_req, \
+ .ack_reg = &MXC_IOMAN->i2cs_ack, \
+ .req_val.i2cs = { .io_sel = m, \
+ .mapping_req = ien } }
+
+#define IOMAN_SPIM0(io, ss0, ss1, ss2, ss3, ss4, q, f) { \
+ .req_reg = &MXC_IOMAN->spim0_req, \
+ .ack_reg = &MXC_IOMAN->spim0_ack, \
+ .req_val.spim0 = { .core_io_req = io, \
+ .ss0_io_req = ss0, \
+ .ss1_io_req = ss1, \
+ .ss2_io_req = ss2, \
+ .ss3_io_req = ss3, \
+ .ss4_io_req = ss4, \
+ .quad_io_req = q, \
+ .fast_mode = f } }
+
+#define IOMAN_SPIM1(io, ss0, ss1, ss2, q, f) { \
+ .req_reg = &MXC_IOMAN->spim1_req, \
+ .ack_reg = &MXC_IOMAN->spim1_ack, \
+ .req_val.spim1 = { .core_io_req = io, \
+ .ss0_io_req = ss0, \
+ .ss1_io_req = ss1, \
+ .ss2_io_req = ss2, \
+ .quad_io_req = q, \
+ .fast_mode = f } }
+
+#define IOMAN_SPIM2(m, io, ss0, ss1, ss2, sr0, sr1, q, f) { \
+ .req_reg = &MXC_IOMAN->spim2_req, \
+ .ack_reg = &MXC_IOMAN->spim2_ack, \
+ .req_val.spim2 = { .mapping_req = m, \
+ .core_io_req = io, \
+ .ss0_io_req = ss0, \
+ .ss1_io_req = ss1, \
+ .ss2_io_req = ss2, \
+ .sr0_io_req = sr0, \
+ .sr1_io_req = sr1, \
+ .quad_io_req = q, \
+ .fast_mode = f } }
+
+#define IOMAN_SPIB(io, q, f) { \
+ .req_reg = &MXC_IOMAN->spib_req, \
+ .ack_reg = &MXC_IOMAN->spib_ack, \
+ .req_val.spib = { .core_io_req = io, \
+ .quad_io_req = q, \
+ .fast_mode = f } }
+
+#define IOMAN_OWM(io, p) { \
+ .req_reg = &MXC_IOMAN->owm_req, \
+ .ack_reg = &MXC_IOMAN->owm_ack, \
+ .req_val.owm = { .mapping_req = io, \
+ .epu_io_req = p } }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IOMAN_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,424 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-22 12:05:05 -0500 (Tue, 22 Mar 2016) $
+ * $Revision: 22032 $
+ * ******************************************************************************/
+
+/***** Includes *****/
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "lp.h"
+#include "ioman_regs.h"
+
+/***** Definitions *****/
+
+#ifndef LP0_PRE_HOOK
+#define LP0_PRE_HOOK
+#endif
+#ifndef LP1_PRE_HOOK
+#define LP1_PRE_HOOK
+#endif
+#ifndef LP1_POST_HOOK
+#define LP1_POST_HOOK
+#endif
+
+/***** Globals *****/
+
+/***** Functions *****/
+
+/* Clear all wake-up configuration */
+void LP_ClearWakeUpConfig(void)
+{
+ /* Clear GPIO WUD event and configuration registers, globally */
+ MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
+ MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
+
+ /* Mask off all wake-up sources */
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP |
+ MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
+ MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP |
+ MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 |
+ MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
+ MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP |
+ MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER);
+}
+
+/* Clear wake-up flags */
+unsigned int LP_ClearWakeUpFlags(void)
+{
+ unsigned int flags_tmp;
+
+ /* Get flags */
+ flags_tmp = MXC_PWRSEQ->flags;
+
+ /* Clear GPIO WUD event registers, globally */
+ MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH);
+
+ /* Clear power sequencer event flags (write-1-to-clear) */
+ MXC_PWRSEQ->flags = flags_tmp;
+
+ return flags_tmp;
+}
+
+/* Configure the selected pin for wake-up detect */
+int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd)
+{
+ int result = E_NO_ERROR;
+ unsigned int pin;
+
+ /* Check that port and pin are within range */
+ MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
+ MXC_ASSERT(gpio->mask > 0);
+
+ /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
+ if (gpio->port < 4) {
+ MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
+ if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ } else if (gpio->port < 8) {
+ MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
+ if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ } else {
+ MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
+ if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ }
+
+ if (result == E_NO_ERROR) {
+
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+
+ if (gpio->mask & (1 << pin)) {
+
+ /* Enable modifications to WUD configuration */
+ MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
+
+ /* Select pad in WUD control */
+ /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
+ MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
+
+ /* Configure sense level on this pad */
+ MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
+
+ if (act_high) {
+ /* Select active high with PULSE0 (backwards from what you'd expect) */
+ MXC_PWRMAN->wud_pulse0 = 1;
+ } else {
+ /* Select active low with PULSE1 (backwards from what you'd expect) */
+ MXC_PWRMAN->wud_pulse1 = 1;
+ }
+
+ /* Clear out the pad mode */
+ MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
+
+ /* Select this pad to have the wake-up function enabled */
+ MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
+
+ /* Activate with PULSE1 */
+ MXC_PWRMAN->wud_pulse1 = 1;
+
+ if (wk_pu_pd != LP_NO_PULL) {
+ /* Select weak pull-up/pull-down on this pad while in LP1 */
+ MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
+
+ /* Again, logic is opposite of what you'd expect */
+ if (wk_pu_pd == LP_WEAK_PULL_UP) {
+ MXC_PWRMAN->wud_pulse0 = 1;
+ } else {
+ MXC_PWRMAN->wud_pulse1 = 1;
+ }
+ }
+
+ /* Disable configuration each time, required by hardware */
+ MXC_PWRMAN->wud_ctrl = 0;
+ }
+ }
+ }
+
+ /* Disable configuration */
+ MXC_IOMAN->wud_req0 = 0;
+ MXC_IOMAN->wud_req1 = 0;
+ MXC_IOMAN->wud_req2 = 0;
+
+ /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
+
+ return result;
+}
+
+uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
+{
+ uint8_t gpioWokeUp = 0;
+
+ /* Check that port and pin are within range */
+ MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
+ MXC_ASSERT(gpio->mask > 0);
+
+ /* Ports 0-3 are wud_seen0, while 4-7 are wud_seen1, 8 is wud_seen2 */
+ if (gpio->port < 4) {
+ gpioWokeUp = (MXC_PWRMAN->wud_seen0 >> (gpio->port << 3)) & gpio->mask;
+ } else if (gpio->port < 8) {
+ gpioWokeUp = (MXC_PWRMAN->wud_seen1 >> ((gpio->port - 4) << 3)) & gpio->mask;
+ } else {
+ gpioWokeUp = (MXC_PWRMAN->wud_seen2 >> ((gpio->port - 8) << 3)) & gpio->mask;
+ }
+
+ return gpioWokeUp;
+}
+
+int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio)
+{
+ int result = E_NO_ERROR;
+ unsigned int pin;
+
+ /* Check that port and pin are within range */
+ MXC_ASSERT(gpio->port < MXC_GPIO_NUM_PORTS);
+ MXC_ASSERT(gpio->mask > 0);
+
+ /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1, 8 is controlled by wud_req2 */
+ if (gpio->port < 4) {
+ MXC_IOMAN->wud_req0 |= (gpio->mask << (gpio->port << 3));
+ if (MXC_IOMAN->wud_ack0 != MXC_IOMAN->wud_req0) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ } else if (gpio->port < 8) {
+ MXC_IOMAN->wud_req1 |= (gpio->mask << ((gpio->port - 4) << 3));
+ if (MXC_IOMAN->wud_ack1 != MXC_IOMAN->wud_req1) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ } else {
+ MXC_IOMAN->wud_req2 |= (gpio->mask << ((gpio->port - 8) << 3));
+ if (MXC_IOMAN->wud_ack2 != MXC_IOMAN->wud_req2) { /* Order of volatile access does not matter here */
+ result = E_BUSY;
+ }
+ }
+
+ if (result == E_NO_ERROR) {
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
+ if (gpio->mask & (1 << pin)) {
+
+ /* Enable modifications to WUD configuration */
+ MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
+
+ /* Select pad in WUD control */
+ /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
+ MXC_PWRMAN->wud_ctrl |= (gpio->port * 8) + pin;
+
+ /* Clear out the pad mode */
+ MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
+
+ /* Select the wake up function on this pad */
+ MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
+
+ /* disable wake up with PULSE0 */
+ MXC_PWRMAN->wud_pulse0 = 1;
+
+ /* Disable configuration each time, required by hardware */
+ MXC_PWRMAN->wud_ctrl = 0;
+ }
+ }
+ }
+
+ /* Disable configuration */
+ MXC_IOMAN->wud_req0 = 0;
+ MXC_IOMAN->wud_req1 = 0;
+ MXC_IOMAN->wud_req2 = 0;
+
+ return result;
+}
+
+int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en)
+{
+ /* Enable or disable wake on USB plug-in */
+ if (plug_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP;
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP);
+ }
+
+ /* Enable or disable wake on USB unplug */
+ if (unplug_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP;
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
+ }
+
+ return E_NO_ERROR;
+}
+
+int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en,
+ unsigned int prescale_cmp_en, unsigned int rollover_en)
+{
+ /* Note: MXC_PWRSEQ.pwr_misc[0] should be set to have the mask be active low */
+
+ /* Enable or disable wake on RTC Compare 0 */
+ if (comp0_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR0;
+
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR0);
+ }
+
+ /* Enable or disable wake on RTC Compare 1 */
+ if (comp1_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_CMPR1;
+
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_CMPR1);
+ }
+
+ /* Enable or disable wake on RTC Prescaler */
+ if (prescale_cmp_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP;
+
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP);
+ }
+
+ /* Enable or disable wake on RTC Rollover */
+ if (rollover_en) {
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER;
+
+ } else {
+ MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER);
+ }
+
+ return E_NO_ERROR;
+}
+
+
+int LP_EnterLP2(void)
+{
+ /* Clear SLEEPDEEP bit to avoid LP1/LP0 entry*/
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Go into LP2 mode and wait for an interrupt to wake the processor */
+ __WFI();
+
+ return E_NO_ERROR;
+}
+
+int LP_EnterLP1(void)
+{
+ /* Turn on retention controller */
+ MXC_PWRSEQ->retn_ctrl0 |= MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN;
+
+ /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
+
+ /* Set the LP1 select bit so CPU goes to LP1 during SLEEPDEEP */
+ MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;
+
+ /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP1_PRE_HOOK;
+
+ /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
+ MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
+
+ /* Dummy read to make sure SSB writes are complete */
+ MXC_PWRSEQ->reg0;
+
+ /* Enter LP1 -- sequence is per instructions from ARM, Ltd. */
+ __SEV();
+ __WFE();
+ __WFE();
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP1_POST_HOOK;
+
+ /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
+
+ /* Clear SLEEPDEEP bit */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+ /* No error */
+ return E_NO_ERROR;
+}
+
+void LP_EnterLP0(void)
+{
+ /* Disable interrupts, ok not to save state as exit LP0 is a reset */
+ __disable_irq();
+
+ /* Clear the firstboot bit, which is generated by a POR event and locks out LPx modes */
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT);
+
+ /* Turn off retention controller */
+ MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN);
+
+ /* Turn off retention regulator */
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
+
+ /* LP0 ONLY to eliminate ~50nA of leakage on VDD12 */
+ MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
+
+ /* Clear the LP1 select bit so CPU goes to LP0 during SLEEPDEEP */
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_LP1);
+
+ /* The SLEEPDEEP bit will cause a WFE() to trigger LP0/LP1 (depending on ..._REG0_PWR_LP1 state) */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Performance-measurement hook, may be defined as nothing */
+ LP0_PRE_HOOK;
+
+ /* Freeze GPIO using MBUS so that it doesn't change while digital core is alseep */
+ MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE;
+
+ /* Dummy read to make sure SSB writes are complete */
+ MXC_PWRSEQ->reg0;
+
+ /* Go into LP0 -- sequence is per instructions from ARM, Ltd. */
+ __SEV();
+ __WFE();
+ __WFE();
+
+ /* Catch the case where this code does not properly sleep */
+ /* Unfreeze the GPIO by clearing MBUS_GATE (always safe to do) */
+ MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
+ MXC_ASSERT_FAIL();
+ while (1) {
+ __NOP();
+ }
+
+ /* Does not actually return */
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/lp.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,185 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-21 09:04:59 -0500 (Mon, 21 Mar 2016) $
+ * $Revision: 22006 $
+ *
+ ******************************************************************************/
+
+/**
+ * @file lp.h
+ * @brief This is the high level API for the Lower Power
+ */
+
+#ifndef _LP_H_
+#define _LP_H_
+
+#include "gpio.h"
+#include "pwrman_regs.h"
+#include "pwrseq_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***** Definitions *****/
+/**
+ * @brief Enumerations for pull-up and pull-downs
+ *
+ */
+typedef enum {
+ LP_WEAK_PULL_DOWN = -1,
+ LP_NO_PULL = 0,
+ LP_WEAK_PULL_UP = 1
+}
+lp_pu_pd_select_t;
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief Gets the first boot flag
+ *
+ * @returns 0 if FIRST_BOOT was not set, or 1 if FIRST_BOOT was set
+ */
+__STATIC_INLINE unsigned int LP_IsFirstBoot()
+{
+ return ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) >> MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS);
+}
+
+/**
+ * @brief Clears the first boot flag
+ *
+ */
+__STATIC_INLINE void LP_ClearFirstBoot()
+{
+ MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;
+}
+
+/**
+ * @brief Determines of program woke up from LP0
+ *
+ * @returns 0 if not woken up from LP0, or 1 if woken from LP0
+ */
+__STATIC_INLINE unsigned int LP_IsLP0WakeUp()
+{
+ //POR should be set and first boot clear
+ if((MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR) &&
+ ((MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT) == 0))
+ return 1;
+ else
+ return 0;
+
+}
+
+__STATIC_INLINE unsigned int LP_GetWakeUpFlags(void)
+{
+ return MXC_PWRSEQ->flags;
+}
+/**
+ * @brief Clear ALL wake-up configuration on all pins. Disables wake-up entirely.
+ */
+void LP_ClearWakeUpConfig(void);
+
+/**
+ * @brief Read wake-up flags, clear flags, and return to caller.
+ * @returns Wake-up flags from Power Sequencer
+ */
+unsigned int LP_ClearWakeUpFlags(void);
+
+/**
+ * @brief This function configures one GPIO pin to wake the processor from LP0 or LP1.
+ * It is not used for LP2 wake-up, as normal GPIO interrupt processing is active in that mode.
+ * @param gpio GPIO pointer describing the port and pin for selected wake-up source
+ * @param act_high If non-zero, the signal is configured for active high wake-up. Otherwise, active low.
+ * @param wk_pu_pd Selection for the 1 Meg ohm pull-up or pull-down on this pin, see #lp_pu_pd_select_t
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_pu_pd_select_t wk_pu_pd);
+
+/**
+ * @brief Clear the wake-up configuration on one specific GPIO pin
+ * @param gpio GPIO pointer describing the port and pin for selected wake-up source
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio);
+
+/**
+ * @brief Check if a specific gpio triggered the wake up
+ * @param gpio GPIO pointer describing the port and pin(s)
+ * @returns 0 = gpio passed in did not trigger a wake up
+ * nonzero = at least one of the gpio passed in triggered a wake up
+ * the bit set represents which pin is the wake up source
+ */
+uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
+
+/**
+ * @brief Wake on USB plug or unplug
+ * @param plug_en set to 1 to enable wake-up when USB VBUS is detected
+ * @param unplug_en set to 1 to enable wake-up when USB VBUS disappears
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_ConfigUSBWakeUp(unsigned int plug_en, unsigned int unplug_en);
+
+/**
+ * @brief Wake on any enabled event signal from RTC
+ * @param comp0_en set to 1 to enable wake-up when RTC Comparison 0 is set
+ * @param comp1_en set to 1 to enable wake-up when RTC Comparison 1 is set
+ * @param prescale_cmp_en set to 1 to enable wake-up when RTC Prescaler Compare is set
+ * @param rollover_en set to 1 to enable wake-up when RTC Roll-over is set
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_ConfigRTCWakeUp(unsigned int comp0_en, unsigned int comp1_en, unsigned int prescale_cmp_en, unsigned int rollover_en);
+
+/**
+ * @brief Enter LP2 power-saving mode
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_EnterLP2(void);
+
+/**
+ * @brief Enter LP1 mode, which saves CPU state and SRAM. Execution resumes after this call.
+ * @note Interrupts should be globally disabled before calling this function.
+ * @returns #E_NO_ERROR on success, error if unsuccessful.
+ */
+int LP_EnterLP1(void);
+
+/**
+ * @brief Enter the lowest-possible power mode, known as LP0. SRAM contents are lost.
+ * Waking up from LP0 is like a system reset. This function does not return.
+ * @note Interrupts are globally disabled upon entering this function.
+ */
+void LP_EnterLP0(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LP_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,236 @@
+/**
+ * @file
+ * @brief Modular Arithmetic Accelerator (MAA) API Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "maa.h"
+
+/**
+ * @ingroup maa
+ * @{
+ */
+
+///@cond
+#define maa_is_running() (MXC_MAA->ctrl & MXC_F_MAA_CTRL_START ? 1 : 0)
+
+/**
+ * Macro that translates from #mxc_maa_reg_select_t to a pointer for MAA memory operations.
+ */
+#define UMAA_REGFILE_TO_ADDR(base, x) ((base + (MXC_MAA_HALF_SIZE * x)))
+
+/**
+ * Macro that adjusts the pointer so that it is pointing to the last 32-bit word in the maa (sub-)segment
+ */
+#define UMAA_ADDR_INDEX_LAST_32BIT(x) ((uint8_t *)x + (MXC_MAA_HALF_SIZE-4))
+///@endcond
+
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_Init(void)
+{
+ SYS_MAA_Init();
+
+ return MXC_E_MAA_OK;
+}
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_WipeRAM(void)
+{
+ /* Check for running MAA */
+ if (maa_is_running()) {
+ return MXC_E_MAA_ERR;
+ }
+
+ /* Clear register files */
+ memset((void *)MXC_MAA_MEM->seg0, 0, sizeof(MXC_MAA_MEM->seg0));
+ memset((void *)MXC_MAA_MEM->seg1, 0, sizeof(MXC_MAA_MEM->seg1));
+ memset((void *)MXC_MAA_MEM->seg2, 0, sizeof(MXC_MAA_MEM->seg2));
+ memset((void *)MXC_MAA_MEM->seg3, 0, sizeof(MXC_MAA_MEM->seg3));
+ memset((void *)MXC_MAA_MEM->seg4, 0, sizeof(MXC_MAA_MEM->seg4));
+ memset((void *)MXC_MAA_MEM->seg5, 0, sizeof(MXC_MAA_MEM->seg5));
+
+ return MXC_E_MAA_OK;
+}
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_Load(mxc_maa_reg_select_t regfile, const uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag)
+{
+ uint32_t *maaptr;
+ uint32_t fill;
+ unsigned int zerotmp;
+
+ if ((regfile > MXC_E_REG_51) || (size > MXC_MAA_REG_SIZE)) {
+ /* Out of range */
+ return MXC_E_MAA_ERR;
+ }
+
+ if (flag == MXC_MAA_F_MEM_REVERSE) {
+ /* This is not currently implemented */
+ return MXC_E_MAA_ERR;
+ }
+
+ maaptr = (uint32_t *)UMAA_REGFILE_TO_ADDR(MXC_BASE_MAA_MEM, regfile);
+
+ /*
+ * MAA (sub-)segments must be loaded with zero pad to a 64-bit boundary, or the "garbage bits"
+ * will case erroneous results.
+ */
+ /* Find the ceiling for the closest 64-bit boundary based on the selected MAWS */
+ zerotmp = (((MXC_MAA->maws & MXC_F_MAA_MAWS_MODLEN) >> MXC_F_MAA_MAWS_MODLEN_POS) + 63) & 0xfc0;
+ /* Convert to bytes */
+ zerotmp /= 8;
+
+ /* Fill uMAA memory in long word sized chunks */
+ while (size > 3) {
+ *maaptr++ = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
+ data += 4;
+ size -= 4;
+ zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0;
+ }
+
+ /* Remainder */
+ if (size) {
+ fill = data[0];
+ fill |= ((size > 1) ? (data[1] << 8) : 0);
+ fill |= ((size > 2) ? (data[2] << 16) : 0);
+ *maaptr++ = fill;
+
+ /* We just filled 4 bytes in this section */
+ zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0;
+ }
+
+ /* Wipe the remaining "garbage bits" */
+ while (zerotmp) {
+ *maaptr++ = 0;
+ zerotmp = (zerotmp > 4) ? (zerotmp - 4) : 0;
+ }
+
+ return MXC_E_MAA_OK;
+}
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_Unload(mxc_maa_reg_select_t regfile, uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag)
+{
+ uint32_t *maaptr;
+ uint32_t fill;
+
+ if ((regfile > MXC_E_REG_51) || (size > MXC_MAA_REG_SIZE)) {
+ /* Out of range */
+ return MXC_E_MAA_ERR;
+ }
+
+ if (flag == MXC_MAA_F_MEM_REVERSE) {
+ /* This is not currently implemented */
+ return MXC_E_MAA_ERR;
+ }
+
+ maaptr = (uint32_t *)UMAA_REGFILE_TO_ADDR(MXC_BASE_MAA_MEM, regfile);
+
+ /* Unload uMAA memory in long word sized chunks */
+ while (size > 3) {
+ fill = *maaptr++;
+ data[0] = fill & 0xff;
+ data[1] = (fill >> 8) & 0xff;
+ data[2] = (fill >> 16) & 0xff;
+ data[3] = (fill >> 24) & 0xff;
+ data += 4;
+ size -= 4;
+ }
+
+ /* Remainder */
+ if (size) {
+ fill = *maaptr;
+ data[0] = fill & 0xff;
+ if (size > 1) {
+ data[1] = (fill >> 8) & 0xff;
+ }
+ if (size > 2) {
+ data[2] = (fill >> 16) & 0xff;
+ }
+ }
+
+ return MXC_E_MAA_OK;
+}
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_Run(mxc_maa_operation_t op,
+ mxc_maa_reg_select_t al, mxc_maa_reg_select_t bl,
+ mxc_maa_reg_select_t rl, mxc_maa_reg_select_t tl)
+{
+ if (maa_is_running()) {
+ /* Attempt to start the MAA while already running */
+ return MXC_E_MAA_ERR;
+ }
+
+ /* Clear out any previous flags */
+ MXC_MAA->ctrl = 0x00000020;
+
+ /* Construct memory segment selections, select operation, and start the uMAA */
+ MXC_MAA->ctrl = (((al << MXC_F_MAA_CTRL_SEG_A_POS) & MXC_F_MAA_CTRL_SEG_A) |
+ ((bl << MXC_F_MAA_CTRL_SEG_B_POS) & MXC_F_MAA_CTRL_SEG_B) |
+ ((rl << MXC_F_MAA_CTRL_SEG_RES_POS) & MXC_F_MAA_CTRL_SEG_RES) |
+ ((tl << MXC_F_MAA_CTRL_SEG_TMP_POS) & MXC_F_MAA_CTRL_SEG_TMP) |
+ ((op << MXC_F_MAA_CTRL_OPSEL_POS) & MXC_F_MAA_CTRL_OPSEL) |
+ MXC_F_MAA_CTRL_START);
+
+ /* Blocking wait for uMAA to complete. */
+ while ((MXC_MAA->ctrl & MXC_F_MAA_CTRL_IF_DONE) == 0);
+
+ if (MXC_MAA->ctrl & MXC_F_MAA_CTRL_IF_ERROR) {
+ /* MAA signaled error */
+ return MXC_E_MAA_ERR;
+ }
+
+ return MXC_E_MAA_OK;
+}
+
+/* ************************************************************************* */
+mxc_maa_ret_t MAA_SetWordSize(unsigned int len)
+{
+ if ((len > MXC_MAA_REG_SIZE_BITS) || maa_is_running()) {
+ return MXC_E_MAA_ERR;
+ }
+
+ /* Set bit length for calculation, and disable endian swap */
+ MXC_MAA->maws = ((len << MXC_F_MAA_MAWS_MODLEN_POS) & MXC_F_MAA_MAWS_MODLEN);
+
+ return MXC_E_MAA_OK;
+}
+/**@} end of ingroup maa */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/maa.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,224 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the Modular Math
+ * Accelerator (MAA) module.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:20:13 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24665 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MAA_H
+#define _MAA_H
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#include "maa_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup maa MAA
+ * @details The API only supports synchronous operations due to the sensitive
+ * nature of the input and output data.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Definition for the maximum MAA register size on this device in bytes, 128.
+ */
+#define MXC_MAA_REG_SIZE 0x80
+/**
+ * Definition for the maximum MAA register size on this device in bits, 1024.
+ */
+#define MXC_MAA_REG_SIZE_BITS (MXC_MAA_REG_SIZE << 3)
+
+/**
+ * @def Sub-register ("half size"), allowing 2x more operands in MAA at a time when MAWS <= MAX_SIZE/2
+ */
+#define MXC_MAA_HALF_SIZE (MXC_MAA_REG_SIZE/2)
+
+/** Flags for MAA_Load() and MAA_Unload() */
+#define MXC_MAA_F_MEM_VERBATIM 0
+/** Flags for MAA_Load() and MAA_Unload() */
+#define MXC_MAA_F_MEM_REVERSE 1
+
+/**
+ * Enumeration type for Segment and Sub-segment selection
+ */
+/* Warning: Do not change the assigned numbers/ordering without associated changes to UMAA_REGFILE_TO_ADDR(x) */
+typedef enum {
+ /* Register names when MAWS > 512 */
+ MXC_E_REG_0 = 0, /**< Register MXC_E_REG_0: If MAA_MAWS > 512 use this register name. */
+ MXC_E_REG_1 = 2, /**< Register MXC_E_REG_1: If MAA_MAWS > 512 use this register name. */
+ MXC_E_REG_2 = 4, /**< Register MXC_E_REG_2: If MAA_MAWS > 512 use this register name. */
+ MXC_E_REG_3 = 6, /**< Register MXC_E_REG_3: If MAA_MAWS > 512 use this register name. */
+ MXC_E_REG_4 = 8, /**< Register MXC_E_REG_4: If MAA_MAWS > 512 use this register name. */
+ MXC_E_REG_5 = 10, /**< Register MXC_E_REG_5: If MAA_MAWS > 512 use this register name. */
+ /* Register names when MAWS < 512 */
+ MXC_E_REG_00 = 0, /**< Register MXC_E_REG_00: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_01 = 1, /**< Register MXC_E_REG_01: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_10 = 2, /**< Register MXC_E_REG_10: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_11 = 3, /**< Register MXC_E_REG_11: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_20 = 4, /**< Register MXC_E_REG_20: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_21 = 5, /**< Register MXC_E_REG_21: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_30 = 6, /**< Register MXC_E_REG_30: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_31 = 7, /**< Register MXC_E_REG_31: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_40 = 8, /**< Register MXC_E_REG_40: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_41 = 9, /**< Register MXC_E_REG_41: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_50 = 10, /**< Register MXC_E_REG_50: If MAA_MAWS < 512 this is the register name. */
+ MXC_E_REG_51 = 11 /**< Register MXC_E_REG_51: If MAA_MAWS < 512 this is the register name. */
+} mxc_maa_reg_select_t;
+
+/**
+ * Enumeration type for MAA operation selection.
+ */
+typedef enum {
+ MXC_E_MAA_EXP = 0, /**< Exponentiate */
+ MXC_E_MAA_SQR = 1, /**< Square */
+ MXC_E_MAA_MUL = 2, /**< Multiply */
+ MXC_E_MAA_SQRMUL = 3, /**< Square followed by Multiply */
+ MXC_E_MAA_ADD = 4, /**< Addition */
+ MXC_E_MAA_SUB = 5 /**< Subtraction */
+} mxc_maa_operation_t;
+
+/**
+ * Enumeration type to set special flags for loading & unloading data.
+ */
+typedef enum {
+
+ MXC_E_MAA_VERBATIM = 0, /**< Copy bytes without reversal and right-justification */
+ MXC_E_MAA_REVERSE /**< Reverse bytes and right-justify (bytes are loaded at the highest address, then descending) */
+} mxc_maa_endian_select_t;
+
+/**
+ * Enumeration type for MAA module specific return codes.
+ */
+typedef enum {
+ MXC_E_MAA_ERR = -1, /**< Error */
+ MXC_E_MAA_OK = 0, /**< No Error */
+ MXC_E_MAA_BUSY /**< MAA engine busy, try again later */
+} mxc_maa_ret_t;
+
+/**
+ * @brief Initialize the required clocks and enable the MAA peripheral
+ * module.
+ * @retval #MXC_E_MAA_ERR on error.
+ * @retval #MXC_E_MAA_BUSY if the MAA is busy.
+ * @retval #MXC_E_MAA_OK if the MAA is initialized successfully.
+ */
+mxc_maa_ret_t MAA_Init(void);
+
+/**
+ * @brief Erase all MAA register RAM
+ * @retval #MXC_E_MAA_ERR on error.
+ * @retval #MXC_E_MAA_BUSY if the MAA is busy.
+ * @retval #MXC_E_MAA_OK if the MAA is initialized successfully.
+ */
+mxc_maa_ret_t MAA_WipeRAM(void);
+
+
+/**
+ * @brief Load the selected MAA register.
+ *
+ * @param regfile Selects the register to load.
+ * @param data Pointer to a data buffer to load into the register.
+ * @param size Size of the data to load.
+ * @param flag Reverse the data so that it will unload properly on
+ * little endian machines, see #mxc_maa_endian_select_t.
+ *
+ * @return #MXC_E_MAA_ERR if any parameter out of range.
+ * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible.
+ * @return #MXC_E_MAA_OK if the selected register is loaded correctly.
+ */
+mxc_maa_ret_t MAA_Load(mxc_maa_reg_select_t regfile, const uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag);
+
+/**
+ * @brief Unload (copy from) the selected MAA register
+ *
+ * @param regfile Selects the register to unload.
+ * @param data Pointer to a buffer to store the unloaded data.
+ * @param size Maximum size of the data to unload.
+ * @param flag Reverse the data so that it will unload properly on
+ * little endian machines, see #mxc_maa_endian_select_t.
+ * @return #MXC_E_MAA_ERR if any parameter out of range.
+ * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible.
+ * @return #MXC_E_MAA_OK if the requested register data is copied correctly
+ * to @p data.
+ */
+mxc_maa_ret_t MAA_Unload(mxc_maa_reg_select_t regfile, uint8_t *data, unsigned int size, mxc_maa_endian_select_t flag);
+
+/**
+ * @brief Execute an MAA operation specified.
+ *
+ * @param op Operation to perform, see #mxc_maa_operation_t.
+ * @param al Segment to use for operand A, see #mxc_maa_reg_select_t.
+ * @param bl Segment to use for operand B.
+ * @param rl Segment which will hold result R after the operation is
+ * complete.
+ * @param tl Segment to use for temporary storage T.
+ *
+ * @return #MXC_E_MAA_ERR if any parameter out of range.
+ * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible.
+ * @return #MXC_E_MAA_OK if the operation completed.
+ */
+mxc_maa_ret_t MAA_Run(mxc_maa_operation_t op, \
+ mxc_maa_reg_select_t al, mxc_maa_reg_select_t bl, \
+ mxc_maa_reg_select_t rl, mxc_maa_reg_select_t tl);
+
+/**
+ * @brief Set the bit length of the modulus.
+ *
+ * @param len Modulus size in bits (ie. \f$ ln_2(modulus) \f$ )
+ *
+ * @return #MXC_E_MAA_ERR if any parameter out of range.
+ * @return #MXC_E_MAA_BUSY if MAA registers are not currently accessible.
+ * @return #MXC_E_MAA_OK if the length is set as requested.
+ */
+mxc_maa_ret_t MAA_SetWordSize(unsigned int len);
+
+/**@} end of group maa*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,60 @@
+/**
+ * @file
+ * @brief Debug Assertion source file.
+ */
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:40:22 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24671 $
+ *
+ *************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+
+/**
+ * @ingroup MXC_Assertions
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals *****/
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+__weak void mxc_assert(const char *expr, const char *file, int line)
+{
+ while(1) {}
+}
+/**@} end of ingroup MXC_Assertions*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_assert.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,108 @@
+/**
+ * @file
+ * @brief Assertion checks for debugging.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24663 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_ASSERT_H_
+#define _MXC_ASSERT_H_
+
+/* **** Includes **** */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup sysconfig
+ * @defgroup MXC_Assertions Assertion Checks for Debugging
+ * @brief Assertion checks for debugging.
+ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ * defined.
+ * @{
+ */
+/* **** Definitions **** */
+
+#ifdef MXC_ASSERT_ENABLE
+/**
+ * Macro that checks the expression for true and generate an assertion.
+ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ * defined.
+ */
+#define MXC_ASSERT(expr) \
+if (!(expr)) \
+{ \
+ mxc_assert(#expr, __FILE__, __LINE__); \
+}
+/**
+ * Macro that generates an assertion with the message "FAIL".
+ * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
+ * defined.
+ */
+#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
+#else
+#define MXC_ASSERT(expr)
+#define MXC_ASSERT_FAIL()
+#endif
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Assert an error when the given expression fails during debugging.
+ * @param expr String with the expression that failed the assertion.
+ * @param file File containing the failed assertion.
+ * @param line Line number for the failed assertion.
+ * @note This is defined as a weak function and can be overridden at the
+ * application layer to print the debugging information.
+ * @code
+ * printf("%s, file: %s, line %d\n", expr, file, line);
+ * @endcode
+ */
+void mxc_assert(const char *expr, const char *file, int line);
+
+/**@} end of group MXC_Assertions*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_ASSERT_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_config.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,43 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ + * $Revision: 21838 $ + * + ******************************************************************************/ + +#ifndef _MXC_CONFIG_H +#define _MXC_CONFIG_H + +#include "mxc_device.h" +#include "mxc_errors.h" + +#endif /* _CONFIG_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_errors.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,96 @@
+/**
+ * @file
+ * @brief List of common error return codes for Maxim Integrated libraries.
+*/
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24663 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _ERRORS_H_
+#define _ERRORS_H_
+
+/**
+ * @ingroup sysconfig
+ * @defgroup MXC_Error_Codes Common Error Codes
+ * @brief A list of common error codes used by the API.
+ * @note A Negative Error Convention is used to avoid conflict with
+ * positive Non-Error returns.
+ * @{
+ */
+
+/**
+ * No Error
+ */
+#define E_NO_ERROR 0
+/** No Error, success */
+#define E_SUCCESS 0
+/** Pointer is NULL */
+#define E_NULL_PTR -1
+/** No such device */
+#define E_NO_DEVICE -2
+/** Parameter not acceptable */
+#define E_BAD_PARAM -3
+/** Value not valid or allowed */
+#define E_INVALID -4
+/** Module not initialized */
+#define E_UNINITIALIZED -5
+/** Busy now, try again later */
+#define E_BUSY -6
+/** Operation not allowed in current state */
+#define E_BAD_STATE -7
+/** Generic error */
+#define E_UNKNOWN -8
+/** General communications error */
+#define E_COMM_ERR -9
+/** Operation timed out */
+#define E_TIME_OUT -10
+/** Expected response did not occur */
+#define E_NO_RESPONSE -11
+/** Operations resulted in unexpected overflow */
+#define E_OVERFLOW -12
+/** Operations resulted in unexpected underflow */
+#define E_UNDERFLOW -13
+/** Data or resource not available at this time */
+#define E_NONE_AVAIL -14
+/** Event was shutdown */
+#define E_SHUTDOWN -15
+/** Event was aborted */
+#define E_ABORT -16
+/** The requested operation is not supported */
+#define E_NOT_SUPPORTED -17
+/**@} end of MXC_Error_Codes group */
+
+#endif /* _ERRORS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,114 @@
+/**
+ * @file
+ * @brief Exclusive access lock utility functions.
+*/
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:16:20 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24663 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_LOCK_H_
+#define _MXC_LOCK_H_
+
+/***** Includes *****/
+#include "mxc_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup sysconfig
+ * @defgroup mxc_lock_utilities Lock functions for Exclusive Access
+ * @brief Lock functions to obtain and release a variable for exclusive
+ * access. These functions are marked interrupt safe if they are
+ * interrupt safe.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Attempts to acquire the lock.
+ * @details This in an interrupt safe function that can be used as a mutex.
+ * The lock variable must remain in scope until the lock is
+ * released. Will not block if another thread has already acquired
+ * the lock.
+ * @param lock Pointer to variable that is used for the lock.
+ * @param value Value to be place in the lock. Can not be 0.
+ *
+ * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
+ */
+__STATIC_INLINE int mxc_get_lock(uint32_t *lock, uint32_t value)
+{
+ do {
+
+ // Return if the lock is taken by a different thread
+ if(__LDREXW((volatile unsigned long *)lock) != 0) {
+ return E_BUSY;
+ }
+
+ // Attempt to take the lock
+ } while(__STREXW(value, (volatile unsigned long *)lock) != 0);
+
+ // Do not start any other memory access until memory barrier is complete
+ __DMB();
+
+ return E_NO_ERROR;
+}
+
+/**
+ * @brief Free the given lock.
+ * @param[in,out] lock Pointer to the variable used for the lock. When the lock
+ * is free, the value pointed to by @p lock is set to zero.
+ */
+__STATIC_INLINE void mxc_free_lock(uint32_t *lock)
+{
+ // Ensure memory operations complete before releasing lock
+ __DMB();
+ *lock = 0;
+}
+
+/**@} end of group mxc_lock_utilities */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_LOCK_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,832 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-06-17 12:59:44 -0500 (Fri, 17 Jun 2016) $
+ * $Revision: 23365 $
+ *
+ ******************************************************************************/
+
+#include <stddef.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "ioman.h"
+#include "clkman.h"
+#include "pwrseq_regs.h"
+#include "pwrman_regs.h"
+#include "spix_regs.h"
+#include "trim_regs.h"
+
+/***** Definitions *****/
+#define SYS_RTC_CLK 32768UL
+
+/******************************************************************************/
+uint32_t SYS_GetFreq(uint32_t clk_scale)
+{
+ uint32_t freq;
+ unsigned int clkdiv;
+
+ if (clk_scale == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
+ freq = 0;
+ } else {
+ clkdiv = 1 << (clk_scale - 1);
+ freq = SystemCoreClock / clkdiv;
+ }
+
+ return freq;
+}
+
+/******************************************************************************/
+uint32_t SYS_CPU_GetFreq(void)
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_CPU));
+}
+
+/******************************************************************************/
+int SYS_ADC_Init(void)
+{
+ /* Power up the ADC AFE, enable clocks */
+ MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE;
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_AES_Init(void)
+{
+ /* Set up clocks for AES block */
+ /* Enable crypto ring oscillator, which is used by all TPU components (AES, uMAA, etc.) */
+ CLKMAN_CryptoClockEnable(1);
+
+ /* Change prescaler to /1 */
+ CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_AES, CLKMAN_SCALE_DIV_1);
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_GPIO_Init(void)
+{
+ if (CLKMAN_GetClkScale(CLKMAN_CLK_GPIO) == CLKMAN_SCALE_DISABLED) {
+ CLKMAN_SetClkScale(CLKMAN_CLK_GPIO, CLKMAN_SCALE_DIV_1);
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg)
+{
+ static int subsequent_call = 0;
+ int err, idx;
+ clkman_scale_t clk_scale;
+ uint32_t min_baud;
+
+ if(sys_cfg == NULL)
+ return E_NULL_PTR;
+
+ if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
+ CLKMAN_SetClkScale(CLKMAN_CLK_UART, sys_cfg->clk_scale);
+ } else if (!subsequent_call) {
+ /* This clock divider is shared amongst all UARTs. Only change it if it
+ * hasn't already been configured. UART_Init() will check for validity
+ * for this baudrate.
+ */
+ subsequent_call = 1;
+
+ /* Setup the clock divider for the given baud rate */
+ clk_scale = CLKMAN_SCALE_DISABLED;
+ do {
+ min_baud = ((SystemCoreClock >> clk_scale++) / (16 * (MXC_F_UART_BAUD_BAUD_DIVISOR >> MXC_F_UART_BAUD_BAUD_DIVISOR_POS)));
+ } while (uart_cfg->baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO);
+
+ /* check if baud rate cannot be reached */
+ if(uart_cfg->baud < min_baud)
+ return E_BAD_STATE;
+
+ CLKMAN_SetClkScale(CLKMAN_CLK_UART, clk_scale);
+ }
+
+ if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ /* Reset the peripheral */
+ idx = MXC_UART_GET_IDX(uart);
+ MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx);
+ MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx));
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
+{
+ int err;
+ int idx = MXC_UART_GET_IDX(uart);
+ ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_UART(idx, 0, 0, 0, 0, 0, 0);
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart)
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_UART));
+}
+
+/******************************************************************************/
+int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg)
+{
+ int err;
+
+ if(cfg == NULL)
+ return E_NULL_PTR;
+
+ CLKMAN_SetClkScale(CLKMAN_CLK_I2CM, cfg->clk_scale);
+ MXC_CLKMAN->i2c_timer_ctrl = 1;
+
+ if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm)
+{
+ int err;
+ int idx = MXC_I2CM_GET_IDX(i2cm);
+ ioman_cfg_t io_cfg;
+
+ switch(idx)
+ {
+ case 0:
+ io_cfg = (ioman_cfg_t)IOMAN_I2CM0(0, 0);
+ break;
+ case 1:
+ io_cfg = (ioman_cfg_t)IOMAN_I2CM1(0, 0);
+ break;
+ case 2:
+ io_cfg = (ioman_cfg_t)IOMAN_I2CM2(0, 0);
+ break;
+ default:
+ return E_BAD_PARAM;
+ }
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm)
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_I2CM));
+}
+
+/******************************************************************************/
+int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg)
+{
+ int err;
+
+ if(cfg == NULL)
+ return E_NULL_PTR;
+
+ CLKMAN_SetClkScale(CLKMAN_CLK_I2CS, cfg->clk_scale);
+ MXC_CLKMAN->i2c_timer_ctrl = 1;
+
+ if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs)
+{
+ int err;
+ ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_I2CS(0, 0);
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs)
+{
+ uint32_t freq, clkdiv;
+
+ if (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) == MXC_V_CLKMAN_CLK_SCALE_DISABLED) {
+ freq = 0;
+ } else {
+ clkdiv = 1 << (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) - 1);
+ freq = (SystemCoreClock / clkdiv);
+ }
+
+ return freq;
+}
+
+/******************************************************************************/
+int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg)
+{
+ int err, idx;
+ clkman_scale_t clk_scale;
+ uint32_t max_baud;
+
+ if(sys_cfg == NULL)
+ return E_NULL_PTR;
+
+ idx = MXC_SPIM_GET_IDX(spim);
+
+ if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
+ if(spim_cfg->baud > ((SystemCoreClock >> (sys_cfg->clk_scale - 1))/2)) {
+ return E_BAD_PARAM;
+ }
+ CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), sys_cfg->clk_scale);
+ } else {
+
+ if(spim_cfg->baud > (SystemCoreClock/2)) {
+ return E_BAD_PARAM;
+ }
+
+ /* Setup the clock divider for the given baud rate */
+ clk_scale = CLKMAN_SCALE_DISABLED;
+ do {
+ max_baud = ((SystemCoreClock >> clk_scale++) / 2);
+ } while (spim_cfg->baud < max_baud && clk_scale < CLKMAN_SCALE_AUTO);
+
+ if(clk_scale == CLKMAN_SCALE_AUTO) {
+ clk_scale--;
+ }
+
+ CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), clk_scale);
+ }
+
+ if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim)
+{
+ int err;
+ int idx = MXC_SPIM_GET_IDX(spim);
+ ioman_cfg_t io_cfg;
+
+ switch(idx)
+ {
+ case 0:
+ io_cfg = (ioman_cfg_t)IOMAN_SPIM0(0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+ case 1:
+ io_cfg = (ioman_cfg_t)IOMAN_SPIM1(0, 0, 0, 0, 0, 0);
+ break;
+ case 2:
+ io_cfg = (ioman_cfg_t)IOMAN_SPIM2(0, 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+ default:
+ return E_BAD_PARAM;
+ }
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim)
+{
+ int idx = MXC_SPIM_GET_IDX(spim);
+ return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx)));
+}
+
+/******************************************************************************/
+int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud)
+{
+ int err;
+ clkman_scale_t clk_scale;
+ uint32_t min_baud;
+
+ if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) {
+ CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), sys_cfg->clk_scale);
+ } else {
+ /* Setup the clock divider for the given baud rate */
+ clk_scale = CLKMAN_SCALE_DISABLED;
+ do {
+ min_baud = ((SystemCoreClock >> clk_scale++) / (2 *
+ (MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK >> MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)));
+ } while (baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO);
+
+ /* check if baud rate cannot be reached */
+ if(baud < min_baud)
+ return E_BAD_STATE;
+
+ CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), clk_scale);
+ }
+
+ if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_SPIX_Shutdown()
+{
+ int err;
+ ioman_cfg_t io_cfg = IOMAN_SPIX(0, 0, 0, 0, 0, 0);
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_SPIX_GetFreq()
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX)));
+}
+
+/******************************************************************************/
+int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg)
+{
+ int err;
+
+ if(sys_cfg == NULL)
+ return E_NULL_PTR;
+
+ if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO)
+ {
+ CLKMAN_SetClkScale(CLKMAN_CLK_OWM, sys_cfg->clk_scale);
+ }
+ else
+ {
+ CLKMAN_SetClkScale(CLKMAN_CLK_OWM, CLKMAN_SCALE_DIV_1);
+ }
+
+ if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+int SYS_OWM_Shutdown(mxc_owm_regs_t *owm)
+{
+ int err;
+
+ ioman_cfg_t io_cfg = IOMAN_OWM(0, 0);
+
+ if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm)
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_OWM));
+}
+
+/******************************************************************************/
+uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr)
+{
+ return SystemCoreClock;
+}
+
+/******************************************************************************/
+int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg)
+{
+ int pin, gpio_index, tmr_index;
+
+ if (cfg != NULL)
+ {
+ /* Make sure the given GPIO mapps to the given TMR */
+ for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++)
+ {
+ if(cfg->mask & (1 << pin))
+ {
+ gpio_index = (MXC_GPIO_MAX_PINS_PER_PORT * cfg->port) + pin;
+ tmr_index = gpio_index % MXC_CFG_TMR_INSTANCES;
+
+ if(tmr_index == MXC_TMR_GET_IDX(tmr))
+ return GPIO_Config(cfg);
+ else
+ return E_BAD_PARAM;
+ }
+ }
+
+ return E_BAD_PARAM;
+
+ } else {
+ return E_NO_ERROR;
+ }
+}
+
+/******************************************************************************/
+uint32_t SYS_SysTick_GetFreq(void)
+{
+ /* Determine is using internal (SystemCoreClock) or external (32768) clock */
+ if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+ return SystemCoreClock;
+ } else {
+ return SYS_RTC_CLK;
+ }
+}
+
+/******************************************************************************/
+uint32_t SYS_PT_GetFreq(void)
+{
+ return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_PT));
+}
+
+/******************************************************************************/
+void SYS_PT_Init(sys_pt_clk_scale clk_scale)
+{
+ /* setup clock divider for pulse train clock */
+ CLKMAN_SetClkScale(CLKMAN_CLK_PT, clk_scale);
+}
+
+/******************************************************************************/
+int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg)
+{
+ int pt_index;
+
+ /* Make sure the given GPIO mapps to the given PT */
+ pt_index = MXC_PT_GET_IDX(pt);
+ if(pt_index < 0) {
+ return E_NOT_SUPPORTED;
+ }
+
+ /* Even number port */
+ if(cfg->port%2 == 0) {
+ /* Pin number should match PT number */
+ if(!(cfg->mask & (0x1 << pt_index))) {
+ return E_NOT_SUPPORTED;
+ }
+ } else {
+ /* Pin number+8 should match PT */
+ if(!((cfg->mask << 8) & (0x1 << pt_index))) {
+ return E_NOT_SUPPORTED;
+ }
+ }
+
+ return GPIO_Config(cfg);
+}
+
+/******************************************************************************/
+void SYS_USB_Enable(uint8_t enable)
+{
+ /* Enable USB clock */
+ CLKMAN_ClockGate(CLKMAN_USB_CLOCK, enable);
+
+ if(enable) {
+ /* Enable USB Power */
+ MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
+ } else {
+ /* Disable USB Power */
+ MXC_PWRMAN->pwr_rst_ctrl &= ~MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED;
+ }
+}
+
+/******************************************************************************/
+int SYS_SysTick_Config(uint32_t ticks, int clk_src)
+{
+
+ if(ticks == 0)
+ return E_BAD_PARAM;
+
+ /* If SystemClock, call default CMSIS config and return */
+ if (clk_src) {
+ return SysTick_Config(ticks);
+ } else { /* External clock source requested
+ enable RTC clock in run mode*/
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN);
+
+ /* Disable SysTick Timer */
+ SysTick->CTRL = 0;
+ /* Check reload value for valid */
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) {
+ /* Reload value impossible */
+ return E_BAD_PARAM;
+ }
+ /* set reload register */
+ SysTick->LOAD = ticks - 1;
+
+ /* set Priority for Systick Interrupt */
+ NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+
+ /* Load the SysTick Counter Value */
+ SysTick->VAL = 0;
+
+ /* Enable SysTick IRQ and SysTick Timer leaving clock source as external */
+ SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Function successful */
+ return E_NO_ERROR;
+ }
+}
+
+/******************************************************************************/
+int SYS_SysTick_Delay(uint32_t ticks)
+{
+ uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i;
+ uint32_t reload, value, ctrl; /* save/restore variables */
+
+ if(ticks == 0)
+ return E_BAD_PARAM;
+
+ /* If SysTick is not enabled we can take it for our delay */
+ if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
+
+ /* Save current state in case it's disabled but already configured, restore at return.*/
+ reload = SysTick->LOAD;
+ value = SysTick->VAL;
+ ctrl = SysTick->CTRL;
+
+ /* get the number of ticks less than max RELOAD. */
+ num_remain = ticks % SysTick_LOAD_RELOAD_Msk;
+
+ /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will
+ give us the number of max SysTicks cycles required */
+ num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk;
+
+ /* Do the required full systick countdowns */
+ if (num_full) {
+ /* load the max count value into systick */
+ SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
+ /* load the starting value */
+ SysTick->VAL = 0;
+ /*enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+ /* CountFlag will get set when VAL reaches zero */
+ for (i = num_full; i > 0; i--) {
+ do {
+ cur_ticks = SysTick->CTRL;
+ } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
+ }
+ /* Disable systick */
+ SysTick->CTRL = 0;
+ }
+ /* Now handle the remainder of ticks */
+ if (num_remain) {
+ SysTick->LOAD = num_remain;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+ /* wait for countflag to get set */
+ do {
+ cur_ticks = SysTick->CTRL;
+ } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
+ /* Disable systick */
+ SysTick->CTRL = 0;
+ }
+
+ /* restore original state of SysTick and return */
+ SysTick->LOAD = reload;
+ SysTick->VAL = value;
+ SysTick->CTRL = ctrl;
+
+ return E_NO_ERROR;
+
+ } else { /* SysTick is enabled
+ When SysTick is enabled count flag can not be used
+ and the reload can not be changed.
+ Do not read the CTRL register -> clears count flag */
+
+ /* Get the reload value for wrap/reload case */
+ reload = SysTick->LOAD;
+
+ /* Read the starting systick value */
+ previous_ticks = SysTick->VAL;
+
+ do {
+ /* get current SysTick value */
+ cur_ticks = SysTick->VAL;
+ /* Check for wrap/reload of timer countval */
+ if (cur_ticks > previous_ticks) {
+ /* subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks) */
+ num_subtract = (previous_ticks + (reload - cur_ticks));
+ } else { /* standard case (no wrap)
+ subtract off the number of ticks since last pass */
+ num_subtract = (previous_ticks - cur_ticks);
+ }
+ /* check to see if we are done. */
+ if (num_subtract >= ticks)
+ return E_NO_ERROR;
+ else
+ ticks -= num_subtract;
+ /* cur_ticks becomes previous_ticks for next timer read. */
+ previous_ticks = cur_ticks;
+ } while (ticks > 0);
+ /* Should not ever be reached */
+ return E_NO_ERROR;
+ }
+}
+
+/******************************************************************************/
+int SYS_RTC_Init(void)
+{
+ /* Enable power for RTC for all LPx states */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN |
+ MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
+
+ /* Enable clock to synchronizers */
+ CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1);
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg)
+{
+ unsigned int startbit = (cfg->port * 8);
+ volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32);
+ *use_vddioh_reg &= ~cfg->mask << (startbit % 32);
+}
+
+/******************************************************************************/
+void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg)
+{
+ unsigned int startbit = (cfg->port * 8);
+ volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32);
+ *use_vddioh_reg |= cfg->mask << (startbit % 32);
+}
+
+/******************************************************************************/
+void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg)
+{
+
+ if(cfg->clk == CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR)
+ {
+ /*enable nanoring in run mode */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
+ }
+ else if(cfg->clk == CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR)
+ {
+ /*enabled RTC in run mode */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN);
+ }
+
+ if(wdt == MXC_WDT0) {
+ /*select clock source */
+ CLKMAN_WdtClkSelect(0, cfg->clk);
+
+ /*Set scale of clock (only used for system clock as source) */
+ CLKMAN_SetClkScale(CLKMAN_CLK_WDT0, cfg->clk_scale);
+
+ /*Enable clock */
+ CLKMAN_ClockGate(CLKMAN_WDT0_CLOCK, 1);
+ } else if (wdt == MXC_WDT1) {
+ /*select clock source */
+ CLKMAN_WdtClkSelect(1, cfg->clk);
+
+ /*Set scale of clock (only used for system clock as source) */
+ CLKMAN_SetClkScale(CLKMAN_CLK_WDT1, cfg->clk_scale);
+
+ /*Enable clock */
+ CLKMAN_ClockGate(CLKMAN_WDT1_CLOCK, 1);
+ }
+}
+
+/******************************************************************************/
+void SYS_PRNG_Init(void)
+{
+ /* Start crypto ring, unconditionally */
+ CLKMAN_CryptoClockEnable(1);
+
+ /* If we find the dividers in anything other than off, don't touch them */
+ if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_PRNG) == CLKMAN_SCALE_DISABLED) {
+ /* Div 1 mode */
+ CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_PRNG, CLKMAN_SCALE_DIV_1);
+ }
+
+ if (CLKMAN_GetClkScale(CLKMAN_CLK_PRNG) == CLKMAN_SCALE_DISABLED) {
+ /* Div 1 mode */
+ CLKMAN_SetClkScale(CLKMAN_CLK_PRNG, CLKMAN_SCALE_DIV_1);
+ }
+}
+
+/******************************************************************************/
+void SYS_MAA_Init(void)
+{
+ /* Start crypto ring, unconditionally */
+ CLKMAN_CryptoClockEnable(1);
+
+ /* If we find the dividers in anything other than off, don't touch them */
+ if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_MAA) == CLKMAN_SCALE_DISABLED) {
+ /* Div 1 mode */
+ CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_MAA, CLKMAN_SCALE_DIV_1);
+ }
+}
+
+/******************************************************************************/
+uint32_t SYS_SRAM_GetSize(void)
+{
+ uint32_t memSize;
+
+ /* Read TRIM value*/
+ int SRAMtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_SRAM) >> MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS;
+
+ /* Decode trim value into memory size in bytes */
+ switch(SRAMtrim)
+ {
+ case MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE:
+ memSize = (MXC_SRAM_FULL_MEM_SIZE >> 2) * 3;
+ break;
+
+ case MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE:
+ memSize = MXC_SRAM_FULL_MEM_SIZE >> 1;
+ break;
+
+ default: /* other values are FULL size */
+ memSize = MXC_SRAM_FULL_MEM_SIZE;
+ break;
+ }
+
+ /* Returns size in bytes */
+ return memSize;
+}
+
+/******************************************************************************/
+uint32_t SYS_FLASH_GetSize(void)
+{
+ uint32_t memSize;
+
+ /* Read TRIM value */
+ int FLASHtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_FLASH) >> MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS;
+
+ /* Decode trim value into memory size in bytes*/
+ switch(FLASHtrim)
+ {
+ case MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE:
+ memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2) * 3;
+ break;
+ case MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE:
+ memSize = (MXC_FLASH_FULL_MEM_SIZE >> 1);
+ break;
+ case MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE:
+ memSize = (MXC_FLASH_FULL_MEM_SIZE >> 3) * 3;
+ break;
+ case MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE:
+ memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2);
+ break;
+ default: /* other values are FULL size */
+ memSize = MXC_FLASH_FULL_MEM_SIZE;
+ break;
+ }
+
+ /* Returns size in bytes */
+ return memSize;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,496 @@
+/**
+ * @file mxc_sys.h
+ * @brief Registers, Bit Masks and Bit Positions for the System Clock Management module.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-08-24 18:33:23 -0500 (Wed, 24 Aug 2016) $
+ * $Revision: 24159 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _MXC_SYS_H_
+#define _MXC_SYS_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "clkman.h"
+#include "ioman.h"
+#include "gpio.h"
+#include "i2cm_regs.h"
+#include "i2cs_regs.h"
+#include "tmr_regs.h"
+#include "pt_regs.h"
+#include "wdt_regs.h"
+#include "owm_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup sys_cfg System Configuration
+ * @ingroup sysconfig
+ * @brief Configuration objects and functions for configuration of the system and peripherals.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Structure type for System Configuration.
+ */
+typedef struct {
+ clkman_scale_t clk_scale; /**< Desired clock scale value for the peripheral */
+ ioman_cfg_t io_cfg; /**< IOMAN configuration object */
+} sys_cfg_t;
+
+/**
+ * Structure type for Watchdog System Configuration.
+ * @ingroup wdt
+ * @{
+ */
+typedef struct {
+ clkman_wdt_clk_select_t clk; /**< Select the clock source for the watchdog */
+ clkman_scale_t clk_scale; /**< Desired clock scale value for the peripheral. @note clk_scale is only applied if the system clock is used as the clk. */
+} sys_cfg_wdt_t;
+/**@}*/
+
+/**
+ * Structure type for UART System Configuration.
+ * @ingroup uart
+ */
+typedef sys_cfg_t sys_cfg_uart_t;
+
+/**
+ * Structure type for I2CM System Configuration.
+ * @ingroup i2cm
+ */
+typedef sys_cfg_t sys_cfg_i2cm_t;
+
+/**
+ * Structure type for I2CS System Configuration.
+ * @ingroup i2cs
+ */
+typedef sys_cfg_t sys_cfg_i2cs_t;
+
+/**
+ * Structure type for SPIM System Configuration.
+ * @ingroup spim
+ */
+typedef sys_cfg_t sys_cfg_spim_t;
+
+/**
+ * Structure type for SPIX System Configuration.
+ * @ingroup spix
+ */
+typedef sys_cfg_t sys_cfg_spix_t;
+
+/**
+ * Structure type for OWM System Configuration.
+ * @ingroup owm
+ */
+typedef sys_cfg_t sys_cfg_owm_t;
+
+/**
+ * Structure type for Timer System Configuration.
+ * @ingroup timer
+ */
+typedef gpio_cfg_t sys_cfg_tmr_t;
+
+/**
+ * Structure type for Pulse Train System Configuration.
+ * @ingroup pulsetrain
+ */
+typedef gpio_cfg_t sys_cfg_pt_t;
+
+/**
+ * Structure type for Pulse Train Clock Scale Configuration.
+ * @ingroup clkman
+ * @ingroup pulsetrain
+ */
+typedef clkman_scale_t sys_pt_clk_scale;
+
+/* **** Include Files **** */
+/* These includes require the above types to be defined first */
+#include "uart.h"
+#include "spim.h"
+
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Get the frequency of a clock scaler
+ * @param clk_scale value of SYSTEM_SOURCE_SELECT field of \ref clkman_clk_ctrl register
+ * @return frequency in Hz
+ */
+uint32_t SYS_GetFreq(uint32_t clk_scale);
+
+/**
+ * @brief Get the frequency of the CPU
+ * @return frequency in Hz
+ */
+uint32_t SYS_CPU_GetFreq(void);
+
+/**
+ * @brief System level initialization for the ADC module.
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup adc
+ */
+int SYS_ADC_Init(void);
+
+/**
+ * @brief System level initialization for the AES module.
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup aes
+ */
+int SYS_AES_Init(void);
+
+/**
+ * @brief System level initialization for the GPIO module.
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup gpio
+ */
+int SYS_GPIO_Init(void);
+
+/**
+ * @brief System level initialization for the UART module.
+ * @param uart Pointer to UART module registers
+ * @param uart_cfg UART configuration object
+ * @param sys_cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup uart
+ */
+int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg);
+
+/**
+ * @brief System level shutdown for UART module
+ * @param uart Pointer to UART module registers
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup uart
+ */
+int SYS_UART_Shutdown(mxc_uart_regs_t *uart);
+
+/**
+ * @brief Get the frequency of the UART module source clock
+ * @param uart Pointer to UART module registers
+ * @return frequency in Hz
+ * @ingroup uart
+ */
+uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart);
+
+/**
+ * @brief System level initialization for I2CM module.
+ * @param i2cm Pointer to I2CM module registers
+ * @param cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup i2cm
+ */
+int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg);
+
+/**
+ * @brief System level shutdown for I2CM module
+ * @param i2cm Pointer to I2CM module registers
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup i2cm
+ */
+int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @brief Get the frequency of the I2CM module source clock
+ * @param i2cm Pointer to I2CM module registers
+ * @return frequency in Hz
+ * @ingroup i2cm
+ */
+uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm);
+
+/**
+ * @brief System level initialization for I2CS module.
+ * @param i2cs Pointer to I2CS module registers
+ * @param cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup i2cs
+ */
+int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg);
+
+/**
+ * @brief System level shutdown for I2CS module
+ * @param i2cs Pointer to I2CS module registers
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup i2cs
+ */
+int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs);
+
+/**
+ * @brief Get the frequency of the I2CS module source clock
+ * @param i2cs Pointer to I2CS module registers
+ * @return frequency in Hz
+ * @ingroup i2cs
+ */
+uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs);
+
+/**
+ * @brief System level initialization for SPIM module.
+ * @param spim Pointer to SPIM module registers
+ * @param spim_cfg SPIM configuration object
+ * @param sys_cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup spim
+ */
+int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg);
+
+/**
+ * @brief System level shutdown for SPIM module
+ * @param spim Pointer to SPIM module registers
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup spim
+ */
+int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim);
+
+/**
+ * @brief Get the frequency of the SPIM module source clock
+ * @param spim Pointer to SPIM module registers
+ * @return frequency in Hz
+ * @ingroup spim
+ */
+uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim);
+
+/**
+ * @brief System level initialization for SPIX module.
+ * @param sys_cfg System configuration object
+ * @param baud Baud rate for clock divider configuration
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup spix
+ */
+int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud);
+
+/**
+ * @brief System level shutdown for SPIX module
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup spix
+ */
+int SYS_SPIX_Shutdown();
+
+/**
+ * @brief Get the frequency of the SPIX module source clock
+ * @return frequency in Hz
+ * @ingroup spix
+ */
+uint32_t SYS_SPIX_GetFreq();
+
+/**
+ * @brief System level initialization for OWM module.
+ * @param owm Pointer to OWM module registers
+ * @param sys_cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup owm
+ */
+int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg);
+
+/**
+ * @brief System level shutdown for OWM module
+ * @param owm Pointer to OWM module registers
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup owm
+ */
+int SYS_OWM_Shutdown(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Get the frequency of the OWM module source clock
+ * @param owm Pointer to OWM module registers
+ * @return frequency in Hz
+ * @ingroup owm
+ */
+uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm);
+
+/**
+ * @brief System level initialization for TMR module.
+ * @param tmr Pointer to TMR module registers
+ * @param cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup timer
+ */
+int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg);
+
+/**
+ * @brief Get the frequency of the TMR module source clock
+ * @param tmr Pointer to TMR module registers
+ * @return frequency in Hz
+ * @ingroup timer
+ */
+uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief Get the frequency of the Pulse Train module source clock
+ * @return frequency in Hz
+ * @ingroup pulsetrain
+ */
+uint32_t SYS_PT_GetFreq(void);
+
+/**
+ * @brief Initialize the global pulse train clock scale
+ * @param clk_scale scale the system clock for the PT clock
+ * @ingroup pulsetrain
+ */
+void SYS_PT_Init(sys_pt_clk_scale clk_scale);
+
+/**
+ * @brief System level initialization for Pulse Train module.
+ * @param pt Pointer to PT module registers
+ * @param cfg System configuration object
+ * @return #E_NO_ERROR if everything is successful
+ * @ingroup pulsetrain
+ */
+int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg);
+
+/**
+ * @brief System level initialization for USB device.
+ * @param enable 1 to enable the peripheral, 0 to disable.
+ * @ingroup usb
+ */
+void SYS_USB_Enable(uint8_t enable);
+
+/**
+ * @brief System Tick Configuration Helper
+ *
+ * The function enables selection of the external clock source for
+ * the System Tick Timer. It initializes the System Timer and its
+ * interrupt, and starts the System Tick Timer. Counter is in free
+ * running mode to generate periodic interrupts.
+ *
+ * @param ticks Number of ticks between two interrupts.
+ * @param clk_src Selects between default SystemClock or External Clock.
+ * - 0 Use external clock source
+ * - 1 SystemClock
+ * @return #E_NO_ERROR Function succeeded.
+ * @return #E_INVALID Invalid reload value requested.
+ *
+ * See CLKMAN_SetRTOSMode(uint8_t enable) if using the external
+ * clock source to drive the System Tick Timer
+ */
+int SYS_SysTick_Config(uint32_t ticks, int clk_src);
+
+/**
+ * @brief Disable System Tick timer
+ */
+__STATIC_INLINE void SYS_SysTick_Disable(void)
+{
+ SysTick->CTRL = 0;
+}
+
+/**
+ * @brief Delay a requested number of SysTick Timer Ticks.
+ * @param ticks Number of System Ticks to delay.
+ * @note This delay function is based on the clock used for the SysTick
+ * timer if the SysTick timer is enabled. If the SysTick timer is
+ * not enabled, the current SysTick registers are saved and the
+ * timer will use the SystemClock as the source for the delay. The
+ * delay is measured in clock ticks and is not based on the SysTick
+ * interval.
+ * @return #E_NO_ERROR if everything is successful
+ */
+int SYS_SysTick_Delay(uint32_t ticks);
+
+/**
+ * @brief Get the frequency of the SysTick Timer
+ * @return frequency in Hz
+ */
+uint32_t SYS_SysTick_GetFreq(void);
+
+/**
+ * @brief Delay a requested number of microseconds.
+ * @param us Number of microseconds to delay.
+ * @note Calls SYS_SysTick_Delay().
+ */
+__STATIC_INLINE void SYS_SysTick_DelayUs(uint32_t us)
+{
+ SYS_SysTick_Delay((uint32_t)(((uint64_t)SYS_SysTick_GetFreq() * us) / 1000000));
+}
+
+/**
+ * @brief System level initialization for RTC module.
+ * @return #E_NO_ERROR if everything is successful
+ */
+int SYS_RTC_Init(void);
+
+/**
+ * @brief Select VDDIO for the specified GPIO pin.
+ * @ingroup gpio
+ */
+void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg);
+
+/**
+ * @brief Select VDDIOH for the specified GPIO pin.
+ */
+void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg);
+
+/**
+ * @brief System level initialization for Watchdog module.
+ * @param wdt Pointer to Watchdog module registers
+ * @param cfg Watchdog System configuration object
+ * @ingroup wdt
+ */
+void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg);
+
+/**
+ * @brief System level initialization for PRNG module. Enable crypto clock
+ * and set divisors to 1 if disabled
+ */
+void SYS_PRNG_Init(void);
+
+/**
+ * @brief System level initialization for MAA module. Enable crypto clock
+ * and set divisors to 1 if disabled
+ * @ingroup maa
+ */
+void SYS_MAA_Init(void);
+
+/**
+ * @brief Gets the size of the SRAM
+ * @return size of SRAM in bytes
+ */
+uint32_t SYS_SRAM_GetSize(void);
+
+/**
+ * @brief Gets the size of the Flash
+ * @return size of Flash in bytes
+ */
+uint32_t SYS_FLASH_GetSize(void);
+
+/**@} end of group sys_cfg */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_SYS_H_*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,93 @@
+/**
+ * @file
+ * @brief This file contains the implementations of the vendor
+ * defined NVIC function.
+ *
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-28 10:27:00 -0500 (Wed, 28 Sep 2016) $
+ * $Revision: 24512 $
+ *
+ *************************************************************************** */
+
+/**
+ * @ingroup mxc_nvic
+ * @{
+ */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include <string.h>
+#include "nvic_table.h"
+
+/* RAM vector_table needs to be aligned with the size of the vector table */
+/* TODO: Use MXC_IRQ_COUNT to automatically set this alignment per DUI0553A 4.3.4 */
+/* Vector Table Offset which requires the next-power-of-two alignment. This */
+/* can be calculated by 4*pow(2,ceil(log2(MXC_IRQ_COUNT))) */
+#if defined ( __ICCARM__ )
+#pragma data_alignment = 512
+#define __isr_vector __vector_table
+#else
+__attribute__ ((aligned (512)))
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************* */
+void NVIC_SetRAM(void)
+{
+ memcpy(&ramVectorTable, (uint32_t*)SCB->VTOR, sizeof(ramVectorTable));
+ SCB->VTOR = (uint32_t)&ramVectorTable;
+}
+
+/* ************************************************************************* */
+int NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void))
+{
+ int index = irqn + 16; /* offset for externals */
+
+ /* If not copied, do copy */
+ if(SCB->VTOR != (uint32_t)&ramVectorTable) {
+ NVIC_SetRAM();
+ }
+
+ ramVectorTable[index] = irq_handler;
+ NVIC_EnableIRQ(irqn);
+
+ return 0;
+}
+/**@} end of group mxc_nvic */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,88 @@
+/**
+ * @file
+ * @brief NVIC utility function and type declarations.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-09 12:24:40 -0500 (Fri, 09 Sep 2016) $
+ * $Revision: 24344 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _NVIC_TABLE_H
+#define _NVIC_TABLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup mxc_nvic NVIC Functions
+ * @ingroup sysconfig
+ * @brief Utility function for setting an IRQ handler dynamically
+ * @{
+ */
+
+/**
+ * @brief Type alias for an IRQ handler.
+ * @details Type alias for an IRQ handler function with prototype:.
+ * @code
+ * void irq_handler(void);
+ * @endcode
+ *
+ */
+typedef void (*irq_fn)(void);
+
+/**
+ * @brief Set an IRQ hander function for an IRQ specified by @p irqn.
+ * @details If the IRQ table is in flash, this function will copy the IRQ table to RAM.
+ *
+ * @param irqn ARM external IRQ number, see #IRQn_Type
+ * @param irq_handler Function to be called at IRQ context
+ */
+int NVIC_SetVector(IRQn_Type irqn, irq_fn irq_handler);
+
+/**
+ * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table.
+ *
+ */
+void NVIC_SetRAM(void);
+
+/**@} end of group mxc_nvic */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _NVIC_TABLE_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,639 @@
+/**
+ * @file
+ * @brief 1-Wire Master (OWM) API Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-14 10:08:53 -0500 (Mon, 14 Mar 2016) $
+ * $Revision: 21855 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "owm.h"
+
+/**
+ * @ingroup owm
+ * @{
+ */
+///@cond
+/* **** Definitions **** */
+#define OWM_CLK_FREQ 1000000 //1-Wire requires 1MHz clock
+
+/* **** Globals **** */
+int LastDiscrepancy;
+int LastDeviceFlag;
+
+/* **** Functions **** */
+static uint8_t CalculateCRC8(uint8_t* data, int len);
+static uint8_t update_crc8(uint8_t crc, uint8_t value);
+///@endcond
+
+
+/* ************************************************************************* */
+int OWM_Init(mxc_owm_regs_t *owm, const owm_cfg_t *cfg, const sys_cfg_owm_t *sys_cfg)
+{
+ int err = 0;
+ uint32_t owm_clk, clk_div = 0;
+ uint32_t ext_pu_mode = 0;
+ uint32_t ext_pu_polarity = 0;
+
+ // Check the OWM register pointer is valid
+ MXC_ASSERT(MXC_OWM_GET_IDX(owm) >= 0);
+
+ if(cfg == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Set system level configurations
+ if ((err = SYS_OWM_Init(owm, sys_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ // Configure clk divisor to get 1MHz OWM clk
+ owm_clk = SYS_OWM_GetFreq(owm);
+
+ if(owm_clk == 0) {
+ return E_UNINITIALIZED;
+ }
+
+ // Return error if clk doesn't divide evenly to 1MHz
+ if(owm_clk % OWM_CLK_FREQ) {
+ return E_NOT_SUPPORTED;
+ }
+
+ clk_div = (owm_clk / (OWM_CLK_FREQ));
+
+ // Can not support lower frequencies
+ if(clk_div == 0) {
+ return E_NOT_SUPPORTED;
+ }
+
+ // Select the PU mode and polarity based on cfg input
+ switch(cfg->ext_pu_mode)
+ {
+ case OWM_EXT_PU_ACT_HIGH:
+ ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED;
+ ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH;
+ break;
+ case OWM_EXT_PU_ACT_LOW:
+ ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_USED;
+ ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_LOW;
+ break;
+ case OWM_EXT_PU_UNUSED:
+ ext_pu_mode = MXC_V_OWM_CFG_EXT_PULLUP_MODE_UNUSED;
+ ext_pu_polarity = MXC_V_OWM_CTRL_STAT_EXT_PULLUP_POL_ACT_HIGH;
+ break;
+ default:
+ return E_BAD_PARAM;
+ }
+
+ // Set clk divisor
+ owm->clk_div_1us = (clk_div << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS) & MXC_F_OWM_CLK_DIV_1US_DIVISOR;
+
+ // Set configuration
+ owm->cfg = (((cfg->int_pu_en << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS) & MXC_F_OWM_CFG_INT_PULLUP_ENABLE) |
+ ((ext_pu_mode << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS) & MXC_F_OWM_CFG_EXT_PULLUP_MODE) |
+ ((cfg->long_line_mode << MXC_F_OWM_CFG_LONG_LINE_MODE) & MXC_F_OWM_CFG_LONG_LINE_MODE_POS));
+
+ owm->ctrl_stat = (((ext_pu_polarity << MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL_POS) & MXC_F_OWM_CTRL_STAT_EXT_PULLUP_POL) |
+ ((cfg->overdrive_spec << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS) & MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE));
+
+ // Clear all interrupt flags
+ owm->intfl = owm->intfl;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int OWM_Shutdown(mxc_owm_regs_t *owm)
+{
+ int err;
+
+ // Disable and clear interrupts
+ owm->inten = 0;
+ owm->intfl = owm->intfl;
+
+ // Release IO pins and disable clk
+ if ((err = SYS_OWM_Shutdown(owm)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int OWM_Reset(mxc_owm_regs_t *owm)
+{
+ owm->intfl = MXC_F_OWM_INTFL_OW_RESET_DONE; // Clear the reset flag
+ owm->ctrl_stat |= MXC_F_OWM_CTRL_STAT_START_OW_RESET; // Generate a reset pulse
+ while((owm->intfl & MXC_F_OWM_INTFL_OW_RESET_DONE) == 0); // Wait for reset time slot to complete
+
+ return (!!(owm->ctrl_stat & MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT)); // Return presence pulse detect status
+}
+
+/* ************************************************************************* */
+int OWM_TouchByte(mxc_owm_regs_t *owm, uint8_t data)
+{
+ owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode
+ owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY); // Clear the flags
+ owm->data = (data << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data
+ while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent
+ while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read
+
+ return (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & 0xFF; // Return the data read
+}
+
+/* ************************************************************************* */
+int OWM_WriteByte(mxc_owm_regs_t *owm, uint8_t data)
+{
+ // Send one byte of data and verify the data sent = data parameter
+ return (OWM_TouchByte(owm, data) == data) ? E_NO_ERROR : E_COMM_ERR;
+}
+
+/* ************************************************************************* */
+int OWM_ReadByte(mxc_owm_regs_t *owm)
+{
+ // Read one byte of data
+ return OWM_TouchByte(owm, 0xFF);
+}
+
+/* ************************************************************************* */
+int OWM_TouchBit(mxc_owm_regs_t *owm, uint8_t bit)
+{
+ MXC_OWM->cfg |= MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 1 bit mode
+ owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY); // Clear the flags
+ owm->data = (bit << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data
+ while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent
+ while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read
+
+ return (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & 0x1; // Return the bit read
+}
+
+/* ************************************************************************* */
+int OWM_WriteBit(mxc_owm_regs_t *owm, uint8_t bit)
+{
+ // Send a bit and verify the bit sent = bit parameter
+ return (OWM_TouchBit(owm, bit) == bit) ? E_NO_ERROR : E_COMM_ERR;
+}
+
+/* ************************************************************************* */
+int OWM_ReadBit(mxc_owm_regs_t *owm)
+{
+ // Read a bit
+ return OWM_TouchBit(owm, 1);
+}
+
+/* ************************************************************************* */
+int OWM_Write(mxc_owm_regs_t *owm, uint8_t* data, int len)
+{
+ int num = 0;
+
+ owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode
+
+ while(num < len) // Loop for number of bytes to write
+ {
+ owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY | MXC_F_OWM_INTEN_LINE_SHORT); // Clear the flags
+ owm->data = (data[num] << MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX; // Write data
+ while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent
+ while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read
+
+ // Verify data sent is correct
+ if(owm->data != data[num]) {
+ return E_COMM_ERR;
+ }
+
+ // Check error flag
+ if(owm->intfl & MXC_F_OWM_INTEN_LINE_SHORT) {
+ return E_COMM_ERR; // Wire was low before transaction
+ }
+
+ num++; // Keep track of how many bytes written
+ }
+
+ return num; // Return number of bytes written
+}
+
+/* ************************************************************************* */
+int OWM_Read(mxc_owm_regs_t *owm, uint8_t* data, int len)
+{
+ int num = 0;
+
+ owm->cfg &= ~MXC_F_OWM_CFG_SINGLE_BIT_MODE; // Set to 8 bit mode
+
+ while(num < len) // Loop for number of bytes to read
+ {
+ owm->intfl = (MXC_F_OWM_INTFL_TX_DATA_EMPTY | MXC_F_OWM_INTFL_RX_DATA_READY | MXC_F_OWM_INTEN_LINE_SHORT); // Clear the flags
+ owm->data = 0xFF; // Write 0xFF for a read
+ while((owm->intfl & MXC_F_OWM_INTFL_TX_DATA_EMPTY) == 0); // Wait for data to be sent
+ while((owm->intfl & MXC_F_OWM_INTFL_RX_DATA_READY) == 0); // Wait for data to be read
+
+ // Check error flag
+ if(owm->intfl & MXC_F_OWM_INTEN_LINE_SHORT) {
+ return E_COMM_ERR; // Wire was low before transaction
+ }
+
+ // Store read data into buffer
+ data[num] = (owm->data >> MXC_F_OWM_DATA_TX_RX_POS) & MXC_F_OWM_DATA_TX_RX;
+
+ num++; // Keep track of how many bytes read
+ }
+
+ return num; // Return number of bytes read
+}
+
+/* ************************************************************************* */
+int OWM_ReadROM(mxc_owm_regs_t *owm, uint8_t* ROMCode)
+{
+ int num_read = 0;
+
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send Read ROM command code
+ if(OWM_WriteByte(owm, READ_ROM_COMMAND) == E_NO_ERROR)
+ {
+ // Read 8 bytes and store in buffer
+ num_read = OWM_Read(owm, ROMCode, 8);
+
+ // Check the number of bytes read
+ if(num_read != 8) {
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // Write failed
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int OWM_MatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode)
+{
+ int num_wrote = 0;
+
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send match ROM command code
+ if(OWM_WriteByte(owm, MATCH_ROM_COMMAND) == E_NO_ERROR)
+ {
+ // Write 8 bytes in ROMCode buffer
+ num_wrote = OWM_Write(owm, ROMCode, 8);
+
+ // Check the number of bytes written
+ if(num_wrote != 8) {
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // Write failed
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int OWM_ODMatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode)
+{
+ int num_wrote = 0;
+
+ // Set to standard speed
+ owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE);
+
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send Overdrive match ROM command code
+ if(OWM_WriteByte(owm, OD_MATCH_ROM_COMMAND) == E_NO_ERROR)
+ {
+ // Set overdrive
+ owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE;
+
+ // Write 8 bytes in ROMCode buffer
+ num_wrote = OWM_Write(owm, ROMCode, 8);
+
+ // Check the number of bytes written
+ if(num_wrote != 8) {
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // Write failed
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int OWM_SkipROM(mxc_owm_regs_t *owm)
+{
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send skip ROM command code
+ return OWM_WriteByte(owm, SKIP_ROM_COMMAND);
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+}
+
+/* ************************************************************************* */
+int OWM_ODSkipROM(mxc_owm_regs_t *owm)
+{
+ // Set to standard speed
+ owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE);
+
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send Overdrive skip ROM command code
+ if(OWM_WriteByte(owm, OD_SKIP_ROM_COMMAND) == E_NO_ERROR)
+ {
+ // Set overdrive speed
+ owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE;
+
+ return E_NO_ERROR;
+ }
+ else
+ {
+ // Write failed
+ return E_COMM_ERR;
+ }
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+}
+
+/* ************************************************************************* */
+int OWM_Resume(mxc_owm_regs_t *owm)
+{
+ // Send reset and wait for presence pulse
+ if(OWM_Reset(owm))
+ {
+ // Send resume command code
+ return OWM_WriteByte(owm, RESUME_COMMAND);
+ }
+ else
+ {
+ // No presence pulse
+ return E_COMM_ERR;
+ }
+}
+
+/* ************************************************************************* */
+int OWM_SearchROM(mxc_owm_regs_t *owm, int newSearch, uint8_t* ROMCode)
+{
+ int nibble_start_bit = 1;
+ int rom_byte_number = 0;
+ uint8_t rom_nibble_mask = 0x0F;
+ uint8_t search_direction = 0;
+ int readValue = 0;
+ int sentBits = 0;
+ int discrepancy = 0;
+ int bit_position = 0;
+ int discrepancy_mask = 0;
+ int last_zero = 0;
+ uint8_t crc8 = 0;
+ int search_result = 0;
+
+ // Clear ROM array
+ memset(ROMCode, 0x0, 8);
+
+ if(newSearch)
+ {
+ // Reset all global variables to start search from begining
+ LastDiscrepancy = 0;
+ LastDeviceFlag = 0;
+ }
+
+ // Check if the last call was the last device
+ if(LastDeviceFlag)
+ {
+ // Reset the search
+ LastDiscrepancy = 0;
+ LastDeviceFlag = 0;
+ return 0;
+ }
+
+ // Send reset and wait for presence pulse
+ if (OWM_Reset(owm))
+ {
+ // Send the search command
+ OWM_WriteByte(owm, SEARCH_ROM_COMMAND);
+
+ // Set search ROM accelerator bit
+ owm->ctrl_stat |= MXC_F_OWM_CTRL_STAT_SRA_MODE;
+
+ // Loop until through all ROM bytes 0-7 (this loops 2 times per byte)
+ while(rom_byte_number < 8)
+ {
+ // Each loop finds the discrepancy bits and finds 4 bits (nibble) of the ROM
+
+ // Set the search direction the same as last time for the nibble masked
+ search_direction = ROMCode[rom_byte_number] & rom_nibble_mask;
+
+ // If the upper nibble is the mask then shift bits to lower nibble
+ if(rom_nibble_mask > 0x0F) {
+ search_direction = search_direction >> 4;
+ }
+
+ // Get the last discrepancy bit position relative to the nibble start bit
+ bit_position = LastDiscrepancy - nibble_start_bit;
+
+ // Check if last discrepancy is witin this nibble
+ if( (bit_position >= 0) && (bit_position < 4) )
+ {
+ // Last discrepancy is within this nibble
+ // Set the bit of the last discrepancy bit
+ search_direction |= (1 << (bit_position));
+ }
+
+ // Performs two read bits and a write bit for 4 bits of the ROM
+ readValue = OWM_TouchByte(owm, search_direction);
+ // Get discrepancy flags
+ discrepancy = readValue & 0xF;
+ // Get the 4 bits sent to select the ROM
+ sentBits = (readValue >> 4) & 0xF;
+
+ // Store the bit location of the MSB discrepancy with sentbit = 0
+ if(discrepancy)
+ {
+ // Initialize bit_position to MSB of nibble
+ bit_position = 3;
+
+ while(bit_position >= 0)
+ {
+ // Get discrepancy flag of the current bit position
+ discrepancy_mask = discrepancy & (1 << bit_position);
+
+ // If there is a discrepancy and the sent bit is 0 save this bit position
+ if( (discrepancy_mask) && !(sentBits & discrepancy_mask))
+ {
+ last_zero = nibble_start_bit + bit_position;
+ break;
+ }
+
+ bit_position--;
+ }
+ }
+
+ // Clear the nibble
+ ROMCode[rom_byte_number] &= ~rom_nibble_mask;
+
+ // Store the sentBits in the ROMCode
+ if(rom_nibble_mask > 0x0F) {
+ ROMCode[rom_byte_number] |= (sentBits << 4);
+ }
+ else {
+ ROMCode[rom_byte_number] |= sentBits;
+ }
+
+ // Increment the nibble start bit and shift mask
+ nibble_start_bit += 4;
+ rom_nibble_mask <<= 4;
+
+ // If the mask is 0 then go to new ROM byte rom_byte_number and reset mask
+ if (rom_nibble_mask == 0)
+ {
+ rom_byte_number++;
+ rom_nibble_mask = 0x0F;
+ }
+
+ } // End while(rom_byte_number < 8)
+
+ // Clear search ROM accelerator
+ owm->ctrl_stat &= ~(MXC_F_OWM_CTRL_STAT_SRA_MODE);
+
+ // Calculate CRC to verify ROM code is correct
+ crc8 = CalculateCRC8(ROMCode, 7);
+
+ // If the search was successful then
+ if ((nibble_start_bit >= 65) && (crc8 == ROMCode[7]))
+ {
+ // Search successful so set LastDiscrepancy,LastDeviceFlag,search_result
+ LastDiscrepancy = last_zero;
+
+ // Check for last device
+ if (LastDiscrepancy == 0) {
+ LastDeviceFlag = 1;
+ }
+
+ search_result = 1;
+ }
+ } // End if (OWM_Reset)
+
+ // If no device found then reset counters so next 'search' will be like a first
+ if (!search_result || !ROMCode[0])
+ {
+ LastDiscrepancy = 0;
+ LastDeviceFlag = 0;
+ search_result = 0;
+ }
+
+ return search_result;
+}
+
+/*
+ * Calcualate CRC8 of the buffer of data provided
+ */
+uint8_t CalculateCRC8(uint8_t* data, int len)
+{
+ int i;
+ uint8_t crc = 0;
+
+ for(i = 0; i < len; i++)
+ {
+ crc = update_crc8(crc, data[i]);
+ }
+
+ return crc;
+}
+
+/*
+ * Calculate the CRC8 of the byte value provided with the current crc value
+ * provided Returns updated crc value
+ */
+uint8_t update_crc8(uint8_t crc, uint8_t val)
+{
+ uint8_t inc, tmp;
+
+ for (inc = 0; inc < 8; inc++)
+ {
+ tmp = (uint8_t)(crc << 7); // Save X7 bit value
+ crc >>= 1; // Shift crc
+ if (((tmp >> 7) ^ (val & 0x01)) == 1) // If X7 xor X8 (input data)
+ {
+ crc ^= 0x8c; // XOR crc with X4 and X5, X1 = X7^X8
+ crc |= 0x80; // Carry
+ }
+ val >>= 1;
+ }
+
+ return crc;
+}
+
+/**@} end of group owm */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/owm.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,320 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the 1-Wire Master
+ * peripheral module.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-03-14 10:08:53 -0500 (Mon, 14 Mar 2016) $
+ * $Revision: 21855 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _OWM_H_
+#define _OWM_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "owm_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup owm 1-Wire Master (OWM)
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type for 1-Wire Overdrive Speed Options.
+ */
+typedef enum {
+ OWM_OVERDRIVE_UNUSED = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US, /**< 12us Overdrive Speed Select. */
+ OWM_OVERDRIVE_12US = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_12US, /**< 12us Overdrive Speed Select. */
+ OWM_OVERDRIVE_10US = MXC_V_OWM_CTRL_STAT_OD_SPEC_MODE_10US /**< 10us Overdrive Speed Select. */
+} owm_overdrive_t;
+
+/**
+ * Enumeration type for specifying options for 1-Wire external pullup mode.
+ */
+typedef enum {
+ OWM_EXT_PU_ACT_HIGH = 0, /**< Pullup pin is active high when enabled. */
+ OWM_EXT_PU_ACT_LOW = 1, /**< Pullup pin is active low when enabled. */
+ OWM_EXT_PU_UNUSED = 2, /**< Pullup pin is not used for an external pullup. */
+} owm_ext_pu_t;
+
+/**
+ * Structure type for 1-Wire Master configuration.
+ */
+typedef struct {
+ uint8_t int_pu_en; /**< 1 = internal pullup on. */
+ owm_ext_pu_t ext_pu_mode; /**< See #owm_ext_pu_t. */
+ uint8_t long_line_mode; /**< 1 = long line mode enable. */
+ owm_overdrive_t overdrive_spec; /**< 0 = timeslot is 12us, 1 = timeslot is 10us. */
+} owm_cfg_t;
+
+
+#define READ_ROM_COMMAND 0x33 /**< Read ROM Command */
+#define MATCH_ROM_COMMAND 0x55 /**< Match ROM Command */
+#define SEARCH_ROM_COMMAND 0xF0 /**< Search ROM Command */
+#define SKIP_ROM_COMMAND 0xCC /**< Skip ROM Command */
+#define OD_SKIP_ROM_COMMAND 0x3C /**< Overdrive Skip ROM Command */
+#define OD_MATCH_ROM_COMMAND 0x69 /**< Overdrive Match ROM Command */
+#define RESUME_COMMAND 0xA5 /**< Resume Command */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize and enable OWM module.
+ * @param owm Pointer to OWM regs.
+ * @param cfg Pointer to OWM configuration.
+ * @param sys_cfg Pointer to system configuration object
+ *
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_NULL_PTR if parameter is a null pointer
+ * @retval #E_BUSY if IOMAN was not configured correctly
+ * @retval #E_UNINITIALIZED if OWM CLK disabled
+ * @retval #E_NOT_SUPPORTED if 1MHz CLK cannot be created with given system and owm CLK
+ * @retval #E_BAD_PARAM if bad cfg parameter passed in
+ */
+int OWM_Init(mxc_owm_regs_t *owm, const owm_cfg_t *cfg, const sys_cfg_owm_t *sys_cfg);
+
+/**
+ * @brief Shutdown OWM module.
+ * @param owm Pointer to OWM regs.
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_BUSY if IOMAN was not released
+ */
+int OWM_Shutdown(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Send 1-Wire reset pulse. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @retval (0) = no presence pulse detected, (1) = presence pulse detected
+ */
+int OWM_Reset(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Send and receive one byte of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param data data to send
+ * @retval data read (1 byte)
+ */
+int OWM_TouchByte(mxc_owm_regs_t *owm, uint8_t data);
+
+/**
+ * @brief Write one byte of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param data data to send
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if data written != data parameter
+ */
+int OWM_WriteByte(mxc_owm_regs_t *owm, uint8_t data);
+
+/**
+ * @brief Read one byte of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @retval data read (1 byte)
+ */
+int OWM_ReadByte(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Send and receive one bit of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param bit bit to send
+ * @retval bit read
+ */
+int OWM_TouchBit(mxc_owm_regs_t *owm, uint8_t bit);
+
+/**
+ * @brief Write one bit of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param bit bit to send
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if bit written != bit parameter
+ */
+int OWM_WriteBit(mxc_owm_regs_t *owm, uint8_t bit);
+
+/**
+ * @brief Read one bit of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @retval bit read
+ */
+int OWM_ReadBit(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Write multiple bytes of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param data Pointer to buffer for write data.
+ * @param len Number of bytes to write.
+ *
+ * @retval Number of bytes written if successful
+ * @retval #E_COMM_ERR if line short detected before transaction
+ */
+int OWM_Write(mxc_owm_regs_t *owm, uint8_t* data, int len);
+
+/**
+ * @brief Read multiple bytes of data. Will block until transaction is complete.
+ * @param owm Pointer to OWM regs.
+ * @param data Pointer to buffer for read data.
+ * @param len Number of bytes to read.
+ *
+ * @retval Number of bytes read if successful
+ * @retval #E_COMM_ERR if line short detected before transaction
+ */
+int OWM_Read(mxc_owm_regs_t *owm, uint8_t* data, int len);
+
+/**
+ * @brief Starts 1-Wire communication with Read ROM command
+ * @note Only use the Read ROM command with one slave on the bus
+ * @param owm Pointer to OWM regs.
+ * @param ROMCode Pointer to buffer for ROM code read
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset, read or write fails
+ */
+int OWM_ReadROM(mxc_owm_regs_t *owm, uint8_t* ROMCode);
+
+/**
+ * @brief Starts 1-Wire communication with Match ROM command
+ * @param owm Pointer to OWM regs.
+ * @param ROMCode Pointer to buffer with ROM code to match
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset or write fails
+ */
+int OWM_MatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode);
+
+/**
+ * @brief Starts 1-Wire communication with Overdrive Match ROM command
+ * @note After Overdrive Match ROM command is sent, the OWM is set to
+ * overdrive speed. To set back to standard speed use OWM_SetOverdrive.
+ * @param owm Pointer to OWM regs.
+ * @param ROMCode Pointer to buffer with ROM code to match
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset or write fails
+ */
+int OWM_ODMatchROM(mxc_owm_regs_t *owm, uint8_t* ROMCode);
+
+/**
+ * @brief Starts 1-Wire communication with Skip ROM command
+ * @param owm Pointer to OWM regs.
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset or write fails
+ */
+int OWM_SkipROM(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Starts 1-Wire communication with Overdrive Skip ROM command
+ * @note After Overdrive Skip ROM command is sent, the OWM is set to
+ * overdrive speed. To set back to standard speed use OWM_SetOverdrive
+ * @param owm Pointer to OWM regs.
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset or write fails
+ */
+int OWM_ODSkipROM(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Starts 1-Wire communication with Resume command
+ * @param owm Pointer to OWM regs.
+ * @retval #E_NO_ERROR if everything is successful
+ * @retval #E_COMM_ERR if reset or write fails
+ */
+int OWM_Resume(mxc_owm_regs_t *owm);
+
+/**
+ * @brief Starts 1-Wire communication with Search ROM command
+ * @param owm Pointer to OWM regs.
+ * @param newSearch (1) = start new search, (0) = continue search for next ROM
+ * @param ROMCode Pointer to buffer with ROM code found
+ * @retval (1) = ROM found, (0) = no new ROM found, end of search
+ */
+int OWM_SearchROM(mxc_owm_regs_t *owm, int newSearch, uint8_t* ROMCode);
+
+/**
+ * @brief Clear interrupt flags.
+ * @param owm Pointer to OWM regs.
+ * @param mask Mask of interrupts to clear.
+ */
+__STATIC_INLINE void OWM_ClearFlags(mxc_owm_regs_t *owm, uint32_t mask)
+{
+ owm->intfl = mask;
+}
+
+/**
+ * @brief Get interrupt flags.
+ * @param owm Pointer to OWM regs.
+ * @retval Mask of active flags.
+ */
+__STATIC_INLINE unsigned OWM_GetFlags(mxc_owm_regs_t *owm)
+{
+ return (owm->intfl);
+}
+
+/**
+ * @brief Enables/Disables the External pullup
+ * @param owm Pointer to OWM regs.
+ * @param enable (1) = enable, (0) = disable
+ */
+__STATIC_INLINE void OWM_SetExtPullup(mxc_owm_regs_t *owm, int enable)
+{
+ if(enable)
+ owm->cfg |= MXC_F_OWM_CFG_EXT_PULLUP_ENABLE;
+ else
+ owm->cfg &= ~(MXC_F_OWM_CFG_EXT_PULLUP_ENABLE);
+}
+
+/**
+ * @brief Enables/Disables Overdrive speed
+ * @param owm Pointer to OWM regs.
+ * @param enable (1) = overdrive, (0) = standard
+ */
+__STATIC_INLINE void OWM_SetOverdrive(mxc_owm_regs_t *owm, int enable)
+{
+ if(enable)
+ owm->cfg |= MXC_F_OWM_CFG_OVERDRIVE;
+ else
+ owm->cfg &= ~(MXC_F_OWM_CFG_OVERDRIVE);
+}
+
+/**@} end of group owm */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _OWM_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,246 @@
+/**
+ * @file
+ * @brief Peripheral Management Unit (PMU) Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:44:03 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24328 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stdio.h>
+#include <stddef.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "pmu.h"
+/**
+ * @ingroup pmuGroup
+ * @{
+ */
+
+#if (MXC_PMU_REV == 0)
+/* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */
+#include "clkman_regs.h"
+/* Channel 5 infinite loop program */
+static const uint32_t pmu_0[] = {
+ PMU_JUMP(0, 0, (uint32_t)pmu_0)
+};
+#endif
+
+/* **** Local Function Prototypes **** */
+static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int);
+
+
+/* ************************************************************************* */
+void PMU_Handler(void)
+{
+ int channel;
+ uint32_t cfg1, cfg2;
+ mxc_pmu_regs_t *MXC_PMUn;
+
+ for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) {
+ MXC_PMUn = &MXC_PMU0[channel];
+
+ if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) {
+ cfg1 = MXC_PMUn->cfg;
+ /* Since any set flags will be cleared by the write-back below, mask them off */
+ cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT);
+
+ /* Clear the interrupt flag */
+ MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT;
+
+ if (callbacks[channel]) {
+ callbacks[channel](cfg1);
+ }
+ }
+ }
+}
+
+/* ************************************************************************* */
+int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback)
+{
+ if(channel >= MXC_CFG_PMU_CHANNELS)
+ return E_BAD_PARAM;
+
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ uint32_t cfg = MXC_PMUn->cfg;
+
+ /* is this channel already running? */
+ if (cfg & MXC_F_PMU_CFG_ENABLE) {
+ return E_BUSY;
+ }
+
+#if (MXC_PMU_REV == 0)
+ /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
+ if (channel == 5) {
+ /* Channel 5 is used for the work-around */
+ return E_BUSY;
+ }
+ /* Select always-ON clock for PMU */
+ MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER;
+ /* Start channel 5 with infinite-loop program */
+ MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */
+ MXC_PMU5->dscadr = (uint32_t)pmu_0;
+ MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
+#endif
+ /* Set callback */
+ callbacks[channel] = callback;
+
+ /* Set start op-code */
+ MXC_PMUn->dscadr = (uint32_t)program_address;
+
+ /* Configure the channel */
+ cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
+
+ /* Enable if necessary */
+ if (callback) {
+ cfg |= MXC_F_PMU_CFG_INT_EN;
+ } else {
+ cfg &= ~MXC_F_PMU_CFG_INT_EN;
+ }
+
+ /* Start the channel */
+ cfg |= MXC_F_PMU_CFG_ENABLE;
+
+ /*If any W1C flags are set, this write will clear them */
+ MXC_PMUn->cfg = cfg;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void PMU_Stop(unsigned int channel)
+{
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ uint32_t cfg = MXC_PMUn->cfg;
+
+ /* Since any set flags will be cleared by the write-back below, mask them off */
+ cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
+
+ /* Clear the enable bit to stop the channel */
+ cfg &= ~MXC_F_PMU_CFG_ENABLE;
+
+ MXC_PMUn->cfg = cfg;
+
+ /* Remove callback */
+ callbacks[channel] = NULL;
+
+#if (MXC_PMU_REV == 0)
+ /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
+ /* Check channels 0-4 for any running channels. If none found, stop channel 5 */
+ if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
+ (MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
+ (MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
+ (MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
+ (MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) {
+ MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE;
+ }
+#endif
+
+}
+
+/* ************************************************************************* */
+int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value)
+{
+ if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1)
+ return E_BAD_PARAM;
+
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+
+ if (counter == 0) {
+ MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS);
+ } else {
+ MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS);
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks)
+{
+ if(channel >= MXC_CFG_PMU_CHANNELS)
+ return E_BAD_PARAM;
+
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ uint32_t cfg = MXC_PMUn->cfg;
+
+ /* Since any set flags will be cleared by the write-back below, mask them off */
+ cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
+
+ /* Adjust timeout settings */
+ cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL);
+ cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) |
+ ((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL);
+
+ MXC_PMUn->cfg = cfg;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+uint32_t PMU_GetFlags(unsigned int channel)
+{
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ uint32_t cfg = MXC_PMUn->cfg;
+
+ /* Mask off configuration bits leaving only flag bits */
+ cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL |
+ MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE);
+
+ return cfg;
+}
+
+/* ************************************************************************* */
+void PMU_ClearFlags(unsigned int channel, unsigned int mask)
+{
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ uint32_t cfg = MXC_PMUn->cfg;
+
+ /* Since any set flags will be cleared by the write-back below, mask them off */
+ cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
+
+ /* Now, apply the caller-supplied bits to clear */
+ cfg |= mask;
+
+ MXC_PMUn->cfg = cfg;
+}
+
+/* ************************************************************************* */
+uint32_t PMU_IsActive(unsigned int channel)
+{
+ mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
+ return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE);
+}
+/**@} end of ingroup pmuGroup */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,299 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the PMU module.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24667 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _PMU_H_
+#define _PMU_H_
+
+/* **** Includes **** */
+#include "pmu_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup pmuGroup Peripheral Management Unit
+ * @brief Peripheral Management Unit (PMU) Interface.
+ * @{
+ */
+
+/**
+ * Enum type for the clock scale used for the PMU timeout clock.
+ */
+typedef enum {
+ PMU_PS_SEL_DISABLE = MXC_V_PMU_CFG_PS_SEL_DISABLE, /**< Timeout disabled */
+ PMU_PS_SEL_DIV_2_8 = MXC_V_PMU_CFG_PS_SEL_DIV_2_8, /**< Timeout clk = PMU clock / 2^8 = 256 */
+ PMU_PS_SEL_DIV_2_16 = MXC_V_PMU_CFG_PS_SEL_DIV_2_16, /**< Timeout clk = PMU clock / 2^16 = 65536 */
+ PMU_PS_SEL_DIV_2_24 = MXC_V_PMU_CFG_PS_SEL_DIV_2_24 /**< Timeout clk = PMU clock / 2^24 = 16777216 */
+}pmu_ps_sel_t;
+
+/**
+ * Enumeration type for the number of clk ticks for the timeout duration.
+ */
+typedef enum {
+ PMU_TO_SEL_TICKS_4 = MXC_V_PMU_CFG_TO_SEL_TICKS_4, /**< timeout = 4 * Timeout clk period */
+ PMU_TO_SEL_TICKS_8 = MXC_V_PMU_CFG_TO_SEL_TICKS_8, /**< timeout = 8 * Timeout clk period */
+ PMU_TO_SEL_TICKS_16 = MXC_V_PMU_CFG_TO_SEL_TICKS_16, /**< timeout = 16 * Timeout clk period */
+ PMU_TO_SEL_TICKS_32 = MXC_V_PMU_CFG_TO_SEL_TICKS_32, /**< timeout = 32 * Timeout clk period */
+ PMU_TO_SEL_TICKS_64 = MXC_V_PMU_CFG_TO_SEL_TICKS_64, /**< timeout = 64 * Timeout clk period */
+ PMU_TO_SEL_TICKS_128 = MXC_V_PMU_CFG_TO_SEL_TICKS_128, /**< timeout = 128 * Timeout clk period */
+ PMU_TO_SEL_TICKS_256 = MXC_V_PMU_CFG_TO_SEL_TICKS_256, /**< timeout = 256 * Timeout clk period */
+ PMU_TO_SEL_TICKS_512 = MXC_V_PMU_CFG_TO_SEL_TICKS_512 /**< timeout = 512 * Timeout clk period */
+}pmu_to_sel_t;
+
+/*
+ * The macros like the one below are designed to help build static PMU programs
+ * as arrays of 32bit words.
+ */
+#define PMU_IS(interrupt, stop) ((!!interrupt) << PMU_INT_POS) | ((!!stop) << PMU_STOP_POS)
+/*
+ * Structure type to build a PMU Move Op Code.
+ */
+typedef struct pmu_move_des_t {
+ uint32_t op_code : 3; /* 0x0 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t read_size : 2;
+ uint32_t read_inc : 1;
+ uint32_t write_size : 2;
+ uint32_t write_inc : 1;
+ uint32_t cont : 1;
+ uint32_t length : 20;
+
+ uint32_t write_address;
+ uint32_t read_address;
+} pmu_move_des_t;
+#define PMU_MOVE(i, s, rs, ri, ws, wi, c, length, wa, ra) \
+ (PMU_MOVE_OP | PMU_IS(i,s) | ((rs & 3) << PMU_MOVE_READS_POS) | ((!!ri) << PMU_MOVE_READI_POS) | \
+ ((ws & 3) << PMU_MOVE_WRITES_POS) | ((!!wi) << PMU_MOVE_WRITEI_POS) | ((!!c) << PMU_MOVE_CONT_POS) | ((length & 0xFFFFF) << PMU_MOVE_LEN_POS)), wa, ra
+
+/* new_value = value | (old_value & ~ mask) */
+typedef struct pmu_write_des_t {
+ uint32_t op_code : 3; /* 0x1 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t : 3;
+ uint32_t write_method : 4;
+ uint32_t : 20;
+
+ uint32_t write_address;
+ uint32_t value;
+ uint32_t mask;
+} pmu_write_des_t;
+#define PMU_WRITE(i, s, wm, a, v, m) (PMU_WRITE_OP | PMU_IS(i,s) | ((wm & 0xF) << PMU_WRITE_METHOD_POS)), a, v, m
+
+typedef struct pmu_wait_des_t {
+ uint32_t op_code : 3; /* 0x2 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t wait : 1;
+ uint32_t sel : 1;
+ uint32_t : 25;
+
+ uint32_t mask1;
+ uint32_t mask2;
+ uint32_t wait_count;
+} pmu_wait_des_t;
+#define PMU_WAIT(i, s, sel, m1, m2, cnt) (PMU_WAIT_OP | PMU_IS(i,s) | ((cnt>0)?(1<<PMU_WAIT_WAIT_POS):0) | ((!!sel) << PMU_WAIT_SEL_POS)), \
+ m1, m2, cnt
+
+typedef struct pmu_jump_des_t {
+ uint32_t op_code : 3; /* 0x3 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t : 27;
+
+ uint32_t address;
+} pmu_jump_des_t;
+#define PMU_JUMP(i, s, a) (PMU_JUMP_OP | PMU_IS(i,s)), a
+
+typedef struct pmu_loop_des_t {
+ uint32_t op_code : 3; /* 0x4 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t sel_counter : 1;
+ uint32_t : 26;
+
+ uint32_t address;
+} pmu_loop_des_t;
+#define PMU_LOOP(i, s, c, a) (PMU_LOOP_OP | PMU_IS(i,s) | ((!!c) << PMU_LOOP_SEL_COUNTER_POS)), a
+
+typedef struct pmu_poll_des_t {
+ uint32_t op_code : 3; /* 0x5 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t : 2;
+ uint32_t and : 1;
+ uint32_t : 24;
+
+ uint32_t poll_addr;
+ uint32_t data;
+ uint32_t mask;
+ uint32_t poll_interval;
+} pmu_poll_des_t;
+#define PMU_POLL(i, s, a, adr, d, m, per) (PMU_POLL_OP | PMU_IS(i,s) | ((!!a) << PMU_POLL_AND_POS)), adr, d, m, per
+
+typedef struct pmu_branch_des_t {
+ uint32_t op_code : 3; /* 0x6 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t : 2;
+ uint32_t and : 1;
+ uint32_t type : 3;
+ uint32_t : 21;
+
+ uint32_t poll_addr;
+ uint32_t data;
+ uint32_t mask;
+ uint32_t address;
+} pmu_branch_des_t;
+#define PMU_BRANCH(i, s, a, t, adr, d, m, badr) \
+ (PMU_BRANCH_OP | PMU_IS(i,s) | ((!!a) << PMU_BRANCH_AND_POS)| ((t & 7) << PMU_BRANCH_TYPE_POS)), adr, d, m, badr
+
+typedef struct pmu_transfer_des_t {
+ uint32_t op_code : 3; /* 0x7 */
+ uint32_t interrupt : 1;
+ uint32_t stop : 1;
+ uint32_t read_size : 2;
+ uint32_t read_inc : 1;
+ uint32_t write_size : 2;
+ uint32_t write_inc : 1;
+ uint32_t : 1;
+ uint32_t tx_length : 20;
+
+ uint32_t write_address;
+ uint32_t read_address;
+
+ uint32_t int_mask : 25; /* valid int_mask is from 0 - 24 */
+ uint32_t : 1;
+ uint32_t burst_size : 6;
+} pmu_transfer_des_t;
+#define PMU_TRANSFER(i, s, rs, ri, ws, wi, l, wa, ra, imsk, b) \
+ (PMU_TRANSFER_OP | PMU_IS(i,s) | ((rs & 3) << PMU_TX_READS_POS) | ((!!ri) << PMU_TX_READI_POS) | \
+ ((ws & 3) << PMU_TX_WRITES_POS) | ((!!wi) << PMU_TX_WRITEI_POS) | ((l & 0xFFFFF) << PMU_TX_LEN_POS)), wa, ra, \
+ ((imsk) | ((b & 0x3F) << PMU_TX_BS_POS))
+/**
+ * Callback function type for the PMU.
+ * @details The callback function signature is:
+ * @code
+ * void callback(int status);
+ * @endcode
+ * @p pmu_status - The callback function argument is a status bit
+ * indicating the status of the PMU program. The callback function
+ * will be called for every opcode that has the interrupt bit set.
+ * If NULL, the channel interrupt will not be enabled.
+ */
+typedef void (*pmu_callback)(int pmu_status);
+
+/**
+ * @brief Start a PMU program on a channel
+ *
+ * @param[in] channel The channel number to start the PMU program.
+ * @param[in] program_address A pointer to the first opcode of the PMU program.
+ * @param[in] callback A pointer to the callback function or NULL. See pmu_callback() for details.
+ *
+ * @return #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback);
+
+/**
+ * @brief Set a loop counter value on a channel
+ * @param channel Channel number to set the value on
+ * @param counter_num Counter number for the channel (0 or 1)
+ * @param value Loop count value
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int PMU_SetCounter(unsigned int channel, unsigned int counter_num, uint16_t value);
+
+/**
+ * @brief Stop a running channel. This will clear the enable bit on the channel
+ * and stop the running PMU program at the current opcode. The callback
+ * function is not called.
+ * @param channel Channel to stop
+ */
+void PMU_Stop(unsigned int channel);
+
+/**
+ * @brief Function to handle PMU interrupts. This function can be called from
+ * the PMU interrupt service routine, or periodically from the
+ * application if interrupts are not enabled.
+ */
+void PMU_Handler(void);
+
+/**
+ * @brief Set the AHB bus operation timeout on a channel
+ * @param channel Selected PMU channel
+ * @param timeoutClkScale Clk scale use for timeout clk
+ * @param timeoutTicks Number of ticks for timeout duration
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks);
+
+/**
+ * @brief Gets the PMU channel's flags
+ * @param channel Selected PMU channel
+ * @return 0 = flags not set, non-zero = flags
+ */
+uint32_t PMU_GetFlags(unsigned int channel);
+
+/**
+ * @brief Clear the PMU channel's flags based on the mask
+ * @param channel Selected PMU channel
+ * @param mask bits of the flags to clear
+ */
+void PMU_ClearFlags(unsigned int channel, unsigned int mask);
+
+/**
+ * @brief Determines if the PMU channel is running
+ * @param channel Selected PMU channel
+ * @return 0 - channel is off
+ * @return non-zero = channel is running
+ */
+uint32_t PMU_IsActive(unsigned int channel);
+
+/**@} end of group pmuGroup*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PMU_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/prng.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,62 @@
+
+/**
+ * @file
+ * @brief PRNG diver source.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:26:15 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24668 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "prng.h"
+#include "mxc_sys.h"
+
+/**
+ * @ingroup prng
+ * @{
+ */
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+void PRNG_Init(void)
+{
+ SYS_PRNG_Init();
+}
+/**@} end of ingroup prng */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/prng.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,123 @@
+/**
+ * @file
+ * @brief Pseudo-random number generator(PRNG) Peripheral Module.
+ * @note The PRNG hardware does not produce true random numbers. The
+ * output should be used as a seed to an approved random-number
+ * algorithm, per a certifying authority such as NIST or PCI. The
+ * approved algorithm will output random numbers which are cerfitied
+ * for use in encryption and authentication algorithms.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:26:15 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24668 $
+ *
+ ******************************************************************************/
+
+/* **** Includes **** */
+#include "prng_regs.h"
+
+/* Define to prevent redundant inclusion */
+#ifndef _PRNG_H_
+#define _PRNG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup prng Pseudo-Random Number Generator (PRNG)
+ * @brief Pseudo-random number generator(PRNG) Peripheral Module.
+ * @note The PRNG hardware does not produce true random numbers. The
+ * output should be used as a seed to an approved random-number
+ * algorithm, per a certifying authority such as NIST or PCI. The
+ * approved algorithm will output random numbers which are cerfitied
+ * for use in encryption and authentication algorithms.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize required clocks and enable PRNG module
+ * @note This function will set the clock divisors to divide by 1 if they are disabled.
+ * Otherwise, the clock divisors are left unchanged.
+ */
+void PRNG_Init(void);
+
+/**
+ * @brief Returns ready bit to indicates that the PRNG_GetSeed can be
+ * called without being held off. Only needs to be called one time after a POR event.
+ *
+ * @retval 0 PRNG not ready
+ * @retval non-zero PRNG ready to read
+ */
+__STATIC_INLINE uint16_t PRNG_Ready(void)
+{
+ return (MXC_PRNG->user_entropy & MXC_F_PRNG_USER_ENTROPY_RND_NUM_READY);
+}
+
+/**
+ * @brief Retrieve a seed value from the PRNG.
+ * @note The PRNG hardware does not produce true random numbers. The
+ * output should be used as a seed to an approved random-number
+ * algorithm, per a certifying authority such as NIST or PCI. The
+ * approved algorithm will output random numbers which are cerfitied
+ * for use in encryption and authentication algorithms.
+ *
+ * @return 16-bit seed value
+ */
+__STATIC_INLINE uint16_t PRNG_GetSeed(void)
+{
+ return MXC_PRNG->rnd_num;
+}
+
+/**
+ * @brief Add user entropy to the PRNG entropy source.
+ *
+ * @param entropy A value to be mixed into the PRNG entropy source.
+ */
+__STATIC_INLINE void PRNG_AddUserEntropy(uint8_t entropy)
+{
+ MXC_PRNG->user_entropy = (uint32_t)entropy;
+}
+/**@}*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PRNG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,145 @@
+/**
+ * @file
+ * @brief Pulse Train Engine Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:43:36 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24327 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "pt.h"
+
+/**
+ * @ingroup pulsetrain
+ * @{
+ */
+
+/* ************************************************************************* */
+void PT_Init(sys_pt_clk_scale clk_scale)
+{
+ //disable all pulse trains
+ MXC_PTG->enable = 0;
+
+ //clear all interrupts
+ MXC_PTG->intfl = MXC_PTG->intfl;
+
+ SYS_PT_Init(clk_scale);
+}
+
+/* ************************************************************************* */
+int PT_PTConfig(mxc_pt_regs_t *pt, pt_pt_cfg_t *cfg, const sys_cfg_pt_t *sysCfg)
+{
+ int err;
+ uint32_t ptClock;
+ uint32_t rate;
+
+ //check for valid base pointer
+ MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0);
+
+ if(cfg == NULL)
+ return E_NULL_PTR;
+
+ if(cfg->bps == 0)
+ return E_BAD_PARAM;
+
+ //disable pulse train
+ PT_Stop(pt);
+
+ //setup system GPIO configuration
+ if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR)
+ return err;
+
+ //get PT clock frequency from SYS level
+ ptClock = SYS_PT_GetFreq();
+
+ if(ptClock == 0)
+ return E_UNINITIALIZED;
+
+ if(ptClock < (cfg->bps))
+ return E_BAD_STATE;
+
+ rate = (ptClock / (cfg->bps));
+
+ pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)
+ & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) |
+ ((cfg->ptLength << MXC_F_PT_RATE_LENGTH_MODE_POS)
+ & MXC_F_PT_RATE_LENGTH_MODE);
+
+ pt->train = cfg->pattern;
+ pt->loop = ((cfg->loop << MXC_F_PT_LOOP_COUNT_POS) & MXC_F_PT_LOOP_COUNT) |
+ ((cfg->loopDelay << MXC_F_PT_LOOP_DELAY_POS) & MXC_F_PT_LOOP_DELAY);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int PT_SqrWaveConfig(mxc_pt_regs_t *pt, uint32_t freq, const sys_cfg_pt_t *sysCfg)
+{
+ int err;
+ uint32_t ptClock;
+ uint32_t rate;
+
+ //check for valid base pointer
+ MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0);
+
+ if(freq == 0)
+ return E_BAD_PARAM;
+
+ //disable pulse train
+ PT_Stop(pt);
+
+ //setup system GPIO configuration
+ if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR)
+ return err;
+
+ //get PT clock frequency from SYS level
+ ptClock = SYS_PT_GetFreq();
+
+ if(ptClock == 0)
+ return E_UNINITIALIZED;
+
+ if(ptClock < (2*freq))
+ return E_BAD_STATE;
+
+ rate = (ptClock / (2*freq)) + 1;
+
+ pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)
+ & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) |
+ (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS);
+
+ return E_NO_ERROR;
+}
+/**@} end of ingroup pulsetrain*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/pt.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,331 @@
+/**
+ * @file
+ * @brief Pulse Train data types, definitions and function prototypes.
+ */
+
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:27:24 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24669 $
+ *
+ ***************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _PT_H_
+#define _PT_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "pt_regs.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup pulsetrain Pulse Train Engine
+ * @brief This is the high level API for the pulse train engine.
+ * @{
+ */
+
+/**
+ * Structure type for pulse train mode configuration.
+ * @note Do not use for square wave
+ */
+typedef struct {
+ uint32_t bps; /**< pulse train bit rate */
+ uint32_t pattern; /**< Output pattern to shift out, starts at LSB */
+ uint8_t ptLength; /**< Number of bits in pulse train, 0 = 32bits, 1 = non valid , 2 = 2 bits, ... */
+ uint16_t loop; /**< Number of times to repeat the train, 0 = continuous */
+ uint16_t loopDelay; /**< Delay between loops specified in bits Example: loopDelay = 4, delays time = time it takes to shift out 4 bits */
+} pt_pt_cfg_t;
+
+/**
+ * @brief This function initializes the pulse trains to a known stopped
+ * state and sets the global PT clock scale.
+ * @param clk_scale Scale the system clock for the global PT clock.
+ */
+void PT_Init(sys_pt_clk_scale clk_scale);
+
+/**
+ * @brief Configures the pulse train in the specified mode.
+ * @details The parameters in the config structure must be set before calling
+ * this function. This function should be used for configuring pulse
+ * train mode only.
+ * @note The pulse train cannot be running when this function is called.
+ *
+ * @param pt Pulse train to operate on.
+ * @param cfg Pointer to pulse train configuration.
+ * @param sysCfg Pointer to pulse train system GPIO configuration.
+ *
+ * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes
+ * "error" if unsuccessful.
+ */
+int PT_PTConfig(mxc_pt_regs_t *pt, pt_pt_cfg_t *cfg, const sys_cfg_pt_t *sysCfg);
+
+/**
+ * @brief Configures the pulse train in the square wave mode.
+ * @details This function should be used for configuring square wave mode only.
+ * @note The pulse train cannot be running when this function is called
+ *
+ * @param pt pulse train to operate on
+ * @param freq square wave output frequency in Hz
+ * @param sysCfg pointer to pulse train system GPIO configuration
+ *
+ * @returns #E_NO_ERROR if everything is successful, \ref MXC_Error_Codes "error" if unsuccessful.
+ */
+int PT_SqrWaveConfig(mxc_pt_regs_t *pt, uint32_t freq, const sys_cfg_pt_t *sysCfg);
+
+/**
+ * @brief Starts the pulse train specified.
+ *
+ * @param pt Pulse train to operate on.
+ */
+__STATIC_INLINE void PT_Start(mxc_pt_regs_t *pt)
+{
+ int ptIndex = MXC_PT_GET_IDX(pt);
+
+ MXC_PTG->enable |= (1 << ptIndex);
+
+ //wait for PT to start
+ while( (MXC_PTG->enable & (1 << ptIndex)) == 0 );
+}
+
+/**
+ * @brief Start multiple pulse train modules together.
+ *
+ * @param pts Set the bits of pulse trains to start
+ * Bit0-\>pt0, Bit1-\>pt1... etc.
+ */
+__STATIC_INLINE void PT_StartMulti(uint32_t pts)
+{
+ MXC_PTG->enable |= pts;
+
+ //wait for PTs to start
+ while( (MXC_PTG->enable & pts) != pts );
+}
+
+/**
+ * @brief Stops a pulse train.
+ *
+ * @param pt Pulse train to operate on.
+ */
+__STATIC_INLINE void PT_Stop(mxc_pt_regs_t *pt)
+{
+ int ptIndex = MXC_PT_GET_IDX(pt);
+
+ MXC_PTG->enable &= ~(1 << ptIndex);
+}
+
+/**
+ * @brief Stop multiple pulse trains together
+ *
+ * @param pts Set the bits of pulse trains to stop
+ * Bit0-\>pt0, Bit1-\>pt1... etc.
+ */
+__STATIC_INLINE void PT_StopMulti(uint32_t pts)
+{
+ MXC_PTG->enable &= ~(pts);
+}
+
+/**
+ * @brief Determines if the pulse train is running.
+ *
+ * @param pt Pulse train to operate on.
+ *
+ * @return 0 Pulse train is off.
+ * @return \>0 Pulse train is on.
+ */
+__STATIC_INLINE uint32_t PT_IsActive(mxc_pt_regs_t *pt)
+{
+ int ptIndex = MXC_PT_GET_IDX(pt);
+
+ return (!!(MXC_PTG->enable & (1 << ptIndex)));
+}
+
+/**
+ * @brief Determines if the pulse trains selected are running
+ *
+ * @param pts Set the bits of pulse trains to check Bit0-\>pt0,
+ * Bit1-\>pt1... etc.
+ *
+ * @return 0 All pulse trains are off.
+ * @return \>0 At least one pulse train is on.
+ */
+__STATIC_INLINE uint32_t PT_IsActiveMulti(uint32_t pts)
+{
+ return (MXC_PTG->enable & pts);
+}
+
+/**
+ * @brief Sets the pattern of the pulse train
+ *
+ * @param pt Pointer to pulse train to operate on
+ * @param pattern Output pattern.
+ *
+ */
+__STATIC_INLINE void PT_SetPattern(mxc_pt_regs_t *pt, uint32_t pattern)
+{
+ pt->train = pattern;
+}
+
+/**
+ * @brief Enable pulse train interrupt.
+ *
+ * @param pt Pointer to pulse train to operate on.
+ */
+__STATIC_INLINE void PT_EnableINT(mxc_pt_regs_t *pt)
+{
+ int ptIndex = MXC_PT_GET_IDX(pt);
+
+ MXC_PTG->inten |= (1 << ptIndex);
+}
+
+/**
+ * @brief Enable interrupts for the pulse trains selected.
+ *
+ * @param pts Bit mask of which pulse trains to enable. Set the bit
+ * position of each pulse train to enable it. Bit0-\>pt0,
+ * Bit1-\>pt1... etc, 1 will enable the interrupt, 0 to leave
+ * a PT channel in its current state.
+ */
+__STATIC_INLINE void PT_EnableINTMulti(uint32_t pts)
+{
+ MXC_PTG->inten |= pts;
+}
+
+/**
+ * @brief Disable pulse train interrupt.
+ *
+ * @param pt pulse train to operate on.
+ */
+__STATIC_INLINE void PT_DisableINT(mxc_pt_regs_t *pt)
+{
+ int ptIndex = MXC_PT_GET_IDX(pt);
+
+ MXC_PTG->inten &= ~(1 << ptIndex);
+}
+
+/**
+ * @brief Disable interrupts for the pulse trains selected.
+ *
+ * @param pts Bit mask of what pulse trains to disable. Set the bit
+ * position of each pulse train to disable it. Bit0-\>pt0,
+ * Bit1-\>pt1... etc, 1 will disable the interrupt, 0 to leave
+ * a PT channel in its current state.
+ */
+__STATIC_INLINE void PT_DisableINTMulti(uint32_t pts)
+{
+ MXC_PTG->inten &= ~pts;
+}
+/**
+ * @brief Gets the pulse trains's interrupt flags.
+ *
+ * @return The Pulse Train Interrupt Flags, \ref PT_INTFL_Register Register
+ * for details.
+ */
+__STATIC_INLINE uint32_t PT_GetFlags(void)
+{
+ return MXC_PTG->intfl;
+}
+
+/**
+ * @brief Clears the pulse train's interrupt flag.
+ *
+ * @param mask bits to clear, see \ref PT_INTFL_Register Register for details.
+ */
+__STATIC_INLINE void PT_ClearFlags(uint32_t mask)
+{
+ MXC_PTG->intfl = mask;
+}
+
+/**
+ * @brief Setup and enables a pulse train to restart after another pulse
+ * train has exited its loop. Each pulse train can have up to two
+ * restart triggers.
+ *
+ * @param ptToRestart pulse train to restart after @c ptStop ends.
+ * @param ptStop pulse train that stops and triggers @p ptToRestart
+ * to begin.
+ * @param restartIndex selects which restart trigger to set (0 or 1).
+ */
+__STATIC_INLINE void PT_SetRestart(mxc_pt_regs_t *ptToRestart, mxc_pt_regs_t *ptStop, uint8_t restartIndex)
+{
+ int ptStopIndex = MXC_PT_GET_IDX(ptStop);
+
+ MXC_ASSERT(ptStopIndex >= 0);
+
+ if(restartIndex) {
+ ptToRestart->restart |= (ptStopIndex << MXC_F_PT_RESTART_PT_Y_SELECT_POS) |
+ MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT;
+ } else {
+ ptToRestart->restart |= (ptStopIndex << MXC_F_PT_RESTART_PT_X_SELECT_POS) |
+ MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT;
+ }
+}
+
+/**
+ * @brief Disable the restart for the specified pulse train
+ *
+ * @param ptToRestart pulse train to disable the restart
+ * @param restartIndex selects which restart trigger to disable (0 or 1)
+ */
+__STATIC_INLINE void PT_RestartDisable(mxc_pt_regs_t *ptToRestart, uint8_t restartIndex)
+{
+ if(restartIndex)
+ ptToRestart->restart &= ~MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT;
+ else
+ ptToRestart->restart &= ~MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT;
+}
+
+/**
+ * @brief Resynchronize individual pulse trains together. Resync will stop
+ * those resync_pts; others will be still running
+ *
+ * @param resyncPts pulse train modules that need to be re-synced by bit
+ * number. Bit0-\>pt0, Bit1-\>pt1... etc.
+ */
+__STATIC_INLINE void PT_Resync(uint32_t resyncPts)
+{
+ MXC_PTG->resync = resyncPts;
+ while(MXC_PTG->resync);
+}
+/**@} end of group pulsetrains*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _PT_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,197 @@
+/**
+ * @file
+ * @brief Real-Time Clock Function Implementations.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:43:13 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24326 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+
+#include "rtc.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+
+ /**
+ * @ingroup rtc
+ * @{
+ */
+/* ************************************************************************* */
+int RTC_Init(const rtc_cfg_t *cfg)
+{
+ int err;
+ int i = 0;
+
+ //init function -> validate configuration pointer is not NULL
+ if (cfg == NULL)
+ return E_NULL_PTR;
+ //check to make sure that the passed in parameters, prescaler mask and snooze, are valid
+ if ((cfg->prescalerMask > ((rtc_prescale_t)cfg->prescaler)) || (cfg->snoozeCount > MXC_F_RTC_SNZ_VAL_VALUE))
+ return E_INVALID;
+
+ // Set system level configurations
+ if ((err = SYS_RTC_Init()) != E_NO_ERROR) {
+ return err;
+ }
+
+ //disable rtc
+ MXC_RTCTMR->ctrl &= ~(MXC_F_RTC_CTRL_ENABLE);
+
+ //disable all interrupts
+ MXC_RTCTMR->inten = 0;
+
+ //clear all interrupts
+ MXC_RTCTMR->flags = RTC_FLAGS_CLEAR_ALL;
+
+ //reset starting count
+ MXC_RTCTMR->timer = 0;
+
+ //set the compare registers to the values passed in
+ for(i = 0; i < RTC_NUM_COMPARE; i++)
+ MXC_RTCTMR->comp[i] = cfg->compareCount[i];
+
+ // set the prescaler
+ MXC_RTCTMR->prescale = cfg->prescaler;
+ // set the prescale mask, checked it for validity on entry
+ MXC_RTCTMR->prescale_mask = cfg->prescalerMask;
+
+ //set snooze mode (rtc_snooze_t)
+ MXC_RTCTMR->ctrl &= (~MXC_F_RTC_CTRL_SNOOZE_ENABLE);
+ MXC_RTCTMR->ctrl |= (cfg->snoozeMode << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS);
+
+ //set the snooze count. Checked for validity on entry.
+ MXC_RTCTMR->snz_val = (cfg->snoozeCount << MXC_F_RTC_SNZ_VAL_VALUE_POS) & MXC_F_RTC_SNZ_VAL_VALUE;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+ //reset trim to defaults, trim disabled, trim faster override disabled
+ MXC_RTCTMR->trim_ctrl &= ~(MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R | MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R);
+
+ //set trim slower control bit to 0, which is trim faster by default
+ MXC_RTCTMR->trim_value &= ~(MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int RTC_SetCompare(uint8_t compareIndex, uint32_t counts)
+{
+ //check for invalid index
+ if (compareIndex >= RTC_NUM_COMPARE)
+ return E_INVALID;
+
+ MXC_RTCTMR->comp[compareIndex] = counts;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+uint32_t RTC_GetCompare(uint8_t compareIndex)
+{
+ //Debug Assert for Invalid Index
+ MXC_ASSERT(compareIndex < RTC_NUM_COMPARE);
+ //check for invalid index
+ if (compareIndex >= RTC_NUM_COMPARE)
+ return (uint32_t)(E_BAD_PARAM); /* Unsigned int, so if out of bounds we return 0xFFFFFFFD (-3) */
+
+ return MXC_RTCTMR->comp[compareIndex];
+}
+
+/* ************************************************************************* */
+int RTC_SetTrim(uint32_t trim, uint8_t trimSlow)
+{
+ // make sure rtc is disabled
+ if(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)
+ return E_BAD_STATE; // RTC is active, bad state
+
+ // Can check against this because it starts at bit 0 in the register
+ // Need to check because too large of a value messes with the upper bits in
+ // the trim register.
+ if (trim > MXC_F_RTC_TRIM_VALUE_TRIM_VALUE)
+ return E_INVALID;
+
+ // write the trim to the hardware trim_value register
+ MXC_RTCTMR->trim_value = (trim << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS) & MXC_F_RTC_TRIM_VALUE_TRIM_VALUE;
+
+ if(trimSlow)
+ MXC_RTCTMR->trim_value |= MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL;
+ else
+ MXC_RTCTMR->trim_value &= ~MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+uint32_t RTC_GetTrim()
+{
+ return MXC_RTCTMR->trim_value; // return the register value for trim
+}
+
+/* ************************************************************************* */
+int RTC_TrimEnable(void)
+{
+ // make sure rtc is disabled
+ if(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)
+ return E_BAD_STATE; // RTC is active, bad state
+
+ MXC_RTCTMR->trim_ctrl = MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void RTC_TrimDisable(void)
+{
+ // clear the trim enable bit
+ MXC_RTCTMR->trim_ctrl &= ~MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+ return;
+}
+
+/**@} end of ingroup rtc*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/rtc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,476 @@
+/**
+ * @file
+ * @brief Real-Time Clock data types, definitions and function prototypes.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24670 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "rtc_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup rtc Real-Time Clock (RTC)
+ * @brief Functions, types, and registers for the Real-Time Clock Peripheral.
+ * @{
+ */
+
+/* **** Definitions **** */
+/**
+ * Enumeration type for scaling down the 4096Hz input clock to the RTC.
+ */
+typedef enum {
+ RTC_PRESCALE_DIV_2_0 = MXC_V_RTC_PRESCALE_DIV_2_0, /**< \f$ f_{RTC} = \frac {4096} {2^{0}} = 4096Hz \f$ */
+ RTC_PRESCALE_DIV_2_1 = MXC_V_RTC_PRESCALE_DIV_2_1, /**< \f$ f_{RTC} = \frac {4096} {2^{1}} = 2048Hz \f$ */
+ RTC_PRESCALE_DIV_2_2 = MXC_V_RTC_PRESCALE_DIV_2_2, /**< \f$ f_{RTC} = \frac {4096} {2^{2}} = 1024Hz \f$ */
+ RTC_PRESCALE_DIV_2_3 = MXC_V_RTC_PRESCALE_DIV_2_3, /**< \f$ f_{RTC} = \frac {4096} {2^{3}} = 512Hz \f$ */
+ RTC_PRESCALE_DIV_2_4 = MXC_V_RTC_PRESCALE_DIV_2_4, /**< \f$ f_{RTC} = \frac {4096} {2^{4}} = 256Hz \f$ */
+ RTC_PRESCALE_DIV_2_5 = MXC_V_RTC_PRESCALE_DIV_2_5, /**< \f$ f_{RTC} = \frac {4096} {2^{5}} = 128Hz \f$ */
+ RTC_PRESCALE_DIV_2_6 = MXC_V_RTC_PRESCALE_DIV_2_6, /**< \f$ f_{RTC} = \frac {4096} {2^{6}} = 64Hz \f$ */
+ RTC_PRESCALE_DIV_2_7 = MXC_V_RTC_PRESCALE_DIV_2_7, /**< \f$ f_{RTC} = \frac {4096} {2^{7}} = 32Hz \f$ */
+ RTC_PRESCALE_DIV_2_8 = MXC_V_RTC_PRESCALE_DIV_2_8, /**< \f$ f_{RTC} = \frac {4096} {2^{8}} = 16Hz \f$ */
+ RTC_PRESCALE_DIV_2_9 = MXC_V_RTC_PRESCALE_DIV_2_9, /**< \f$ f_{RTC} = \frac {4096} {2^{9}} = 8Hz \f$ */
+ RTC_PRESCALE_DIV_2_10 = MXC_V_RTC_PRESCALE_DIV_2_10, /**< \f$ f_{RTC} = \frac {4096} {2^{10}} = 4Hz \f$ */
+ RTC_PRESCALE_DIV_2_11 = MXC_V_RTC_PRESCALE_DIV_2_11, /**< \f$ f_{RTC} = \frac {4096} {2^{11}} = 2Hz \f$ */
+ RTC_PRESCALE_DIV_2_12 = MXC_V_RTC_PRESCALE_DIV_2_12, /**< \f$ f_{RTC} = \frac {4096} {2^{12}} = 1Hz \f$ */
+} rtc_prescale_t;
+
+/**
+ * Mask of the RTC Flags for the Active Transaction.
+ */
+#define RTC_CTRL_ACTIVE_TRANS (MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE | \
+ MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE | \
+ MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE | \
+ MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE | \
+ MXC_F_RTC_CTRL_RTC_SET_ACTIVE | \
+ MXC_F_RTC_CTRL_RTC_CLR_ACTIVE | \
+ MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE | \
+ MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE | \
+ MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE | \
+ MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE | \
+ MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE | \
+ MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE | \
+ MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE | \
+ MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE | \
+ MXC_F_RTC_CTRL_ACTIVE_TRANS_0)
+
+/**
+ * Mask used to clear all RTC interrupt flags, see \ref RTC_FLAGS_Register Register.
+ */
+#define RTC_FLAGS_CLEAR_ALL (MXC_F_RTC_FLAGS_COMP0 | \
+ MXC_F_RTC_FLAGS_COMP1| \
+ MXC_F_RTC_FLAGS_PRESCALE_COMP | \
+ MXC_F_RTC_FLAGS_OVERFLOW | \
+ MXC_F_RTC_FLAGS_TRIM)
+/**
+ * Enumeration type to select the type of RTC Snooze Mode for an alarm condition.
+ */
+typedef enum {
+ RTC_SNOOZE_DISABLE = MXC_V_RTC_CTRL_SNOOZE_DISABLE, /**< Snooze Mode Disabled */
+ RTC_SNOOZE_MODE_A = MXC_V_RTC_CTRL_SNOOZE_MODE_A, /**< \f$ COMP1 = COMP1 + RTC\_SNZ\_VALUE \f$ when snooze flag is set */
+ RTC_SNOOZE_MODE_B = MXC_V_RTC_CTRL_SNOOZE_MODE_B, /**< \f$ COMP1 = RTC\_TIMER + RTC\_SNZ\_VALUE \f$ when snooze flag is set */
+} rtc_snooze_t;
+
+/**
+ * Number of RTC Compare registers for this peripheral instance.
+ */
+#define RTC_NUM_COMPARE 2
+
+/**
+ * Structure type that represents the current configuration of the RTC.
+ */
+
+typedef struct {
+ rtc_prescale_t prescaler; /**< prescale value for the input 4096Hz clock. */
+ rtc_prescale_t prescalerMask; /**< Mask value used to compare to the rtc prescale value, when the \f$ (Count_{prescaler}\,\&\,Prescale\,Mask) == 0 \f$, the prescale compare flag will be set. */
+ uint32_t compareCount[RTC_NUM_COMPARE]; /**< Values used for setting the RTC alarms. See RTC_SetCompare() and RTC_GetCompare(). */
+ uint32_t snoozeCount; /**< The number of RTC ticks to snooze if enabled. */
+ rtc_snooze_t snoozeMode; /**< The desired snooze mode, see #rtc_snooze_t. */
+} rtc_cfg_t;
+
+/**
+ * @brief Initializes the RTC
+ * @note Must setup clocking and power prior to this function.
+ *
+ * @param cfg RTC configuration object.
+ *
+ * @retval #E_NO_ERROR RTC initialized successfully.
+ * @retval #E_NULL_PTR \p cfg pointer is NULL.
+ * @retval #E_INVALID if comparison index, prescaler mask or snooze mask
+ * are out of bounds, see #rtc_cfg_t.
+ */
+int RTC_Init(const rtc_cfg_t *cfg);
+
+/**
+ * @brief Enable and start the real-time clock continuing from its current value.
+ */
+__STATIC_INLINE void RTC_Start(void)
+{
+ MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Disable and stop the real-time clock counting.
+ */
+__STATIC_INLINE void RTC_Stop(void)
+{
+ MXC_RTCTMR->ctrl &= ~(MXC_F_RTC_CTRL_ENABLE);
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Returns the state (running or disabled) for the RTC.
+ *
+ * @retval 0 Disabled.
+ * @retval Non-zero Active.
+ */
+__STATIC_INLINE uint32_t RTC_IsActive(void)
+{
+ return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
+}
+
+/**
+ * @brief Set the current count of the RTC
+ *
+ * @param count The desired count value to set for the RTC count.
+ */
+__STATIC_INLINE void RTC_SetCount(uint32_t count)
+{
+ MXC_RTCTMR->timer = count;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Get the current count value of the RTC.
+ *
+ * @retval The value of the RTC counter.
+ */
+__STATIC_INLINE uint32_t RTC_GetCount(void)
+{
+ return (MXC_RTCTMR->timer);
+}
+
+/**
+ * @brief Sets the compare value for the RTC.
+ *
+ * @param compareIndex Index of comparator to set, see #RTC_NUM_COMPARE
+ * for the total number of compare registers
+ * available.
+ * @param counts The value to set for the compare.
+ * @retval #E_NO_ERROR Compare count register set successfully for
+ * requested comparator.
+ * @retval #E_INVALID compareIndex is @>= RTC_NUM_COMPARE.
+ */
+int RTC_SetCompare(uint8_t compareIndex, uint32_t counts);
+
+/**
+ * @brief Gets the compare value for the RTC.
+ *
+ * @param compareIndex Index of the compare value to return. See #RTC_NUM_COMPARE
+ * for the total number of compare registers available.
+ *
+ * @returns The current value of the specified compare register for the RTC.
+ */
+uint32_t RTC_GetCompare(uint8_t compareIndex);
+
+/**
+ * @brief Set the prescale reload value for the real-time clock.
+ * @details The prescale reload value determines the number of 4kHz ticks
+ * that will occur before the timer is incremented.
+ * <table>
+ * <caption id="prescaler_val">Prescaler Settings and Corresponding RTC Resolutions</caption>
+ * <tr><th>PRESCALE <th>Prescale Reload <th>4kHz ticks in LSB <th>Min Timer Value (sec) <th> Max Timer Value (sec) <th>Max Timer Value (Days) <th> Max Timer Value (Years)
+ * <tr><td align="right">0h<td align="center">RTC_PRESCALE_DIV_2_0<td align="right">1<td align="right">0.00024<td align="right">1048576<td align="right">12<td align="right">0.0
+ * <tr><td align="right">1h<td align="center">RTC_PRESCALE_DIV_2_1<td align="right">2<td align="right">0.00049<td align="right">2097152<td align="right">24<td align="right">0.1
+ * <tr><td align="right">2h<td align="center">RTC_PRESCALE_DIV_2_2<td align="right">4<td align="right">0.00098<td align="right">4194304<td align="right">49<td align="right">0.1
+ * <tr><td align="right">3h<td align="center">RTC_PRESCALE_DIV_2_3<td align="right">8<td align="right">0.00195<td align="right">8388608<td align="right">97<td align="right">0.3
+ * <tr><td align="right">4h<td align="center">RTC_PRESCALE_DIV_2_4<td align="right">16<td align="right">0.00391<td align="right">16777216<td align="right">194 <td align="right">0.5
+ * <tr><td align="right">5h<td align="center">RTC_PRESCALE_DIV_2_5<td align="right">32<td align="right">0.00781<td align="right">33554432<td align="right">388 <td align="right">1.1
+ * <tr><td align="right">6h<td align="center">RTC_PRESCALE_DIV_2_6<td align="right">64<td align="right">0.01563<td align="right">67108864<td align="right">777 <td align="right">2.2
+ * <tr><td align="right">7h<td align="center">RTC_PRESCALE_DIV_2_7<td align="right">128<td align="right">0.03125<td align="right">134217728<td align="right">1553 <td align="right">4.4
+ * <tr><td align="right">8h<td align="center">RTC_PRESCALE_DIV_2_8<td align="right">256<td align="right">0.06250<td align="right">268435456<td align="right">3107 <td align="right">8.7
+ * <tr><td align="right">9h<td align="center">RTC_PRESCALE_DIV_2_9<td align="right">512<td align="right">0.12500<td align="right">536870912<td align="right">6214 <td align="right">17.5
+ * <tr><td align="right">Ah<td align="center">RTC_PRESCALE_DIV_2_10<td align="right">1024 <td align="right">0.25000<td align="right">1073741824<td align="right">12428<td align="right">34.9
+ * <tr><td align="right">Bh<td align="center">RTC_PRESCALE_DIV_2_11<td align="right">2048 <td align="right">0.50000<td align="right">2147483648<td align="right">24855<td align="right">69.8
+ * <tr><td align="right">Ch<td align="center">RTC_PRESCALE_DIV_2_12<td align="right">4096 <td align="right">1.00000<td align="right">4294967296<td align="right">49710<td align="right">139.6
+ * </table>
+ *
+ * @param prescaler Prescale value to set, see #rtc_prescale_t.
+ */
+__STATIC_INLINE void RTC_SetPrescaler(rtc_prescale_t prescaler)
+{
+ MXC_RTCTMR->prescale = prescaler;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Get the current value of the real-time clock prescaler.
+ *
+ * @retval rtc_prescale_t Returns the current RTC prescaler setting,
+ * See #rtc_prescale_t for values of the prescaler.
+ */
+__STATIC_INLINE rtc_prescale_t RTC_GetPrescaler(void)
+{
+ return (rtc_prescale_t)(MXC_RTCTMR->prescale);
+}
+
+/**
+ * @brief Set the prescaler mask, which is used to set the RTC prescale counter
+ * compare flag when the prescaler timer matches the bits indicated
+ * by the mask.
+ * @param mask A bit mask that is used to set the prescale compare flag if the
+ * prescale timer has the corresponding bits set. @note This mask must
+ * be less than or equal to the prescaler reload value.
+ * See RTC_SetPrescaler()
+ * @details When \f$ Count_{prescaler}\,\&\,Prescale\,Mask = 0 \f$, the prescale compare flag is set
+ * @retval int Returns #E_NO_ERROR if prescale value is valid and is set.
+ * @retval int Returns #E_INVALID if mask is \> than prescaler value
+ */
+__STATIC_INLINE int RTC_SetPrescalerMask(rtc_prescale_t mask)
+{
+ if (mask > ((rtc_prescale_t)(MXC_RTCTMR->prescale)))
+ {
+ return E_INVALID;
+ }
+ MXC_RTCTMR->prescale_mask = mask;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+ return E_NO_ERROR;
+}
+
+/**
+ * @brief Set the count for snooze mode. See RTC_Snooze().
+ * @details This value is used to set the snooze count. The meaning of this value is dependant on the snooze mode. p
+ * See RTC_SetSnoozeMode() for details of calculating the snooze time period based on the mode and snooze count.
+ * @param count Sets the count used for snooze when snooze mode is
+ * enabled and the snooze flag is set.
+ * @retval #E_NO_ERROR Snooze value is set correctly and value is valid.
+ * @retval #E_INVALID SnoozeCount exceeds maximum supported, see
+ * MXC_F_RTC_SNZ_VAL_VALUE
+ */
+__STATIC_INLINE int RTC_SetSnoozeCount(uint32_t count)
+{
+ // Check to make sure max value is not being exceeded
+ if (count > MXC_F_RTC_SNZ_VAL_VALUE)
+ return E_INVALID;
+
+ MXC_RTCTMR->snz_val = count;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+ return E_NO_ERROR;
+}
+
+/**
+ * @brief Gets the current Snooze Count value.
+ * @details Returns the current value for the Snooze Count. This value is
+ * used as part of the snooze calculation depending on the snooze
+ * mode. See RTC_SetSnoozeMode() for details of calculating the
+ * snooze time period based on the mode and count.
+ * @return Value of the snooze register.
+ */
+__STATIC_INLINE uint32_t RTC_GetSnoozeCount(void)
+{
+ return MXC_RTCTMR->snz_val;
+}
+
+/**
+ * @brief Activates snooze mode.
+ * @details Begins a snooze of the RTC. When this function is called
+ * the snooze time period is determined based on the snooze mode and the count.
+ * See RTC_GetCount() and RTC_SetSnoozeMode()
+ */
+__STATIC_INLINE void RTC_Snooze(void)
+{
+ MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_SNOOZE_A | MXC_F_RTC_FLAGS_SNOOZE_B;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Sets the Snooze Mode.
+ * @details <table> <caption id="snoozeModesTable">Snooze Modes</caption>
+ * <tr><th>Mode<th>Snooze Time Calculation
+ * <tr><td>RTC_SNOOZE_DISABLE<td>Snooze Disabled
+ * <tr><td>RTC_SNOOZE_MODE_A<td>\f$ compare1 = compare1 + snoozeCount \f$
+ * <tr><td>RTC_SNOOZE_MODE_B<td>\f$ compare1 = count + snoozeCount \f$
+ * </table>
+ * @note @a count is the value of the RTC counter when RTC_Snooze()
+ * is called to start a snooze cycle and @a snoozeCount is the value set by the RTC_SetSnoozeCount(uint32_t count) function.
+ *
+ * @param mode Specifies the desired snooze mode, see #rtc_snooze_t.
+ *
+ */
+__STATIC_INLINE void RTC_SetSnoozeMode(rtc_snooze_t mode)
+{
+ uint32_t ctrl;
+ // Get the control register and mask off the non-snooze bits
+ ctrl = (MXC_RTCTMR->ctrl & ~(MXC_F_RTC_CTRL_SNOOZE_ENABLE));
+ // set the requested snooze mode bits and save the settings
+ MXC_RTCTMR->ctrl = (ctrl | (mode << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS));
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Enables the interrupts specified for the RTC.
+ * @details <table>
+ * <caption id="RTC_interrupts">RTC Interrupts</caption>
+ * <tr><th>Interrupt<th>Mask
+ * <tr><td>Compare 0<td>#MXC_F_RTC_INTEN_COMP0
+ * <tr><td>Compare 1 and Snooze<td>#MXC_F_RTC_INTEN_COMP1
+ * <tr><td>Prescale Comp<td>#MXC_F_RTC_INTEN_PRESCALE_COMP
+ * <tr><td>RTC Count Overflow<td>#MXC_F_RTC_INTEN_OVERFLOW
+ * <tr><td>Trim<td>#MXC_F_RTC_INTEN_TRIM
+ * </table>
+ * @param mask A mask of the RTC interrupts to enable, 1 = Enable. See
+ * @ref RTC_FLAGS_Register Register for the RTC interrupt enable bit masks and positions.
+ */
+__STATIC_INLINE void RTC_EnableINT(uint32_t mask)
+{
+ MXC_RTCTMR->inten |= mask;
+}
+
+/**
+ * @brief Disable the interrupts specified for the RTC. See the
+ * @ref RTC_INTEN_Register Register for the RTC interrupt enable bit masks and positions.
+ *
+ * @param mask A mask of the RTC interrupts to disable, 1 = Disable.
+ */
+__STATIC_INLINE void RTC_DisableINT(uint32_t mask)
+{
+ MXC_RTCTMR->inten &= ~mask;
+}
+
+/**
+ * @brief Returns the current interrupt flags that are set.
+ *
+ * @return A mask of the current interrupt flags, see the
+ * @ref RTC_FLAGS_Register Register for the details of the RTC interrupt
+ * flags.
+ */
+__STATIC_INLINE uint32_t RTC_GetFlags(void)
+{
+ return (MXC_RTCTMR->flags);
+}
+
+/**
+ * @brief Clears the interrupt flags specified.
+ *
+ * @param mask A mask of interrupts to clear, see the @ref RTC_FLAGS_Register
+ * Register for the interrupt flag bit masks and positions.
+ */
+__STATIC_INLINE void RTC_ClearFlags(uint32_t mask)
+{
+ MXC_RTCTMR->flags = mask;
+
+ //wait for pending actions to complete
+ while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+/**
+ * @brief Gets the active transaction flags, see @ref RTC_CTRL_Register Register for the list of ACTIVE flags.
+ *
+ * @retval 0 No active transactions.
+ * @retval nonzero A mask of active transaction bits.
+ */
+__STATIC_INLINE uint32_t RTC_GetActiveTrans(void)
+{
+ return (MXC_RTCTMR->ctrl & RTC_CTRL_ACTIVE_TRANS);
+}
+
+/**
+ * @brief Sets the trim value and trim slow/fast option.
+ * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC.
+ *
+ * @param trim The desired trim value. @note The maximum trim value setting is 0x03FFFF.
+ * @param trimSlow 1 = trim slow, 0 = trim fast
+ *
+ * @return #E_NO_ERROR Trim value is valid and set.
+ * @return #E_INVALID Trim value exceeds max trim.
+ * @return #E_BAD_STATE RTC is active.
+ */
+int RTC_SetTrim(uint32_t trim, uint8_t trimSlow);
+
+/**
+ * @brief Gets the current trim value.
+ * @note Ensure RTC is disabled prior to calling this function, see RTC_Stop(void).
+ *
+ * @retval uint32_t Current trim value of RTC.
+ */
+uint32_t RTC_GetTrim(void);
+
+/**
+ * @brief Enable the trim.
+ * @warning The RTC must be disabled prior to calling this function, see RTC_Stop(void) to disable the RTC.
+ * @retval #E_NO_ERROR Trim is enabled.
+ * @retval #E_INVALID RTC is active, see RTC_Stop(void).
+ */
+int RTC_TrimEnable(void);
+
+/**
+ * @brief Disable the trim.
+ */
+void RTC_TrimDisable(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,725 @@
+/**
+ * @file
+ * @brief Serial Peripheral Interface Master (SPIM) Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:32:38 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24324 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include <string.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+#include "mxc_lock.h"
+#include "spim.h"
+
+/**
+ * @ingroup spim
+ * @{
+ */
+/* **** Definitions **** */
+#define SPIM_MAX_BYTE_LEN 32
+#define SPIM_MAX_PAGE_LEN 32
+
+/* **** Globals **** */
+
+// Saves the state of the non-blocking requests
+typedef struct {
+ spim_req_t *req;
+ unsigned head_rem;
+} spim_req_head_t;
+
+static spim_req_head_t states[MXC_CFG_SPIM_INSTANCES];
+
+/* **** Local Function Prototypes **** */
+
+static unsigned SPIM_ReadRXFIFO(mxc_spim_regs_t *spim, mxc_spim_fifo_regs_t *fifo,
+ uint8_t *data, unsigned len);
+
+static uint32_t SPIM_TransHandler(mxc_spim_regs_t *spim, spim_req_t *req, int spim_num);
+
+/* ************************************************************************* */
+int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg)
+{
+ int err, spim_num;
+ uint32_t spim_clk, clocks;
+
+ spim_num = MXC_SPIM_GET_IDX(spim);
+ MXC_ASSERT(spim_num >= 0);
+
+ // Check the input parameters
+ if(cfg == NULL)
+ return E_NULL_PTR;
+
+ if(cfg->baud == 0)
+ return E_BAD_PARAM;
+
+ // Set system level configurations
+ if ((err = SYS_SPIM_Init(spim, cfg, sys_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+
+ /* Configure the baud, make sure the SPIM clk is enabled and the baud
+ is less than the maximum */
+ spim_clk = SYS_SPIM_GetFreq(spim);
+ if((spim_clk == 0) || ((spim_clk == SystemCoreClock) && ((spim_clk/2) < cfg->baud))) {
+ return E_BAD_PARAM;
+ }
+
+ // Initialize state pointers
+ states[spim_num].req = NULL;
+ states[spim_num].head_rem = 0;
+
+ // Drain the FIFOs, enable SPIM, enable SCK Feedback
+ spim->gen_ctrl = 0;
+ spim->gen_ctrl = (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN | MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN |
+ MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE);
+
+ // Set mode and page size
+ spim->mstr_cfg = (((cfg->mode << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS) & MXC_F_SPIM_MSTR_CFG_SPI_MODE) |
+ MXC_S_SPIM_MSTR_CFG_PAGE_32B | (0x2 << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS));
+
+ // Configure the SSEL polarity
+ spim->ss_sr_polarity = ((cfg->ssel_pol << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS) &
+ MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY);
+
+#if(MXC_SPIM_REV == 0)
+ // Disable the feedback clock in modes 1 and 2
+ if((cfg->mode == 1) || (cfg->mode == 2)) {
+ spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE;
+ spim->mstr_cfg |= (0x1 << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS);
+ }
+#else
+ // Increase the RX FIFO margin
+ MXC_SPIM1->spcl_ctrl = ((MXC_SPIM1->spcl_ctrl & ~(MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN)) |
+ (0x3 << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS));
+#endif
+
+ // Calculate the hi/lo clock setting
+ if(spim_clk/2 > cfg->baud) {
+
+ /* Disable the feedback mode and use the sample mode with an appropriate hi/lo clk
+ to achieve the lower baud rate */
+ spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE;
+
+ clocks = (spim_clk / (2*cfg->baud));
+
+ if(clocks == 0 || clocks > 0x10) {
+ return E_BAD_PARAM;
+ }
+
+ // 0 => 16 in the 4 bit field for HI_CLK and LO_CLK
+ if(clocks == 0x10) {
+ clocks = 0;
+ }
+
+ } else {
+ // Continue to use feedback mode and set hi/lo clk to 1
+ clocks = 1;
+ }
+
+ spim->mstr_cfg |= (((clocks << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS) & MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK) |
+ ((clocks << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS) & MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK));
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int SPIM_Shutdown(mxc_spim_regs_t *spim)
+{
+ int spim_num, err;
+ spim_req_t *temp_req;
+
+ // Disable and clear interrupts
+ spim->inten = 0;
+ spim->intfl = spim->intfl;
+
+ // Disable SPIM and FIFOS
+ spim->gen_ctrl &= ~(MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN | MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN |
+ MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
+
+ // Call all of the pending callbacks for this SPIM
+ spim_num = MXC_SPIM_GET_IDX(spim);
+ if(states[spim_num].req != NULL) {
+
+ // Save the request
+ temp_req = states[spim_num].req;
+
+ // Unlock this SPIM
+ mxc_free_lock((uint32_t*)&states[spim_num].req);
+
+ // Callback if not NULL
+ if(temp_req->callback != NULL) {
+ temp_req->callback(temp_req, E_SHUTDOWN);
+ }
+ }
+
+ // Clear system level configurations
+ if ((err = SYS_SPIM_Shutdown(spim)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass)
+{
+ int spim_num;
+ mxc_spim_fifo_regs_t *fifo;
+ uint16_t header = 0x1;
+ uint32_t num = len;
+
+ // Make sure the SPIM has been initialized
+ if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0)
+ return E_UNINITIALIZED;
+
+ if(!(len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Check the previous transaction if we're switching the slave select
+ if((ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >>
+ MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) {
+
+ // Return E_BUSY if the slave select is still asserted
+ return E_BUSY;
+ }
+
+ // Attempt to lock this SPIM
+ spim_num = MXC_SPIM_GET_IDX(spim);
+ if(mxc_get_lock((uint32_t*)&states[spim_num].req, 1) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Set which slave select we are using
+ spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) |
+ ((ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL));
+
+ //force deass to a 1 or 0
+ deass = !!deass;
+
+#if(MXC_SPIM_REV == 0)
+ // Wait for all of the data to transmit
+ while(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) {}
+
+ // Disable the feedback clock, save state
+ uint32_t gen_ctrl = spim->gen_ctrl;
+ spim->gen_ctrl &= ~MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE;
+#endif
+
+ // Get the TX and RX FIFO for this SPIM
+ fifo = MXC_SPIM_GET_SPIM_FIFO(spim_num);
+
+ // Send the headers to transmit the clocks
+ while(len > 32) {
+ fifo->trans_16[0] = header;
+ fifo->trans_16[0] = 0xF000;
+ fifo->trans_16[0] = 0xF000;
+ len -= 32;
+ }
+
+ if(len) {
+ if(len < 32) {
+ header |= (len << 4);
+ }
+ header |= (deass << 13);
+
+ fifo->trans_16[0] = header;
+
+ if(len > 16) {
+ fifo->trans_16[0] = 0xF000;
+ }
+ fifo->trans_16[0] = 0xF000;
+ }
+
+#if(MXC_SPIM_REV == 0)
+ // Wait for all of the data to transmit
+ while(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) {}
+
+ // Restore feedback clock setting
+ spim->gen_ctrl |= (gen_ctrl & MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE);
+#endif
+
+ // Unlock this SPIM
+ mxc_free_lock((uint32_t*)&states[spim_num].req);
+
+ return num;
+}
+
+
+/* ************************************************************************* */
+int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req)
+{
+ int spim_num;
+
+ // Make sure the SPIM has been initialized
+ if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0)
+ return E_UNINITIALIZED;
+
+ // Check the input parameters
+ if(req == NULL)
+ return E_NULL_PTR;
+
+ if((req->rx_data == NULL) && (req->tx_data == NULL))
+ return E_NULL_PTR;
+
+ if(!(req->len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Check the previous transaction if we're switching the slave select
+ if((req->ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >>
+ MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) {
+
+ // Return E_BUSY if the slave select is still asserted
+ return E_BUSY;
+ }
+
+ // Attempt to register this write request
+ spim_num = MXC_SPIM_GET_IDX(spim);
+ if(mxc_get_lock((uint32_t*)&states[spim_num].req, (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Set which slave select we are using
+ spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) |
+ ((req->ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL));
+
+ //force deass to a 1 or 0
+ req->deass = !!req->deass;
+
+ // Clear the number of bytes counter
+ req->read_num = 0;
+ req->write_num = 0;
+ req->callback = NULL;
+ states[spim_num].head_rem = 0;
+
+ // Start the transaction, keep calling the handler until complete
+ while(SPIM_TransHandler(spim, req, spim_num) != 0);
+
+ if(req->tx_data == NULL) {
+ return req->read_num;
+ }
+ return req->write_num;
+}
+
+/* ************************************************************************* */
+int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req)
+{
+ int spim_num;
+
+ // Make sure the SPIM has been initialized
+ if((spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN) == 0)
+ return E_UNINITIALIZED;
+
+ // Check the input parameters
+ if(req == NULL)
+ return E_NULL_PTR;
+
+ if((req->rx_data == NULL) && (req->tx_data == NULL))
+ return E_NULL_PTR;
+
+ if(!(req->len > 0)) {
+ return E_NO_ERROR;
+ }
+
+
+ // Check the previous transaction if we're switching the slave select
+ if((req->ssel != ((spim->mstr_cfg & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) >>
+ MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) && (spim->gen_ctrl & MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT)) {
+
+ // Return E_BUSY if the slave select is still asserted
+ return E_BUSY;
+ }
+
+ // Attempt to register this write request
+ spim_num = MXC_SPIM_GET_IDX(spim);
+ if(mxc_get_lock((uint32_t*)&states[spim_num].req, (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Set which slave select we are using
+ spim->mstr_cfg = ((spim->mstr_cfg & ~MXC_F_SPIM_MSTR_CFG_SLAVE_SEL) |
+ ((req->ssel << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS) & MXC_F_SPIM_MSTR_CFG_SLAVE_SEL));
+
+ //force deass to a 1 or 0
+ req->deass = !!req->deass;
+
+ // Clear the number of bytes counter
+ req->read_num = 0;
+ req->write_num = 0;
+ states[spim_num].head_rem = 0;
+
+ // Start the transaction, enable the interrupts
+ spim->inten = SPIM_TransHandler(spim, req, spim_num);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int SPIM_AbortAsync(spim_req_t *req)
+{
+ int spim_num;
+ mxc_spim_regs_t *spim;
+
+ // Check the input parameters
+ if(req == NULL) {
+ return E_BAD_PARAM;
+ }
+
+ // Find the request, set to NULL
+ for(spim_num = 0; spim_num < MXC_CFG_SPIM_INSTANCES; spim_num++) {
+ if(req == states[spim_num].req) {
+
+ spim = MXC_SPIM_GET_SPIM(spim_num);
+
+ // Disable interrupts, clear the flags
+ spim->inten = 0;
+ spim->intfl = spim->intfl;
+
+ // Reset the SPIM to cancel the on ongoing transaction
+ spim->gen_ctrl &= ~(MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN);
+ spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN);
+
+ // Unlock this SPIM
+ mxc_free_lock((uint32_t*)&states[spim_num].req);
+
+ // Callback if not NULL
+ if(req->callback != NULL) {
+ req->callback(req, E_ABORT);
+ }
+
+ return E_NO_ERROR;
+ }
+ }
+
+ return E_BAD_PARAM;
+}
+
+/* ************************************************************************* */
+void SPIM_Handler(mxc_spim_regs_t *spim)
+{
+ int spim_num;
+ uint32_t flags;
+
+ // Clear the interrupt flags
+ spim->inten = 0;
+ flags = spim->intfl;
+ spim->intfl = flags;
+
+ spim_num = MXC_SPIM_GET_IDX(spim);
+
+ // Figure out if this SPIM has an active request
+ if((states[spim_num].req != NULL) && (flags)) {
+ spim->inten = SPIM_TransHandler(spim, states[spim_num].req, spim_num);
+ }
+}
+
+/* ************************************************************************* */
+int SPIM_Busy(mxc_spim_regs_t *spim)
+{
+ // Check to see if there are any ongoing transactions
+ if((states[MXC_SPIM_GET_IDX(spim)].req == NULL) &&
+ !(spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED)) {
+
+ return E_NO_ERROR;
+ }
+
+ return E_BUSY;
+}
+
+/* ************************************************************************* */
+int SPIM_PrepForSleep(mxc_spim_regs_t *spim)
+{
+ if(SPIM_Busy(spim) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Disable interrupts
+ spim->inten = 0;
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static unsigned SPIM_ReadRXFIFO(mxc_spim_regs_t *spim, mxc_spim_fifo_regs_t *fifo,
+ uint8_t *data, unsigned len)
+{
+ unsigned num = 0;
+ unsigned avail = ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >>
+ MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
+
+ // Get data from the RXFIFO
+ while(avail && (len - num)) {
+
+ if((avail >= 4) && ((len-num) >= 4)) {
+ // Save data from the RXFIFO
+ uint32_t temp = fifo->rslts_32[0];
+ data[num+0] = ((temp & 0x000000FF) >> 0);
+ data[num+1] = ((temp & 0x0000FF00) >> 8);
+ data[num+2] = ((temp & 0x00FF0000) >> 16);
+ data[num+3] = ((temp & 0xFF000000) >> 24);
+ num+=4;
+ avail-=4;
+ } else if ((avail >= 2) && ((len-num) >= 2)) {
+ // Save data from the RXFIFO
+ uint16_t temp = fifo->rslts_16[0];
+ data[num+0] = ((temp & 0x00FF) >> 0);
+ data[num+1] = ((temp & 0xFF00) >> 8);
+ num+=2;
+ avail-=2;
+ } else {
+ // Save data from the RXFIFO
+ data[num] = fifo->rslts_8[0];
+ num+=1;
+ avail-=1;
+ }
+
+ // Check to see if there is more data in the FIFO
+ if(avail == 0) {
+ avail = ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >>
+ MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
+ }
+ }
+
+ return num;
+}
+
+uint16_t header_save;
+
+
+/* ************************************************************************* */
+static uint32_t SPIM_TransHandler(mxc_spim_regs_t *spim, spim_req_t *req, int spim_num)
+{
+ uint8_t read, write;
+ uint16_t header;
+ uint32_t pages, bytes, inten;
+ unsigned remain, bytes_read, head_rem_temp, avail;
+ mxc_spim_fifo_regs_t *fifo;
+
+ inten = 0;
+
+ // Get the FIFOS for this UART
+ fifo = MXC_SPIM_GET_SPIM_FIFO(spim_num);
+
+ // Figure out if we're reading
+ if(req->rx_data != NULL) {
+ read = 1;
+ } else {
+ read = 0;
+ }
+
+ // Figure out if we're writing
+ if(req->tx_data != NULL) {
+ write = 1;
+ } else {
+ write = 0;
+ }
+
+ // Read byte from the FIFO if we are reading
+ if(read) {
+
+ // Read all of the data in the RXFIFO, or until we don't need anymore
+ bytes_read = SPIM_ReadRXFIFO(spim, fifo, &req->rx_data[req->read_num],
+ (req->len - req->read_num));
+
+ req->read_num += bytes_read;
+
+ // Adjust head_rem if we are only reading
+ if(!write && (states[spim_num].head_rem > 0)) {
+ states[spim_num].head_rem -= bytes_read;
+ }
+
+ // Figure out how many byte we have left to read
+ if(states[spim_num].head_rem > 0) {
+ remain = states[spim_num].head_rem;
+ } else {
+ remain = req->len - req->read_num;
+ }
+
+ if(remain) {
+
+ // Set the RX interrupts
+ if (remain > MXC_CFG_SPIM_FIFO_DEPTH) {
+ spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL) |
+ ((MXC_CFG_SPIM_FIFO_DEPTH - 2) <<
+ MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
+
+ } else {
+ spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL) |
+ ((remain - 1) << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
+ }
+
+ inten |= MXC_F_SPIM_INTEN_RX_FIFO_AF;
+ }
+ }
+
+ // Figure out how many bytes we have left to send headers for
+ if(write) {
+ remain = req->len - req->write_num;
+ } else {
+ remain = req->len - req->read_num;
+ }
+
+ // See if we need to send a new header
+ if(states[spim_num].head_rem <= 0 && remain) {
+
+ // Set the transaction configuration in the header
+ header = ((write << 0) | (read << 1) | (req->width << 9));
+
+ if(remain >= SPIM_MAX_BYTE_LEN) {
+
+ // Send a 32 byte header
+ if(remain == SPIM_MAX_BYTE_LEN) {
+
+ header |= ((0x1 << 2) | (req->deass << 13));
+
+ // Save the number of bytes we need to write to the FIFO
+ bytes = SPIM_MAX_BYTE_LEN;
+
+ } else {
+ // Send in increments of 32 byte pages
+ header |= (0x2 << 2);
+ pages = remain / SPIM_MAX_PAGE_LEN;
+
+ if(pages >= 32) {
+ // 0 maps to 32 in the header
+ bytes = 32 * SPIM_MAX_PAGE_LEN;
+ } else {
+ header |= (pages << 4);
+ bytes = pages * SPIM_MAX_PAGE_LEN;
+ }
+
+ // Check if this is the last header we will send
+ if((remain - bytes) == 0) {
+ header |= (req->deass << 13);
+ }
+ }
+
+ header_save = header;
+ fifo->trans_16[0] = header;
+
+ // Save the number of bytes we need to write to the FIFO
+ states[spim_num].head_rem = bytes;
+
+ } else {
+
+ // Send final header with the number of bytes remaining and if
+ // we want to de-assert the SS at the end of the transaction
+ header |= ((0x1 << 2) | (remain << 4) | (req->deass << 13));
+ fifo->trans_16[0] = header;
+ states[spim_num].head_rem = remain;
+ }
+ }
+
+ // Put data into the FIFO if we are writing
+ remain = req->len - req->write_num;
+ head_rem_temp = states[spim_num].head_rem;
+ if(write && head_rem_temp) {
+
+ // Fill the FIFO
+ avail = (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >>
+ MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS));
+
+ // Use memcpy for everything except the last byte in odd length transactions
+ while((avail >= 2) && (head_rem_temp >= 2)) {
+
+ unsigned length;
+ if(head_rem_temp < avail) {
+ length = head_rem_temp;
+ } else {
+ length = avail;
+ }
+
+ // Only memcpy even numbers
+ length = ((length / 2) * 2);
+
+ memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
+
+ head_rem_temp -= length;
+ req->write_num += length;
+
+ avail = (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >>
+ MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS));
+ }
+
+ // Copy the last byte and pad with 0xF0 to not get confused as header
+ if((avail >= 1) && (head_rem_temp == 1)) {
+
+ // Write the last byte
+ fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]);
+
+ avail -= 1;
+ req->write_num += 1;
+ head_rem_temp -= 1;
+ }
+
+ states[spim_num].head_rem = head_rem_temp;
+ remain = req->len - req->write_num;
+
+ // Set the TX interrupts
+ if(remain) {
+
+ // Set the TX FIFO almost empty interrupt if we have to refill
+ spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL) |
+ ((MXC_CFG_SPIM_FIFO_DEPTH - 2) << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS));
+
+ inten |= MXC_F_SPIM_INTEN_TX_FIFO_AE;
+
+ }
+ }
+
+ // Check to see if we've finished reading and writing
+ if(((read && (req->read_num == req->len)) || !read) &&
+ ((req->write_num == req->len) || !write)) {
+
+ // Disable interrupts
+ spim->inten = 0;
+
+ // Unlock this SPIM
+ mxc_free_lock((uint32_t*)&states[spim_num].req);
+
+ // Callback if not NULL
+ if(req->callback != NULL) {
+ req->callback(req, E_NO_ERROR);
+ }
+ }
+
+ // Enable the SPIM interrupts
+ return inten;
+}
+/**@} end of ingroup spim */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spim.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,347 @@
+/**
+ * @file
+ * @brief Registers, Bit Masks and Bit Positions for the SPI Master module.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24672 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "spim_regs.h"
+
+/* Define to prevent redundant inclusion */
+#ifndef _SPIM_H_
+#define _SPIM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @ingroup commperipherals
+ * @defgroup spi_comm SPI
+ * @brief SPI Master and Slave Communication Peripherals
+ */
+
+/**
+ * @ingroup spi_comm
+ * @defgroup spim SPI Master
+ * @brief Serial Peripheral Interface Master (SPIM) Communications
+ * Interface.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type for selecting the active levels for the SPI Master Slave Select (SS) lines.
+ */
+typedef enum {
+ SPIM_SSEL0_HIGH = (0x1 << 0), /**< Slave Select 0 High. */
+ SPIM_SSEL0_LOW = 0, /**< Slave Select 0 Low. */
+ SPIM_SSEL1_HIGH = (0x1 << 1), /**< Slave Select 1 High. */
+ SPIM_SSEL1_LOW = 0, /**< Slave Select 1 Low. */
+ SPIM_SSEL2_HIGH = (0x1 << 2), /**< Slave Select 2 High. */
+ SPIM_SSEL2_LOW = 0, /**< Slave Select 2 Low. */
+ SPIM_SSEL3_HIGH = (0x1 << 3), /**< Slave Select 3 High. */
+ SPIM_SSEL3_LOW = 0, /**< Slave Select 3 Low. */
+ SPIM_SSEL4_HIGH = (0x1 << 4), /**< Slave Select 4 High. */
+ SPIM_SSEL4_LOW = 0 /**< Slave Select 4 Low. */
+}
+spim_ssel_t;
+
+/**
+ * Enumeration type for setting the number data lines to use for communication.
+ */
+typedef enum {
+ SPIM_WIDTH_1 = 0, /**< 1 Data Line. */
+ SPIM_WIDTH_2 = 1, /**< 2 Data Lines (x2). */
+ SPIM_WIDTH_4 = 2 /**< 4 Data Lines (x4). */
+} spim_width_t;
+
+/**
+ * Structure type for configuring a SPIM port.
+ */
+typedef struct {
+ uint8_t mode; /**< SPIM mode selection, 0 to 3. */
+ uint32_t ssel_pol; /**< Mask of active levels for the slave select signals, see #spim_ssel_t. */
+ uint32_t baud; /**< Baud rate in Hz. */
+} spim_cfg_t;
+
+/**
+ * Structure type representing a SPI Master Transaction request.
+ */
+typedef struct spim_req spim_req_t;
+
+/**
+ * @brief Callback function type used in asynchromous SPIM communications requests.
+ * @details The function declaration for the SPIM callback is:
+ * @code
+ * void callback(spim_req_t * req, int error_code);
+ * @endcode
+ * | | |
+ * | -----: | :----------------------------------------- |
+ * | \p req | Pointer to a #spim_req object representing the active SPIM active transaction. |
+ * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
+ * @addtogroup spim_async
+ */
+typedef void (*spim_callback_fn)(spim_req_t * req, int error_code);
+
+/**
+ * @brief Structure definition for an SPI Master Transaction request.
+ * @note When using this structure for an asynchronous operation, the
+ * structure must remain allocated until the callback is completed.
+ * @addtogroup spim_async
+ */
+struct spim_req {
+ uint8_t ssel; /**< Number of the Slave Select to use. */
+ uint8_t deass; /**< Set to de-assert slave select at the completions of the transaction.*/
+ const uint8_t *tx_data; /**< Pointer to a buffer to transmit data from. */
+ uint8_t *rx_data; /**< Pointer to a buffer to store data received. */
+ spim_width_t width; /**< Number of data lines to use, see #spim_width_t. */
+ unsigned len; /**< Number of bytes to send from the \p tx_data buffer. */
+ unsigned read_num; /**< Number of bytes read and stored in \p rx_data buffer. */
+ unsigned write_num; /**< Number of bytes sent from the \p tx_data buffer, this will be filled by the driver after up to \p len bytes have been transmitted. */
+ spim_callback_fn callback; /**< Function pointer to a callback function if desired, NULL otherwise */
+};
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize the SPIM peripheral module.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ * @param cfg Pointer to an SPIM configuration object.
+ * @param sys_cfg Pointer to a system configuration object to select the
+ * peripheral clock rate and assign the requested GPIO.
+ *
+ * @return #E_NO_ERROR if the SPIM port is initialized successfully, @ref MXC_Error_Codes
+ * "error" if unsuccessful.
+ */
+int SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *cfg, const sys_cfg_spim_t *sys_cfg);
+
+/**
+ * @brief Shutdown the SPIM peripheral module instance represented by the
+ * @p spim parameter.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ *
+ * @return #E_NO_ERROR if the SPIM is shutdown successfully, @ref
+ * MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIM_Shutdown(mxc_spim_regs_t *spim);
+
+/**
+ * @brief Send Clock cycles on SCK without reading or writing.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ * @param len Number of clock cycles to send.
+ * @param ssel Slave select number.
+ * @param deass De-assert slave select at the end of the transaction.
+ *
+ * @return Cycles transacted if everything is successful, @ref
+ * MXC_Error_Codes "error" if unsuccessful.
+ */
+int SPIM_Clocks(mxc_spim_regs_t *spim, uint32_t len, uint8_t ssel, uint8_t deass);
+
+/**
+ * @brief Read/write SPIM data. This function will block until the
+ * transaction is complete.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ * @param req Request for a SPIM transaction.
+ * @note If a callback function is registered it will not be called when using a blocking function.
+ *
+ * @return Bytes transacted if everything is successful, error if
+ * unsuccessful.
+ */
+int SPIM_Trans(mxc_spim_regs_t *spim, spim_req_t *req);
+/**
+ * @defgroup spim_async SPIM Asynchrous Functions
+ * @{
+ */
+/**
+ * @brief Asynchronously read/write SPIM data.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ * @param req Request for a SPIM transaction.
+ * @note Request struct must remain allocated until callback.
+ *
+ * @return #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes
+ * "error" if unsuccessful.
+ */
+int SPIM_TransAsync(mxc_spim_regs_t *spim, spim_req_t *req);
+
+/**
+ * @brief Abort asynchronous request.
+ *
+ * @param req Pointer to a request structure for a SPIM transaction.
+ *
+ * @return #E_NO_ERROR if request aborted, , @ref MXC_Error_Codes "error" if
+ * unsuccessful.
+ */
+int SPIM_AbortAsync(spim_req_t *req);
+
+/**
+ * @brief SPIM interrupt handler.
+ * @details This function should be called by the application from the
+ * interrupt handler if SPIM interrupts are enabled. Alternately,
+ * this function can be periodically polled by the application if
+ * SPIM interrupts are disabled.
+ *
+ * @param spim Base address of the SPIM module.
+ */
+void SPIM_Handler(mxc_spim_regs_t *spim);
+
+/**
+ * @brief Check the SPIM to see if it's busy.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ *
+ * @retval #E_NO_ERROR if idle.
+ * @retval #E_BUSY if in use.
+ */
+int SPIM_Busy(mxc_spim_regs_t *spim);
+/**@} end of spim_async define group */
+
+/**
+ * @brief Attempts to prepare the SPIM for Low Power Sleep Modes.
+ * @details Checks for any ongoing transactions. Disables interrupts if the
+ * SPIM is idle.
+ *
+ * @param spim The spim
+ *
+ * @return #E_NO_ERROR if ready to sleep.
+ * @return #E_BUSY if not able to sleep at this time.
+ */
+int SPIM_PrepForSleep(mxc_spim_regs_t *spim);
+
+/**
+ * @brief Enables the SPIM without overwriting the existing configuration.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ */
+__STATIC_INLINE void SPIM_Enable(mxc_spim_regs_t *spim)
+{
+ spim->gen_ctrl |= (MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN |
+ MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
+}
+
+/**
+ * @brief Drains/empties the data in the RX FIFO.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ */
+__STATIC_INLINE void SPIM_DrainRX(mxc_spim_regs_t *spim)
+{
+ uint32_t ctrl_save = spim->gen_ctrl;
+ spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN);
+ spim->gen_ctrl = ctrl_save;
+}
+
+/**
+ * @brief Drains/empties the data in the TX FIFO.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ */
+__STATIC_INLINE void SPIM_DrainTX(mxc_spim_regs_t *spim)
+{
+ uint32_t ctrl_save = spim->gen_ctrl;
+ spim->gen_ctrl = (ctrl_save & ~MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN);
+ spim->gen_ctrl = ctrl_save;
+}
+
+/**
+ * @brief Returns the number of bytes free in the TX FIFO.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ *
+ * @return Number of bytes free in Transmit FIFO.
+ */
+__STATIC_INLINE unsigned SPIM_NumWriteAvail(mxc_spim_regs_t *spim)
+{
+ return (MXC_CFG_SPIM_FIFO_DEPTH - ((spim->fifo_ctrl &
+ MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS));
+}
+
+/**
+ * @brief Returns the number of bytes available to read in the RX FIFO.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ *
+ * @return Number of bytes in RX FIFO.
+ */
+__STATIC_INLINE unsigned SPIM_NumReadAvail(mxc_spim_regs_t *spim)
+{
+ return ((spim->fifo_ctrl & MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED) >>
+ MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS);
+}
+
+/**
+ * @brief Clear the SPIM interrupt flags.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ * @param mask Mask of the SPIM interrupt flags to clear, see @ref
+ * SPIM_INTFL_Register Register for the SPIM interrupt flag
+ * bit masks.
+ */
+__STATIC_INLINE void SPIM_ClearFlags(mxc_spim_regs_t *spim, uint32_t mask)
+{
+ spim->intfl = mask;
+}
+
+/**
+ * @brief Read the current SPIM interrupt flags.
+ *
+ * @param spim Pointer to the SPIM register structure.
+ *
+ * @return Mask of currently set SPIM interrupt flags, see @ref
+ * SPIM_INTFL_Register Register for the SPIM interrupt flag bit
+ * masks.
+ */
+__STATIC_INLINE unsigned SPIM_GetFlags(mxc_spim_regs_t *spim)
+{
+ return (spim->intfl);
+}
+
+/**@} end of group spim_comm */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPIM_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,297 @@
+/**
+ * @file
+ * @brief SPI execute in place driver.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:31:41 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24323 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "spix.h"
+#include "spix_regs.h"
+
+/**
+ * @ingroup spix
+ * @{
+ */
+
+/* **** Definitions **** */
+#define CMD_CLOCKS 8
+#define ADDR_3BYTE_CLOCKS 24
+#define ADDR_4BYTE_CLOCKS 32
+
+/***** Globals *****/
+
+/***** Functions *****/
+
+/******************************************************************************/
+#if defined ( __GNUC__ )
+#undef IAR_SPIX_PRAGMA //Make sure this is not defined for GCC
+#endif
+
+#if IAR_SPIX_PRAGMA
+// IAR memory section declaration for the SPIX functions to be loaded in RAM.
+#pragma section=".spix_config"
+#endif
+
+#if(MXC_SPIX_REV == 0)
+
+#if defined ( __GNUC__ )
+__attribute__ ((section(".spix_config"), noinline))
+#endif /* __GNUC */
+
+#if IAR_SPIX_PRAGMA
+#pragma location=".spix_config" // IAR locate function in RAM section .spix_config
+#pragma optimize=no_inline // IAR no inline optimization on this function
+#endif /* IAR_PRAGMA */
+
+static void SPIX_UpdateFBIgnore()
+{
+ // Update the feedback ignore clocks
+ uint8_t clocks = 0;
+ uint8_t no_cmd_clocks = 0;
+
+ // Adjust the clocks for the command
+ if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) ==
+ MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO) {
+
+ clocks += CMD_CLOCKS/4;
+ } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) ==
+ MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO) {
+
+ clocks += CMD_CLOCKS/2;
+ } else {
+
+ clocks += CMD_CLOCKS;
+ }
+
+ // Adjust the clocks for the address
+ if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) ==
+ MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO) {
+
+ if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
+ clocks += ADDR_4BYTE_CLOCKS/4;
+ no_cmd_clocks += ADDR_4BYTE_CLOCKS/4;
+ } else {
+ clocks += ADDR_3BYTE_CLOCKS/4;
+ no_cmd_clocks += ADDR_3BYTE_CLOCKS/4;
+ }
+
+ } else if((MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) ==
+ MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO) {
+
+ if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
+ clocks += ADDR_4BYTE_CLOCKS/2;
+ no_cmd_clocks += ADDR_4BYTE_CLOCKS/2;
+ } else {
+ clocks += ADDR_3BYTE_CLOCKS/2;
+ no_cmd_clocks += ADDR_3BYTE_CLOCKS/2;
+ }
+ } else {
+
+ if(MXC_SPIX->fetch_ctrl & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR) {
+ clocks += ADDR_4BYTE_CLOCKS;
+ no_cmd_clocks += ADDR_4BYTE_CLOCKS;
+ } else {
+ clocks += ADDR_3BYTE_CLOCKS;
+ no_cmd_clocks += ADDR_3BYTE_CLOCKS;
+ }
+ }
+
+ // Adjust for the mode clocks
+ clocks += ((MXC_SPIX->mode_ctrl & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) >>
+ MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS);
+
+ // Set the FB Ignore clocks
+ MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS) |
+ (clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS));
+
+ MXC_SPIX->sck_fb_ctrl = ((MXC_SPIX->sck_fb_ctrl & ~MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD) |
+ (no_cmd_clocks << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS));
+}
+#endif /* MXC_SPIX_REV==0 */
+
+/******************************************************************************/
+#if defined ( __GNUC__ )
+__attribute__ ((section(".spix_config"), noinline))
+#endif /* __GNUC */
+
+#if IAR_SPIX_PRAGMA
+#pragma location=".spix_config" // IAR locate function in RAM section .spix_config
+#pragma optimize=no_inline // IAR no inline optimization on this function
+#endif /* IAR_SPIX_PRAGMA */
+int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample)
+{
+ int err;
+ uint32_t spix_clk, clocks;
+
+ // Check the input parameters
+ if(sys_cfg == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Set system level configurations
+ if ((err = SYS_SPIX_Init(sys_cfg, baud)) != E_NO_ERROR) {
+ return err;
+ }
+
+ // Configure the mode and baud
+ spix_clk = SYS_SPIX_GetFreq();
+ if(spix_clk <= 0) {
+ return E_UNINITIALIZED;
+ }
+
+ // Make sure that we can generate this frequency
+ clocks = (spix_clk / (2*baud));
+ if((clocks <= 0) || (clocks >= 0x10)) {
+ return E_BAD_PARAM;
+ }
+
+ // Set the baud
+ MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg &
+ ~(MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK | MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK)) |
+ (clocks << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS) |
+ (clocks << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS));
+
+ if(sample != 0) {
+ // Use sample mode
+ MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT) |
+ (sample << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS));
+
+ MXC_SPIX->sck_fb_ctrl &= ~(MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE |
+ MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK);
+ } else {
+ // Use Feedback mode
+ MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT);
+
+ MXC_SPIX->sck_fb_ctrl |= (MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE |
+ MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK);
+
+
+#if(MXC_SPIX_REV == 0)
+ SPIX_UpdateFBIgnore();
+#endif
+ }
+
+ return E_NO_ERROR;
+}
+
+/******************************************************************************/
+#if defined ( __GNUC__ )
+__attribute__ ((section(".spix_config"), noinline))
+#endif /* __GNUC */
+
+#if IAR_SPIX_PRAGMA
+#pragma location=".spix_config" // IAR locate function in RAM section .spix_config
+#pragma optimize=no_inline // IAR no inline optimization on this function
+#endif /* IAR_SPIX_PRAGMA */
+
+void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay)
+{
+
+ // Set the slave select
+ MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~MXC_F_SPIX_MASTER_CFG_SLAVE_SEL) |
+ (ssel << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS));
+
+ if(pol != 0) {
+ // Active high
+ MXC_SPIX->master_cfg &= ~(MXC_F_SPIX_MASTER_CFG_SS_ACT_LO);
+ } else {
+ // Active low
+ MXC_SPIX->master_cfg |= MXC_F_SPIX_MASTER_CFG_SS_ACT_LO;
+ }
+
+ // Set the delays
+ MXC_SPIX->master_cfg = ((MXC_SPIX->master_cfg & ~(MXC_F_SPIX_MASTER_CFG_ACT_DELAY |
+ MXC_F_SPIX_MASTER_CFG_INACT_DELAY)) |
+ (act_delay << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS) |
+ (inact_delay << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS));
+}
+
+/******************************************************************************/
+#if defined ( __GNUC__ )
+__attribute__ ((section(".spix_config"), noinline))
+#endif /* __GNUC */
+
+#if IAR_SPIX_PRAGMA
+#pragma location=".spix_config" // IAR locate function in RAM section .spix_config
+#pragma optimize=no_inline // IAR no inline optimization on this function
+#endif /* IAR_SPIX_PRAGMA */
+
+void SPIX_ConfigFetch(const spix_fetch_t *fetch)
+{
+ // Configure how the SPIX fetches data
+ MXC_SPIX->fetch_ctrl = (((fetch->cmd << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_VALUE) |
+ ((fetch->cmd_width << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH) |
+ ((fetch->addr_width << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH) |
+ ((fetch->data_width << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS) & MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH) |
+ ((fetch->addr_size << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS) & MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR));
+
+ // Set the command mode and clocks
+ MXC_SPIX->mode_ctrl = (((fetch->mode_clocks << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS) & MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS) |
+ (!!fetch->no_cmd_mode << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS));
+
+ MXC_SPIX->mode_data = (((fetch->mode_data << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS) & MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS) |
+ MXC_F_SPIX_MODE_DATA_MODE_DATA_OE);
+
+#if(MXC_SPIX_REV == 0)
+ SPIX_UpdateFBIgnore();
+#endif
+}
+
+/******************************************************************************/
+#if defined ( __GNUC__ )
+__attribute__ ((section(".spix_config"), noinline))
+#endif /* __GNUC */
+
+#if IAR_SPIX_PRAGMA
+#pragma location=".spix_config" // IAR locate function in RAM section .spix_config
+#pragma optimize=no_inline // IAR no inline optimization on this function
+#endif /* IAR_SPIX_PRAGMA */
+
+int SPIX_Shutdown(mxc_spix_regs_t *spix)
+{
+ int err;
+
+ // Clear system level configurations
+ if ((err = SYS_SPIX_Shutdown()) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/spix.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,140 @@
+/**
+ * @file
+ * @brief This is the high level API for the SPI Execute in Place (SPIX)
+ * module.
+ * @note If using this SPIX with IAR Embedded Workbench for ARM, it is
+ * required to define <tt>IAR_SPIX_PRAGMA=1</tt>. This should be
+ * done under Project->Options-> C/C++ Compiler->Preprocessor in the
+ * Defined Symbols input box. See the IAR documentation for
+ * additional information on how to set a preprocessor define in a
+ * project.
+ */
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:45:55 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24674 $
+ *
+ **************************************************************************** */
+
+
+
+#include "mxc_sys.h"
+#include "spix_regs.h"
+
+/* Define to prevent redundant inclusion */
+#ifndef _SPIX_H_
+#define _SPIX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup spix SPIX
+ * @brief SPI Execute In Place.
+ * @{
+ */
+
+/* **** Definitions **** */
+/// @brief Options for number of I/O pins to use during for each fetch stage
+typedef enum {
+ SPIX_SINGLE_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE,
+ SPIX_DUAL_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO,
+ SPIX_QUAD_IO = MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO
+} spix_width_t;
+
+/// @brief Options for number of address bytes to use during fetch
+typedef enum {
+ SPIX_3BYTE_FETCH_ADDR = 0,
+ SPIX_4BYTE_FETCH_ADDR = 1
+} spix_addr_size_t;
+
+/// @brief SPIX fetch configuration.
+typedef struct {
+ spix_width_t cmd_width; ///< Number of I/O lines used for command SPI transaction.
+ spix_width_t addr_width; ///< Number of I/O lines used for address SPI transaction.
+ spix_width_t data_width; ///< Number of I/O lines used for data SPI transaction.
+ spix_addr_size_t addr_size; ///< Use 3 or 4 byte addresses for fetches.
+ uint8_t cmd; ///< Command value to initiate fetch.
+ uint8_t mode_clocks; ///< Number of SPI clocks required during mode phase of fetch.
+ uint8_t no_cmd_mode; ///< Read command sent only once.
+ uint16_t mode_data; ///< Data sent with mode clocks.
+} spix_fetch_t;
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+ /**
+ * @brief Configure SPI execute in place clocking.
+ * @param sys_cfg Pointer to system level configuration structure.
+ * @param baud Frequency in hertz to set the clock to. May not be able
+ * to achieve with the given clock divider.
+ * @param sample Number of SPIX clocks to delay the sampling of the SDIO
+ * lines. Will use feedback mode if set to 0.
+ * @return #E_NO_ERROR if everything is successful
+ */
+int SPIX_ConfigClock(const sys_cfg_spix_t *sys_cfg, uint32_t baud, uint8_t sample);
+
+/**
+ * @brief Configure SPI execute in place slave select.
+ * @param ssel Index of which slave select line to use.
+ * @param pol Polarity of slave select (0 for active low, 1 for
+ * active high).
+ * @param act_delay SPIX clocks between slave select assert and active
+ * SPI clock.
+ * @param inact_delay SPIX clocks between active SPI clock and slave
+ * select deassert.
+ */
+void SPIX_ConfigSlave(uint8_t ssel, uint8_t pol, uint8_t act_delay, uint8_t inact_delay);
+
+/**
+ * @brief Configure how the SPIX fetches data.
+ * @param fetch Pointer to configuration struct that describes how to
+ * fetch data.
+ */
+void SPIX_ConfigFetch(const spix_fetch_t *fetch);
+
+/**
+ * @brief Shutdown SPIX module.
+ * @param spix Pointer to SPIX regs.
+ * @return #E_NO_ERROR if everything is successful
+ */
+int SPIX_Shutdown(mxc_spix_regs_t *spix);
+
+/**@} end of group spix */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SPIX_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,399 @@
+/**
+ * @file
+ * @brief Timer Peripheral Driver Source.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:30:35 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24322 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "mxc_assert.h"
+#include "tmr.h"
+
+/**
+ * @ingroup tmr
+ * @{
+ */
+static tmr_prescale_t prescaler[MXC_CFG_TMR_INSTANCES];
+
+/* ************************************************************************* */
+int TMR_Init(mxc_tmr_regs_t *tmr, tmr_prescale_t prescale, const sys_cfg_tmr_t *sysCfg)
+{
+ int err;
+ int tmrNum;
+
+ //get the timer number
+ tmrNum = MXC_TMR_GET_IDX(tmr);
+
+ //check for valid pointer
+ MXC_ASSERT(tmrNum >= 0);
+
+ //steup system GPIO config
+ if((err = SYS_TMR_Init(tmr, sysCfg)) != E_NO_ERROR)
+ return err;
+
+ //save the prescale value for this timer
+ prescaler[tmrNum] = prescale;
+
+ //Disable timer and clear settings
+ tmr->ctrl = 0;
+
+ //reset all counts to 0
+ tmr->count32 = 0;
+ tmr->count16_0 = 0;
+ tmr->count16_1 = 0;
+
+ // Clear interrupt flag
+ tmr->intfl = MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void TMR32_Config(mxc_tmr_regs_t *tmr, const tmr32_cfg_t *config)
+{
+ //stop timer
+ TMR32_Stop(tmr);
+
+ //setup timer configuration register
+ //clear tmr2x16 (32bit mode), mode and polarity bits
+ tmr->ctrl &= ~(MXC_F_TMR_CTRL_TMR2X16 | MXC_F_TMR_CTRL_MODE |
+ MXC_F_TMR_CTRL_POLARITY);
+
+ //set mode and polarity
+ tmr->ctrl |= ((config->mode << MXC_F_TMR_CTRL_MODE_POS) |
+ (config->polarity << MXC_F_TMR_CTRL_POLARITY_POS));
+
+ //setup timer Tick registers
+ tmr->term_cnt32 = config->compareCount;
+
+ return;
+}
+
+/* ************************************************************************* */
+void TMR32_PWMConfig(mxc_tmr_regs_t *tmr, const tmr32_cfg_pwm_t *config)
+{
+ //stop timer
+ TMR32_Stop(tmr);
+
+ //setup timer configuration register
+ //clear tmr2x16 (32bit mode), mode and polarity bits
+ tmr->ctrl &= ~(MXC_F_TMR_CTRL_TMR2X16 | MXC_F_TMR_CTRL_MODE |
+ MXC_F_TMR_CTRL_POLARITY);
+
+ //set mode and polarity
+ tmr->ctrl |= ((TMR32_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) |
+ (config->polarity << MXC_F_TMR_CTRL_POLARITY_POS));
+
+ tmr->pwm_cap32 = config->dutyCount;
+
+ //setup timer Tick registers
+ tmr->count32 = 0;
+ tmr->term_cnt32 = config->periodCount;
+
+ return;
+}
+
+/* ************************************************************************* */
+void TMR16_Config(mxc_tmr_regs_t *tmr, uint8_t index, const tmr16_cfg_t *config)
+{
+ //stop timer
+ TMR16_Stop(tmr, index);
+
+ if(index > 0) { //configure timer 16_1
+
+ //setup timer configuration register
+ tmr->ctrl |= MXC_F_TMR_CTRL_TMR2X16; //1 = 16bit mode
+
+ //set mode
+ if(config->mode)
+ tmr->ctrl |= MXC_F_TMR_CTRL_MODE_16_1;
+ else
+ tmr->ctrl &= ~MXC_F_TMR_CTRL_MODE_16_1;
+
+ //setup timer Ticks registers
+ tmr->term_cnt16_1 = config->compareCount;
+ } else { //configure timer 16_0
+
+ //setup timer configuration register
+ tmr->ctrl |= MXC_F_TMR_CTRL_TMR2X16; //1 = 16bit mode
+
+ //set mode
+ if(config->mode)
+ tmr->ctrl |= MXC_F_TMR_CTRL_MODE_16_0;
+ else
+ tmr->ctrl &= ~MXC_F_TMR_CTRL_MODE_16_0;
+
+ //setup timer Ticks registers
+ tmr->term_cnt16_0 = config->compareCount;
+ }
+
+ return;
+}
+
+/* ************************************************************************* */
+void TMR32_Start(mxc_tmr_regs_t *tmr)
+{
+ int tmrNum;
+ uint32_t ctrl;
+
+ //get the timer number
+ tmrNum = MXC_TMR_GET_IDX(tmr);
+
+ //prescaler gets reset to 0 when timer is disabled
+ //set the prescale to the saved value for this timer
+ ctrl = tmr->ctrl;
+ ctrl &= ~(MXC_F_TMR_CTRL_PRESCALE); //clear prescaler bits
+ ctrl |= prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS; //set prescaler
+ ctrl |= MXC_F_TMR_CTRL_ENABLE0; //set enable to start the timer
+
+ tmr->ctrl = ctrl;
+
+ return;
+}
+
+/* ************************************************************************* */
+void TMR16_Start(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ int tmrNum;
+ uint32_t ctrl;
+
+ //get the timer number
+ tmrNum = MXC_TMR_GET_IDX(tmr);
+
+ ctrl = tmr->ctrl;
+
+ //prescaler gets reset to 0 when both 16 bit timers are disabled
+ //set the prescale to the saved value for this timer if is is not already set
+ if((ctrl & MXC_F_TMR_CTRL_PRESCALE) != (uint32_t)(prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS)) {
+ ctrl &= ~(MXC_F_TMR_CTRL_PRESCALE); //clear prescaler bits
+ ctrl |= prescaler[tmrNum] << MXC_F_TMR_CTRL_PRESCALE_POS; //set prescaler
+ }
+
+ if(index > 0)
+ ctrl |= MXC_F_TMR_CTRL_ENABLE1; //start timer 16_1
+ else
+ ctrl |= MXC_F_TMR_CTRL_ENABLE0; //start timer 16_0
+
+ tmr->ctrl = ctrl;
+
+ return;
+}
+
+/* ************************************************************************* */
+uint32_t TMR_GetPrescaler(mxc_tmr_regs_t *tmr)
+{
+ int tmrNum;
+
+ //get the timer number
+ tmrNum = MXC_TMR_GET_IDX(tmr);
+
+ return ((uint32_t)prescaler[tmrNum]);
+}
+
+
+/* ************************************************************************* */
+int TMR32_GetPWMTicks(mxc_tmr_regs_t *tmr, uint8_t dutyPercent, uint32_t freq, uint32_t *dutyTicks, uint32_t *periodTicks)
+{
+ uint32_t timerClock;
+ uint32_t prescale;
+ uint64_t ticks;
+
+ if(dutyPercent > 100)
+ return E_BAD_PARAM;
+
+ if(freq == 0)
+ return E_BAD_PARAM;
+
+ timerClock = SYS_TMR_GetFreq(tmr);
+ prescale = TMR_GetPrescaler(tmr);
+
+ if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12)
+ return E_UNINITIALIZED;
+
+ ticks = timerClock / (1 << (prescale & 0xF)) / freq;
+
+ //make sure ticks is within a 32 bit value
+ if (!(ticks & 0xffffffff00000000) && (ticks & 0xffffffff)) {
+ *periodTicks = ticks;
+
+ *dutyTicks = ((uint64_t)*periodTicks * dutyPercent) / 100;
+
+ return E_NO_ERROR;
+ }
+
+ return E_INVALID;
+}
+
+/* ************************************************************************* */
+int TMR32_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks)
+{
+ uint32_t unit_div0, unit_div1;
+ uint32_t timerClock;
+ uint32_t prescale;
+ uint64_t temp_ticks;
+
+ timerClock = SYS_TMR_GetFreq(tmr);
+ prescale = TMR_GetPrescaler(tmr);
+
+ if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12)
+ return E_UNINITIALIZED;
+
+ switch (units) {
+ case TMR_UNIT_NANOSEC:
+ unit_div0 = 1000000;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_MICROSEC:
+ unit_div0 = 1000;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_MILLISEC:
+ unit_div0 = 1;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_SEC:
+ unit_div0 = 1;
+ unit_div1 = 1;
+ break;
+ default:
+ return E_BAD_PARAM;
+ }
+
+ temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF)));
+
+ //make sure ticks is within a 32 bit value
+ if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) {
+ *ticks = temp_ticks;
+ return E_NO_ERROR;
+ }
+
+ return E_INVALID;
+}
+
+/* ************************************************************************* */
+int TMR16_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint16_t *ticks)
+{
+ uint32_t unit_div0, unit_div1;
+ uint32_t timerClock;
+ uint32_t prescale;
+ uint64_t temp_ticks;
+
+ timerClock = SYS_TMR_GetFreq(tmr);
+ prescale = TMR_GetPrescaler(tmr);
+
+ if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12)
+ return E_UNINITIALIZED;
+
+ switch (units) {
+ case TMR_UNIT_NANOSEC:
+ unit_div0 = 1000000;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_MICROSEC:
+ unit_div0 = 1000;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_MILLISEC:
+ unit_div0 = 1;
+ unit_div1 = 1000;
+ break;
+ case TMR_UNIT_SEC:
+ unit_div0 = 1;
+ unit_div1 = 1;
+ break;
+ default:
+ return E_BAD_PARAM;
+ }
+
+ temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF)));
+
+ //make sure ticks is within a 32 bit value
+ if (!(temp_ticks & 0xffffffffffff0000) && (temp_ticks & 0xffff)) {
+ *ticks = temp_ticks;
+ return E_NO_ERROR;
+ }
+
+ return E_INVALID;
+}
+
+
+/* ************************************************************************* */
+int TMR_TicksToTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units)
+{
+ uint64_t temp_time = 0;
+
+ uint32_t timerClock = SYS_TMR_GetFreq(tmr);
+ uint32_t prescale = TMR_GetPrescaler(tmr);
+
+ if(timerClock == 0 || prescale > TMR_PRESCALE_DIV_2_12)
+ return E_UNINITIALIZED;
+
+ tmr_unit_t temp_unit = TMR_UNIT_NANOSEC;
+ temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000);
+ if (!(temp_time & 0xffffffff00000000)) {
+ *time = temp_time;
+ *units = temp_unit;
+ return E_NO_ERROR;
+ }
+
+ temp_unit = TMR_UNIT_MICROSEC;
+ temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000);
+ if (!(temp_time & 0xffffffff00000000)) {
+ *time = temp_time;
+ *units = temp_unit;
+ return E_NO_ERROR;
+ }
+
+ temp_unit = TMR_UNIT_MILLISEC;
+ temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock;
+ if (!(temp_time & 0xffffffff00000000)) {
+ *time = temp_time;
+ *units = temp_unit;
+ return E_NO_ERROR;
+ }
+
+ temp_unit = TMR_UNIT_SEC;
+ temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock;
+ if (!(temp_time & 0xffffffff00000000)) {
+ *time = temp_time;
+ *units = temp_unit;
+ return E_NO_ERROR;
+ }
+
+ return E_INVALID;
+}
+/**@} end of ingroup tmr */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,611 @@
+/**
+ * @file
+ * @brief Timer0 & Timer1 32/16-Bit Peripheral Driver.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24675 $
+ *
+ *************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _TIMER_H
+#define _TIMER_H
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "tmr_regs.h"
+#include "mxc_sys.h"
+
+/* **** Extern CPP **** */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup periphlibs
+ * @defgroup tmr Timers
+ * @brief 32/16-bit Timers
+ * @{
+ */
+
+/**
+ * Enumeration type for units of time.
+ */
+typedef enum {
+ TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */
+ TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */
+ TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */
+ TMR_UNIT_SEC, /**< Second Unit Indicator. */
+} tmr_unit_t;
+
+/**
+ * Enumeration type to select the 32-bit Timer Mode.
+ */
+typedef enum {
+ TMR32_MODE_ONE_SHOT = MXC_V_TMR_CTRL_MODE_ONE_SHOT, /**< One-shot Mode */
+ TMR32_MODE_CONTINUOUS = MXC_V_TMR_CTRL_MODE_CONTINUOUS, /**< Continuous Mode */
+ TMR32_MODE_COUNTER = MXC_V_TMR_CTRL_MODE_COUNTER, /**< Counter Mode */
+ TMR32_MODE_PWM = MXC_V_TMR_CTRL_MODE_PWM, /**< Pulse Width Modulation Mode */
+ TMR32_MODE_CAPTURE = MXC_V_TMR_CTRL_MODE_CAPTURE, /**< Capture Mode */
+ TMR32_MODE_COMPARE = MXC_V_TMR_CTRL_MODE_COMPARE, /**< Compare Mode */
+ TMR32_MODE_GATED = MXC_V_TMR_CTRL_MODE_GATED, /**< Gated Mode */
+ TMR32_MODE_MEASURE = MXC_V_TMR_CTRL_MODE_MEASURE /**< Measure Mode */
+} tmr32_mode_t;
+
+/**
+ * Enumeration type to select a 16-bit Timer Mode.
+ * @note 16-bit times only support One Shot and Continuous timers.
+ */
+typedef enum {
+ TMR16_MODE_ONE_SHOT = MXC_V_TMR_CTRL_MODE_ONE_SHOT, /**< One-Shot Mode. */
+ TMR16_MODE_CONTINUOUS = MXC_V_TMR_CTRL_MODE_CONTINUOUS /**< Continuous Mode. */
+} tmr16_mode_t;
+
+/**
+ * Enumeration type to select the Prescale Divider for the timer module. The prescaler
+ * divides the peripheral input clock to the timer by a selectable divisor.
+ */
+typedef enum {
+ TMR_PRESCALE_DIV_2_0 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{0} = 1 \f$ */
+ TMR_PRESCALE_DIV_2_1 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{1} = 2 \f$ */
+ TMR_PRESCALE_DIV_2_2 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{2} = 4 \f$ */
+ TMR_PRESCALE_DIV_2_3 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_8, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{3} = 8 \f$ */
+ TMR_PRESCALE_DIV_2_4 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_16, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{4} = 16 \f$ */
+ TMR_PRESCALE_DIV_2_5 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_32, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{5} = 32 \f$ */
+ TMR_PRESCALE_DIV_2_6 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_64, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{6} = 64 \f$ */
+ TMR_PRESCALE_DIV_2_7 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_128, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{7} = 128 \f$ */
+ TMR_PRESCALE_DIV_2_8 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_256, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{8} = 256 \f$ */
+ TMR_PRESCALE_DIV_2_9 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_512, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{9} = 512 \f$ */
+ TMR_PRESCALE_DIV_2_10 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_1024, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{10} = 1024 \f$ */
+ TMR_PRESCALE_DIV_2_11 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_2048, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{11} = 2048 \f$ */
+ TMR_PRESCALE_DIV_2_12 = MXC_V_TMR_CTRL_PRESCALE_DIVIDE_BY_4096, /**< Divide the peripheral input clock by \f$ TMR_{Prescaler} = 2^{12} = 4096 \f$ */
+} tmr_prescale_t;
+
+/**
+ * Enumeration type to set the polarity bit for pwm timer.
+ */
+typedef enum {
+ TMR_POLARITY_UNUSED = 0, /**< @internal Unused polarity @endinternal */
+
+ TMR_POLARITY_INIT_LOW = 0, /**< GPIO initial output level = low */
+ TMR_POLARITY_INIT_HIGH = 1, /**< GPIO initial output level = high */
+
+ TMR_POLARITY_RISING_EDGE = 0, /**< timer trigger on GPIO rising edge */
+ TMR_POLARITY_FALLING_EDGE = 1, /**< timer trigger on GPIO falling edge */
+} tmr_polarity_t;
+
+/**
+ * Enumeration type to set the polarity bit for pwm timer.
+ */
+typedef enum {
+ TMR_PWM_INVERTED = 0, /**< duty cycle = low pulse */
+ TMR_PWM_NONINVERTED, /**< duty cycle = high pulse */
+} tmr_pwm_polarity_t;
+
+/**
+ * Structure type for Configuring a 32-bit timer in all modes except PWM.
+ */
+typedef struct {
+ tmr32_mode_t mode; /**< Desired timer mode, see #tmr32_mode_t for valid modes. @note If PWM mode is desired, setting the mode to TMR32_MODE_PWM is valid. To configure PWM Mode, see #tmr32_cfg_pwm_t. */
+ tmr_polarity_t polarity; /**< Polarity for GPIO */
+ uint32_t compareCount; /**< Ticks to stop, reset back to 1, or compare timer */
+} tmr32_cfg_t;
+
+/**
+ * Structure type for Configuring PWM Mode for a 32-bit timer.
+ */
+typedef struct {
+ tmr_pwm_polarity_t polarity; /**< PWM polarity selection, see #tmr_pwm_polarity_t. */
+ uint32_t periodCount; /**< PWM period in number of timer ticks. */
+ uint32_t dutyCount; /**< PWM duty cycle in number of timer ticks. */
+} tmr32_cfg_pwm_t;
+
+/**
+ * Structure type for Configuring a 16-bit Timer.
+ */
+typedef struct {
+ tmr16_mode_t mode; /**< 16-bit timer mode, see #tmr16_mode_t for supported modes. */
+ uint16_t compareCount; /**< Number of timer ticks to either stop or reset the timer. */
+} tmr16_cfg_t;
+
+
+
+/**
+ * @brief Initializes the timer to a known state.
+ * @details This function initializes the timer to a known state and saves
+ * the prescaler. The timer will be left disabled. TMR_Init should
+ * be called before TMR_Config.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param prescale clock divider for the timer clock
+ * @param sysCfg Pointer to the timer system GPIO configuration. If not
+ * using GPIO for the timer instance, set this parameter
+ * to NULL.
+ *
+ * @retval #E_NO_ERROR Timer initialized successfully.
+ * @retval Error Code Timer was not initialized, see @ref MXC_Error_Codes.
+ */
+int TMR_Init(mxc_tmr_regs_t *tmr, tmr_prescale_t prescale, const sys_cfg_tmr_t *sysCfg);
+
+/**
+ * @brief Configures the timer in the specified mode.
+ * @details The parameters in config structure must be set before calling
+ * this function. This function should be used for configuring the
+ * timer in all 32 bit modes other than PWM.
+ * @note The timer cannot be running when this function is called
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param config pointer to timer configuration
+ */
+void TMR32_Config(mxc_tmr_regs_t *tmr, const tmr32_cfg_t *config);
+
+/**
+ * @brief Configures the timer in PWM mode.
+ * @details The parameters in config structure must be set before calling
+ * this function. This function should be used for configuring the
+ * timer in PWM mode only.
+ * @note The timer cannot be running when this function is called
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param config pointer to timer configuration
+ */
+void TMR32_PWMConfig(mxc_tmr_regs_t *tmr, const tmr32_cfg_pwm_t *config);
+
+/**
+ * @brief Configures the timer in the specified mode.
+ * @details The parameters in config structure must be set before calling
+ * this function. This function should be used for configuring the
+ * timer in all 16 bit modes.
+ * @note The timer cannot be running when this function is called
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ * @param config pointer to timer configuration
+ */
+void TMR16_Config(mxc_tmr_regs_t *tmr, uint8_t index, const tmr16_cfg_t *config);
+
+/**
+ * @brief Starts the specified timer.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ */
+void TMR32_Start(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief Starts the specified timer.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ */
+void TMR16_Start(mxc_tmr_regs_t *tmr, uint8_t index);
+
+/**
+ * @brief Stops the specified 32 bit timer.
+ * @details All other timer states are left unchanged.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ */
+__STATIC_INLINE void TMR32_Stop(mxc_tmr_regs_t *tmr)
+{
+ tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0;
+}
+
+/**
+ * @brief Stop the specified 16 bit timer.
+ * @details All other timer states are left unchanged.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ */
+__STATIC_INLINE void TMR16_Stop(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE1;
+ else
+ tmr->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0;
+}
+
+/**
+ * @brief Determines if the timer is running
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ *
+ * @return 0 = timer is off, non-zero = timer is on
+ */
+__STATIC_INLINE uint32_t TMR32_IsActive(mxc_tmr_regs_t *tmr)
+{
+ return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE0);
+}
+
+/**
+ * @brief Determines if the timer is running
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ *
+ * @return 0 Timer is off.
+ * @return Non-zero Timer is on.
+ */
+__STATIC_INLINE uint32_t TMR16_IsActive(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE1);
+ else
+ return (tmr->ctrl & MXC_F_TMR_CTRL_ENABLE0);
+}
+
+/**
+ * @brief Enables the timer's interrupt
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ */
+__STATIC_INLINE void TMR32_EnableINT(mxc_tmr_regs_t *tmr)
+{
+ tmr->inten |= MXC_F_TMR_INTEN_TIMER0;
+}
+
+/**
+ * @brief Enables the timer's interrupt
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ */
+__STATIC_INLINE void TMR16_EnableINT(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ tmr->inten |= MXC_F_TMR_INTEN_TIMER1;
+ else
+ tmr->inten |= MXC_F_TMR_INTEN_TIMER0;
+}
+
+/**
+ * @brief Disables the timer's interrupt
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ */
+__STATIC_INLINE void TMR32_DisableINT(mxc_tmr_regs_t *tmr)
+{
+ tmr->inten &= ~MXC_F_TMR_INTEN_TIMER0;
+}
+
+/**
+ * @brief Disables the timer's interrupt
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ */
+__STATIC_INLINE void TMR16_DisableINT(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ tmr->inten &= ~MXC_F_TMR_INTEN_TIMER1;
+ else
+ tmr->inten &= ~MXC_F_TMR_INTEN_TIMER0;
+}
+
+/**
+ * @brief Gets the timer's interrupt flag
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ *
+ * @return 0 = flag not set, non-zero = flag is set
+ */
+__STATIC_INLINE uint32_t TMR32_GetFlag(mxc_tmr_regs_t *tmr)
+{
+ return (tmr->intfl & MXC_F_TMR_INTFL_TIMER0);
+}
+
+/**
+ * @brief Gets the timer's interrupt flag
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ *
+ * @return 0 = flag not set, non-zero = flag is set
+ */
+__STATIC_INLINE uint32_t TMR16_GetFlag(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ return (tmr->intfl & MXC_F_TMR_INTFL_TIMER1);
+ else
+ return (tmr->intfl & MXC_F_TMR_INTFL_TIMER0);
+}
+
+/**
+ * @brief Clears the timer interrupt flag
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ */
+__STATIC_INLINE void TMR32_ClearFlag(mxc_tmr_regs_t *tmr)
+{
+ tmr->intfl = MXC_F_TMR_INTFL_TIMER0;
+}
+
+/**
+ * @brief Clears the timer interrupt flag for the specified index
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ */
+__STATIC_INLINE void TMR16_ClearFlag(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ tmr->intfl = MXC_F_TMR_INTFL_TIMER1;
+ else
+ tmr->intfl = MXC_F_TMR_INTFL_TIMER0;
+}
+
+/**
+ * @brief Set the current tick value to start counting from.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param count value to set the current ticks
+ */
+__STATIC_INLINE void TMR32_SetCount(mxc_tmr_regs_t *tmr, uint32_t count)
+{
+ tmr->count32 = count;
+}
+
+/**
+ * @brief Set the current tick value to start counting from.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ * @param count value to set the current ticks
+ */
+__STATIC_INLINE void TMR16_SetCount(mxc_tmr_regs_t *tmr, uint8_t index, uint16_t count)
+{
+ if (index)
+ tmr->count16_1 = count;
+ else
+ tmr->count16_0 = count;
+}
+
+/**
+ * @brief Gets the most current count value.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ *
+ * @return current count value in ticks
+ */
+__STATIC_INLINE uint32_t TMR32_GetCount(mxc_tmr_regs_t *tmr)
+{
+ return (tmr->count32);
+}
+
+/**
+ * @brief Gets the most current count value.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer(0 = 16_0 or 1 = 16_1)
+ *
+ * @return current count value in ticks
+ */
+__STATIC_INLINE uint32_t TMR16_GetCount(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if(index)
+ return tmr->count16_1;
+ else
+ return tmr->count16_0;
+}
+
+/**
+ * @brief Gets the most recent capture value.
+ * @details Used in Capture or Measure timer modes
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ *
+ * @return capture value in ticks
+ */
+__STATIC_INLINE uint32_t TMR32_GetCapture(mxc_tmr_regs_t *tmr)
+{
+ return (tmr->pwm_cap32);
+}
+
+/**
+ * @brief Set a new compare tick value for timer
+ * @details Depending on the timer mode this is the tick value to stop the
+ * timer, reset ticks to 1, or compare the timer
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param count new terminal/compare value in timer counts
+ */
+__STATIC_INLINE void TMR32_SetCompare(mxc_tmr_regs_t *tmr, uint32_t count)
+{
+ tmr->term_cnt32 = count;
+}
+
+/**
+ * @brief Get compare tick value for timer
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @return compare value in ticks
+ */
+__STATIC_INLINE uint32_t TMR32_GetCompare(mxc_tmr_regs_t *tmr)
+{
+ return tmr->term_cnt32;
+}
+
+/**
+ * @brief Set a new compare tick value for timer
+ * @details Depending on the timer mode this is the tick value to stop the
+ * timer, reset ticks to 1, or compare the timer
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ * @param count new terminal/compare value in timer counts
+ */
+__STATIC_INLINE void TMR16_SetCompare(mxc_tmr_regs_t *tmr, uint8_t index, uint16_t count)
+{
+ if (index)
+ tmr->term_cnt16_1 = count;
+ else
+ tmr->term_cnt16_0 = count;
+}
+
+/**
+ * @brief Get compare tick value for timer
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param index selects which 16 bit timer (0 = 16_0 or 1 = 16_1)
+ * @return compare value in ticks
+ */
+__STATIC_INLINE uint32_t TMR16_GetCompare(mxc_tmr_regs_t *tmr, uint8_t index)
+{
+ if (index)
+ return tmr->term_cnt16_1;
+ return tmr->term_cnt16_0;
+}
+
+/**
+ * @brief Returns the prescale value used by the timer
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ *
+ * @return prescaler
+ */
+uint32_t TMR_GetPrescaler(mxc_tmr_regs_t *tmr);
+
+/**
+ * @brief Set a new duty cycle when the timer is used in PWM mode.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param dutyCount duty cycle value in timer counts
+ */
+__STATIC_INLINE void TMR32_SetDuty(mxc_tmr_regs_t *tmr, uint32_t dutyCount)
+{
+ tmr->pwm_cap32 = dutyCount;
+}
+
+/**
+ * @brief Set a new duty cycle when the timer is used in PWM mode.
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param dutyPercent duty cycle value in percent (0 to 100%)
+ */
+__STATIC_INLINE void TMR32_SetDutyPer(mxc_tmr_regs_t *tmr, uint32_t dutyPercent)
+{
+ uint32_t periodCount = tmr->term_cnt32;
+ tmr->pwm_cap32 = ((uint64_t)periodCount * dutyPercent) / 100;
+}
+
+/**
+ * @brief Set a new period value for PWM timer
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param period new period value in timer counts
+ */
+__STATIC_INLINE void TMR32_SetPeriod(mxc_tmr_regs_t *tmr, uint32_t period)
+{
+ tmr->term_cnt32 = period;
+}
+
+/**
+ * @brief Converts frequency and duty cycle % to period and duty ticks
+ * @note TMR_Init should be called before this function to set the prescaler
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param dutyPercent duty cycle in percent (0 to 100%)
+ * @param freq frequency of pwm signal in Hz
+ * @param dutyTicks calculated duty cycle in ticks
+ * @param periodTicks calculated period in ticks
+ *
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ *
+ */
+int TMR32_GetPWMTicks(mxc_tmr_regs_t *tmr, uint8_t dutyPercent, uint32_t freq, uint32_t *dutyTicks, uint32_t *periodTicks);
+
+/**
+ * @brief Converts a time and units to a number of ticks for the 32-bit timer.
+ * @note TMR_Init should be called before this function to set the prescaler
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param time time value.
+ * @param units time units.
+ * @param ticks calculated number of ticks.
+ *
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int TMR32_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks);
+
+/**
+ * @brief Converts a time and units to a number of ticks for the 16-bit timer.
+ * @note TMR_Init should be called before this function to set the prescaler
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param time time value.
+ * @param units time units.
+ * @param ticks calculated number of ticks.
+ *
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int TMR16_TimeToTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint16_t *ticks);
+
+/**
+ * @brief Converts a number of ticks to a time and units for the timer.
+ * @note TMR_Init should be called before this function to set the prescaler
+ *
+ * @param tmr Pointer to timer registers for the timer instance to modify.
+ * @param ticks number of ticks.
+ * @param time calculated time value.
+ * @param units calculated time units.
+ *
+ * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
+ */
+int TMR_TicksToTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TIMER_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,174 @@
+/**
+ * @file
+ * @brief Timer utility functions.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:30:35 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24322 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "mxc_assert.h"
+#include "tmr.h"
+#include "tmr_utils.h"
+
+
+/**
+ * @ingroup tmr_utilities
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/* **** Globals **** */
+
+/* **** Functions **** */
+
+/* ************************************************************************** */
+void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us)
+{
+ TMR_TO_Start(tmr, us);
+
+ while(TMR_TO_Check(tmr) != E_TIME_OUT) {}
+}
+
+/* ************************************************************************** */
+void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us)
+{
+ unsigned clk_shift = 0;
+ uint64_t max_us;
+ uint32_t ticks;
+
+ // Adjust the clk shift amout by how long the timeout is
+ // Start with the fastest clock to give the greatest accuracy
+ do {
+ max_us = (uint64_t)((0xFFFFFFFFUL / ((uint64_t)SystemCoreClock >> clk_shift++)) * 1000000UL);
+ } while(us > max_us);
+
+ // Calculate the number of timer ticks we need to wait
+ TMR_Init(tmr, (tmr_prescale_t)clk_shift, NULL);
+ TMR32_TimeToTicks(tmr, us, TMR_UNIT_MICROSEC, &ticks);
+
+ // Initialize the timer in one-shot mode
+ tmr32_cfg_t cfg;
+ cfg.mode = TMR32_MODE_ONE_SHOT;
+ cfg.compareCount = ticks;
+ TMR32_Stop(tmr);
+ TMR32_Config(tmr, &cfg);
+
+ TMR32_ClearFlag(tmr);
+ TMR32_Start(tmr);
+}
+
+/* ************************************************************************** */
+int TMR_TO_Check(mxc_tmr_regs_t* tmr)
+{
+ if(TMR32_GetFlag(tmr)) {
+ return E_TIME_OUT;
+ }
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************** */
+void TMR_TO_Stop(mxc_tmr_regs_t* tmr)
+{
+ TMR32_Stop(tmr);
+ TMR32_SetCount(tmr, 0x0);
+}
+
+/* ************************************************************************** */
+void TMR_TO_Clear(mxc_tmr_regs_t* tmr)
+{
+ TMR32_ClearFlag(tmr);
+ TMR32_SetCount(tmr, 0x0);
+}
+
+/* ************************************************************************** */
+unsigned TMR_TO_Elapsed(mxc_tmr_regs_t* tmr)
+{
+ uint32_t elapsed;
+ tmr_unit_t units;
+
+ TMR_TicksToTime(tmr, TMR32_GetCount(tmr), &elapsed, &units);
+
+ switch(units) {
+ case TMR_UNIT_NANOSEC:
+ default:
+ return (elapsed / 1000);
+ case TMR_UNIT_MICROSEC:
+ return (elapsed);
+ case TMR_UNIT_MILLISEC:
+ return (elapsed * 1000);
+ case TMR_UNIT_SEC:
+ return (elapsed * 1000000);
+ }
+}
+
+/* ************************************************************************** */
+unsigned TMR_TO_Remaining(mxc_tmr_regs_t* tmr)
+{
+ uint32_t remaining_ticks, remaining_time;
+ tmr_unit_t units;
+
+ remaining_ticks = TMR32_GetCompare(tmr) - TMR32_GetCount(tmr);
+ TMR_TicksToTime(tmr, remaining_ticks, &remaining_time, &units);
+
+ switch(units) {
+ case TMR_UNIT_NANOSEC:
+ default:
+ return (remaining_time / 1000);
+ case TMR_UNIT_MICROSEC:
+ return (remaining_time);
+ case TMR_UNIT_MILLISEC:
+ return (remaining_time * 1000);
+ case TMR_UNIT_SEC:
+ return (remaining_time * 1000000);
+ }
+}
+
+/* ************************************************************************** */
+void TMR_SW_Start(mxc_tmr_regs_t* tmr)
+{
+ TMR_TO_Start(tmr, 0xFFFFFFFF);
+}
+
+/* ************************************************************************** */
+unsigned TMR_SW_Stop(mxc_tmr_regs_t* tmr)
+{
+ unsigned elapsed = TMR_TO_Elapsed(tmr);
+ TMR_TO_Stop(tmr);
+ return elapsed;
+}
+/** @} end of ingroup tmr_utilities */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,136 @@
+/**
+ * @file
+ * @brief Timer utility functions.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:49:16 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24675 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _TMR_UTILS_H
+#define _TMR_UTILS_H
+
+/***** Includes *****/
+#include "mxc_config.h"
+#include "tmr_regs.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup tmr
+ * @defgroup tmr_utils Timer Utility Functions
+ * @{
+ */
+/* **** Definitions **** */
+/** Macro to convert the parameter \p s from seconds to micro-seconds. */
+#define SEC(s) (((unsigned long)s) * 1000000UL)
+/** Macro to convert the parameter \p ms from milli-seconds to micro-seconds. */
+#define MSEC(ms) (ms * 1000UL)
+/** Macro to convert the parameter \p us to micro-seconds. */
+#define USEC(us) (us)
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Delays for the specified number of microseconds.
+ * @param tmr TMR module to operate on
+ * @param us Number of microseconds to delay.
+ */
+void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us);
+
+/**
+ * @brief Start the timeout time for the specified number of microseconds.
+ * @param tmr TMR module to operate on
+ * @param us Number of microseconds in the timeout.
+ */
+void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us);
+
+/**
+ * @brief Check if the timeout has occured.
+ * @param tmr TMR module to operate on
+ * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has.
+ */
+int TMR_TO_Check(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Stops the timer for the timeout.
+ * @param tmr TMR module to operate on
+ */
+void TMR_TO_Stop(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Clears the timeout flag.
+ * @param tmr TMR module to operate on
+ */
+void TMR_TO_Clear(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Get the number of microseconds elapsed since TMR_TO_Start().
+ * @param tmr TMR module to operate on
+ * @return Number of microseconds since TMR_TO_Start().
+ */
+unsigned TMR_TO_Elapsed(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Get the number of microseconds remaining in the timeout.
+ * @param tmr TMR module to operate on
+ * @return Number of microseconds since TMR_TO_Start().
+ */
+unsigned TMR_TO_Remaining(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Start the stopwatch.
+ * @param tmr TMR module to operate on
+ */
+void TMR_SW_Start(mxc_tmr_regs_t* tmr);
+
+/**
+ * @brief Stop the stopwatch and return the number of microseconds that
+ * have elapsed.
+ * @param tmr TMR module to operate on
+ * @return Number of microseconds since TMR_TO_Start().
+ */
+unsigned TMR_SW_Stop(mxc_tmr_regs_t* tmr);
+/**@} end of defgroup tmr_utils*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TMR_UTILS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,661 @@
+/**
+ * @file
+ * @brief This file contains the function implementations for the UART
+ * serial communications peripheral module.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:00:36 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24319 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <string.h>
+#include "mxc_config.h"
+#include "mxc_assert.h"
+#include "mxc_lock.h"
+#include "mxc_sys.h"
+#include "uart.h"
+
+/**
+ * @ingroup uart_comm
+ * @{
+ */
+/* **** Definitions **** */
+///@cond
+#define UART_ERRORS (MXC_F_UART_INTEN_RX_FIFO_OVERFLOW | \
+ MXC_F_UART_INTEN_RX_FRAMING_ERR | \
+ MXC_F_UART_INTEN_RX_PARITY_ERR)
+
+#define UART_READ_INTS (MXC_F_UART_INTEN_RX_FIFO_AF | \
+ MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | \
+ MXC_F_UART_INTEN_RX_STALLED | \
+ UART_ERRORS)
+
+#define UART_WRITE_INTS (MXC_F_UART_INTEN_TX_UNSTALLED | \
+ MXC_F_UART_INTEN_TX_FIFO_AE)
+
+#define UART_RXFIFO_USABLE (MXC_UART_FIFO_DEPTH-3)
+///@endcond
+//
+/* **** Globals **** */
+
+// Saves the state of the non-blocking read requests
+static uart_req_t *rx_states[MXC_CFG_UART_INSTANCES];
+
+// Saves the state of the non-blocking write requests
+static uart_req_t *tx_states[MXC_CFG_UART_INSTANCES];
+
+/* **** Functions **** */
+static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
+static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
+ uint32_t flags);
+
+/* ************************************************************************* */
+int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg)
+{
+ int err;
+ int uart_num;
+ uint32_t uart_clk;
+ uint8_t baud_shift;
+ uint16_t baud_div;
+ uint32_t baud, diff_baud;
+ uint32_t baud_1, diff_baud_1;
+
+ // Check the input parameters
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ // Set system level configurations
+ if(sys_cfg != NULL) {
+ if ((err = SYS_UART_Init(uart, cfg, sys_cfg)) != E_NO_ERROR) {
+ return err;
+ }
+ }
+
+ // Initialize state pointers
+ rx_states[uart_num] = NULL;
+ tx_states[uart_num] = NULL;
+
+ // Drain FIFOs and enable UART
+ uart->ctrl = 0;
+ uart->ctrl = (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
+ MXC_F_UART_CTRL_RX_FIFO_EN |
+ (UART_RXFIFO_USABLE << MXC_F_UART_CTRL_RTS_LEVEL_POS));
+
+ // Configure data size, stop bit, parity, cts, and rts
+ uart->ctrl |= ((cfg->size << MXC_F_UART_CTRL_DATA_SIZE_POS) |
+ (cfg->extra_stop << MXC_F_UART_CTRL_EXTRA_STOP_POS) |
+ (cfg->parity << MXC_F_UART_CTRL_PARITY_POS) |
+ (cfg->cts << MXC_F_UART_CTRL_CTS_EN_POS) |
+ (cfg->rts << MXC_F_UART_CTRL_RTS_EN_POS));
+
+ // Configure the baud rate and divisor
+ uart_clk = SYS_UART_GetFreq(uart);
+ MXC_ASSERT(uart_clk > 0);
+
+ baud_shift = 2;
+ baud_div = (uart_clk / (cfg->baud * 4));
+
+ // Can not support higher frequencies
+ if(!baud_div) {
+ return E_NOT_SUPPORTED;
+ }
+
+ // Decrease the divisor if baud_div is overflowing
+ while(baud_div > 0xFF) {
+ if(baud_shift == 0) {
+ return E_NOT_SUPPORTED;
+ }
+ baud_shift--;
+ baud_div = (uart_clk / (cfg->baud * (16 >> baud_shift)));
+ }
+
+ // Adjust baud_div so we don't overflow with the calculations below
+ if(baud_div == 0xFF) {
+ baud_div = 0xFE;
+ }
+ if(baud_div == 0) {
+ baud_div = 1;
+ }
+
+ // Figure out if the truncation increased the error
+ baud = (uart_clk / (baud_div * (16 >> baud_shift)));
+ baud_1 = (uart_clk / ((baud_div+1) * (16 >> baud_shift)));
+
+ if(cfg->baud > baud) {
+ diff_baud = cfg->baud - baud;
+ } else {
+ diff_baud = baud - cfg->baud;
+ }
+
+ if(cfg->baud > baud_1) {
+ diff_baud_1 = cfg->baud - baud_1;
+ } else {
+ diff_baud_1 = baud_1 - cfg->baud;
+ }
+
+ if(diff_baud < diff_baud_1) {
+ uart->baud = ((baud_div & MXC_F_UART_BAUD_BAUD_DIVISOR) |
+ (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
+ } else {
+ uart->baud = (((baud_div+1) & MXC_F_UART_BAUD_BAUD_DIVISOR) |
+ (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_Shutdown(mxc_uart_regs_t *uart)
+{
+ int uart_num, err;
+ uart_req_t *temp_req;
+
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ // Disable and clear interrupts
+ uart->inten = 0;
+ uart->intfl = uart->intfl;
+
+ // Disable UART and FIFOS
+ uart->ctrl &= ~(MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
+ MXC_F_UART_CTRL_RX_FIFO_EN);
+
+ // Call all of the pending callbacks for this UART
+ if(rx_states[uart_num] != NULL) {
+
+ // Save the request
+ temp_req = rx_states[uart_num];
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ // Callback if not NULL
+ if(temp_req->callback != NULL) {
+ temp_req->callback(temp_req, E_SHUTDOWN);
+ }
+ }
+
+ if(tx_states[uart_num] != NULL) {
+
+ // Save the request
+ temp_req = tx_states[uart_num];
+
+ // Unlock this UART to write
+ mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+ // Callback if not NULL
+ if(temp_req->callback != NULL) {
+ temp_req->callback(temp_req, E_SHUTDOWN);
+ }
+ }
+
+ // Clears system level configurations
+ if ((err = SYS_UART_Shutdown(uart)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len)
+{
+ int num, uart_num;
+ mxc_uart_fifo_regs_t *fifo;
+
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ if(data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the UART has been initialized
+ if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Lock this UART from writing
+ while(mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {}
+
+ // Get the FIFO for this UART
+ fifo = MXC_UART_GET_FIFO(uart_num);
+
+ num = 0;
+
+ while(num < len) {
+
+ // Wait for TXFIFO to not be full
+ while((uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ==
+ MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) {}
+
+ // Write the data to the FIFO
+#if(MXC_UART_REV == 0)
+ uart->intfl = MXC_F_UART_INTFL_TX_DONE;
+#endif
+ fifo->tx = data[num++];
+ }
+
+ // Unlock this UART to write
+ mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+ return num;
+}
+
+/* ************************************************************************* */
+int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num)
+{
+ int num_local, remain, uart_num;
+ mxc_uart_fifo_regs_t *fifo;
+
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ if(data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the UART has been initialized
+ if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Lock this UART from reading
+ while(mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {}
+
+ // Get the FIFO for this UART
+ fifo = MXC_UART_GET_FIFO(uart_num);
+
+ num_local = 0;
+ remain = len;
+ while(remain) {
+
+ // Save the data in the FIFO
+ while((uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) && remain) {
+ data[num_local] = fifo->rx;
+ num_local++;
+ remain--;
+ }
+
+ // Break if there is an error
+ if(uart->intfl & UART_ERRORS) {
+ break;
+ }
+ }
+
+ // Save the number of bytes read if pointer is valid
+ if(num != NULL) {
+ *num = num_local;
+ }
+
+ // Check for errors
+ if(uart->intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
+
+ // Clear errors and return error code
+ uart->intfl = UART_ERRORS;
+
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ return E_OVERFLOW;
+
+ } else if(uart->intfl & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
+ MXC_F_UART_INTFL_RX_PARITY_ERR)) {
+
+ // Clear errors and return error code
+ uart->intfl = UART_ERRORS;
+
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ return E_COMM_ERR;
+ }
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ return num_local;
+}
+
+/* ************************************************************************* */
+int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
+{
+ int uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ // Check the input parameters
+ if(req->data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the UART has been initialized
+ if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(req->len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Attempt to register this write request
+ if(mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Clear the number of bytes counter
+ req->num = 0;
+
+ // Start the write
+ UART_WriteHandler(uart, req, uart_num);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
+{
+ int uart_num;
+ uint32_t flags;
+
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ if(req->data == NULL) {
+ return E_NULL_PTR;
+ }
+
+ // Make sure the UART has been initialized
+ if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
+ return E_UNINITIALIZED;
+ }
+
+ if(!(req->len > 0)) {
+ return E_NO_ERROR;
+ }
+
+ // Attempt to register this write request
+ if(mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Clear the number of bytes counter
+ req->num = 0;
+
+ // Start the read
+ flags = uart->intfl;
+ uart->intfl = flags;
+ UART_ReadHandler(uart, req, uart_num, flags);
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int UART_AbortAsync(uart_req_t *req)
+{
+ int uart_num;
+
+ // Figure out if this was a read or write request, find the request, set to NULL
+ for(uart_num = 0; uart_num < MXC_CFG_UART_INSTANCES; uart_num++) {
+ if(req == rx_states[uart_num]) {
+
+ // Disable read interrupts, clear flags.
+ MXC_UART_GET_UART(uart_num)->inten &= ~UART_READ_INTS;
+ MXC_UART_GET_UART(uart_num)->intfl = UART_READ_INTS;
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ // Callback if not NULL
+ if(req->callback != NULL) {
+ req->callback(req, E_ABORT);
+ }
+
+ return E_NO_ERROR;
+ }
+
+ if(req == tx_states[uart_num]) {
+
+ // Disable write interrupts, clear flags.
+ MXC_UART_GET_UART(uart_num)->inten &= ~(UART_WRITE_INTS);
+ MXC_UART_GET_UART(uart_num)->intfl = UART_WRITE_INTS;
+
+ // Unlock this UART to write
+ mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+ // Callback if not NULL
+ if(req->callback != NULL) {
+ req->callback(req, E_ABORT);
+ }
+
+ return E_NO_ERROR;
+ }
+ }
+
+ return E_BAD_PARAM;
+}
+
+/* ************************************************************************* */
+void UART_Handler(mxc_uart_regs_t *uart)
+{
+ int uart_num;
+ uint32_t flags;
+
+ uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ flags = uart->intfl;
+ uart->intfl = flags;
+
+ // Figure out if this UART has an active Read request
+ if((rx_states[uart_num] != NULL) && (flags & UART_READ_INTS)) {
+ UART_ReadHandler(uart, rx_states[uart_num], uart_num, flags);
+ }
+
+ // Figure out if this UART has an active Write request
+ if((tx_states[uart_num] != NULL) && (flags & (UART_WRITE_INTS))) {
+
+ UART_WriteHandler(uart, tx_states[uart_num], uart_num);
+ }
+}
+/* ************************************************************************* */
+int UART_Busy(mxc_uart_regs_t *uart)
+{
+ int uart_num = MXC_UART_GET_IDX(uart);
+ MXC_ASSERT(uart_num >= 0);
+
+ // Check to see if there are any ongoing transactions or if the UART is disabled
+ if(((tx_states[uart_num] == NULL) &&
+ !(uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) &&
+#if(MXC_UART_REV == 0)
+ (uart->intfl & MXC_F_UART_INTFL_TX_DONE)) ||
+#else
+ (uart->idle & MXC_F_UART_IDLE_TX_RX_IDLE)) ||
+#endif
+ !(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
+
+ return E_NO_ERROR;
+ }
+
+ return E_BUSY;
+}
+
+/* ************************************************************************* */
+int UART_PrepForSleep(mxc_uart_regs_t *uart)
+{
+ if(UART_Busy(uart) != E_NO_ERROR) {
+ return E_BUSY;
+ }
+
+ // Leave read interrupts enabled, if already enabled
+ uart->inten &= UART_READ_INTS;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
+{
+ int avail, remain;
+ mxc_uart_fifo_regs_t *fifo;
+
+ // Disable write interrupts
+ uart->inten &= ~(UART_WRITE_INTS);
+
+ // Get the FIFO for this UART
+ fifo = MXC_UART_GET_FIFO(uart_num);
+
+ // Refill the TX FIFO
+ avail = UART_NumWriteAvail(uart);
+ remain = req->len - req->num;
+
+ while(avail && remain) {
+
+ // Write the data to the FIFO
+#if(MXC_UART_REV == 0)
+ uart->intfl = MXC_F_UART_INTFL_TX_DONE;
+#endif
+ fifo->tx = req->data[req->num++];
+ remain--;
+ avail--;
+ }
+
+ // All of the bytes have been written to the FIFO
+ if(!remain) {
+
+ // Unlock this UART to write
+ mxc_free_lock((uint32_t*)&tx_states[uart_num]);
+
+ if(req->callback != NULL) {
+ req->callback(req, E_NO_ERROR);
+ }
+
+ } else {
+
+ // Interrupt when there is one byte left in the TXFIFO
+ uart->tx_fifo_ctrl = ((MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
+
+ // Enable almost empty interrupt
+ uart->inten |= (MXC_F_UART_INTEN_TX_FIFO_AE);
+ }
+}
+
+/* ************************************************************************* */
+static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
+ uint32_t flags)
+{
+ int avail, remain;
+ mxc_uart_fifo_regs_t *fifo;
+
+ // Disable interrupts
+ uart->inten &= ~UART_READ_INTS;
+
+ // Get the FIFO for this UART, uart_num
+ fifo = MXC_UART_GET_FIFO(uart_num);
+
+ // Save the data in the FIFO while we still need data
+ avail = UART_NumReadAvail(uart);
+ remain = req->len - req->num;
+ while(avail && remain) {
+ req->data[req->num++] = fifo->rx;
+ remain--;
+ avail--;
+ }
+
+ // Check for errors
+ if(flags & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ if(req->callback != NULL) {
+ req->callback(req, E_OVERFLOW);
+ }
+
+ return;
+ }
+
+ if(flags & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
+ MXC_F_UART_INTFL_RX_PARITY_ERR)) {
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ if(req->callback != NULL) {
+ req->callback(req, E_COMM_ERR);
+ }
+
+ return;
+ }
+
+ // Check to see if we're done receiving
+ if(remain == 0) {
+
+ // Unlock this UART to read
+ mxc_free_lock((uint32_t*)&rx_states[uart_num]);
+
+ if(req->callback != NULL) {
+ req->callback(req, E_NO_ERROR);
+ }
+
+ return;
+ }
+
+ if(remain == 1) {
+ uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | UART_ERRORS);
+
+ } else {
+ // Set the RX FIFO AF threshold
+ if(remain < UART_RXFIFO_USABLE) {
+ uart->rx_fifo_ctrl = ((remain - 1) <<
+ MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
+ } else {
+ uart->rx_fifo_ctrl = (UART_RXFIFO_USABLE <<
+ MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
+ }
+ uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_AF | UART_ERRORS);
+ }
+}
+/**@} end of ingroup uart_comm */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,347 @@
+/**
+ * @file
+ * @brief UART data types, definitions and function prototypes.
+ */
+ /* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:51:14 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24676 $
+ *
+ **************************************************************************** */
+
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "mxc_sys.h"
+#include "uart_regs.h"
+
+/* Define to prevent redundant inclusion */
+#ifndef _UART_H_
+#define _UART_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup commperipherals
+ * @defgroup uart_comm UART
+ * @brief UART serial communications peripheral.
+ * @{
+ */
+
+/* **** Definitions **** */
+
+/**
+ * Enumeration type for defining the number of bits per character.
+ */
+typedef enum {
+ UART_DATA_SIZE_5_BITS = MXC_V_UART_CTRL_DATA_SIZE_5_BITS,
+ UART_DATA_SIZE_6_BITS = MXC_V_UART_CTRL_DATA_SIZE_6_BITS,
+ UART_DATA_SIZE_7_BITS = MXC_V_UART_CTRL_DATA_SIZE_7_BITS,
+ UART_DATA_SIZE_8_BITS = MXC_V_UART_CTRL_DATA_SIZE_8_BITS
+}
+uart_data_size_t;
+
+/**
+ * Enumeration type for selecting Parity and type.
+ */
+typedef enum {
+ UART_PARITY_DISABLE = MXC_V_UART_CTRL_PARITY_DISABLE,
+ UART_PARITY_ODD = MXC_V_UART_CTRL_PARITY_ODD,
+ UART_PARITY_EVEN = MXC_V_UART_CTRL_PARITY_EVEN,
+ UART_PARITY_MARK = MXC_V_UART_CTRL_PARITY_MARK
+} uart_parity_t;
+
+/**
+ * Configuration structure type for a UART port.
+ */
+typedef struct {
+ uint8_t extra_stop; /**< Number of stop bits.
+ * @li 0 for one stop bit
+ * @li 1 for two stop bits
+ */
+ uint8_t cts; /**< CTS Enable/Disable.
+ * @li 1 to enable CTS
+ * @li 0 to disable CTS
+ */
+ uint8_t rts; /**< RTS Enable/Disable.
+ * @li 1 to enable RTS
+ * @li 0 to disable RTS
+ */
+ uint32_t baud; /**< Baud rate in Hz. */
+ uart_data_size_t size; /**< Set the number of bits per character, see #uart_data_size_t. */
+ uart_parity_t parity; /**< Set the parity, see #uart_parity_t for supported parity types. */
+} uart_cfg_t;
+
+/**
+ * Structure type for a UART asynchronous transaction request.
+ */
+typedef struct uart_req uart_req_t;
+
+/**
+ * @brief Type alias \c uart_async_callback for a callback function with signature of: \code void callback)(uart_req_t* , int error_code) \endcode
+ * @param uart_req_t* Pointer to the transaction request.
+ * @param error_code Return code for the UART request. @see mxc_errors.h.
+ * @addtogroup uart_async
+ */
+typedef void (*uart_async_callback)(uart_req_t*, int);
+
+/**
+ * Structure for a UART asynchronous transaction request.
+ * @note When using this structure for an asynchronous operation, the
+ * structure must remain allocated until the callback is completed.
+ * @addtogroup uart_async
+ */
+struct uart_req {
+ uint8_t *data; /**< Data buffer for characters. */
+ unsigned len; /**< Length of characters in data to send or receive. */
+ unsigned num; /**< Number of characters actually sent or received. */
+ uart_async_callback callback; /**< Pointer to a callback function of type uart_async_callback(). */
+};
+
+
+/* **** Globals **** */
+
+/* **** Function Prototypes **** */
+
+/**
+ * @brief Initialize and enable UART module.
+ * @param uart Pointer to the UART registers.
+ * @param cfg Pointer to UART configuration.
+ * @param sys_cfg Pointer to system configuration object
+ * @returns #E_NO_ERROR UART initialized successfully, @ref MXC_Error_Codes "error" if
+ * unsuccessful.
+ */
+int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg);
+
+/**
+ * @brief Shutdown UART module.
+ * @param uart Pointer to the UART registers.
+ * @returns #E_NO_ERROR UART shutdown successfully, @ref MXC_Error_Codes "error" if
+ * unsuccessful.
+ */
+int UART_Shutdown(mxc_uart_regs_t *uart);
+
+/**
+ * @brief Write UART data. This function blocks until the write transaction
+ * is complete.
+ * @param uart Pointer to the UART registers.
+ * @param data Pointer to buffer for write data.
+ * @param len Number of bytes to write.
+ * @note Will return once data has been put into FIFO, not necessarily
+ * transmitted.
+ * @return Number of bytes written if successful, error if unsuccessful.
+ */
+int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len);
+
+/**
+ * @brief Read UART data, <em>blocking</em> until transaction is complete.
+ *
+ * @param uart Pointer to the UART registers.
+ * @param data Pointer to buffer to save the data read.
+ * @param len Number of bytes to read.
+ * @param num Pointer to store the number of bytes actually read, pass NULL if not needed.
+ *
+ * @return Number of bytes read, @ref MXC_Error_Codes "error" if
+ * unsuccessful.
+ */
+int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num);
+
+/**
+ * @ingroup uart_comm
+ * @defgroup uart_async UART Asynchronous Functions
+ */
+
+/**
+ * @brief Asynchronously write/transmit data to the UART.
+ *
+ * @param uart Pointer to the UART registers.
+ * @param req Request for a UART transaction.
+ * @note Request struct must remain allocated until callback.
+ *
+ * @return #E_NO_ERROR Asynchronous write successfully started, @ref
+ * MXC_Error_Codes "error" if unsuccessful.
+ * @addtogroup uart_async
+ */
+int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req);
+
+/**
+ * @brief Asynchronously Read UART data.
+ *
+ * @param uart Pointer to the UART registers.
+ * @param req Pointer to request for a UART transaction.
+ * @note Request struct must remain allocated until callback function is called.
+ *
+ * @return #E_NO_ERROR Asynchronous read successfully started, @ref
+ * MXC_Error_Codes "error" if unsuccessful.
+ * @addtogroup uart_async
+ */
+int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req);
+
+/**
+ * @brief Abort asynchronous request.
+ *
+ * @param req Pointer to a request for a UART transaction, see #uart_req.
+ *
+ * @return #E_NO_ERROR Asynchronous request aborted successfully, error if unsuccessful.
+ * @addtogroup uart_async
+ */
+int UART_AbortAsync(uart_req_t *req);
+
+/**
+ * @brief UART interrupt handler.
+ * @details This function should be called by the application from the
+ * interrupt handler if UART interrupts are enabled. Alternately,
+ * this function can be periodically called by the application if
+ * UART interrupts are disabled. Only necessary to call this when
+ * using asynchronous functions.
+ *
+ * @param uart Pointer to the UART registers.
+ * @addtogroup uart_async
+ */
+void UART_Handler(mxc_uart_regs_t *uart);
+
+/**
+ * @brief Check to see if the UART is busy.
+ *
+ * @param uart Pointer to the UART registers.
+ *
+ * @return #E_NO_ERROR UART is idle.
+ * @return #E_BUSY UART is in use.
+ */
+int UART_Busy(mxc_uart_regs_t *uart);
+
+/**
+ * @brief Prepare the UART for entry into a Low-Power mode (LP0/LP1).
+ * @details Checks for any ongoing transactions. Disables interrupts if the
+ * UART is idle.
+ *
+ * @param uart Pointer to the UART registers.
+ * @return #E_NO_ERROR UART is ready to enter Low-Power modes (LP0/LP1).
+ * @return #E_BUSY UART is active and busy and not ready to enter a
+ * Low-Power mode (LP0/LP1).
+ *
+ */
+int UART_PrepForSleep(mxc_uart_regs_t *uart);
+
+/**
+ * @brief Enables the UART.
+ * @note This function does not change the existing UART configuration.
+ *
+ * @param uart Pointer to the UART registers.
+ */
+__STATIC_INLINE void UART_Enable(mxc_uart_regs_t *uart)
+{
+ uart->ctrl |= (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
+ MXC_F_UART_CTRL_RX_FIFO_EN);
+}
+
+/**
+ * @brief Drains/empties and data in the RX FIFO.
+ *
+ * @param uart Pointer to the UART registers.
+ */
+__STATIC_INLINE void UART_DrainRX(mxc_uart_regs_t *uart)
+{
+ uint32_t ctrl_save = uart->ctrl;
+ uart->ctrl = (ctrl_save & ~MXC_F_UART_CTRL_RX_FIFO_EN);
+ uart->ctrl = ctrl_save;
+}
+
+/**
+ * @brief Drains/empties any data in the TX FIFO.
+ *
+ * @param uart Pointer to the UART registers.
+ */
+__STATIC_INLINE void UART_DrainTX(mxc_uart_regs_t *uart)
+{
+ uint32_t ctrl_save = uart->ctrl;
+ uart->ctrl = (ctrl_save & ~MXC_F_UART_CTRL_TX_FIFO_EN);
+ uart->ctrl = ctrl_save;
+}
+
+/**
+ * @brief Returns the number of unused bytes available in the UART TX FIFO.
+ *
+ * @param uart Pointer to the UART registers.
+ *
+ * @return Number of unused bytes in the TX FIFO.
+ */
+__STATIC_INLINE unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart)
+{
+ return (MXC_UART_FIFO_DEPTH - (uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY));
+}
+
+/**
+ * @brief Returns the number of bytes available to be read from the RX
+ * FIFO.
+ *
+ * @param uart Pointer to the UART registers.
+ *
+ * @return The number of bytes available to read in the RX FIFO.
+ */
+__STATIC_INLINE unsigned UART_NumReadAvail(mxc_uart_regs_t *uart)
+{
+ return (uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY);
+}
+
+/**
+ * @brief Clear interrupt flags.
+ *
+ * @param uart Pointer to the UART registers.
+ * @param mask Mask of the UART interrupts to clear, see
+ * @ref UART_INTFL_Register Register.
+ */
+__STATIC_INLINE void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask)
+{
+ uart->intfl = mask;
+}
+
+/**
+ * @brief Get interrupt flags.
+ *
+ * @param uart Pointer to the UART registers.
+ *
+ * @return Mask of active flags.
+ */
+__STATIC_INLINE unsigned UART_GetFlags(mxc_uart_regs_t *uart)
+{
+ return (uart->intfl);
+}
+
+/**@} end of group uart_comm */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UART_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,290 @@
+/**
+ * @file
+ * @brief Watchdog driver source.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:27:05 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24321 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "wdt.h"
+/**
+ * @ingroup wdt
+ * @{
+ */
+static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function
+
+/* ************************************************************************* */
+int WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg, uint8_t unlock_key)
+{
+ if ((wdt == NULL) || (cfg == NULL))
+ return E_NULL_PTR;
+
+ //setup watchdog clock
+ SYS_WDT_Init(wdt, cfg);
+
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable all interrupts
+ interruptEnable = 0;
+ wdt->enable = interruptEnable;
+
+ //enable the watchdog clock and clear all other settings
+ wdt->ctrl = MXC_F_WDT_CTRL_EN_CLOCK;
+
+ //clear all interrupt flags
+ wdt->flags = WDT_FLAGS_CLEAR_ALL;
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_EnableInt(mxc_wdt_regs_t *wdt, wdt_period_t int_period, uint8_t unlock_key)
+{
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //stop timer and clear interval period
+ wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_PERIOD | MXC_F_WDT_CTRL_EN_TIMER);
+
+ //set interval period
+ wdt->ctrl |= (int_period << MXC_F_WDT_CTRL_INT_PERIOD_POS);
+
+ //enable timeout interrupt
+ interruptEnable |= MXC_F_WDT_ENABLE_TIMEOUT;
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_DisableInt(mxc_wdt_regs_t *wdt, uint8_t unlock_key)
+{
+ //unlock register to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable timeout interrupt
+ interruptEnable &= ~MXC_F_WDT_ENABLE_TIMEOUT;
+ wdt->enable = interruptEnable;
+
+ //lock register to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_EnableWait(mxc_wdt_regs_t *wdt, wdt_period_t wait_period, uint8_t unlock_key)
+{
+ // Make sure wait_period is valid
+ if (wait_period >= WDT_PERIOD_MAX)
+ return E_INVALID;
+
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //stop timer and clear wait period
+ wdt->ctrl &= ~(MXC_F_WDT_CTRL_WAIT_PERIOD | MXC_F_WDT_CTRL_EN_TIMER);
+
+ //set wait period
+ wdt->ctrl |= (wait_period << MXC_F_WDT_CTRL_WAIT_PERIOD_POS);
+
+ //enable wait interrupt
+ interruptEnable |= MXC_F_WDT_ENABLE_PRE_WIN;
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_DisableWait(mxc_wdt_regs_t *wdt, uint8_t unlock_key)
+{
+ //unlock register to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable wait interrupt
+ interruptEnable &= ~MXC_F_WDT_ENABLE_PRE_WIN;
+ wdt->enable = interruptEnable;
+
+ //lock register to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_EnableReset(mxc_wdt_regs_t *wdt, wdt_period_t rst_period, uint8_t unlock_key)
+{
+ // Make sure wait_period is valid
+ if (rst_period >= WDT_PERIOD_MAX)
+ return E_INVALID;
+
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //stop timer and clear reset period
+ wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_PERIOD | MXC_F_WDT_CTRL_EN_TIMER);
+
+ //set reset period
+ wdt->ctrl |= (rst_period << MXC_F_WDT_CTRL_RST_PERIOD_POS);
+
+ //enable reset0
+ interruptEnable |= MXC_F_WDT_ENABLE_RESET_OUT;
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_DisableReset(mxc_wdt_regs_t *wdt, uint8_t unlock_key)
+{
+ //unlock register to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable reset0
+ interruptEnable &= ~MXC_F_WDT_ENABLE_RESET_OUT;
+ wdt->enable = interruptEnable;
+
+ //lock register to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT_Start(mxc_wdt_regs_t *wdt, uint8_t unlock_key)
+{
+ //check if watchdog is already running
+ if(WDT_IsActive(wdt))
+ return E_BAD_STATE;
+
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ WDT_Reset(wdt);
+
+ //enable interrupts
+ wdt->enable = interruptEnable;
+
+ //start timer
+ wdt->ctrl |= MXC_F_WDT_CTRL_EN_TIMER;
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void WDT_Reset(mxc_wdt_regs_t *wdt)
+{
+ //reset the watchdog counter
+ wdt->clear = MXC_V_WDT_RESET_KEY_0;
+ wdt->clear = MXC_V_WDT_RESET_KEY_1;
+
+ //clear all interrupt flags
+ wdt->flags = WDT_FLAGS_CLEAR_ALL;
+
+ //wait for all interrupts to clear
+ while(wdt->flags != 0) {
+ wdt->flags = WDT_FLAGS_CLEAR_ALL;
+ }
+
+ return;
+}
+
+/* ************************************************************************* */
+int WDT_Stop(mxc_wdt_regs_t *wdt, uint8_t unlock_key)
+{
+ //unlock ctrl to be writable
+ wdt->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (wdt->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disabled the timer and interrupts
+ wdt->enable = 0;
+ wdt->ctrl &= ~(MXC_F_WDT_CTRL_EN_TIMER);
+
+ //lock ctrl to read-only
+ wdt->lock_ctrl = MXC_V_WDT_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+/**@} end of ingroup wdt */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,254 @@
+/**
+ * @file
+ * @brief This is the high level API for the watchdog timer interface module
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24677 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _WDT_H
+#define _WDT_H
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "wdt_regs.h"
+#include "mxc_assert.h"
+#include "mxc_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @ingroup periphlibs
+ * @defgroup wdttimers Watch Dog Timers
+ * @brief Watch Dog Timer High Level APIs.
+ */
+/**
+ * @ingroup wdttimers
+ * @defgroup wdt0 Watch Dog Timer 0/1
+ * @brief WDT0/WDT1 configuration and control API.
+ * @{
+ */
+
+/**
+ * Definition used for clearing all of the WDT instances flags for Timeout, Pre-Window and Reset Out.
+ */
+#define WDT_FLAGS_CLEAR_ALL (MXC_F_WDT_FLAGS_TIMEOUT| MXC_F_WDT_FLAGS_PRE_WIN | MXC_F_WDT_FLAGS_RESET_OUT)
+/**
+ * Enumeration type to define the Watchdog Timer's Period
+ */
+typedef enum {
+ WDT_PERIOD_2_31_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS, /**< \f$ 2^{31} \f$ WDT clocks. */
+ WDT_PERIOD_2_30_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS, /**< \f$ 2^{30} \f$ WDT clocks. */
+ WDT_PERIOD_2_29_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS, /**< \f$ 2^{29} \f$ WDT clocks. */
+ WDT_PERIOD_2_28_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS, /**< \f$ 2^{28} \f$ WDT clocks. */
+ WDT_PERIOD_2_27_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS, /**< \f$ 2^{27} \f$ WDT clocks. */
+ WDT_PERIOD_2_26_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS, /**< \f$ 2^{26} \f$ WDT clocks. */
+ WDT_PERIOD_2_25_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS, /**< \f$ 2^{25} \f$ WDT clocks. */
+ WDT_PERIOD_2_24_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS, /**< \f$ 2^{24} \f$ WDT clocks. */
+ WDT_PERIOD_2_23_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS, /**< \f$ 2^{23} \f$ WDT clocks. */
+ WDT_PERIOD_2_22_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS, /**< \f$ 2^{22} \f$ WDT clocks. */
+ WDT_PERIOD_2_21_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS, /**< \f$ 2^{21} \f$ WDT clocks. */
+ WDT_PERIOD_2_20_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS, /**< \f$ 2^{20} \f$ WDT clocks. */
+ WDT_PERIOD_2_19_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS, /**< \f$ 2^{19} \f$ WDT clocks. */
+ WDT_PERIOD_2_18_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS, /**< \f$ 2^{18} \f$ WDT clocks. */
+ WDT_PERIOD_2_17_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS, /**< \f$ 2^{17} \f$ WDT clocks. */
+ WDT_PERIOD_2_16_CLKS = MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS, /**< \f$ 2^{16} \f$ WDT clocks. */
+ WDT_PERIOD_MAX /**< Maximum Period is Max - 1 */
+} wdt_period_t;
+
+/**
+ * @brief Initializes system level clocks and sets watchdog in a known disabled state
+ * @note The clk_scale in cfg is only used if the system clock is selected for clk.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param cfg Watchdog system configuration, see sys_cfg_wdt_t.
+ * @param unlock_key Watchdog unlock key
+ *
+ * @retval #E_NO_ERROR Watchdog Timer initialized as requested
+ * @retval #E_NULL_PTR NULL pointer for Watchdog Timer Instance or Configuration parameters.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg, uint8_t unlock_key);
+
+/**
+ * @brief Configures and enables the interrupt timeout for the watchdog specified.
+ *
+ * @param wdt Watchdog module to operate on
+ * @param int_period Interrupt period as defined by wdt_period_t.
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Interrupt enabled
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_EnableInt(mxc_wdt_regs_t *wdt, wdt_period_t int_period, uint8_t unlock_key);
+
+/**
+ * @brief Disables the interrupt timeout for the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Interrupt disabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_DisableInt(mxc_wdt_regs_t *wdt, uint8_t unlock_key);
+
+/**
+ * @brief Configures and enables the pre-window timeout for the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param wait_period Pre-window period, see wdt_period_t for accepted values.
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Pre-window timeout set to wait_period
+ * @retval #E_BAD_STATE WDT unable to be unlocked
+ * @retval #E_INVALID Requested Period is greater than the maximum supported
+ */
+int WDT_EnableWait(mxc_wdt_regs_t *wdt, wdt_period_t wait_period, uint8_t unlock_key);
+
+/**
+ * @brief Disables the pre-window timeout for the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Wait disabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_DisableWait(mxc_wdt_regs_t *wdt, uint8_t unlock_key);
+
+/**
+ * @brief Configures and enables the reset timeout for the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param rst_period Reset period, see wdt_period_t for accepted values.
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Watchdog Timer Reset enabled with the rst_period time.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ * @retval #E_INVALID Requested Period is greater than the maximum supported
+ */
+int WDT_EnableReset(mxc_wdt_regs_t *wdt, wdt_period_t rst_period, uint8_t unlock_key);
+
+/**
+ * @brief Disables the reset timeout for the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param unlock_key Key to unlock watchdog. See #MXC_V_WDT_UNLOCK_KEY.
+ *
+ * @retval #E_NO_ERROR Reset disabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_DisableReset(mxc_wdt_regs_t *wdt, uint8_t unlock_key);
+
+/**
+ * @brief Gets the watchdog interrupt flags
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance.
+ *
+ * @retval uint32_t Value of the Watchdog Timer Flags.
+ *
+ */
+__STATIC_INLINE uint32_t WDT_GetFlags(mxc_wdt_regs_t *wdt)
+{
+ return (wdt->flags);
+}
+
+/**
+ * @brief Clears the watchdog interrupt flags based on the mask
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param mask Watchdog Flags to clear
+ *
+ */
+__STATIC_INLINE void WDT_ClearFlags(mxc_wdt_regs_t *wdt, uint32_t mask)
+{
+ wdt->flags = mask;
+}
+
+/**
+ * @brief Starts the specified Watchdog Timer instance.
+ *
+ * @param wdt Pointer to the Watchdog Timer instance
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR Interrupt enabled.
+ * @retval #E_BAD_STATE WDT1 Already Running
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ *
+ */
+int WDT_Start(mxc_wdt_regs_t *wdt, uint8_t unlock_key);
+
+/**
+ * @brief Feeds the watchdog specified.
+ *
+ * @param wdt Watchdog module to operate on
+ *
+ */
+void WDT_Reset(mxc_wdt_regs_t *wdt);
+
+/**
+ * @brief Stops the watchdog specified.
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR Interrupt enabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT failed to unlock.
+ */
+int WDT_Stop(mxc_wdt_regs_t *wdt, uint8_t unlock_key);
+
+/**
+ * @brief Determines if the watchdog is running
+ *
+ * @param wdt Pointer to the Watchdog Timer Instance
+ *
+ * @retval 0 Watchdog timer is Disabled.
+ * @retval non-zero Watchdog timer is Active
+ */
+__STATIC_INLINE int WDT_IsActive(mxc_wdt_regs_t *wdt)
+{
+ return (!!(wdt->ctrl & MXC_F_WDT_CTRL_EN_TIMER));
+}
+
+/**@} end of group wdt*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,275 @@
+/**
+ * @file
+ * @brief Watchdog Timer 2 Function Implementations.
+ */
+/* *****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-09-08 17:06:34 -0500 (Thu, 08 Sep 2016) $
+ * $Revision: 24320 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include <stddef.h>
+#include "wdt2.h"
+#include "pwrseq_regs.h"
+
+/**
+ * @ingroup wdt2
+ * @{
+ */
+static uint32_t interruptEnable = 0; //keeps track to interrupts to enable in start function
+
+/* ************************************************************************* */
+int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key)
+{
+ //enable nanoring in run and sleep mode
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN);
+
+ //unlock ctrl to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable all interrupts
+ interruptEnable = 0;
+ MXC_WDT2->enable = interruptEnable;
+
+ //enable the watchdog clock and clear all other settings
+ MXC_WDT2->ctrl = (MXC_F_WDT2_CTRL_EN_CLOCK);
+
+ //clear all interrupt flags
+ MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
+
+ if(runInSleep) {
+ // turn on nanoring during sleep
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
+ //turn on timer during sleep
+ MXC_WDT2->ctrl |= MXC_F_WDT2_CTRL_EN_TIMER_SLP;
+ } else {
+ // turn off nanoring during sleep
+ MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_NREN_SLP);
+ //turn off timer during sleep
+ MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER_SLP);
+ }
+
+ //lock ctrl to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key)
+{
+ // Make sure interrupt period is valid
+ if (int_period >= WDT2_PERIOD_MAX)
+ return E_INVALID;
+
+ //unlock ctrl to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //stop timer and clear interval period
+ MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_INT_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
+
+ //set interval period
+ MXC_WDT2->ctrl |= (int_period << MXC_F_WDT2_CTRL_INT_PERIOD_POS);
+
+ //enable timeout wake-up
+ interruptEnable |= MXC_F_WDT2_ENABLE_TIMEOUT;
+
+ //lock ctrl to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ // Enable wake-up
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT2_DisableWakeUp(uint8_t unlock_key)
+{
+ //unlock register to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable timeout wake-up
+ interruptEnable &= ~MXC_F_WDT2_ENABLE_TIMEOUT;
+ MXC_WDT2->enable = interruptEnable;
+
+ //lock register to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ // disable wake-up
+ MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key)
+{
+ // Make sure reset period is valid
+ if (rst_period >= WDT2_PERIOD_MAX)
+ return E_INVALID;
+
+ //unlock ctrl to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //stop timer and clear reset period
+ MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_RST_PERIOD | MXC_F_WDT2_CTRL_EN_TIMER);
+
+ //set reset period
+ MXC_WDT2->ctrl |= (rst_period << MXC_F_WDT2_CTRL_RST_PERIOD_POS);
+
+ //int flag has to be clear before interrupt enable can be written
+ MXC_WDT2->flags = MXC_F_WDT2_FLAGS_RESET_OUT;
+
+ //enable reset0
+ interruptEnable |= MXC_F_WDT2_ENABLE_RESET_OUT;
+
+ //lock ctrl to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ //enable RSTN on WDT2 reset
+ MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT2_DisableReset(uint8_t unlock_key)
+{
+ //unlock register to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disable reset
+ interruptEnable &= ~MXC_F_WDT2_ENABLE_RESET_OUT;
+ MXC_WDT2->enable = interruptEnable;
+
+ //lock register to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ //disable RSTN on WDT2 reset
+ MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+int WDT2_Start(uint8_t unlock_key)
+{
+ //check if watchdog is already running
+ if(WDT2_IsActive())
+ return E_BAD_STATE;
+
+ //unlock ctrl to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ WDT2_Reset();
+
+ //enable interrupts
+ MXC_WDT2->enable = interruptEnable;
+
+ //start timer
+ MXC_WDT2->ctrl |= (MXC_F_WDT2_CTRL_EN_TIMER);
+
+ //lock ctrl to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+
+/* ************************************************************************* */
+void WDT2_Reset(void)
+{
+ //reset the watchdog counter
+ MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_0;
+ MXC_WDT2->clear = MXC_V_WDT2_RESET_KEY_1;
+
+ //clear all interrupt flags
+ MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
+
+ //wait for all interrupts to clear
+ while(MXC_WDT2->flags != 0) {
+ MXC_WDT2->flags = WDT2_FLAGS_CLEAR_ALL;
+ }
+
+ return;
+}
+
+/* ************************************************************************* */
+int WDT2_Stop(uint8_t unlock_key)
+{
+ //check if watchdog is not running
+ if(!WDT2_IsActive())
+ return E_BAD_STATE;
+
+ //unlock ctrl to be writable
+ MXC_WDT2->lock_ctrl = unlock_key;
+
+ //check to make sure it unlocked
+ if (MXC_WDT2->lock_ctrl & 0x01)
+ return E_BAD_STATE;
+
+ //disabled the timer and interrupts
+ MXC_WDT2->enable = 0;
+ MXC_WDT2->ctrl &= ~(MXC_F_WDT2_CTRL_EN_TIMER);
+
+ //lock ctrl to read-only
+ MXC_WDT2->lock_ctrl = MXC_V_WDT2_LOCK_KEY;
+
+ return E_NO_ERROR;
+}
+/**@} end of group wdt2*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/wdt2.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,218 @@
+/**
+ * @file
+ * @brief WDT2 peripheral module API.
+ */
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2016-10-10 19:54:34 -0500 (Mon, 10 Oct 2016) $
+ * $Revision: 24678 $
+ *
+ **************************************************************************** */
+
+/* Define to prevent redundant inclusion */
+#ifndef _WDT2_H
+#define _WDT2_H
+
+/* **** Includes **** */
+#include "mxc_config.h"
+#include "wdt2_regs.h"
+#include "mxc_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @ingroup wdttimers
+ * @defgroup wdt2 Watch Dog Timer 2
+ * @brief WDT2 configuration and control API.
+ * @{
+ */
+
+/**
+ * @def Definition to clear all WDT2 flags
+ */
+#define WDT2_FLAGS_CLEAR_ALL (MXC_F_WDT2_FLAGS_TIMEOUT | MXC_F_WDT2_FLAGS_RESET_OUT)
+/**
+ * Enumeration type to select the Watchdog Timer's Period
+ */
+typedef enum {
+ WDT2_PERIOD_2_25_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS, /**< \f$ 2^{25}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_24_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS, /**< \f$ 2^{24}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_23_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS, /**< \f$ 2^{23}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_22_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS, /**< \f$ 2^{22}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_21_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS, /**< \f$ 2^{21}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_20_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS, /**< \f$ 2^{20}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_19_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS, /**< \f$ 2^{19}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_18_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS, /**< \f$ 2^{18}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_17_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS, /**< \f$ 2^{17}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_16_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS, /**< \f$ 2^{16}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_15_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS, /**< \f$ 2^{15}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_14_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS, /**< \f$ 2^{14}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_13_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS, /**< \f$ 2^{13}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_12_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS, /**< \f$ 2^{12}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_11_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS, /**< \f$ 2^{11}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_2_10_CLKS = MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS, /**< \f$ 2^{10}\f$ Nano Ring clocks. */
+ WDT2_PERIOD_MAX /**< Maximum Period is Max - 1 */
+} wdt2_period_t;
+
+
+/**
+ * @brief Initializes the NanoRing for the watchdog clock and sets watchdog
+ * in a known disabled state
+ * @param runInSleep If non-zero, the WDT2 operates in Sleep Modes for
+ * the device, 0 disables the WDT2 during Sleep Modes.
+ * @param unlock_key The WDT2 unlock key value, use
+ * #MXC_V_WDT2_UNLOCK_KEY
+ *
+ * @retval #E_NO_ERROR Watchdog Timer initialized as requested
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_Init(uint8_t runInSleep, uint8_t unlock_key);
+
+/**
+ * @brief Configures and enables the wake-up timeout for the watchdog
+ * specified.
+ *
+ * @param int_period Interrupt period.
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR WDT2 Interrupt period enabled with the int_period
+ * time.
+ * @retval #E_INVALID Requested Period is greater than the maximum
+ * supported
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_EnableWakeUp(wdt2_period_t int_period, uint8_t unlock_key);
+
+/**
+ * @brief Disables the interrupt timeout for the watchdog specified.
+ *
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR Wakeup disabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_DisableWakeUp(uint8_t unlock_key);
+
+/**
+ * @brief Configures and enables the reset timeout for the watchdog
+ * specified.
+ *
+ * @param rst_period Reset period.
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR Reset timeout enabled with the rst_period time.
+ * @retval #E_INVALID Requested Period is greater than the maximum
+ * supported
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_EnableReset(wdt2_period_t rst_period, uint8_t unlock_key);
+
+/**
+ * @brief Disables the reset timeout for the watchdog specified.
+ *
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR Reset disabled.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_DisableReset(uint8_t unlock_key);
+
+/**
+ * @brief Gets the watchdog flags
+ *
+ * @retval 0 No flags set.
+ * @retval non-zero The WDT2 interrupt flags that are
+ * set, see @ref WDT2_FLAGS_Register "WDT2_FLAGS
+ * register".
+ */
+__STATIC_INLINE uint32_t WDT2_GetFlags(void)
+{
+ return (MXC_WDT2->flags);
+}
+
+/**
+ * @brief Clears the watchdog flags based on the @p mask.
+ *
+ * @param mask bits to clear
+ */
+__STATIC_INLINE void WDT2_ClearFlags(uint32_t mask)
+{
+ MXC_WDT2->flags = mask;
+}
+
+/**
+ * @brief Starts the watchdog specified.
+ *
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR WDT2 started.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_Start(uint8_t unlock_key);
+
+/**
+ * @brief Feeds the watchdog specified.
+ *
+ * @retval #E_NO_ERROR WDT2 reset successfully.
+ */
+void WDT2_Reset(void);
+
+/**
+ * @brief Stops the WatchDog Timer 2.
+ *
+ * @param unlock_key Key to unlock watchdog.
+ *
+ * @retval #E_NO_ERROR WDT2 stopped.
+ * @retval #E_BAD_STATE Invalid unlock_key, WDT2 failed to unlock.
+ */
+int WDT2_Stop(uint8_t unlock_key);
+
+/**
+ * @brief Determines if the watchdog is running
+ *
+ * @retval 0 Inactive
+ * @retval non-zero Active
+ */
+__STATIC_INLINE int WDT2_IsActive(void)
+{
+ return (!!(MXC_WDT2->ctrl & MXC_F_WDT2_CTRL_EN_TIMER));
+}
+
+/**@} end of group wdt2*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WDT_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,116 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "gpio_regs.h"
+#include "uart_regs.h"
+#include "i2cm_regs.h"
+#include "spim_regs.h"
+#include "pt_regs.h"
+#include "adc_regs.h"
+#include "uart.h"
+#include "adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct port_s {
+ PortName port;
+ uint32_t mask;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PinMode mode;
+};
+
+struct gpio_irq_s {
+ uint8_t port;
+ uint8_t pin;
+ uint8_t rise_en;
+ uint8_t fall_en;
+ uint32_t id;
+};
+
+struct serial_s {
+ int index;
+ mxc_uart_regs_t *uart;
+ mxc_uart_fifo_regs_t *fifo;
+ uint32_t id;
+ uart_cfg_t cfg;
+ sys_cfg_uart_t sys_cfg;
+ PinName tx;
+ PinName rx;
+};
+
+struct i2c_s {
+ mxc_i2cm_regs_t *i2c;
+ mxc_i2cm_fifo_regs_t *fifo;
+ int start_pending;
+ sys_cfg_i2cm_t sys_cfg;
+};
+
+struct spi_s {
+ int index;
+ mxc_spim_regs_t *spi;
+};
+
+struct pwmout_s {
+ mxc_pt_regs_t *pwm;
+ int period;
+ int pulse_width;
+};
+
+struct analogin_s {
+ mxc_adc_regs_t *adc;
+ mxc_adc_chsel_t channel;
+};
+
+typedef struct {
+ volatile uint32_t *reg_req;
+ volatile uint32_t *reg_ack;
+ uint32_t req_val;
+ uint32_t ack_mask;
+} pin_function_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/pinmap.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,81 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "objects.h"
+#include "gpio_regs.h"
+
+void pin_function(PinName name, int function)
+{
+ MBED_ASSERT(name != (PinName)NC);
+
+ if ((function >= 0) && (function <= 0xF)) {
+ unsigned int port = PINNAME_TO_PORT(name);
+ unsigned int pin = PINNAME_TO_PIN(name);
+ uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4));
+ MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4));
+ } else {
+ /* Assume this is a pointer to a pin function object */
+ pin_function_t *obj = (pin_function_t*)function;
+
+ if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) {
+ /* Request pin mapping */
+ *obj->reg_req |= obj->req_val;
+
+ /* Check for acknowledgment */
+ MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val);
+ }
+ }
+}
+
+void pin_mode(PinName name, PinMode mode)
+{
+ MBED_ASSERT(name != (PinName)NC);
+ unsigned int port = PINNAME_TO_PORT(name);
+ unsigned int pin = PINNAME_TO_PIN(name);
+
+ /* Must set mode while retaining direction */
+
+ /* Get the current direction */
+ uint32_t curr_mode = (MXC_GPIO->out_mode[port] >> (pin * 4)) & 0xF;
+ PinDirection direction = PIN_OUTPUT;
+ if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) ||
+ (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN) ||
+ (curr_mode == MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z)) {
+ direction = PIN_INPUT;
+ }
+
+ /* Set mode based on current direction */
+ pin_dir_mode(name, direction, mode);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/port_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,98 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "gpio_regs.h"
+#include "clkman_regs.h"
+
+PinName port_pin(PortName port, int pin_n)
+{
+ return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection direction)
+{
+ obj->port = port;
+ obj->mask = mask;
+ obj->reg_out = &MXC_GPIO->out_val[port];
+ obj->reg_in = &MXC_GPIO->in_val[port];
+ obj->mode = PullDefault;
+
+ /* Ensure that the GPIO clock is enabled */
+ MXC_CLKMAN->sys_clk_ctrl_6_gpio = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+
+ uint32_t i;
+ // The function is set per pin: reuse gpio logic
+ for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) {
+ if (obj->mask & (1 << i)) {
+ gpio_set(port_pin(obj->port, i));
+ pin_dir_mode(port_pin(obj->port, i), direction, obj->mode);
+ }
+ }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+ uint32_t i;
+ obj->mode = mode;
+ // The mode is set per pin: reuse pinmap logic
+ for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) {
+ if (obj->mask & (1 << i)) {
+ pin_mode(port_pin(obj->port, i), mode);
+ }
+ }
+}
+
+void port_dir(port_t *obj, PinDirection direction)
+{
+ uint32_t i;
+ // The mode is set per pin: reuse gpio logic
+ for (i = 0; i < MXC_GPIO_MAX_PINS_PER_PORT; i++) {
+ if (obj->mask & (1 << i)) {
+ pin_dir_mode(port_pin(obj->port, i), direction, obj->mode);
+ }
+ }
+}
+
+void port_write(port_t *obj, int value)
+{
+ *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+ return (*obj->reg_in & obj->mask);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/pwmout_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,221 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "pwmout_api.h"
+#include "pinmap.h"
+#include "clkman_regs.h"
+#include "PeripheralPins.h"
+
+#define MXC_GPIO_OUT_MODE_FIELD_WIDTH 4
+#define MXC_GPIO_OUT_MODE_FIELD_MASK ((uint32_t)0xFFFFFFFF >> (32 - MXC_GPIO_OUT_MODE_FIELD_WIDTH))
+#define MXC_GPIO_FUNC_SEL_FIELD_WIDTH 4
+#define MXC_GPIO_FUNC_SEL_FIELD_MASK ((uint32_t)0xFFFFFFFF >> (32 - MXC_GPIO_FUNC_SEL_FIELD_WIDTH))
+
+
+//******************************************************************************
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+ // Make sure the pin is free for GPIO use
+ unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+ unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT);
+ MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin));
+
+ int i = 0;
+ PinMap pwm = PinMap_PWM[0];
+
+ // Check if there is a pulse train already active on this port
+ int pin_func = (MXC_GPIO->func_sel[port] & (MXC_GPIO_FUNC_SEL_FIELD_MASK << (port_pin * MXC_GPIO_FUNC_SEL_FIELD_WIDTH))) >>
+ (port_pin * MXC_GPIO_FUNC_SEL_FIELD_WIDTH);
+ MBED_ASSERT((pin_func < 1) || (pin_func > 3));
+
+ // Search through PinMap_PWM to find the pin
+ while (pwm.pin != pin) {
+ pwm = PinMap_PWM[++i];
+ }
+
+ // Find a free PT instance on this pin
+ while (pwm.pin == pin) {
+
+ // Check to see if this PT instance is free
+ if (((mxc_pt_regs_t*)pwm.peripheral)->rate_length & MXC_F_PT_RATE_LENGTH_MODE) {
+ break;
+ }
+
+ pwm = PinMap_PWM[++i];
+
+ // Raise an assertion if we can not allocate another PT instance.
+ MBED_ASSERT(pwm.pin == pin);
+ }
+
+ // Enable the clock
+ MXC_CLKMAN->sys_clk_ctrl_7_pt = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
+
+ // Set the obj pointer to the propper PWM instance
+ obj->pwm = (mxc_pt_regs_t*)pwm.peripheral;
+
+ // Initialize object period and pulse width
+ obj->period = -1;
+ obj->pulse_width = -1;
+
+ // Disable the output
+ obj->pwm->train = 0x0;
+ obj->pwm->rate_length = 0x0;
+
+ // Configure the pin
+ pin_mode(pin, (PinMode)PullNone);
+ pin_function(pin, pwm.function);
+
+ // default to 20ms: standard for servos, and fine for e.g. brightness control
+ pwmout_period_us(obj, 20000);
+ pwmout_write (obj, 0);
+
+ // Set the drive mode to normal
+ MXC_SET_FIELD(&MXC_GPIO->out_mode[port],
+ (MXC_GPIO_OUT_MODE_FIELD_MASK << (port_pin * MXC_GPIO_OUT_MODE_FIELD_WIDTH)),
+ (MXC_V_GPIO_OUT_MODE_NORMAL << (port_pin * MXC_GPIO_OUT_MODE_FIELD_WIDTH)));
+
+ // Enable this PWM channel
+ MXC_PTG->enable |= (1 << MXC_PT_GET_IDX(obj->pwm));
+}
+
+//******************************************************************************
+void pwmout_free(pwmout_t* obj)
+{
+ // Set the registers to the reset value
+ obj->pwm->train = 0;
+ obj->pwm->rate_length = 0x08000000;
+}
+
+//******************************************************************************
+static void pwmout_update(pwmout_t* obj)
+{
+ // Calculate and set the divider ratio
+ int div = (obj->period * (SystemCoreClock / 1000000))/32;
+ if (div < 2) {
+ div = 2;
+ }
+ MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div);
+
+ // Change the duty cycle to adjust the pulse width
+ obj->pwm->train = (0xFFFFFFFF << (32 - ((32 * obj->pulse_width) / obj->period)));
+}
+
+
+//******************************************************************************
+void pwmout_write(pwmout_t* obj, float percent)
+{
+ // Saturate percent if outside of range
+ if(percent < 0.0f) {
+ percent = 0.0f;
+ } else if(percent > 1.0f) {
+ percent = 1.0f;
+ }
+
+ // Resize the pulse width to set the duty cycle
+ pwmout_pulsewidth_us(obj, (int)(percent*obj->period));
+}
+
+//******************************************************************************
+float pwmout_read(pwmout_t* obj)
+{
+ // Check for when pulsewidth or period equals 0
+ if((obj->pulse_width == 0) || (obj->period == 0)) {
+ return 0;
+ }
+
+ // Return the duty cycle
+ return ((float)obj->pulse_width / (float)obj->period);
+}
+
+//******************************************************************************
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+ pwmout_period_us(obj, (int)(seconds * 1000000.0f));
+}
+
+//******************************************************************************
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+ pwmout_period_us(obj, ms * 1000);
+}
+
+//******************************************************************************
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+ // Check the range of the period
+ MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32)));
+
+ // Set pulse width to half the period if uninitialized
+ if (obj->pulse_width == -1) {
+ obj->pulse_width = us / 2;
+ }
+
+ // Save the period
+ obj->period = us;
+
+ // Update the registers
+ pwmout_update(obj);
+}
+
+//******************************************************************************
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+ pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0f));
+}
+
+//******************************************************************************
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+ pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+//******************************************************************************
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+ // Check the range of the pulsewidth
+ MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock / 32)));
+
+ // Initialize period to double the pulsewidth if uninitialized
+ if (obj->period == -1) {
+ obj->period = 2 * us;
+ }
+
+ // Save the pulsewidth
+ obj->pulse_width = us;
+
+ // Update the register
+ pwmout_update(obj);
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,253 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "rtc_api.h"
+#include "lp_ticker_api.h"
+#include "rtc.h"
+#include "lp.h"
+
+#define PRESCALE_VAL RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
+#define SHIFT_AMT (RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
+
+#define WINDOW 1000
+
+static int rtc_inited = 0;
+static volatile uint32_t overflow_cnt = 0;
+
+static uint64_t rtc_read64(void);
+
+//******************************************************************************
+static void overflow_handler(void)
+{
+ overflow_cnt++;
+ RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
+}
+
+//******************************************************************************
+void rtc_init(void)
+{
+ if (rtc_inited) {
+ return;
+ }
+ rtc_inited = 1;
+
+ overflow_cnt = 0;
+
+ /* Enable power for RTC for all LPx states */
+ MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN |
+ MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
+
+ /* Enable clock to synchronizers */
+ CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1);
+
+ // Prepare interrupt handlers
+ NVIC_SetVector(RTC0_IRQn, lp_ticker_irq_handler);
+ NVIC_EnableIRQ(RTC0_IRQn);
+ NVIC_SetVector(RTC3_IRQn, overflow_handler);
+ NVIC_EnableIRQ(RTC3_IRQn);
+
+ // Enable wakeup on RTC rollover
+ LP_ConfigRTCWakeUp(0, 0, 0, 1);
+
+ /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
+ * if it is already running.
+ */
+ if (!RTC_IsActive()) {
+ rtc_cfg_t cfg = {0};
+ cfg.prescaler = PRESCALE_VAL;
+ cfg.snoozeMode = RTC_SNOOZE_DISABLE;
+
+ int retval = RTC_Init(&cfg);
+ MBED_ASSERT(retval == E_NO_ERROR);
+
+ RTC_EnableINT(MXC_F_RTC_FLAGS_OVERFLOW);
+ RTC_Start();
+ }
+}
+
+//******************************************************************************
+void lp_ticker_init(void)
+{
+ rtc_init();
+}
+
+//******************************************************************************
+void rtc_free(void)
+{
+ if (RTC_IsActive()) {
+ // Clear and disable RTC
+ MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
+ RTC_Stop();
+ }
+}
+
+//******************************************************************************
+int rtc_isenabled(void)
+{
+ return RTC_IsActive();
+}
+
+//******************************************************************************
+time_t rtc_read(void)
+{
+ uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
+ uint32_t ovf1, ovf2;
+
+ // Make sure RTC is setup before trying to read
+ if (!rtc_inited) {
+ rtc_init();
+ }
+
+ // Ensure coherency between overflow_cnt and timer
+ do {
+ ovf_cnt_1 = overflow_cnt;
+ ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
+ timer_cnt = RTC_GetCount();
+ ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
+ ovf_cnt_2 = overflow_cnt;
+ } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
+
+ // Account for an unserviced interrupt
+ if (ovf1) {
+ ovf_cnt_1++;
+ }
+
+ return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
+}
+
+//******************************************************************************
+static uint64_t rtc_read64(void)
+{
+ uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
+ uint32_t ovf1, ovf2;
+ uint64_t current_us;
+
+ // Make sure RTC is setup before trying to read
+ if (!rtc_inited) {
+ rtc_init();
+ }
+
+ // Ensure coherency between overflow_cnt and timer
+ do {
+ ovf_cnt_1 = overflow_cnt;
+ ovf1 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
+ timer_cnt = RTC_GetCount();
+ ovf2 = RTC_GetFlags() & MXC_F_RTC_FLAGS_OVERFLOW;
+ ovf_cnt_2 = overflow_cnt;
+ } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
+
+ // Account for an unserviced interrupt
+ if (ovf1) {
+ ovf_cnt_1++;
+ }
+
+ current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
+
+ return current_us;
+}
+
+//******************************************************************************
+void rtc_write(time_t t)
+{
+ // Make sure RTC is setup before accessing
+ if (!rtc_inited) {
+ rtc_init();
+ }
+
+ RTC_Stop();
+ RTC_SetCount(t << SHIFT_AMT);
+ overflow_cnt = t >> (32 - SHIFT_AMT);
+ RTC_Start();
+}
+
+//******************************************************************************
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+ uint32_t comp_value;
+ uint64_t curr_ts64;
+ uint64_t ts64;
+
+ // Note: interrupts are disabled before this function is called.
+
+ // Disable the alarm while it is prepared
+ RTC_DisableINT(MXC_F_RTC_INTEN_COMP0);
+
+ curr_ts64 = rtc_read64();
+ ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
+
+ // If this event is older than a recent window, it must be in the future
+ if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
+ ts64 += 0x100000000ULL;
+ }
+
+ uint32_t timer = RTC_GetCount();
+ if (ts64 <= curr_ts64) {
+ // This event has already occurred. Set the alarm to expire immediately.
+ comp_value = timer + 1;
+ } else {
+ comp_value = (ts64 << SHIFT_AMT) / 1000000;
+ }
+
+ // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
+ if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
+ comp_value = timer + 2;
+ }
+
+ MXC_RTCTMR->comp[0] = comp_value;
+ MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
+ RTC_EnableINT(MXC_F_RTC_INTEN_COMP0);
+
+ // Enable wakeup from RTC
+ LP_ConfigRTCWakeUp(1, 0, 0, 1);
+
+ // Wait for pending transactions
+ while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+}
+
+//******************************************************************************
+inline void lp_ticker_disable_interrupt(void)
+{
+ RTC_DisableINT(MXC_F_RTC_INTEN_COMP0);
+}
+
+//******************************************************************************
+inline void lp_ticker_clear_interrupt(void)
+{
+ RTC_ClearFlags(MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS);
+}
+
+//******************************************************************************
+inline uint32_t lp_ticker_read(void)
+{
+ return rtc_read64();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,381 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <string.h>
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "serial_api.h"
+#include "gpio_api.h"
+#include "uart.h"
+#include "uart_regs.h"
+#include "ioman_regs.h"
+#include "PeripheralPins.h"
+
+#define DEFAULT_BAUD 9600
+
+#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAMING_ERR | \
+ MXC_F_UART_INTFL_RX_PARITY_ERR | \
+ MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
+
+// Variables for managing the stdio UART
+int stdio_uart_inited = 0;
+serial_t stdio_uart = {0};
+
+// Variables for interrupt driven
+static uart_irq_handler irq_handler;
+static serial_t *objs[MXC_CFG_UART_INSTANCES];
+
+static void usurp_pin(PinName, int);
+
+//******************************************************************************
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+ // Determine which uart is associated with each pin
+ UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+ UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+ UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+
+ // Make sure that both pins are pointing to the same uart
+ MBED_ASSERT(uart != (UARTName)NC);
+
+ // Set the obj pointer to the proper uart
+ obj->uart = (mxc_uart_regs_t*)uart;
+
+ // Set the uart index
+ obj->index = MXC_UART_GET_IDX(obj->uart);
+ obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
+
+ // Record the pins requested
+ obj->tx = tx;
+ obj->rx = rx;
+
+ // Merge pin function requests for use with CMSIS init func
+ ioman_req_t io_req = {0};
+ pin_function_t *pin_func = NULL;
+ if (tx != NC) {
+ pin_func = (pin_function_t *)pinmap_find_function(tx, PinMap_UART_TX);
+ io_req.value = pin_func->req_val;
+ }
+ if (rx != NC) {
+ pin_func = (pin_function_t *)pinmap_find_function(rx, PinMap_UART_RX);
+ io_req.value |= pin_func->req_val;
+ }
+
+ // Using req and ack pointers of last pin function lookup
+ obj->sys_cfg.io_cfg.req_reg = pin_func->reg_req;
+ obj->sys_cfg.io_cfg.ack_reg = pin_func->reg_ack;
+ obj->sys_cfg.io_cfg.req_val = io_req;
+ obj->sys_cfg.clk_scale = CLKMAN_SCALE_DIV_8;
+
+ // Configure the UART with default parameters
+ obj->cfg.extra_stop = 0;
+ obj->cfg.cts = 0;
+ obj->cfg.rts = 0;
+ obj->cfg.baud = DEFAULT_BAUD;
+ obj->cfg.size = UART_DATA_SIZE_8_BITS;
+ obj->cfg.parity = UART_PARITY_DISABLE;
+
+ // Manage stdio UART
+ if (uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ stdio_uart = *obj;
+ }
+
+ int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg);
+ MBED_ASSERT(retval == E_NO_ERROR);
+}
+
+//******************************************************************************
+void serial_baud(serial_t *obj, int baudrate)
+{
+ obj->cfg.baud = baudrate;
+ int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg);
+ MBED_ASSERT(retval == E_NO_ERROR);
+}
+
+//******************************************************************************
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+ switch (data_bits) {
+ case 5:
+ obj->cfg.size = UART_DATA_SIZE_5_BITS;
+ break;
+ case 6:
+ obj->cfg.size = UART_DATA_SIZE_6_BITS;
+ break;
+ case 7:
+ obj->cfg.size = UART_DATA_SIZE_7_BITS;
+ break;
+ case 8:
+ obj->cfg.size = UART_DATA_SIZE_8_BITS;
+ break;
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+
+ switch (parity) {
+ case ParityNone:
+ obj->cfg.parity = UART_PARITY_DISABLE;
+ break;
+ case ParityOdd :
+ obj->cfg.parity = UART_PARITY_ODD;
+ break;
+ case ParityEven:
+ obj->cfg.parity = UART_PARITY_EVEN;
+ break;
+ case ParityForced1:
+ case ParityForced0:
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+
+ switch (stop_bits) {
+ case 1:
+ obj->cfg.extra_stop = 0;
+ break;
+ case 2:
+ obj->cfg.extra_stop = 1;
+ break;
+ default:
+ MBED_ASSERT(0);
+ break;
+ }
+
+ int retval = UART_Init(obj->uart, &obj->cfg, NULL);
+ MBED_ASSERT(retval == E_NO_ERROR);
+}
+
+//******************************************************************************
+void uart_handler(serial_t *obj)
+{
+ if (obj && obj->id) {
+ irq_handler(obj->id, RxIrq);
+ }
+}
+
+void uart0_handler(void) { uart_handler(objs[0]); }
+void uart1_handler(void) { uart_handler(objs[1]); }
+void uart2_handler(void) { uart_handler(objs[2]); }
+void uart3_handler(void) { uart_handler(objs[3]); }
+
+//******************************************************************************
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+ irq_handler = handler;
+ obj->id = id;
+}
+
+//******************************************************************************
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+ switch (obj->index) {
+ case 0:
+ NVIC_SetVector(UART0_IRQn, uart0_handler);
+ NVIC_EnableIRQ(UART0_IRQn);
+ break;
+ case 1:
+ NVIC_SetVector(UART1_IRQn, uart1_handler);
+ NVIC_EnableIRQ(UART1_IRQn);
+ break;
+ case 2:
+ NVIC_SetVector(UART2_IRQn, uart2_handler);
+ NVIC_EnableIRQ(UART2_IRQn);
+ break;
+ case 3:
+ NVIC_SetVector(UART3_IRQn, uart3_handler);
+ NVIC_EnableIRQ(UART3_IRQn);
+ break;
+ default:
+ MBED_ASSERT(0);
+ }
+
+ if (irq == RxIrq) {
+ // Enable RX FIFO Threshold Interrupt
+ if (enable) {
+ // Clear pending interrupts
+ obj->uart->intfl = obj->uart->intfl;
+ obj->uart->inten |= (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
+ } else {
+ // Clear pending interrupts
+ obj->uart->intfl = obj->uart->intfl;
+ obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
+ }
+ } else if (irq == TxIrq) {
+ // Set TX Almost Empty level to interrupt when empty
+ MXC_SET_FIELD(&obj->uart->tx_fifo_ctrl, MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL,
+ (MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
+
+ // Enable TX Almost Empty Interrupt
+ if (enable) {
+ // Clear pending interrupts
+ obj->uart->intfl = obj->uart->intfl;
+ obj->uart->inten |= MXC_F_UART_INTFL_TX_FIFO_AE;
+ } else {
+ // Clear pending interrupts
+ obj->uart->intfl = obj->uart->intfl;
+ obj->uart->inten &= ~MXC_F_UART_INTFL_TX_FIFO_AE;
+ }
+ } else {
+ MBED_ASSERT(0);
+ }
+}
+
+//******************************************************************************
+int serial_getc(serial_t *obj)
+{
+ int c = -1;
+
+ if (obj->rx != NC) {
+ // Wait for data to be available
+ while ((obj->uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) == 0);
+
+ c = obj->fifo->rx;
+ }
+
+ return c;
+}
+
+//******************************************************************************
+void serial_putc(serial_t *obj, int c)
+{
+ if (obj->tx != NC) {
+ // Wait for room in the FIFO without blocking interrupts.
+ while (UART_NumWriteAvail(obj->uart) == 0);
+
+ // Must clear before every write to the buffer to know that the FIFO
+ // is empty when the TX DONE bit is set
+ obj->uart->intfl = MXC_F_UART_INTFL_TX_DONE;
+ obj->fifo->tx = (uint8_t)c;
+ }
+}
+
+//******************************************************************************
+int serial_readable(serial_t *obj)
+{
+ return UART_NumReadAvail(obj->uart);
+}
+
+//******************************************************************************
+int serial_writable(serial_t *obj)
+{
+ return UART_NumWriteAvail(obj->uart);
+}
+
+//******************************************************************************
+void serial_clear(serial_t *obj)
+{
+ // Clear the RX and TX FIFOs
+ UART_DrainRX(obj->uart);
+ UART_DrainTX(obj->uart);
+}
+
+//******************************************************************************
+void serial_break_set(serial_t *obj)
+{
+ // Make sure that nothing is being sent
+ while (((obj->uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY)
+ >> MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS) > 0);
+ while (!(obj->uart->intfl & MXC_F_UART_INTFL_TX_DONE));
+
+ // Configure TX to output 0
+ usurp_pin(obj->tx, 0);
+
+ // GPIO is setup now, but we need to unmap UART from the pin
+ pin_function_t *pin_func = (pin_function_t *)pinmap_find_function(obj->tx, PinMap_UART_TX);
+ *pin_func->reg_req &= ~MXC_F_IOMAN_UART_REQ_IO_REQ;
+ MBED_ASSERT((*pin_func->reg_ack & MXC_F_IOMAN_UART_ACK_IO_ACK) == 0);
+}
+
+//******************************************************************************
+void serial_break_clear(serial_t *obj)
+{
+ // Configure TX to output 1
+ usurp_pin(obj->tx, 1);
+ // Return TX to UART control
+ serial_pinout_tx(obj->tx);
+}
+
+//******************************************************************************
+void serial_pinout_tx(PinName tx)
+{
+ pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+//******************************************************************************
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+ pin_function_t rtscts_pin_func = {0};
+
+ obj->cfg.cts = 0;
+ obj->cfg.rts = 0;
+
+ if ((FlowControlCTS == type) || (FlowControlRTSCTS == type)) {
+ UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+ UARTName uart = (UARTName)pinmap_merge(uart_cts, (UARTName)obj->uart);
+ // Assert pin is usable with existing uart
+ MBED_ASSERT(uart != (UARTName)NC);
+
+ pin_function_t *pin_func;
+ pin_func = (pin_function_t *)pinmap_find_function(txflow, PinMap_UART_CTS);
+ rtscts_pin_func.req_val |= pin_func->req_val;
+
+ obj->cfg.cts = 1;
+ }
+
+ if ((FlowControlRTS == type) || (FlowControlRTSCTS == type)) {
+ UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+ UARTName uart = (UARTName)pinmap_merge(uart_rts, (UARTName)obj->uart);
+ MBED_ASSERT(uart != (UARTName)NC);
+
+ pin_function_t *pin_func;
+ pin_func = (pin_function_t *)pinmap_find_function(rxflow, PinMap_UART_RTS);
+ rtscts_pin_func.req_val |= pin_func->req_val;
+
+ obj->cfg.rts = 1;
+ }
+
+ obj->sys_cfg.io_cfg.req_val.value |= rtscts_pin_func.req_val;
+
+ int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg);
+ MBED_ASSERT(retval == E_NO_ERROR);
+}
+
+//******************************************************************************
+static void usurp_pin(PinName pin, int state)
+{
+ gpio_t gpio;
+ gpio_init_out(&gpio, pin);
+ gpio_write(&gpio, state);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/sleep.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "sleep_api.h"
+#include "lp.h"
+
+void sleep(void)
+{
+ LP_EnterLP2();
+}
+
+// Low-power stop mode
+void deepsleep(void)
+{
+ sleep();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/spi_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,181 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "spi_api.h" // mbed HAL
+#include "spim_regs.h" // bare metal
+#include "spim.h" // Maxim CMSIS driver
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+//******************************************************************************
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+ // Make sure pins are pointing to the same SPI instance
+ SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+ SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+ SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+ SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+ SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+ SPIName spi_cntl;
+
+ // Control is SCK and optionaly SS
+ if ((SPIName)spi_ssel != (SPIName)NC) {
+ spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+ } else {
+ spi_cntl = spi_sclk;
+ }
+
+ SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+
+ MBED_ASSERT((SPIName)spi != (SPIName)NC);
+
+ obj->spi = (mxc_spim_regs_t *)spi;
+
+ // Merge pin function requests for use with CMSIS init func
+ ioman_req_t io_req;
+ pin_function_t *pin_func;
+ pin_func = (pin_function_t *)pinmap_find_function(mosi, PinMap_SPI_MOSI);
+ io_req.value = pin_func->req_val;
+ pin_func = (pin_function_t *)pinmap_find_function(miso, PinMap_SPI_MISO);
+ io_req.value |= pin_func->req_val;
+ pin_func = (pin_function_t *)pinmap_find_function(sclk, PinMap_SPI_SCLK);
+ io_req.value |= pin_func->req_val;
+ if ((SPIName)spi_ssel != (SPIName)NC) {
+ pin_func = (pin_function_t *)pinmap_find_function(ssel, PinMap_SPI_SSEL);
+ io_req.value |= pin_func->req_val;
+ }
+
+ // Using req and ack pointers of last pin function lookup
+ sys_cfg_spim_t sys_cfg;
+ sys_cfg.io_cfg.req_reg = pin_func->reg_req;
+ sys_cfg.io_cfg.ack_reg = pin_func->reg_ack;
+ sys_cfg.io_cfg.req_val = io_req;
+ sys_cfg.clk_scale = CLKMAN_SCALE_AUTO;
+
+ // Defaults
+ spim_cfg_t spim_cfg;
+ spim_cfg.mode = 0;
+ spim_cfg.ssel_pol = 0;
+ spim_cfg.baud = 1000000;
+
+ SPIM_Init(obj->spi, &spim_cfg, &sys_cfg);
+
+ obj->index = MXC_SPIM_GET_IDX(obj->spi);
+}
+
+//******************************************************************************
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+ // Check the validity of the inputs
+ MBED_ASSERT(bits == 8);
+
+ // Only supports master mode
+ MBED_ASSERT(!slave);
+
+ // Set the mode
+ obj->spi->mstr_cfg &= ~(MXC_F_SPIM_MSTR_CFG_SPI_MODE);
+ obj->spi->mstr_cfg |= (mode << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS);
+}
+
+//******************************************************************************
+void spi_frequency(spi_t *obj, int hz)
+{
+ // Maximum frequency is half the system frequency
+ MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
+ unsigned clocks = ((SystemCoreClock / 2) / hz);
+
+ // Figure out the divider ratio
+ int clk_div = 1;
+ while(clk_div < 10) {
+ if(clocks < 0x10) {
+ break;
+ }
+ clk_div++;
+ clocks = clocks >> 1;
+ }
+
+ // Turn on the SPI clock
+ if(obj->index == 0) {
+ MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div;
+ } else if(obj->index == 1) {
+ MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div;
+ } else if(obj->index == 2) {
+ MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div;
+ } else {
+ MBED_ASSERT(0);
+ }
+
+ // Set the number of clocks to hold sclk high and low
+ MXC_SET_FIELD(&obj->spi->mstr_cfg,
+ (MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK | MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK),
+ ((clocks << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS)));
+}
+
+//******************************************************************************
+int spi_master_write(spi_t *obj, int value)
+{
+ spim_req_t req;
+ uint8_t out;
+ uint8_t in;
+
+ out = value;
+
+ req.ssel = 0;
+ req.deass = 0;
+ req.tx_data = &out;
+ req.rx_data = ∈
+ req.width = SPIM_WIDTH_1;
+ req.len = 1;
+ req.ssel = 0;
+ req.deass = 1;
+ req.callback = NULL;
+
+ SPIM_Trans(obj->spi, &req);
+
+ return *req.rx_data;
+}
+
+//******************************************************************************
+int spi_busy(spi_t *obj)
+{
+ return SPIM_Busy(obj->spi);
+}
+
+//******************************************************************************
+uint8_t spi_get_module(spi_t *obj)
+{
+ return obj->index;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,257 @@
+/*******************************************************************************
+ * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <stddef.h>
+#include "mbed_error.h"
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "tmr.h"
+
+#define US_TIMER MXC_TMR0
+#define US_TIMER_IRQn TMR0_0_IRQn
+
+static int us_ticker_inited = 0;
+static uint32_t ticks_per_us;
+static uint32_t tick_win;
+static volatile uint64_t current_cnt; // Hold the current ticks
+static volatile uint64_t event_cnt; // Holds the value of the next event
+
+#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us)
+
+//******************************************************************************
+static inline void inc_current_cnt(uint32_t inc)
+{
+ // Overflow the ticker when the us ticker overflows
+ current_cnt += inc;
+ if (current_cnt > MAX_TICK_VAL) {
+ current_cnt -= (MAX_TICK_VAL + 1);
+ }
+}
+
+//******************************************************************************
+static inline int event_passed(uint64_t current, uint64_t event)
+{
+ // Determine if the event has already happened.
+ // If the event is behind the current ticker, within a window,
+ // then the event has already happened.
+ if (((current < tick_win) && ((event < current) ||
+ (event > (MAX_TICK_VAL - (tick_win - current))))) ||
+ ((event < current) && (event > (current - tick_win)))) {
+ return 1;
+ }
+
+ return 0;
+}
+
+//******************************************************************************
+static inline uint64_t event_diff(uint64_t current, uint64_t event)
+{
+ // Check to see if the ticker will overflow before the event
+ if(current <= event) {
+ return (event - current);
+ }
+
+ return ((MAX_TICK_VAL - current) + event);
+}
+
+//******************************************************************************
+static void tmr_handler(void)
+{
+ uint32_t cmp = TMR32_GetCompare(US_TIMER);
+ TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts
+ TMR32_ClearFlag(US_TIMER);
+ NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+
+ inc_current_cnt(cmp);
+
+ if (event_passed(current_cnt + TMR32_GetCount(US_TIMER), event_cnt)) {
+ // the timestamp has expired
+ event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
+ us_ticker_irq_handler();
+ } else {
+ uint64_t diff = event_diff(current_cnt, event_cnt);
+ if (diff < (uint64_t)0xFFFFFFFF) {
+ // the event occurs before the next overflow
+ TMR32_SetCompare(US_TIMER, diff);
+
+ // Since the timer keeps counting after the terminal value is reached, it is possible that the new
+ // terminal value is in the past.
+ if (TMR32_GetCompare(US_TIMER) < TMR32_GetCount(US_TIMER)) {
+ // the timestamp has expired
+ TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts
+ TMR32_ClearFlag(US_TIMER);
+ NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+ event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
+ us_ticker_irq_handler();
+ }
+ }
+ }
+}
+
+//******************************************************************************
+void us_ticker_init(void)
+{
+ if (us_ticker_inited) {
+ return;
+ }
+
+ us_ticker_inited = 1;
+ current_cnt = 0;
+ event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
+ ticks_per_us = SystemCoreClock / 1000000;
+ tick_win = SystemCoreClock / 100; // Set the tick window to 10ms
+
+ int retval = TMR_Init(US_TIMER, TMR_PRESCALE_DIV_2_0, NULL);
+ MBED_ASSERT(retval == E_NO_ERROR);
+
+ tmr32_cfg_t cfg;
+ cfg.mode = TMR32_MODE_CONTINUOUS;
+ cfg.polarity = TMR_POLARITY_UNUSED;
+ cfg.compareCount = 0xFFFFFFFF;
+ TMR32_Config(US_TIMER, &cfg);
+
+ NVIC_SetVector(US_TIMER_IRQn, tmr_handler);
+ NVIC_EnableIRQ(US_TIMER_IRQn);
+ TMR32_EnableINT(US_TIMER);
+
+ TMR32_Start(US_TIMER);
+}
+
+//******************************************************************************
+void us_ticker_deinit(void)
+{
+ TMR32_Stop(US_TIMER);
+ TMR32_DisableINT(US_TIMER);
+ TMR32_ClearFlag(US_TIMER);
+ us_ticker_inited = 0;
+}
+
+//******************************************************************************
+uint32_t us_ticker_read(void)
+{
+ uint64_t current_cnt1, current_cnt2;
+ uint32_t cmp, cnt;
+ uint32_t flag1, flag2;
+
+ if (!us_ticker_inited) {
+ us_ticker_init();
+ }
+
+ // Ensure coherency between current_cnt and TMR32_GetCount()
+ do {
+ current_cnt1 = current_cnt;
+ flag1 = TMR32_GetFlag(US_TIMER);
+ cmp = TMR32_GetCompare(US_TIMER);
+ cnt = TMR32_GetCount(US_TIMER);
+ flag2 = TMR32_GetFlag(US_TIMER);
+ current_cnt2 = current_cnt;
+ } while ((current_cnt1 != current_cnt2) || (flag1 != flag2));
+
+ // Account for an unserviced interrupt
+ if (flag1) {
+ current_cnt1 += cmp;
+ }
+
+ current_cnt1 += cnt;
+
+ return (current_cnt1 / ticks_per_us);
+}
+
+//******************************************************************************
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ // Note: interrupts are disabled before this function is called.
+
+ TMR32_Stop(US_TIMER);
+
+ if (TMR32_GetFlag(US_TIMER)) {
+ TMR32_ClearFlag(US_TIMER);
+ NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+ inc_current_cnt(TMR32_GetCompare(US_TIMER));
+ }
+
+ // add and reset the current count value
+ inc_current_cnt(TMR32_GetCount(US_TIMER));
+ TMR32_SetCount(US_TIMER, 0);
+
+ // add the number of cycles that the timer is disabled here for
+ inc_current_cnt(200);
+
+ event_cnt = (uint64_t)timestamp * ticks_per_us;
+
+ // Check to see if the event has already passed
+ if (!event_passed(current_cnt, event_cnt)) {
+ uint64_t diff = event_diff(current_cnt, event_cnt);
+ if (diff < (uint64_t)0xFFFFFFFF) {
+ // the event occurs before the next overflow
+ TMR32_SetCompare(US_TIMER, diff);
+ } else {
+ // the event occurs after the next overflow
+ TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // set to max
+ }
+ } else {
+ // the requested timestamp occurs in the past
+ // set the timer up to immediately expire
+ TMR32_SetCompare(US_TIMER, 1);
+ }
+
+ TMR32_Start(US_TIMER);
+}
+
+//******************************************************************************
+void us_ticker_disable_interrupt(void)
+{
+ // There are no more events, set timer overflow to the max
+ TMR32_SetCompare(US_TIMER, 0xFFFFFFFF);
+}
+
+//******************************************************************************
+void us_ticker_clear_interrupt(void)
+{
+ // cleared in the local handler
+}
+
+//******************************************************************************
+void us_ticker_set(timestamp_t timestamp)
+{
+ TMR32_Stop(US_TIMER);
+ current_cnt = (uint64_t)timestamp * ticks_per_us;
+ TMR32_SetCount(US_TIMER, 0);
+ TMR32_SetCompare(US_TIMER, 0xFFFFFFFF);
+ TMR32_Start(US_TIMER);
+
+ if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) {
+ // The next timestamp has elapsed. Trigger the interrupt to handle it.
+ NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ }
+}
--- a/targets/TARGET_Maxim/mbed_rtx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_Maxim/mbed_rtx.h Thu Feb 02 17:01:33 2017 +0000 @@ -77,6 +77,21 @@ #define OS_CLOCK 96000000 #endif +#elif defined(TARGET_MAX32630) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20080000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 96000000 +#endif + #endif #endif // MBED_MBED_RTX_H
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 Nordic Semiconductor
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 3
+
+typedef enum {
+ p0 = 0,
+ p1 = 1,
+ p2 = 2,
+ p3 = 3,
+ p4 = 4,
+ p5 = 5,
+ p6 = 6,
+ p7 = 7,
+ p8 = 8,
+ p9 = 9,
+ p10 = 10,
+ p11 = 11,
+ p12 = 12,
+ p13 = 13,
+ p14 = 14,
+ p15 = 15,
+ p16 = 16,
+ p17 = 17,
+ p18 = 18,
+ p19 = 19,
+ p20 = 20,
+ p21 = 21,
+ p22 = 22,
+ p23 = 23,
+ p24 = 24,
+ p25 = 25,
+ p26 = 26,
+ p27 = 27,
+ p28 = 28,
+ p29 = 29,
+ p30 = 30,
+ p31 = 31,
+
+ //NORMAL PINS...
+ P0_0 = p0,
+ P0_1 = p1,
+ P0_2 = p2,
+ P0_3 = p3,
+ P0_4 = p4,
+ P0_5 = p5,
+ P0_6 = p6,
+ P0_7 = p7,
+
+ P0_8 = p8,
+ P0_9 = p9,
+ P0_10 = p10,
+ P0_11 = p11,
+ P0_12 = p12,
+ P0_13 = p13,
+ P0_14 = p14,
+ P0_15 = p15,
+
+ P0_16 = p16,
+ P0_17 = p17,
+ P0_18 = p18,
+ P0_19 = p19,
+ P0_20 = p20,
+ P0_21 = p21,
+ P0_22 = p22,
+ P0_23 = p23,
+
+ P0_24 = p24,
+ P0_25 = p25,
+ P0_26 = p26,
+ P0_27 = p27,
+ P0_28 = p28,
+ P0_29 = p29,
+ P0_30 = p30,
+ P0_31 = p31,
+
+ LED1 = p13,
+ LED2 = p23,
+ LED3 = p24,
+ LED4 = p25,
+
+ BUTTON1 = p20,
+ BUTTON2 = p21,
+ BUTTON3 = p22,
+ BUTTON4 = p0,
+
+ RX_PIN_NUMBER = p16,
+ TX_PIN_NUMBER = p17,
+ CTS_PIN_NUMBER = p20,
+ RTS_PIN_NUMBER = p21,
+
+ // mBed interface Pins
+ USBTX = TX_PIN_NUMBER,
+ USBRX = RX_PIN_NUMBER,
+
+ SPI_PSELMOSI0 = p15,
+ SPI_PSELMISO0 = p9,
+ SPI_PSELSS0 = p29,
+ SPI_PSELSCK0 = p11,
+
+ SPI_PSELMOSI1 = p17,
+ SPI_PSELMISO1 = p20,
+ SPI_PSELSS1 = p16,
+ SPI_PSELSCK1 = p21,
+
+ SPIS_PSELMOSI = p17,
+ SPIS_PSELMISO = p20,
+ SPIS_PSELSS = p16,
+ SPIS_PSELSCK = p21,
+
+ I2C_SDA0 = p31,
+ I2C_SCL0 = p30,
+
+ D0 = p16,
+ D1 = p17,
+ D2 = p20,
+ D3 = p21,
+ D4 = p22,
+ D5 = p0,
+ D6 = p13,
+ D7 = p23,
+
+ D8 = p24,
+ D9 = p25,
+ D10 = p29,
+ D11 = p15,
+ D12 = p9,
+ D13 = p11,
+
+ D14 = p30,
+ D15 = p31,
+
+ A0 = p3,
+ A1 = p4,
+ A2 = p5,
+ A3 = p6,
+ A4 = p26,
+ A5 = p27,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/device.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_DELTA_DFCM_NNN50/mbed_overrides.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+void mbed_sdk_init()
+{
+ char* debug_date = __DATE__;
+ char* debug_time = __TIME__;
+
+ // Default RF switch setting, pull p19 to low and p28 to high for turning antenna switch to BLE radiated path
+ NRF_GPIO->PIN_CNF[p19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+ | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+ | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
+ | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
+ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+ NRF_GPIO->PIN_CNF[p28] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+ | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+ | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
+ | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
+ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+
+ NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
+ NRF_GPIO->OUTSET = (GPIO_OUTCLR_PIN28_High << GPIO_OUTCLR_PIN28_Pos);
+
+ // Config External Crystal to 32MHz
+ NRF_CLOCK->XTALFREQ = 0x00;
+ NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+ NRF_CLOCK->TASKS_HFCLKSTART = 1;
+ while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0) {
+ // Do nothing.
+ }
+
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/PeripheralPins.h Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +//*** ADC *** +#ifdef DEVICE_ANALOGIN +extern const PinMap PinMap_ADC[]; +#endif + +//*** DAC *** +#ifdef DEVICE_ANALOGOUT +extern const PinMap PinMap_DAC[]; +#endif + +//*** I2C *** +#if DEVICE_I2C +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; +#endif + +//*** PWM *** +#if DEVICE_PWMOUT +extern const PinMap PinMap_PWM[]; +#endif + +//*** SERIAL *** +#ifdef DEVICE_SERIAL +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +#ifdef DEVICE_SERIAL_FC +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; +#endif +#endif + +//*** SPI *** +#ifdef DEVICE_SPI +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; +#endif + +//*** CAN *** +#ifdef DEVICE_CAN +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; +#endif + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/PinNamesTypes.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMESTYPES_H
+#define MBED_PINNAMESTYPES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
+ ((PUPD & 0x07) << 4) |\
+ ((AFNUM & 0x0F) << 7)))
+
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
+ ((PUPD & 0x07) << 4) |\
+ ((AFNUM & 0x0F) << 7) |\
+ ((CHANNEL & 0x1F) << 11) |\
+ ((INVERTED & 0x01) << 16)))
+
+#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
+#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
+#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
+#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
+#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
+
+#define STM_MODE_INPUT (0)
+#define STM_MODE_OUTPUT_PP (1)
+#define STM_MODE_OUTPUT_OD (2)
+#define STM_MODE_AF_PP (3)
+#define STM_MODE_AF_OD (4)
+#define STM_MODE_ANALOG (5)
+#define STM_MODE_IT_RISING (6)
+#define STM_MODE_IT_FALLING (7)
+#define STM_MODE_IT_RISING_FALLING (8)
+#define STM_MODE_EVT_RISING (9)
+#define STM_MODE_EVT_FALLING (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET (12)
+// The last mode is only valid for specific families, so we put it in the end
+#define STM_MODE_ANALOG_ADC_CONTROL (13)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X) ((uint32_t)(X) & 0xF)
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ PullNone = 0,
+ PullUp = 1,
+ PullDown = 2,
+ OpenDrain = 3,
+ PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/PortNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4,
+ PortF = 5,
+ PortG = 6,
+ PortH = 7,
+ PortI = 8,
+ PortJ = 9,
+ PortK = 10
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,73 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** - -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -241,14 +202,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -67,7 +67,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -188,14 +149,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -157,14 +118,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2, /* used for compilation needs */
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -156,14 +117,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2, /* used for compilation needs */
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -184,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -184,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -185,14 +146,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F0/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin) {
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin) {
- obj->pin = pin;
- if (pin == (PinName)NC) {
- return;
- }
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode) {
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction) {
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F0/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
- *obj->reg_clr = obj->mask;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,69 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** - -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -192,14 +153,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -65,7 +65,6 @@
int index;
};
-#include "gpio_object.h"
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -203,14 +164,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -180,14 +141,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F1/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC) {
- return;
- }
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F1/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
- *obj->reg_clr = obj->mask;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -254,14 +215,6 @@
#define STDIO_UART_RX SERIAL_RX
#define STDIO_UART UART_3
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set_clr = &gpio->BSRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F2/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set_clr = obj->mask;
- } else {
- *obj->reg_set_clr = obj->mask << 16;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F2/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -139,6 +139,7 @@
int index;
};
+#define GPIO_IP_WITHOUT_BRR
#include "gpio_object.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F3/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -244,14 +205,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f303xc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f303xc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xc.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -2397,9 +2397,6 @@
#define COMP1_CSR_COMP1INSEL_0 (0x1U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000010 */
#define COMP1_CSR_COMP1INSEL_1 (0x2U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000020 */
#define COMP1_CSR_COMP1INSEL_2 (0x4U << COMP1_CSR_COMP1INSEL_Pos) /*!< 0x00000040 */
-#define COMP1_CSR_COMP1NONINSEL_Pos (7U)
-#define COMP1_CSR_COMP1NONINSEL_Msk (0x1U << COMP1_CSR_COMP1NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP1_CSR_COMP1NONINSEL COMP1_CSR_COMP1NONINSEL_Msk /*!< COMP1 non inverting input select */
#define COMP1_CSR_COMP1OUTSEL_Pos (10U)
#define COMP1_CSR_COMP1OUTSEL_Msk (0xFU << COMP1_CSR_COMP1OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP1_CSR_COMP1OUTSEL COMP1_CSR_COMP1OUTSEL_Msk /*!< COMP1 output select */
@@ -2438,12 +2435,11 @@
#define COMP2_CSR_COMP2MODE_0 (0x1U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000004 */
#define COMP2_CSR_COMP2MODE_1 (0x2U << COMP2_CSR_COMP2MODE_Pos) /*!< 0x00000008 */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
-#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
+#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
-#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
@@ -2534,12 +2530,11 @@
#define COMP4_CSR_COMP4MODE_0 (0x1U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000004 */
#define COMP4_CSR_COMP4MODE_1 (0x2U << COMP4_CSR_COMP4MODE_Pos) /*!< 0x00000008 */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
-#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
+#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
-#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
@@ -2630,12 +2625,11 @@
#define COMP6_CSR_COMP6MODE_0 (0x1U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000004 */
#define COMP6_CSR_COMP6MODE_1 (0x2U << COMP6_CSR_COMP6MODE_Pos) /*!< 0x00000008 */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
-#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
+#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
-#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
@@ -2729,12 +2723,11 @@
#define COMP_CSR_COMPxMODE_0 (0x1U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000004 */
#define COMP_CSR_COMPxMODE_1 (0x2U << COMP_CSR_COMPxMODE_Pos) /*!< 0x00000008 */
#define COMP_CSR_COMPxINSEL_Pos (4U)
-#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
+#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxNONINSEL_Pos (7U)
#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
@@ -7183,9 +7176,6 @@
#define EXTI_IMR_MR26_Pos (26U)
#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27_Pos (27U)
-#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28_Pos (28U)
#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
@@ -7227,7 +7217,9 @@
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#define EXTI_IMR_IM25 EXTI_IMR_MR25
#define EXTI_IMR_IM26 EXTI_IMR_MR26
+#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
+#endif
#define EXTI_IMR_IM28 EXTI_IMR_MR28
#define EXTI_IMR_IM29 EXTI_IMR_MR29
#define EXTI_IMR_IM30 EXTI_IMR_MR30
@@ -7319,9 +7311,6 @@
#define EXTI_EMR_MR26_Pos (26U)
#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27_Pos (27U)
-#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28_Pos (28U)
#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
@@ -7363,7 +7352,9 @@
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#define EXTI_EMR_EM25 EXTI_EMR_MR25
#define EXTI_EMR_EM26 EXTI_EMR_MR26
+#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
+#endif
#define EXTI_EMR_EM28 EXTI_EMR_MR28
#define EXTI_EMR_EM29 EXTI_EMR_MR29
#define EXTI_EMR_EM30 EXTI_EMR_MR30
@@ -7473,6 +7464,24 @@
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@@ -7576,14 +7585,32 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -7684,14 +7711,32 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7781,6 +7826,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7792,14 +7838,32 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#define EXTI_PR_PIF31 EXTI_PR_PR31
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7818,10 +7882,11 @@
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@@ -7842,10 +7907,10 @@
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
@@ -7856,8 +7921,14 @@
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@@ -7868,8 +7939,14 @@
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@@ -7880,8 +7957,14 @@
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@@ -7892,8 +7975,15 @@
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -10976,6 +11066,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -12582,9 +12673,9 @@
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@@ -12859,6 +12950,11 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -174,14 +135,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f334x8.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f334x8.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f334x8.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -6634,48 +6634,24 @@
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos (21U)
-#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23_Pos (23U)
#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_MR24_Pos (24U)
-#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26_Pos (26U)
-#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27_Pos (27U)
-#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28_Pos (28U)
-#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29_Pos (29U)
-#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31_Pos (31U)
-#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -6696,20 +6672,36 @@
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#if defined(EXTI_IMR_MR18)
#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#endif
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
+#if defined(EXTI_IMR_MR24)
#define EXTI_IMR_IM24 EXTI_IMR_MR24
+#endif
#define EXTI_IMR_IM25 EXTI_IMR_MR25
+#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
+#endif
+#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
+#endif
+#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
+#endif
+#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
+#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
+#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
+#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@@ -6770,48 +6762,24 @@
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos (21U)
-#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23_Pos (23U)
#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
-#define EXTI_EMR_MR24_Pos (24U)
-#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26_Pos (26U)
-#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27_Pos (27U)
-#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28_Pos (28U)
-#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29_Pos (29U)
-#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31_Pos (31U)
-#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -6832,20 +6800,36 @@
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#if defined(EXTI_EMR_MR18)
#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#endif
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
+#if defined(EXTI_EMR_MR24)
#define EXTI_EMR_EM24 EXTI_EMR_MR24
+#endif
#define EXTI_EMR_EM25 EXTI_EMR_MR25
+#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
+#endif
+#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
+#endif
+#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
+#endif
+#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
+#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
+#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
+#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -6902,30 +6886,18 @@
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos (21U)
-#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR29_Pos (29U)
-#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
-#define EXTI_RTSR_TR31_Pos (31U)
-#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -6946,14 +6918,40 @@
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#if defined(EXTI_RTSR_TR18)
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#endif
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
+#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
+#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
+#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
+#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -7010,30 +7008,18 @@
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos (21U)
-#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR29_Pos (29U)
-#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
-#define EXTI_FTSR_TR31_Pos (31U)
-#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -7054,14 +7040,40 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#if defined(EXTI_FTSR_TR18)
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#endif
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#if defined(EXTI_FTSR_TR21)
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#endif
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#if defined(EXTI_FTSR_TR29)
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#endif
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#if defined(EXTI_FTSR_TR31)
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -7118,30 +7130,18 @@
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos (21U)
-#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER29_Pos (29U)
-#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
-#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
-#define EXTI_SWIER_SWIER31_Pos (31U)
-#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
-#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -7162,14 +7162,40 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#if defined(EXTI_SWIER_SWIER18)
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#endif
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#if defined(EXTI_SWIER_SWIER21)
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#endif
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#if defined(EXTI_SWIER_SWIER29)
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#endif
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#if defined(EXTI_SWIER_SWIER31)
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7226,30 +7252,18 @@
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos (21U)
-#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
-#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
-#define EXTI_PR_PR29_Pos (29U)
-#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
-#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
-#define EXTI_PR_PR31_Pos (31U)
-#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
-#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -7259,6 +7273,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7270,14 +7285,40 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#if defined(EXTI_PR_PR18)
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#endif
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#if defined(EXTI_PR_PR21)
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#endif
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#if defined(EXTI_PR_PR29)
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#endif
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#if defined(EXTI_PR_PR31)
+#define EXTI_PR_PIF31 EXTI_PR_PR31
+#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7285,21 +7326,19 @@
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
-#define EXTI_IMR2_MR33_Pos (1U)
-#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
-#define EXTI_IMR2_MR34_Pos (2U)
-#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
-#define EXTI_IMR2_MR35_Pos (3U)
-#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#if defined(EXTI_IMR2_MR33)
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#endif
+#if defined(EXTI_IMR2_MR34)
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#endif
+#if defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
@@ -7309,69 +7348,87 @@
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
-#define EXTI_EMR2_MR33_Pos (1U)
-#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
-#define EXTI_EMR2_MR34_Pos (2U)
-#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
-#define EXTI_EMR2_MR35_Pos (3U)
-#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#if defined(EXTI_EMR2_MR33)
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#endif
+#if defined(EXTI_EMR2_MR34)
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#endif
+#if defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
-#define EXTI_RTSR2_TR33_Pos (1U)
-#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#if defined(EXTI_RTSR2_TR33)
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#endif
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
-#define EXTI_FTSR2_TR33_Pos (1U)
-#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#if defined(EXTI_FTSR2_TR33)
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#endif
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
-#define EXTI_SWIER2_SWIER33_Pos (1U)
-#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#if defined(EXTI_SWIER2_SWIER33)
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#endif
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
-#define EXTI_PR2_PR33_Pos (1U)
-#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
-#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#if defined(EXTI_PR2_PR33)
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#endif
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -12980,6 +13037,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -14713,6 +14771,10 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -67,7 +67,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -184,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f302x8.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f302x8.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f302x8.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -2280,9 +2280,6 @@
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxNONINSEL_Pos (7U)
-#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
-#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@@ -6434,9 +6431,6 @@
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos (21U)
-#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
@@ -6449,24 +6443,12 @@
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26_Pos (26U)
-#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27_Pos (27U)
#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28_Pos (28U)
-#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29_Pos (29U)
-#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31_Pos (31U)
-#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -6490,17 +6472,27 @@
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
#define EXTI_IMR_IM24 EXTI_IMR_MR24
#define EXTI_IMR_IM25 EXTI_IMR_MR25
+#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
+#endif
#define EXTI_IMR_IM27 EXTI_IMR_MR27
+#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
+#endif
+#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
+#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
+#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
+#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@@ -6570,9 +6562,6 @@
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos (21U)
-#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
@@ -6585,24 +6574,12 @@
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26_Pos (26U)
-#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27_Pos (27U)
#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28_Pos (28U)
-#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29_Pos (29U)
-#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31_Pos (31U)
-#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -6626,17 +6603,27 @@
#define EXTI_EMR_EM18 EXTI_EMR_MR18
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
#define EXTI_EMR_EM24 EXTI_EMR_MR24
#define EXTI_EMR_EM25 EXTI_EMR_MR25
+#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
+#endif
#define EXTI_EMR_EM27 EXTI_EMR_MR27
+#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
+#endif
+#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
+#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
+#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
+#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -6702,21 +6689,12 @@
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos (21U)
-#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR29_Pos (29U)
-#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
-#define EXTI_RTSR_TR31_Pos (31U)
-#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -6740,11 +6718,35 @@
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
+#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
+#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
+#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
+#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -6810,21 +6812,12 @@
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos (21U)
-#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR29_Pos (29U)
-#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
-#define EXTI_FTSR_TR31_Pos (31U)
-#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -6845,14 +6838,38 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#if defined(EXTI_FTSR_TR21)
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#endif
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#if defined(EXTI_FTSR_TR29)
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#endif
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#if defined(EXTI_FTSR_TR31)
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -6918,21 +6935,12 @@
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos (21U)
-#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER29_Pos (29U)
-#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
-#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
-#define EXTI_SWIER_SWIER31_Pos (31U)
-#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
-#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -6953,14 +6961,38 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#if defined(EXTI_SWIER_SWIER21)
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#endif
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#if defined(EXTI_SWIER_SWIER29)
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#endif
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#if defined(EXTI_SWIER_SWIER31)
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7026,21 +7058,12 @@
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos (21U)
-#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
-#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
-#define EXTI_PR_PR29_Pos (29U)
-#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
-#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
-#define EXTI_PR_PR31_Pos (31U)
-#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
-#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -7050,6 +7073,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7061,14 +7085,38 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#if defined(EXTI_PR_PR21)
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#endif
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#if defined(EXTI_PR_PR29)
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#endif
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#if defined(EXTI_PR_PR31)
+#define EXTI_PR_PIF31 EXTI_PR_PR31
+#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7076,21 +7124,19 @@
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
-#define EXTI_IMR2_MR33_Pos (1U)
-#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
-#define EXTI_IMR2_MR34_Pos (2U)
-#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
-#define EXTI_IMR2_MR35_Pos (3U)
-#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#if defined(EXTI_IMR2_MR33)
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#endif
+#if defined(EXTI_IMR2_MR34)
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#endif
+#if defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@@ -7100,69 +7146,87 @@
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
-#define EXTI_EMR2_MR33_Pos (1U)
-#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
-#define EXTI_EMR2_MR34_Pos (2U)
-#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
-#define EXTI_EMR2_MR35_Pos (3U)
-#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#if defined(EXTI_EMR2_MR33)
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#endif
+#if defined(EXTI_EMR2_MR34)
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#endif
+#if defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
-#define EXTI_RTSR2_TR33_Pos (1U)
-#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#if defined(EXTI_RTSR2_TR33)
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#endif
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
-#define EXTI_FTSR2_TR33_Pos (1U)
-#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#if defined(EXTI_FTSR2_TR33)
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#endif
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
-#define EXTI_SWIER2_SWIER33_Pos (1U)
-#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#if defined(EXTI_SWIER2_SWIER33)
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#endif
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
-#define EXTI_PR2_PR33_Pos (1U)
-#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
-#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#if defined(EXTI_PR2_PR33)
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#endif
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -10130,6 +10194,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -11749,9 +11814,9 @@
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@@ -11985,6 +12050,10 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -159,14 +120,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f303x8.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f303x8.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303x8.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -6446,48 +6446,24 @@
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos (21U)
-#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23_Pos (23U)
#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_MR24_Pos (24U)
-#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26_Pos (26U)
-#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27_Pos (27U)
-#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28_Pos (28U)
-#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29_Pos (29U)
-#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31_Pos (31U)
-#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -6508,20 +6484,36 @@
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#if defined(EXTI_IMR_MR18)
#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#endif
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
+#if defined(EXTI_IMR_MR24)
#define EXTI_IMR_IM24 EXTI_IMR_MR24
+#endif
#define EXTI_IMR_IM25 EXTI_IMR_MR25
+#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
+#endif
+#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
+#endif
+#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
+#endif
+#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
+#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
+#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
+#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@@ -6582,48 +6574,24 @@
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos (21U)
-#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23_Pos (23U)
#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
-#define EXTI_EMR_MR24_Pos (24U)
-#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26_Pos (26U)
-#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27_Pos (27U)
-#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28_Pos (28U)
-#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29_Pos (29U)
-#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31_Pos (31U)
-#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -6644,20 +6612,36 @@
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#if defined(EXTI_EMR_MR18)
#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#endif
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
+#if defined(EXTI_EMR_MR24)
#define EXTI_EMR_EM24 EXTI_EMR_MR24
+#endif
#define EXTI_EMR_EM25 EXTI_EMR_MR25
+#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
+#endif
+#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
+#endif
+#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
+#endif
+#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
+#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
+#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
+#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -6714,30 +6698,18 @@
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos (21U)
-#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR29_Pos (29U)
-#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
-#define EXTI_RTSR_TR31_Pos (31U)
-#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -6758,14 +6730,40 @@
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#if defined(EXTI_RTSR_TR18)
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#endif
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
+#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
+#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
+#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
+#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -6822,30 +6820,18 @@
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos (21U)
-#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR29_Pos (29U)
-#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
-#define EXTI_FTSR_TR31_Pos (31U)
-#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -6866,14 +6852,40 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#if defined(EXTI_FTSR_TR18)
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#endif
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#if defined(EXTI_FTSR_TR21)
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#endif
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#if defined(EXTI_FTSR_TR29)
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#endif
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#if defined(EXTI_FTSR_TR31)
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -6930,30 +6942,18 @@
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos (21U)
-#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER29_Pos (29U)
-#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
-#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
-#define EXTI_SWIER_SWIER31_Pos (31U)
-#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
-#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -6974,14 +6974,40 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#if defined(EXTI_SWIER_SWIER18)
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#endif
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#if defined(EXTI_SWIER_SWIER21)
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#endif
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#if defined(EXTI_SWIER_SWIER29)
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#endif
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#if defined(EXTI_SWIER_SWIER31)
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7038,30 +7064,18 @@
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos (21U)
-#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
-#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
-#define EXTI_PR_PR29_Pos (29U)
-#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
-#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
-#define EXTI_PR_PR31_Pos (31U)
-#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
-#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -7071,6 +7085,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7082,14 +7097,40 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#if defined(EXTI_PR_PR18)
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#endif
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#if defined(EXTI_PR_PR21)
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#endif
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#if defined(EXTI_PR_PR29)
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#endif
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#if defined(EXTI_PR_PR31)
+#define EXTI_PR_PIF31 EXTI_PR_PR31
+#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7097,21 +7138,19 @@
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
-#define EXTI_IMR2_MR33_Pos (1U)
-#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
-#define EXTI_IMR2_MR34_Pos (2U)
-#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
-#define EXTI_IMR2_MR35_Pos (3U)
-#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#if defined(EXTI_IMR2_MR33)
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#endif
+#if defined(EXTI_IMR2_MR34)
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#endif
+#if defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@@ -7121,69 +7160,87 @@
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
-#define EXTI_EMR2_MR33_Pos (1U)
-#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
-#define EXTI_EMR2_MR34_Pos (2U)
-#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
-#define EXTI_EMR2_MR35_Pos (3U)
-#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#if defined(EXTI_EMR2_MR33)
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#endif
+#if defined(EXTI_EMR2_MR34)
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#endif
+#if defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
-#define EXTI_RTSR2_TR33_Pos (1U)
-#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#if defined(EXTI_RTSR2_TR33)
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#endif
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
-#define EXTI_FTSR2_TR33_Pos (1U)
-#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#if defined(EXTI_FTSR2_TR33)
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#endif
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
-#define EXTI_SWIER2_SWIER33_Pos (1U)
-#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#if defined(EXTI_SWIER2_SWIER33)
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#endif
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
-#define EXTI_PR2_PR33_Pos (1U)
-#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
-#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#if defined(EXTI_PR2_PR33)
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#endif
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -10025,6 +10082,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -11755,6 +11813,10 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303K8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -192,14 +153,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f303xe.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f303xe.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xe.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -2531,18 +2531,11 @@
#define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
-#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
+#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
-#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
-#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
-#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
-#define COMP2_CSR_COMP2WNDWEN_Pos (9U)
-#define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */
#define COMP2_CSR_COMP2OUTSEL_Pos (10U)
#define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
@@ -2604,18 +2597,11 @@
#define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
-#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
+#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
-#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
-#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
-#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
-#define COMP4_CSR_COMP4WNDWEN_Pos (9U)
-#define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */
#define COMP4_CSR_COMP4OUTSEL_Pos (10U)
#define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
@@ -2677,20 +2663,11 @@
#define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
-#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
+#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
-#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
-#if defined(STM32F303xE)
-#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
-#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
-#endif
-#define COMP6_CSR_COMP6WNDWEN_Pos (9U)
-#define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */
#define COMP6_CSR_COMP6OUTSEL_Pos (10U)
#define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
@@ -2755,18 +2732,11 @@
#define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
#define COMP_CSR_COMPxINSEL_Pos (4U)
-#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
+#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
-#define COMP_CSR_COMPxNONINSEL_Pos (7U)
-#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
-#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
-#define COMP_CSR_COMPxWNDWEN_Pos (9U)
-#define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */
-#define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@@ -7500,6 +7470,24 @@
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@@ -7603,14 +7591,32 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -7711,14 +7717,32 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7808,6 +7832,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7819,14 +7844,32 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#define EXTI_PR_PIF31 EXTI_PR_PR31
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7845,10 +7888,11 @@
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@@ -7869,10 +7913,10 @@
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
@@ -7883,8 +7927,14 @@
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@@ -7895,8 +7945,14 @@
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@@ -7907,8 +7963,14 @@
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@@ -7919,8 +7981,15 @@
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -12757,6 +12826,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -14394,9 +14464,9 @@
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@@ -14688,6 +14758,12 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -259,14 +220,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f303xe.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -2531,18 +2531,11 @@
#define COMP2_CSR_COMP2EN_Msk (0x1U << COMP2_CSR_COMP2EN_Pos) /*!< 0x00000001 */
#define COMP2_CSR_COMP2EN COMP2_CSR_COMP2EN_Msk /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL_Pos (4U)
-#define COMP2_CSR_COMP2INSEL_Msk (0x40007U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00400070 */
+#define COMP2_CSR_COMP2INSEL_Msk (0x7U << COMP2_CSR_COMP2INSEL_Pos) /*!< 0x00000070 */
#define COMP2_CSR_COMP2INSEL COMP2_CSR_COMP2INSEL_Msk /*!< COMP2 inverting input select */
#define COMP2_CSR_COMP2INSEL_0 (0x00000010U) /*!< COMP2 inverting input select bit 0 */
#define COMP2_CSR_COMP2INSEL_1 (0x00000020U) /*!< COMP2 inverting input select bit 1 */
#define COMP2_CSR_COMP2INSEL_2 (0x00000040U) /*!< COMP2 inverting input select bit 2 */
-#define COMP2_CSR_COMP2INSEL_3 (0x00400000U) /*!< COMP2 inverting input select bit 3 */
-#define COMP2_CSR_COMP2NONINSEL_Pos (7U)
-#define COMP2_CSR_COMP2NONINSEL_Msk (0x1U << COMP2_CSR_COMP2NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP2_CSR_COMP2NONINSEL COMP2_CSR_COMP2NONINSEL_Msk /*!< COMP2 non inverting input select */
-#define COMP2_CSR_COMP2WNDWEN_Pos (9U)
-#define COMP2_CSR_COMP2WNDWEN_Msk (0x1U << COMP2_CSR_COMP2WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP2_CSR_COMP2WNDWEN COMP2_CSR_COMP2WNDWEN_Msk /*!< COMP2 window mode enable */
#define COMP2_CSR_COMP2OUTSEL_Pos (10U)
#define COMP2_CSR_COMP2OUTSEL_Msk (0xFU << COMP2_CSR_COMP2OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP2_CSR_COMP2OUTSEL COMP2_CSR_COMP2OUTSEL_Msk /*!< COMP2 output select */
@@ -2604,18 +2597,11 @@
#define COMP4_CSR_COMP4EN_Msk (0x1U << COMP4_CSR_COMP4EN_Pos) /*!< 0x00000001 */
#define COMP4_CSR_COMP4EN COMP4_CSR_COMP4EN_Msk /*!< COMP4 enable */
#define COMP4_CSR_COMP4INSEL_Pos (4U)
-#define COMP4_CSR_COMP4INSEL_Msk (0x40007U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00400070 */
+#define COMP4_CSR_COMP4INSEL_Msk (0x7U << COMP4_CSR_COMP4INSEL_Pos) /*!< 0x00000070 */
#define COMP4_CSR_COMP4INSEL COMP4_CSR_COMP4INSEL_Msk /*!< COMP4 inverting input select */
#define COMP4_CSR_COMP4INSEL_0 (0x00000010U) /*!< COMP4 inverting input select bit 0 */
#define COMP4_CSR_COMP4INSEL_1 (0x00000020U) /*!< COMP4 inverting input select bit 1 */
#define COMP4_CSR_COMP4INSEL_2 (0x00000040U) /*!< COMP4 inverting input select bit 2 */
-#define COMP4_CSR_COMP4INSEL_3 (0x00400000U) /*!< COMP4 inverting input select bit 3 */
-#define COMP4_CSR_COMP4NONINSEL_Pos (7U)
-#define COMP4_CSR_COMP4NONINSEL_Msk (0x1U << COMP4_CSR_COMP4NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP4_CSR_COMP4NONINSEL COMP4_CSR_COMP4NONINSEL_Msk /*!< COMP4 non inverting input select */
-#define COMP4_CSR_COMP4WNDWEN_Pos (9U)
-#define COMP4_CSR_COMP4WNDWEN_Msk (0x1U << COMP4_CSR_COMP4WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP4_CSR_COMP4WNDWEN COMP4_CSR_COMP4WNDWEN_Msk /*!< COMP4 window mode enable */
#define COMP4_CSR_COMP4OUTSEL_Pos (10U)
#define COMP4_CSR_COMP4OUTSEL_Msk (0xFU << COMP4_CSR_COMP4OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP4_CSR_COMP4OUTSEL COMP4_CSR_COMP4OUTSEL_Msk /*!< COMP4 output select */
@@ -2677,20 +2663,11 @@
#define COMP6_CSR_COMP6EN_Msk (0x1U << COMP6_CSR_COMP6EN_Pos) /*!< 0x00000001 */
#define COMP6_CSR_COMP6EN COMP6_CSR_COMP6EN_Msk /*!< COMP6 enable */
#define COMP6_CSR_COMP6INSEL_Pos (4U)
-#define COMP6_CSR_COMP6INSEL_Msk (0x40007U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00400070 */
+#define COMP6_CSR_COMP6INSEL_Msk (0x7U << COMP6_CSR_COMP6INSEL_Pos) /*!< 0x00000070 */
#define COMP6_CSR_COMP6INSEL COMP6_CSR_COMP6INSEL_Msk /*!< COMP6 inverting input select */
#define COMP6_CSR_COMP6INSEL_0 (0x00000010U) /*!< COMP6 inverting input select bit 0 */
#define COMP6_CSR_COMP6INSEL_1 (0x00000020U) /*!< COMP6 inverting input select bit 1 */
#define COMP6_CSR_COMP6INSEL_2 (0x00000040U) /*!< COMP6 inverting input select bit 2 */
-#define COMP6_CSR_COMP6INSEL_3 (0x00400000U) /*!< COMP6 inverting input select bit 3 */
-#if defined(STM32F303xE)
-#define COMP6_CSR_COMP6NONINSEL_Pos (7U)
-#define COMP6_CSR_COMP6NONINSEL_Msk (0x1U << COMP6_CSR_COMP6NONINSEL_Pos) /*!< 0x00000080 */
-#define COMP6_CSR_COMP6NONINSEL COMP6_CSR_COMP6NONINSEL_Msk /*!< COMP6 non inverting input select */
-#endif
-#define COMP6_CSR_COMP6WNDWEN_Pos (9U)
-#define COMP6_CSR_COMP6WNDWEN_Msk (0x1U << COMP6_CSR_COMP6WNDWEN_Pos) /*!< 0x00000200 */
-#define COMP6_CSR_COMP6WNDWEN COMP6_CSR_COMP6WNDWEN_Msk /*!< COMP6 window mode enable */
#define COMP6_CSR_COMP6OUTSEL_Pos (10U)
#define COMP6_CSR_COMP6OUTSEL_Msk (0xFU << COMP6_CSR_COMP6OUTSEL_Pos) /*!< 0x00003C00 */
#define COMP6_CSR_COMP6OUTSEL COMP6_CSR_COMP6OUTSEL_Msk /*!< COMP6 output select */
@@ -2755,18 +2732,11 @@
#define COMP_CSR_COMPxSW1_Msk (0x1U << COMP_CSR_COMPxSW1_Pos) /*!< 0x00000002 */
#define COMP_CSR_COMPxSW1 COMP_CSR_COMPxSW1_Msk /*!< COMPx SW1 switch control */
#define COMP_CSR_COMPxINSEL_Pos (4U)
-#define COMP_CSR_COMPxINSEL_Msk (0x40007U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00400070 */
+#define COMP_CSR_COMPxINSEL_Msk (0x7U << COMP_CSR_COMPxINSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_COMPxINSEL COMP_CSR_COMPxINSEL_Msk /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 (0x00000010U) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 (0x00000020U) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 (0x00000040U) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxINSEL_3 (0x00400000U) /*!< COMPx inverting input select bit 3 */
-#define COMP_CSR_COMPxNONINSEL_Pos (7U)
-#define COMP_CSR_COMPxNONINSEL_Msk (0x1U << COMP_CSR_COMPxNONINSEL_Pos) /*!< 0x00000080 */
-#define COMP_CSR_COMPxNONINSEL COMP_CSR_COMPxNONINSEL_Msk /*!< COMPx non inverting input select */
-#define COMP_CSR_COMPxWNDWEN_Pos (9U)
-#define COMP_CSR_COMPxWNDWEN_Msk (0x1U << COMP_CSR_COMPxWNDWEN_Pos) /*!< 0x00000200 */
-#define COMP_CSR_COMPxWNDWEN COMP_CSR_COMPxWNDWEN_Msk /*!< COMPx window mode enable */
#define COMP_CSR_COMPxOUTSEL_Pos (10U)
#define COMP_CSR_COMPxOUTSEL_Msk (0xFU << COMP_CSR_COMPxOUTSEL_Pos) /*!< 0x00003C00 */
#define COMP_CSR_COMPxOUTSEL COMP_CSR_COMPxOUTSEL_Msk /*!< COMPx output select */
@@ -7500,6 +7470,24 @@
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
@@ -7603,14 +7591,32 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -7711,14 +7717,32 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7808,6 +7832,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7819,14 +7844,32 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#define EXTI_PR_PIF31 EXTI_PR_PR31
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7845,10 +7888,11 @@
#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xFU << EXTI_IMR2_IM_Pos) /*!< 0x0000000F */
@@ -7869,10 +7913,10 @@
#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
@@ -7883,8 +7927,14 @@
#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
@@ -7895,8 +7945,14 @@
#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
@@ -7907,8 +7963,14 @@
#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
@@ -7919,8 +7981,15 @@
#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -12757,6 +12826,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -14394,9 +14464,9 @@
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
@@ -14688,6 +14758,12 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -187,14 +148,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/stm32f334x8.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/stm32f334x8.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f334x8.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -6634,48 +6634,24 @@
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19_Pos (19U)
#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20_Pos (20U)
#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos (21U)
-#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22_Pos (22U)
#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23_Pos (23U)
#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_MR24_Pos (24U)
-#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR_MR25_Pos (25U)
#define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26_Pos (26U)
-#define EXTI_IMR_MR26_Msk (0x1U << EXTI_IMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_IMR_MR26 EXTI_IMR_MR26_Msk /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27_Pos (27U)
-#define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28_Pos (28U)
-#define EXTI_IMR_MR28_Msk (0x1U << EXTI_IMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_IMR_MR28 EXTI_IMR_MR28_Msk /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29_Pos (29U)
-#define EXTI_IMR_MR29_Msk (0x1U << EXTI_IMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_IMR_MR29 EXTI_IMR_MR29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR_MR30_Pos (30U)
#define EXTI_IMR_MR30_Msk (0x1U << EXTI_IMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_IMR_MR30 EXTI_IMR_MR30_Msk /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31_Pos (31U)
-#define EXTI_IMR_MR31_Msk (0x1U << EXTI_IMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_IMR_MR31 EXTI_IMR_MR31_Msk /*!< Interrupt Mask on line 31 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -6696,20 +6672,36 @@
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
+#if defined(EXTI_IMR_MR18)
#define EXTI_IMR_IM18 EXTI_IMR_MR18
+#endif
#define EXTI_IMR_IM19 EXTI_IMR_MR19
#define EXTI_IMR_IM20 EXTI_IMR_MR20
+#if defined(EXTI_IMR_MR21)
#define EXTI_IMR_IM21 EXTI_IMR_MR21
+#endif
#define EXTI_IMR_IM22 EXTI_IMR_MR22
#define EXTI_IMR_IM23 EXTI_IMR_MR23
+#if defined(EXTI_IMR_MR24)
#define EXTI_IMR_IM24 EXTI_IMR_MR24
+#endif
#define EXTI_IMR_IM25 EXTI_IMR_MR25
+#if defined(EXTI_IMR_MR26)
#define EXTI_IMR_IM26 EXTI_IMR_MR26
+#endif
+#if defined(EXTI_IMR_MR27)
#define EXTI_IMR_IM27 EXTI_IMR_MR27
+#endif
+#if defined(EXTI_IMR_MR28)
#define EXTI_IMR_IM28 EXTI_IMR_MR28
+#endif
+#if defined(EXTI_IMR_MR29)
#define EXTI_IMR_IM29 EXTI_IMR_MR29
+#endif
#define EXTI_IMR_IM30 EXTI_IMR_MR30
+#if defined(EXTI_IMR_MR31)
#define EXTI_IMR_IM31 EXTI_IMR_MR31
+#endif
#define EXTI_IMR_IM_Pos (0U)
#define EXTI_IMR_IM_Msk (0xFFFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0xFFFFFFFF */
@@ -6770,48 +6762,24 @@
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19_Pos (19U)
#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20_Pos (20U)
#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos (21U)
-#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
-#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22_Pos (22U)
#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23_Pos (23U)
#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
-#define EXTI_EMR_MR24_Pos (24U)
-#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
-#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR_MR25_Pos (25U)
#define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
#define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26_Pos (26U)
-#define EXTI_EMR_MR26_Msk (0x1U << EXTI_EMR_MR26_Pos) /*!< 0x04000000 */
-#define EXTI_EMR_MR26 EXTI_EMR_MR26_Msk /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27_Pos (27U)
-#define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
-#define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28_Pos (28U)
-#define EXTI_EMR_MR28_Msk (0x1U << EXTI_EMR_MR28_Pos) /*!< 0x10000000 */
-#define EXTI_EMR_MR28 EXTI_EMR_MR28_Msk /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29_Pos (29U)
-#define EXTI_EMR_MR29_Msk (0x1U << EXTI_EMR_MR29_Pos) /*!< 0x20000000 */
-#define EXTI_EMR_MR29 EXTI_EMR_MR29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR_MR30_Pos (30U)
#define EXTI_EMR_MR30_Msk (0x1U << EXTI_EMR_MR30_Pos) /*!< 0x40000000 */
#define EXTI_EMR_MR30 EXTI_EMR_MR30_Msk /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31_Pos (31U)
-#define EXTI_EMR_MR31_Msk (0x1U << EXTI_EMR_MR31_Pos) /*!< 0x80000000 */
-#define EXTI_EMR_MR31 EXTI_EMR_MR31_Msk /*!< Event Mask on line 31 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -6832,20 +6800,36 @@
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
+#if defined(EXTI_EMR_MR18)
#define EXTI_EMR_EM18 EXTI_EMR_MR18
+#endif
#define EXTI_EMR_EM19 EXTI_EMR_MR19
#define EXTI_EMR_EM20 EXTI_EMR_MR20
+#if defined(EXTI_EMR_MR21)
#define EXTI_EMR_EM21 EXTI_EMR_MR21
+#endif
#define EXTI_EMR_EM22 EXTI_EMR_MR22
#define EXTI_EMR_EM23 EXTI_EMR_MR23
+#if defined(EXTI_EMR_MR24)
#define EXTI_EMR_EM24 EXTI_EMR_MR24
+#endif
#define EXTI_EMR_EM25 EXTI_EMR_MR25
+#if defined(EXTI_EMR_MR26)
#define EXTI_EMR_EM26 EXTI_EMR_MR26
+#endif
+#if defined(EXTI_EMR_MR27)
#define EXTI_EMR_EM27 EXTI_EMR_MR27
+#endif
+#if defined(EXTI_EMR_MR28)
#define EXTI_EMR_EM28 EXTI_EMR_MR28
+#endif
+#if defined(EXTI_EMR_MR29)
#define EXTI_EMR_EM29 EXTI_EMR_MR29
+#endif
#define EXTI_EMR_EM30 EXTI_EMR_MR30
+#if defined(EXTI_EMR_MR31)
#define EXTI_EMR_EM31 EXTI_EMR_MR31
+#endif
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -6902,30 +6886,18 @@
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19_Pos (19U)
#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20_Pos (20U)
#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos (21U)
-#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22_Pos (22U)
#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR29_Pos (29U)
-#define EXTI_RTSR_TR29_Msk (0x1U << EXTI_RTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_RTSR_TR29 EXTI_RTSR_TR29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR_TR30_Pos (30U)
#define EXTI_RTSR_TR30_Msk (0x1U << EXTI_RTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR_TR30 EXTI_RTSR_TR30_Msk /*!< Rising trigger event configuration bit of line 30 */
-#define EXTI_RTSR_TR31_Pos (31U)
-#define EXTI_RTSR_TR31_Msk (0x1U << EXTI_RTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_RTSR_TR31 EXTI_RTSR_TR31_Msk /*!< Rising trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -6946,14 +6918,40 @@
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#if defined(EXTI_RTSR_TR18)
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#endif
#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
#define EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#if defined(EXTI_RTSR_TR21)
#define EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#endif
#define EXTI_RTSR_RT22 EXTI_RTSR_TR22
+#if defined(EXTI_RTSR_TR23)
+#define EXTI_RTSR_RT23 EXTI_RTSR_TR23
+#endif
+#if defined(EXTI_RTSR_TR24)
+#define EXTI_RTSR_RT24 EXTI_RTSR_TR24
+#endif
+#if defined(EXTI_RTSR_TR25)
+#define EXTI_RTSR_RT25 EXTI_RTSR_TR25
+#endif
+#if defined(EXTI_RTSR_TR26)
+#define EXTI_RTSR_RT26 EXTI_RTSR_TR26
+#endif
+#if defined(EXTI_RTSR_TR27)
+#define EXTI_RTSR_RT27 EXTI_RTSR_TR27
+#endif
+#if defined(EXTI_RTSR_TR28)
+#define EXTI_RTSR_RT28 EXTI_RTSR_TR28
+#endif
+#if defined(EXTI_RTSR_TR29)
#define EXTI_RTSR_RT29 EXTI_RTSR_TR29
+#endif
#define EXTI_RTSR_RT30 EXTI_RTSR_TR30
+#if defined(EXTI_RTSR_TR31)
#define EXTI_RTSR_RT31 EXTI_RTSR_TR31
+#endif
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -7010,30 +7008,18 @@
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19_Pos (19U)
#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20_Pos (20U)
#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos (21U)
-#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
-#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22_Pos (22U)
#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR29_Pos (29U)
-#define EXTI_FTSR_TR29_Msk (0x1U << EXTI_FTSR_TR29_Pos) /*!< 0x20000000 */
-#define EXTI_FTSR_TR29 EXTI_FTSR_TR29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR_TR30_Pos (30U)
#define EXTI_FTSR_TR30_Msk (0x1U << EXTI_FTSR_TR30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR_TR30 EXTI_FTSR_TR30_Msk /*!< Falling trigger event configuration bit of line 30 */
-#define EXTI_FTSR_TR31_Pos (31U)
-#define EXTI_FTSR_TR31_Msk (0x1U << EXTI_FTSR_TR31_Pos) /*!< 0x80000000 */
-#define EXTI_FTSR_TR31 EXTI_FTSR_TR31_Msk /*!< Falling trigger event configuration bit of line 31 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -7054,14 +7040,40 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
-#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
-#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
-#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
-#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
-#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
-#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#if defined(EXTI_FTSR_TR18)
+#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#endif
+#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#if defined(EXTI_FTSR_TR21)
+#define EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#endif
+#define EXTI_FTSR_FT22 EXTI_FTSR_TR22
+#if defined(EXTI_FTSR_TR23)
+#define EXTI_FTSR_FT23 EXTI_FTSR_TR23
+#endif
+#if defined(EXTI_FTSR_TR24)
+#define EXTI_FTSR_FT24 EXTI_FTSR_TR24
+#endif
+#if defined(EXTI_FTSR_TR25)
+#define EXTI_FTSR_FT25 EXTI_FTSR_TR25
+#endif
+#if defined(EXTI_FTSR_TR26)
+#define EXTI_FTSR_FT26 EXTI_FTSR_TR26
+#endif
+#if defined(EXTI_FTSR_TR27)
+#define EXTI_FTSR_FT27 EXTI_FTSR_TR27
+#endif
+#if defined(EXTI_FTSR_TR28)
+#define EXTI_FTSR_FT28 EXTI_FTSR_TR28
+#endif
+#if defined(EXTI_FTSR_TR29)
+#define EXTI_FTSR_FT29 EXTI_FTSR_TR29
+#endif
+#define EXTI_FTSR_FT30 EXTI_FTSR_TR30
+#if defined(EXTI_FTSR_TR31)
+#define EXTI_FTSR_FT31 EXTI_FTSR_TR31
+#endif
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -7118,30 +7130,18 @@
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19_Pos (19U)
#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20_Pos (20U)
#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos (21U)
-#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22_Pos (22U)
#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER29_Pos (29U)
-#define EXTI_SWIER_SWIER29_Msk (0x1U << EXTI_SWIER_SWIER29_Pos) /*!< 0x20000000 */
-#define EXTI_SWIER_SWIER29 EXTI_SWIER_SWIER29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER_SWIER30_Pos (30U)
#define EXTI_SWIER_SWIER30_Msk (0x1U << EXTI_SWIER_SWIER30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER_SWIER30 EXTI_SWIER_SWIER30_Msk /*!< Software Interrupt on line 30 */
-#define EXTI_SWIER_SWIER31_Pos (31U)
-#define EXTI_SWIER_SWIER31_Msk (0x1U << EXTI_SWIER_SWIER31_Pos) /*!< 0x80000000 */
-#define EXTI_SWIER_SWIER31 EXTI_SWIER_SWIER31_Msk /*!< Software Interrupt on line 31 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -7162,14 +7162,40 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
-#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
-#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
-#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
-#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
-#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
-#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#if defined(EXTI_SWIER_SWIER18)
+#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#endif
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#if defined(EXTI_SWIER_SWIER21)
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#endif
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+#if defined(EXTI_SWIER_SWIER23)
+#define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
+#endif
+#if defined(EXTI_SWIER_SWIER24)
+#define EXTI_SWIER_SWI24 EXTI_SWIER_SWIER24
+#endif
+#if defined(EXTI_SWIER_SWIER25)
+#define EXTI_SWIER_SWI25 EXTI_SWIER_SWIER25
+#endif
+#if defined(EXTI_SWIER_SWIER26)
+#define EXTI_SWIER_SWI26 EXTI_SWIER_SWIER26
+#endif
+#if defined(EXTI_SWIER_SWIER27)
+#define EXTI_SWIER_SWI27 EXTI_SWIER_SWIER27
+#endif
+#if defined(EXTI_SWIER_SWIER28)
+#define EXTI_SWIER_SWI28 EXTI_SWIER_SWIER28
+#endif
+#if defined(EXTI_SWIER_SWIER29)
+#define EXTI_SWIER_SWI29 EXTI_SWIER_SWIER29
+#endif
+#define EXTI_SWIER_SWI30 EXTI_SWIER_SWIER30
+#if defined(EXTI_SWIER_SWIER31)
+#define EXTI_SWIER_SWI31 EXTI_SWIER_SWIER31
+#endif
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -7226,30 +7252,18 @@
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
#define EXTI_PR_PR19_Pos (19U)
#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR_PR20_Pos (20U)
#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos (21U)
-#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
-#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR_PR22_Pos (22U)
#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
-#define EXTI_PR_PR29_Pos (29U)
-#define EXTI_PR_PR29_Msk (0x1U << EXTI_PR_PR29_Pos) /*!< 0x20000000 */
-#define EXTI_PR_PR29 EXTI_PR_PR29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR_PR30_Pos (30U)
#define EXTI_PR_PR30_Msk (0x1U << EXTI_PR_PR30_Pos) /*!< 0x40000000 */
#define EXTI_PR_PR30 EXTI_PR_PR30_Msk /*!< Pending bit for line 30 */
-#define EXTI_PR_PR31_Pos (31U)
-#define EXTI_PR_PR31_Msk (0x1U << EXTI_PR_PR31_Pos) /*!< 0x80000000 */
-#define EXTI_PR_PR31 EXTI_PR_PR31_Msk /*!< Pending bit for line 31 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -7259,6 +7273,7 @@
#define EXTI_PR_PIF4 EXTI_PR_PR4
#define EXTI_PR_PIF5 EXTI_PR_PR5
#define EXTI_PR_PIF6 EXTI_PR_PR6
+#define EXTI_PR_PIF6 EXTI_PR_PR6
#define EXTI_PR_PIF7 EXTI_PR_PR7
#define EXTI_PR_PIF8 EXTI_PR_PR8
#define EXTI_PR_PIF9 EXTI_PR_PR9
@@ -7270,14 +7285,40 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
-#define EXTI_PR_PIF20 EXTI_PR_PR20
-#define EXTI_PR_PIF21 EXTI_PR_PR21
-#define EXTI_PR_PIF22 EXTI_PR_PR22
-#define EXTI_PR_PIF29 EXTI_PR_PR29
-#define EXTI_PR_PIF30 EXTI_PR_PR30
-#define EXTI_PR_PIF31 EXTI_PR_PR31
+#if defined(EXTI_PR_PR18)
+#define EXTI_PR_PIF18 EXTI_PR_PR18
+#endif
+#define EXTI_PR_PIF19 EXTI_PR_PR19
+#define EXTI_PR_PIF20 EXTI_PR_PR20
+#if defined(EXTI_PR_PR21)
+#define EXTI_PR_PIF21 EXTI_PR_PR21
+#endif
+#define EXTI_PR_PIF22 EXTI_PR_PR22
+#if defined(EXTI_PR_PR23)
+#define EXTI_PR_PIF23 EXTI_PR_PR23
+#endif
+#if defined(EXTI_PR_PR24)
+#define EXTI_PR_PIF24 EXTI_PR_PR24
+#endif
+#if defined(EXTI_PR_PR25)
+#define EXTI_PR_PIF25 EXTI_PR_PR25
+#endif
+#if defined(EXTI_PR_PR26)
+#define EXTI_PR_PIF26 EXTI_PR_PR26
+#endif
+#if defined(EXTI_PR_PR27)
+#define EXTI_PR_PIF27 EXTI_PR_PR27
+#endif
+#if defined(EXTI_PR_PR28)
+#define EXTI_PR_PIF28 EXTI_PR_PR28
+#endif
+#if defined(EXTI_PR_PR29)
+#define EXTI_PR_PIF29 EXTI_PR_PR29
+#endif
+#define EXTI_PR_PIF30 EXTI_PR_PR30
+#if defined(EXTI_PR_PR31)
+#define EXTI_PR_PIF31 EXTI_PR_PR31
+#endif
#define EXTI_32_63_SUPPORT /* EXTI support more than 32 lines */
@@ -7285,21 +7326,19 @@
#define EXTI_IMR2_MR32_Pos (0U)
#define EXTI_IMR2_MR32_Msk (0x1U << EXTI_IMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_MR32 EXTI_IMR2_MR32_Msk /*!< Interrupt Mask on line 32 */
-#define EXTI_IMR2_MR33_Pos (1U)
-#define EXTI_IMR2_MR33_Msk (0x1U << EXTI_IMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_IMR2_MR33 EXTI_IMR2_MR33_Msk /*!< Interrupt Mask on line 33 */
-#define EXTI_IMR2_MR34_Pos (2U)
-#define EXTI_IMR2_MR34_Msk (0x1U << EXTI_IMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_IMR2_MR34 EXTI_IMR2_MR34_Msk /*!< Interrupt Mask on line 34 */
-#define EXTI_IMR2_MR35_Pos (3U)
-#define EXTI_IMR2_MR35_Msk (0x1U << EXTI_IMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_IMR2_MR35 EXTI_IMR2_MR35_Msk /*!< Interrupt Mask on line 35 */
/* References Defines */
-#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
-#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
-#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
-#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+
+#define EXTI_IMR2_IM32 EXTI_IMR2_MR32
+#if defined(EXTI_IMR2_MR33)
+#define EXTI_IMR2_IM33 EXTI_IMR2_MR33
+#endif
+#if defined(EXTI_IMR2_MR34)
+#define EXTI_IMR2_IM34 EXTI_IMR2_MR34
+#endif
+#if defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM35 EXTI_IMR2_MR35
+#endif
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x1U << EXTI_IMR2_IM_Pos) /*!< 0x00000001 */
@@ -7309,69 +7348,87 @@
#define EXTI_EMR2_MR32_Pos (0U)
#define EXTI_EMR2_MR32_Msk (0x1U << EXTI_EMR2_MR32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_MR32 EXTI_EMR2_MR32_Msk /*!< Event Mask on line 32 */
-#define EXTI_EMR2_MR33_Pos (1U)
-#define EXTI_EMR2_MR33_Msk (0x1U << EXTI_EMR2_MR33_Pos) /*!< 0x00000002 */
-#define EXTI_EMR2_MR33 EXTI_EMR2_MR33_Msk /*!< Event Mask on line 33 */
-#define EXTI_EMR2_MR34_Pos (2U)
-#define EXTI_EMR2_MR34_Msk (0x1U << EXTI_EMR2_MR34_Pos) /*!< 0x00000004 */
-#define EXTI_EMR2_MR34 EXTI_EMR2_MR34_Msk /*!< Event Mask on line 34 */
-#define EXTI_EMR2_MR35_Pos (3U)
-#define EXTI_EMR2_MR35_Msk (0x1U << EXTI_EMR2_MR35_Pos) /*!< 0x00000008 */
-#define EXTI_EMR2_MR35 EXTI_EMR2_MR35_Msk /*!< Event Mask on line 34 */
/* References Defines */
-#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
-#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
-#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
-#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#define EXTI_EMR2_EM32 EXTI_EMR2_MR32
+#if defined(EXTI_EMR2_MR33)
+#define EXTI_EMR2_EM33 EXTI_EMR2_MR33
+#endif
+#if defined(EXTI_EMR2_MR34)
+#define EXTI_EMR2_EM34 EXTI_EMR2_MR34
+#endif
+#if defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM35 EXTI_EMR2_MR35
+#endif
/****************** Bit definition for EXTI_RTSR2 register ********************/
#define EXTI_RTSR2_TR32_Pos (0U)
#define EXTI_RTSR2_TR32_Msk (0x1U << EXTI_RTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_TR32 EXTI_RTSR2_TR32_Msk /*!< Rising trigger event configuration bit of line 32 */
-#define EXTI_RTSR2_TR33_Pos (1U)
-#define EXTI_RTSR2_TR33_Msk (0x1U << EXTI_RTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR2_TR33 EXTI_RTSR2_TR33_Msk /*!< Rising trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
-#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#define EXTI_RTSR2_RT32 EXTI_RTSR2_TR32
+#if defined(EXTI_RTSR2_TR33)
+#define EXTI_RTSR2_RT33 EXTI_RTSR2_TR33
+#endif
+#if defined(EXTI_RTSR2_TR34)
+#define EXTI_RTSR2_RT34 EXTI_RTSR2_TR34
+#endif
+#if defined(EXTI_RTSR2_TR35)
+#define EXTI_RTSR2_RT35 EXTI_RTSR2_TR35
+#endif
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_TR32_Pos (0U)
#define EXTI_FTSR2_TR32_Msk (0x1U << EXTI_FTSR2_TR32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_TR32 EXTI_FTSR2_TR32_Msk /*!< Falling trigger event configuration bit of line 32 */
-#define EXTI_FTSR2_TR33_Pos (1U)
-#define EXTI_FTSR2_TR33_Msk (0x1U << EXTI_FTSR2_TR33_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR2_TR33 EXTI_FTSR2_TR33_Msk /*!< Falling trigger event configuration bit of line 33 */
/* References Defines */
-#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
-#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#define EXTI_FTSR2_FT32 EXTI_FTSR2_TR32
+#if defined(EXTI_FTSR2_TR33)
+#define EXTI_FTSR2_FT33 EXTI_FTSR2_TR33
+#endif
+#if defined(EXTI_FTSR2_TR34)
+#define EXTI_FTSR2_FT34 EXTI_FTSR2_TR34
+#endif
+#if defined(EXTI_FTSR2_TR35)
+#define EXTI_FTSR2_FT35 EXTI_FTSR2_TR35
+#endif
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWIER32_Pos (0U)
#define EXTI_SWIER2_SWIER32_Msk (0x1U << EXTI_SWIER2_SWIER32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWIER32 EXTI_SWIER2_SWIER32_Msk /*!< Software Interrupt on line 32 */
-#define EXTI_SWIER2_SWIER33_Pos (1U)
-#define EXTI_SWIER2_SWIER33_Msk (0x1U << EXTI_SWIER2_SWIER33_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER2_SWIER33 EXTI_SWIER2_SWIER33_Msk /*!< Software Interrupt on line 33 */
/* References Defines */
-#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
-#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWIER32
+#if defined(EXTI_SWIER2_SWIER33)
+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWIER33
+#endif
+#if defined(EXTI_SWIER2_SWIER34)
+#define EXTI_SWIER2_SWI34 EXTI_SWIER2_SWIER34
+#endif
+#if defined(EXTI_SWIER2_SWIER35)
+#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWIER35
+#endif
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PR32_Pos (0U)
#define EXTI_PR2_PR32_Msk (0x1U << EXTI_PR2_PR32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PR32 EXTI_PR2_PR32_Msk /*!< Pending bit for line 32 */
-#define EXTI_PR2_PR33_Pos (1U)
-#define EXTI_PR2_PR33_Msk (0x1U << EXTI_PR2_PR33_Pos) /*!< 0x00000002 */
-#define EXTI_PR2_PR33 EXTI_PR2_PR33_Msk /*!< Pending bit for line 33 */
/* References Defines */
-#define EXTI_PR2_PIF32 EXTI_PR2_PR32
-#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#define EXTI_PR2_PIF32 EXTI_PR2_PR32
+#if defined(EXTI_PR2_PR33)
+#define EXTI_PR2_PIF33 EXTI_PR2_PR33
+#endif
+#if defined(EXTI_PR2_PR34)
+#define EXTI_PR2_PIF34 EXTI_PR2_PR34
+#endif
+#if defined(EXTI_PR2_PR35)
+#define EXTI_PR2_PIF35 EXTI_PR2_PR35
+#endif
+
/******************************************************************************/
/* */
@@ -12980,6 +13037,7 @@
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
+
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
@@ -14713,6 +14771,10 @@
/************************** TIM Instances : Advanced-control timers ***********/
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
/****************** TIM Instances : supporting clock selection ****************/
#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.3.0
- * @date 29-April-2015
+ * @version V2.3.1
+ * @date 16-December-2016
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -121,11 +121,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.3.0
+ * @brief CMSIS Device version number V2.3.1
*/
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/system_stm32f3xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/system_stm32f3xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/system_stm32f3xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/device/system_stm32f3xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.3.0 - * @date 29-April-2015 + * @version V2.3.1 + * @date 16-December-2016 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F334R8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F3/device/Release_Notes_stm32f3xx_hal.html Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/Release_Notes_stm32f3xx_hal.html Thu Feb 02 17:01:33 2017 +0000
@@ -676,7 +676,60 @@
<tr style="">
<td style="padding: 0in;" valign="top">
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0
+/ 16-December-2016</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main changes</span></u></b>
+</p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
+enhancements implementation</span></span></li></ul><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal">
+
+<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Enhance HAL delay and time base implementation</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
+new templates
+stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c
+and stm32f0xx_hal_timebase_tim_template.c which can be used to override
+the native
+HAL time base functions (defined as weak) to use either RTC or
+Timer as time
+base tick source. For more details about the usage of these drivers,
+please refer to HAL\HAL_TimeBase examples </span><span style="font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">and FreeRTOS-based applications</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black; font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.3.0</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL CEC </span>driver:<span class="Apple-converted-space"> </span> Overall driver rework with compatibility break versus previous HAL version</span><br><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove
+HAL CEC receive interrupt process function HAL_CEC_Receive_IT()
+and enable the "receive" mode during the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
+field from the CEC_InitTypeDef structure and manage
+it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana; color: black;"><span style="font-style: italic;">HAL TIM driver </span>: add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure</span><br><br></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update HAL Driver compliancy with:</span></li><ul style="color: black;"><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL CEC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall driver rework with break of compatibility with HAL V1.3.0<br></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
+field from the CEC_InitTypeDef structure and manage
+it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update driver to implement the new CEC state machine:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">"rxState"</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>field in CEC_HandleTypeDef structure to provide the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update CEC process to manage the new CEC states.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;">/</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">IRDA/SMARTCARD</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">IRQ Handler global optimization </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add error management in case of DMA transfer through
+ </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">XferAbortCallback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">The user Timeout value must be estimated for the overall process
+duration</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI</span></b><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"></span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in; color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Polling mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: black;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Interrupt mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Minimize access on SPI registers</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">All modes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update timeout management to check on global processes</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update error code management in all processes</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in polling mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()<o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in interrupt mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Prevent data packing mode
+in reception for </span><span style="font-size: 10pt; font-family: "Arial",sans-serif;" lang="EN-US">STM32F302xC, STM32F303xC, STM32F373xC, STM32F358xx, STM32F378xx</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-size: 10pt; font-family: "Arial",sans-serif;" lang="EN-US">Add check of DMA handle definition before calling HAL_SPI_Receive_DMA, HAL_SPI_Transmit_DMA, HAL_SPI_TransmitReceive_DMA</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(a null statement shall only occur on a line by itself).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.8 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(statement forming the body of a switch, while, do
while or for statement shall be a compound statement).</span></li></ul></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA</span></b></li><ul style="color: black;"><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Global
+ driver code optimization to reduce memory footprint </span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to
+ register/unregister the different callbacks identified by the enum
+ typedef HAL_DMA_CallbackIDTypeDef</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
+ new Error Code HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove
+ DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in
+ HAL_DMA_StateTypeDef</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HA<span style="color: black;">L I2C</span></span></span><span style="font-size: 10pt; font-family: Verdana; color: rgb(51, 102, 255);"><span style="font-weight: bold;"></span></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Move I2C_NO_OPTION_FRAME in private section</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: rgb(51, 102, 255);" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Update IS_I2C_FASTMODEPLUS macro. Add I2C_FMP_NOT_SUPPORTED definition</span><br></span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">On slave, reset LISTEN_TX state in case of direction change</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Remove GCC warnings</span><br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE
+bit from TIMx_CR1 register</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New
+API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and
+__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit
+from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add TIM1 ETR remap enums for STM32F334xx devices</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIMEx_RemapConfig() prototype changed for STM32F334x8 device<br></span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">Remove
+TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">API update : Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() function to disable MOE bit without condition</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove useless XferSize field initialisation in HAL_SMBUS_Slave_Transmit_IT()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt; color: black;" class="MsoNormal"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;">Add
+support of Zone read/write feature thanks to new XferOptions parameter
+values SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC,
+SMBUS_OTHER_AND_LAST_FRAME_NO_PEC and
+SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
+ PCD </span></li><ul style="color: red;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules : (10.3, 105) </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.3 (illegal explicit conversion from underlying MISRA type "unsigned int" to "uint32_t *").</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL PWR</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename PWR_CR register defines to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCxEN ==> ENSDx</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename RCC_CFGR register defines </span><span style="font-size: 10pt; font-family: Verdana;">to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCPRE ==> SDPRE</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL CORTEX </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_MPU_Disable() to clear the whole control register. Also remove STATIC INLINE and move function to c file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL CAN </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add __HAL_UNLOCK() call when all mailboxes are busy</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when timeout is reached<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL ADC </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add ADC_EXTERNALTRIGINJECCONV_T2_CC1 and ADC_EXTERNALTRIGINJECCONV_T2_TRGO definitions</span></li></ul></ul>
+<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL COMP</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Creation of generic defines for defines specific to COMP instances</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modify definition of LL_COMP_OUTPUT_TIM4_IC2_COMP4, LL_COMP_OUTPUT_TIM4_IC3_COMP5 and LL_COMP_OUTPUT_TIM4_IC4_COMP6 literals</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Rename
+LL_COMP_OUTPUT_TIM1_IC4_COMP2 and LL_COMP_OUTPUT_TIM1_IC4_COMP1_2 in
+LL_COMP_OUTPUT_TIM2_IC4_COMP2 and LL_COMP_OUTPUT_TIM2_IC4_COMP1_2</span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;"></span></span><span style="font-family: Verdana; font-size: 10pt; color: black;">Correct COMP inputs definition</span><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;"></span><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL EXTI</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Move
+LL_EXTI_LINE_18, LL_EXTI_LINE_33, LL_EXTI_LINE_34, LL_EXTI_LINE_35,
+LL_EXTI_LINE_36, LL_EXTI_LINE_37, LL_EXTI_LINE_38 and LL_EXTI_LINE_39
+defines under compilation switch (</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">availability depends on devices)</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL PWR</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename PWR_CR register defines to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;">: SDADCxEN ==> ENSDx</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RCC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename RCC_CFGR register defines </span><span style="font-size: 10pt; font-family: Verdana;">to be aligned with </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F3xx Reference Manual</span><span style="font-size: 10pt; font-family: Verdana;"> : SDADCPRE ==> SDPRE</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL SYSTEM</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: rgb(51, 102, 255);"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add LL_SYSCFG_EnableIT_FPU_xxx functions</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="color: black;">Replace
+LL_SYSCFG_TIM18_RMP_DMA2_CH4 and LL_SYSCFG_TIM18_RMP_DMA1_CH4 by
+LL_SYSCFG_TIM18_RMP_DMA2_CH5 and LL_SYSCFG_TIM18_RMP_DMA1_CH5</span><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F3xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename
+LL_TIM_TIM16_TI1_RMP defines : LL_TIM_TIM16_TI1_RMP_GPIO,
+LL_TIM_TIM16_TI1_RMP_RTC, LL_TIM_TIM16_TI1_RMP_HSE_32,
+LL_TIM_TIM16_TI1_RMP_MCO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Remove
+TIM_CR2_OIS2N, TIM_CR2_OIS3, TIM_CR2_OIS3N, TIM_CR2_OIS4 managment for STM32F373xC and STM32F378xx devices</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Move
+LL_TIM_OCREF_CLR_INT_OCREF_CLR and LL_TIM_OCREF_CLR_INT_ETR
+defines under compilation switch (</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">availability depends on devices)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana; font-size: 10pt;">New APIs to insure BDTR register initialization in a single write operation </span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">LL_TIM_BDTR_StructInit()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">LL_TIM_BDTR_Init()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span></span></li><ul style="color: black;"><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL HRTIM</span></span></li><ul style="color: black;"><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt;">Add shift operation in HRTIM_TIM_SetCompareMode()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_I2C</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
/ 12-Sept-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32_hal_legacy.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32_hal_legacy.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -138,6 +138,7 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -240,9 +241,9 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -355,6 +356,7 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 + /** * @} */ @@ -852,6 +854,8 @@ #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 +#define __DIV_LPUART UART_DIV_LPUART + #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK @@ -913,48 +917,48 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} @@ -2227,26 +2231,26 @@ #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET @@ -2648,10 +2652,22 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY -#if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE -#define RCC_IT_CSS RCC_IT_CSSHSE -#endif +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG @@ -2768,11 +2784,14 @@ #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE - +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -70,18 +70,18 @@
* @{
*/
/**
- * @brief STM32F3xx HAL Driver version number V1.3.0
+ * @brief STM32F3xx HAL Driver version number V1.4.0
*/
-#define __STM32F3xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F3xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F3xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24)\
- |(__STM32F3xx_HAL_VERSION_SUB1 << 16)\
- |(__STM32F3xx_HAL_VERSION_SUB2 << 8 )\
+#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F3xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
+#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
+#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
+ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32F3xx_HAL_VERSION_RC))
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+#define IDCODE_DEVID_MASK (0x00000FFFU)
/**
* @}
*/
@@ -154,7 +154,7 @@
HAL_StatusTypeDef HAL_Init(void)
{
/* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0)
+#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
@@ -237,10 +237,10 @@
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(SystemCoreClock / 1000);
+ HAL_SYSTICK_Config(SystemCoreClock / 1000U);
/*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
/* Return function status */
return HAL_OK;
@@ -367,7 +367,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE) >> 16);
+ return((DBGMCU->IDCODE) >> 16U);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@@ -80,9 +80,9 @@
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- CFGR2 Register ---*/
/* Alias word address of BYP_ADDR_PAR bit */
-#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
+#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
#define BYPADDRPAR_BitNumber 0x04
-#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
+#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
/**
* @}
*/
@@ -96,54 +96,54 @@
* - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
* @{
*/
-#define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
-#define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
- 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
-#define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
- 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
-#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
-#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
- 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
-#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
- 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
-#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
- 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
+#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4U) */
+#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
+ 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6U) */
+#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
+ 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7U) */
+#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3U) */
+#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
+ 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4U) */
+#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
+#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
+ 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
#if defined(SYSCFG_CFGR3_DMA_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
-#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
+#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 4 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 11: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 01: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
- 10: Map on DMA1 channel 4 */
-#define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 11: Map on DMA1 channel 2U */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 01: Map on DMA1 channel 4U */
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 10: Map on DMA1 channel 6U */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 11: Map on DMA1 channel 3U */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 01: Map on DMA1 channel 5U */
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 10: Map on DMA1 channel 7U */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 11: Map on DMA1 channel 7U */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 01: Map on DMA1 channel 3U */
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+ 10: Map on DMA1 channel 5U */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 11: Map on DMA1 channel 6U */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 01: Map on DMA1 channel 2U */
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+ 10: Map on DMA1 channel 4U */
+#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
x0: No remap (ADC2 on DMA2)
- 10: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
- 11: Map on DMA1 channel 4 */
+ 10: Map on DMA1 channel 2U */
+#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
+ 11: Map on DMA1 channel 4U */
#endif /* SYSCFG_CFGR3_DMA_RMP */
#if defined(SYSCFG_CFGR3_DMA_RMP)
@@ -190,20 +190,20 @@
* - 01: CFGR3 register in SYSCFG
* @{
*/
-#define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
+#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
0: No remap (DAC trigger is TIM8_TRGO)
1: Remap (DAC trigger is TIM3_TRGO) */
-#define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
+#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
0: No remap
1: Remap (TIM1_TRG3 = TIM17_OC) */
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
-#define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
+#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
-#define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: Remap (DAC trigger is TIM15_TRGO)
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
-#define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
+#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: No remap
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
@@ -241,7 +241,7 @@
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
- 0: No remap (EXTI line 15)
+ 0: No remap (EXTI line 15U)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
@@ -250,11 +250,11 @@
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U))
/**
* @}
*/
@@ -283,13 +283,13 @@
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
- 0: No remap (EXTI line 15)
+ 0: No remap (EXTI line 15U)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
1: Remap (TIM20_CC4) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
- 0: No remap (EXTI line 2)
+ 0: No remap (EXTI line 2U)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
0: No remap (TIM4_CC1)
@@ -310,17 +310,17 @@
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U) == HAL_REMAPADCTRIGGER_ADC12_EXT13U) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U) == HAL_REMAPADCTRIGGER_ADC12_EXT15U) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15U) == HAL_REMAPADCTRIGGER_ADC34_EXT15U) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
- (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11U) == HAL_REMAPADCTRIGGER_ADC34_JEXT11U) || \
+ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14U) == HAL_REMAPADCTRIGGER_ADC34_JEXT14U))
/**
* @}
*/
@@ -356,34 +356,34 @@
/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
* @{
*/
-#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
-#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
-#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
-#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
+#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0U */
+#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1U */
+#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2U */
+#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3U */
#if defined(SYSCFG_RCR_PAGE4)
/* More than 4KB CCM-SRAM defined */
-#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
-#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
-#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
-#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
+#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4U */
+#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5U */
+#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6U */
+#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7U */
#endif /* SYSCFG_RCR_PAGE4 */
#if defined(SYSCFG_RCR_PAGE8)
-#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
-#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
-#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
-#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
-#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
-#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
-#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
-#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
+#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8U */
+#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9U */
+#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10U) /*!< ICODE SRAM Write protection page 10U */
+#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11U) /*!< ICODE SRAM Write protection page 11U */
+#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12U) /*!< ICODE SRAM Write protection page 12U */
+#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13U) /*!< ICODE SRAM Write protection page 13U */
+#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14U) /*!< ICODE SRAM Write protection page 14U */
+#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15U) /*!< ICODE SRAM Write protection page 15U */
#endif /* SYSCFG_RCR_PAGE8 */
#if defined(SYSCFG_RCR_PAGE8)
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF))
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
#elif defined(SYSCFG_RCR_PAGE4)
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF))
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
#else
-#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F))
+#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
#endif /* SYSCFG_RCR_PAGE8 */
/**
* @}
@@ -571,7 +571,7 @@
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
@@ -579,13 +579,13 @@
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
#if defined(SYSCFG_CFGR1_MEM_MODE_2)
#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
/**
* @}
@@ -605,7 +605,7 @@
*/
#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
@@ -613,7 +613,7 @@
*/
#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
@@ -621,7 +621,7 @@
*/
#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
/**
* @}
@@ -638,22 +638,22 @@
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
- }while(0)
+ }while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
- }while(0)
+ }while(0U)
#elif defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
*/
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
- }while(0)
+ }while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
/**
* @}
@@ -668,11 +668,11 @@
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0)
+ }while(0U)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -685,11 +685,11 @@
*/
#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 |= (__INTERRUPT__); \
- }while(0)
+ }while(0U)
#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -730,7 +730,7 @@
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -746,7 +746,7 @@
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -762,7 +762,7 @@
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -779,22 +779,22 @@
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
- }while(0)
+ }while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
- }while(0)
+ }while(0U)
#else
/** @brief Trigger remapping enable/disable macros
* @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
*/
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
- }while(0)
+ }while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
- }while(0)
+ }while(0U)
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
/**
* @}
@@ -809,10 +809,10 @@
*/
#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
- }while(0)
+ }while(0U)
#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
- }while(0)
+ }while(0U)
/**
* @}
*/
@@ -827,7 +827,7 @@
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
*/
-#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
+#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
/**
* @}
*/
@@ -843,7 +843,7 @@
*/
#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
SYSCFG->RCR |= (__PAGE_WP__); \
- }while(0)
+ }while(0U)
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_adc.c * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_adc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
@@ -71,36 +71,36 @@
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */
/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
+#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -84,10 +84,10 @@
/* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
/* resolution 12 bits. */
/* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
- #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
- #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
- #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11)
+ #define ADC_CALIBRATION_TIMEOUT ( 10U)
+ #define ADC_ENABLE_TIMEOUT ( 2U)
+ #define ADC_DISABLE_TIMEOUT ( 2U)
+ #define ADC_STOP_CONVERSION_TIMEOUT ( 11U)
/* Timeout to wait for current conversion on going to be completed. */
/* Timeout fixed to worst case, for 1 channel. */
@@ -95,17 +95,17 @@
/* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
/* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
/* Unit: cycles of CPU clock. */
- #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928)
+ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U)
/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
/* Unit: us */
- #define ADC_STAB_DELAY_US ((uint32_t) 10)
+ #define ADC_STAB_DELAY_US ( 10U)
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
/* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+ #define ADC_TEMPSENSOR_DELAY_US ( 10U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
@@ -117,34 +117,34 @@
/* Values defined to be higher than worst cases: low clocks freq, */
/* maximum prescaler. */
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
/* Unit: ms */
- #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
- #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_ENABLE_TIMEOUT ( 2U)
+ #define ADC_DISABLE_TIMEOUT ( 2U)
/* Delay for ADC calibration: */
/* Hardware prerequisite before starting a calibration: the ADC must have */
/* been in power-on state for at least two ADC clock cycles. */
/* Unit: ADC clock cycles */
- #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
+ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U)
/* Timeout value for ADC calibration */
/* Value defined to be higher than worst cases: low clocks freq, */
/* maximum prescaler. */
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
- /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
+ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
/* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
+ #define ADC_CALIBRATION_TIMEOUT ( 10U)
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
- #define ADC_STAB_DELAY_US ((uint32_t) 1)
+ #define ADC_STAB_DELAY_US ( 1U)
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+ #define ADC_TEMPSENSOR_DELAY_US ( 10U)
/* Maximum number of CPU cycles corresponding to 1 ADC cycle */
/* Value fixed to worst case: clock prescalers slowing down ADC clock to */
@@ -152,19 +152,19 @@
/* - AHB prescaler: 16 */
/* - ADC prescaler: 8 */
/* Unit: cycles of CPU clock. */
- #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128)
+ #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U)
/* ADC conversion cycles (unit: ADC clock cycles) */
/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
/* resolution 12 bits) */
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
- #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U)
+ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U)
#endif /* STM32F373xC || STM32F378xx */
/**
* @}
@@ -254,8 +254,8 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
- uint32_t tmpCFGR = 0;
- __IO uint32_t wait_loop_index = 0;
+ uint32_t tmpCFGR = 0U;
+ __IO uint32_t wait_loop_index = 0U;
/* Check ADC handle */
if(hadc == NULL)
@@ -304,8 +304,8 @@
ADC_CLEAR_ERRORCODE(hadc);
/* Initialize HAL ADC API internal variables */
- hadc->InjectionConfig.ChannelCount = 0;
- hadc->InjectionConfig.ContextQueue = 0;
+ hadc->InjectionConfig.ChannelCount = 0U;
+ hadc->InjectionConfig.ContextQueue = 0U;
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
@@ -339,13 +339,13 @@
/* Set the intermediate state before moving the ADC voltage */
/* regulator to state enable. */
CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
- /* Set ADVREGEN bits to 0x01 */
+ /* Set ADVREGEN bits to 0x01U */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
/* Delay for ADC stabilization time. */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -501,7 +501,7 @@
/* Configuration of regular group sequencer: */
/* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
/* Parameter "NbrOfConversion" is discarded. */
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
@@ -512,7 +512,7 @@
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1 ,
ADC_SQR1_L ,
- (hadc->Init.NbrOfConversion - (uint8_t)1) );
+ (hadc->Init.NbrOfConversion - (uint8_t)1U) );
}
else
{
@@ -573,9 +573,9 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmp_cr1 = 0;
- uint32_t tmp_cr2 = 0;
- uint32_t tmp_sqr1 = 0;
+ uint32_t tmp_cr1 = 0U;
+ uint32_t tmp_cr2 = 0U;
+ uint32_t tmp_sqr1 = 0U;
/* Check ADC handle */
if(hadc == NULL)
@@ -642,7 +642,7 @@
/* Configuration of ADC: */
/* - data alignment */
/* - external trigger to start conversion */
- /* - external trigger polarity (always set to 1, because needed for all */
+ /* - external trigger polarity (always set to 1U, because needed for all */
/* triggers: external trigger of SW start) */
/* - continuous conversion mode */
/* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */
@@ -702,7 +702,7 @@
/* Configuration of regular group sequencer: */
/* - if scan mode is disabled, regular channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
/* Parameter "NbrOfConversion" is discarded. */
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
@@ -864,7 +864,7 @@
/* 1. Set the intermediate state before moving the ADC voltage regulator */
/* to disable state. */
CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
- /* 2. Set ADVREGEN bits to 0x10 */
+ /* 2. Set ADVREGEN bits to 0x10U */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1);
/* Reset register CFGR */
@@ -1519,7 +1519,7 @@
uint32_t tickstart;
uint32_t tmp_Flag_EOC;
ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmp_cfgr = 0x0;
+ uint32_t tmp_cfgr = 0x0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1598,7 +1598,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1683,8 +1683,8 @@
uint32_t tickstart;
/* Variables for polling in case of scan mode enabled */
- uint32_t Conversion_Timeout_CPU_cycles_max = 0;
- uint32_t Conversion_Timeout_CPU_cycles = 0;
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1709,10 +1709,10 @@
/* Polling for end of conversion: differentiation if single/sequence */
/* conversion. */
/* - If single conversion for regular group (Scan mode disabled or enabled */
- /* with NbrOfConversion =1), flag EOC is used to determine the */
+ /* with NbrOfConversion =1U), flag EOC is used to determine the */
/* conversion completion. */
/* - If sequence conversion for regular group (scan mode enabled and */
- /* NbrOfConversion >=2), flag EOC is set only at the end of the */
+ /* NbrOfConversion >=2U), flag EOC is set only at the end of the */
/* sequence. */
/* To poll for each conversion, the maximum conversion time is computed */
/* from ADC conversion time (selected sampling time + conversion time of */
@@ -1729,7 +1729,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1757,7 +1757,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1834,7 +1834,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1853,7 +1853,7 @@
/* Analog watchdog (level out of window) event */
/* Note: In case of several analog watchdog enabled, if needed to know */
/* which one triggered and on which ADCx, test ADC state of analog watchdog */
- /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
+ /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */
/* For example: */
/* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */
/* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */
@@ -1951,7 +1951,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -2819,10 +2819,10 @@
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
{
- uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
+ uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
ADC_Common_TypeDef *tmpADC_Common;
- uint32_t tmp_cfgr = 0x0;
- uint32_t tmp_cfgr_jqm = 0x0;
+ uint32_t tmp_cfgr = 0x0U;
+ uint32_t tmp_cfgr_jqm = 0x0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3044,7 +3044,7 @@
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
{
- overrun_error = 1;
+ overrun_error = 1U;
}
else
{
@@ -3058,7 +3058,7 @@
{
if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
{
- overrun_error = 1;
+ overrun_error = 1U;
}
}
else
@@ -3066,12 +3066,12 @@
/* MultiMode is enabled, Common Control Register MDMA bits must be checked */
if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
{
- overrun_error = 1;
+ overrun_error = 1U;
}
}
}
- if (overrun_error == 1)
+ if (overrun_error == 1U)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
@@ -3332,7 +3332,7 @@
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3356,7 +3356,7 @@
HAL_ADC_STATE_BUSY_INTERNAL);
/* Wait two ADC clock cycles */
- while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2)
+ while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U)
{
wait_loop_index++;
}
@@ -3873,7 +3873,7 @@
{
uint32_t tickstart;
uint32_t tmp_Flag_EOC;
- uint32_t tmp_cfgr = 0x00000000;
+ uint32_t tmp_cfgr = 0x00000000U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3910,7 +3910,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -3970,11 +3970,11 @@
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Variables for polling in case of scan mode enabled */
- uint32_t Conversion_Timeout_CPU_cycles_max =0;
- uint32_t Conversion_Timeout_CPU_cycles =0;
+ uint32_t Conversion_Timeout_CPU_cycles_max =0U;
+ uint32_t Conversion_Timeout_CPU_cycles =0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3987,10 +3987,10 @@
/* For injected group, flag JEOC is set only at the end of the sequence, */
/* not for each conversion within the sequence. */
/* - If single conversion for injected group (scan mode disabled or */
- /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
+ /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */
/* conversion completion. */
/* - If sequence conversion for injected group (scan mode enabled and */
- /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
+ /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */
/* sequence. */
/* To poll for each conversion, the maximum conversion time is computed */
/* from ADC conversion time (selected sampling time + conversion time of */
@@ -4006,7 +4006,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -4034,7 +4034,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -4789,7 +4789,7 @@
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
{
- uint32_t tmp_jdr = 0;
+ uint32_t tmp_jdr = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -4855,7 +4855,7 @@
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
{
- uint32_t tmp_jdr = 0;
+ uint32_t tmp_jdr = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -5435,7 +5435,7 @@
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
uint32_t tmpOffsetShifted;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -5447,7 +5447,7 @@
/* Verification of channel number: Channels 1 to 14 are available in */
- /* differential mode. Channels 15, 16, 17, 18 can be used only in */
+ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
/* single-ended mode. */
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
{
@@ -5470,28 +5470,28 @@
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
{
/* Regular sequence configuration */
- /* For Rank 1 to 4 */
- if (sConfig->Rank < 5)
+ /* For Rank 1 to 4U */
+ if (sConfig->Rank < 5U)
{
MODIFY_REG(hadc->Instance->SQR1,
ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
}
- /* For Rank 5 to 9 */
- else if (sConfig->Rank < 10)
+ /* For Rank 5 to 9U */
+ else if (sConfig->Rank < 10U)
{
MODIFY_REG(hadc->Instance->SQR2,
ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
- /* For Rank 10 to 14 */
- else if (sConfig->Rank < 15)
+ /* For Rank 10 to 14U */
+ else if (sConfig->Rank < 15U)
{
MODIFY_REG(hadc->Instance->SQR3 ,
ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
- /* For Rank 15 to 16 */
+ /* For Rank 15 to 16U */
else
{
MODIFY_REG(hadc->Instance->SQR4 ,
@@ -5508,14 +5508,14 @@
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
{
/* Channel sampling time configuration */
- /* For channels 10 to 18 */
+ /* For channels 10 to 18U */
if (sConfig->Channel >= ADC_CHANNEL_10)
{
MODIFY_REG(hadc->Instance->SMPR2 ,
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
}
- else /* For channels 1 to 9 */
+ else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1 ,
ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) ,
@@ -5526,7 +5526,7 @@
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
+ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
/* to 0. */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
@@ -5537,7 +5537,7 @@
switch (sConfig->OffsetNumber)
{
case ADC_OFFSET_1:
- /* Configure offset register 1 */
+ /* Configure offset register 1U */
MODIFY_REG(hadc->Instance->OFR1 ,
ADC_OFR1_OFFSET1_CH |
ADC_OFR1_OFFSET1 ,
@@ -5547,7 +5547,7 @@
break;
case ADC_OFFSET_2:
- /* Configure offset register 2 */
+ /* Configure offset register 2U */
MODIFY_REG(hadc->Instance->OFR2 ,
ADC_OFR2_OFFSET2_CH |
ADC_OFR2_OFFSET2 ,
@@ -5557,7 +5557,7 @@
break;
case ADC_OFFSET_3:
- /* Configure offset register 3 */
+ /* Configure offset register 3U */
MODIFY_REG(hadc->Instance->OFR3 ,
ADC_OFR3_OFFSET3_CH |
ADC_OFR3_OFFSET3 ,
@@ -5567,7 +5567,7 @@
break;
case ADC_OFFSET_4:
- /* Configure offset register 4 */
+ /* Configure offset register 4U */
MODIFY_REG(hadc->Instance->OFR4 ,
ADC_OFR4_OFFSET4_CH |
ADC_OFR4_OFFSET4 ,
@@ -5625,18 +5625,18 @@
/* Channel sampling time configuration (channel ADC_INx +1 */
/* corresponding to differential negative input). */
- /* For channels 10 to 18 */
+ /* For channels 10 to 18U */
if (sConfig->Channel >= ADC_CHANNEL_10)
{
MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1) ,
- ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1) );
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
+ ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
}
- else /* For channels 1 to 9 */
+ else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1) ,
- ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1) );
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) ,
+ ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) );
}
}
@@ -5681,8 +5681,8 @@
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -5766,7 +5766,7 @@
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -5779,21 +5779,21 @@
/* Regular sequence configuration */
- /* For Rank 1 to 6 */
- if (sConfig->Rank < 7)
+ /* For Rank 1 to 6U */
+ if (sConfig->Rank < 7U)
{
MODIFY_REG(hadc->Instance->SQR3 ,
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
- /* For Rank 7 to 12 */
- else if (sConfig->Rank < 13)
+ /* For Rank 7 to 12U */
+ else if (sConfig->Rank < 13U)
{
MODIFY_REG(hadc->Instance->SQR2 ,
ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
}
- /* For Rank 13 to 16 */
+ /* For Rank 13 to 16U */
else
{
MODIFY_REG(hadc->Instance->SQR1 ,
@@ -5803,14 +5803,14 @@
/* Channel sampling time configuration */
- /* For channels 10 to 18 */
+ /* For channels 10 to 18U */
if (sConfig->Channel > ADC_CHANNEL_10)
{
MODIFY_REG(hadc->Instance->SMPR1 ,
ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) ,
ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
}
- else /* For channels 0 to 9 */
+ else /* For channels 0 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR2 ,
ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) ,
@@ -5828,8 +5828,8 @@
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -5901,11 +5901,11 @@
ADC_Common_TypeDef *tmpADC_Common;
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
uint32_t tmpOffsetShifted;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Injected context queue feature: temporary JSQR variables defined in */
/* static to be passed over calls of this function */
- uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
+ uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -5926,7 +5926,7 @@
}
/* Verification of channel number: Channels 1 to 14 are available in */
- /* differential mode. Channels 15, 16, 17, 18 can be used only in */
+ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */
/* single-ended mode. */
if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
{
@@ -5946,10 +5946,10 @@
/* */
/* - if scan mode is disabled: */
/* * Injected channels sequence length is set to 0x00: 1 channel */
- /* converted (channel on injected rank 1) */
+ /* converted (channel on injected rank 1U) */
/* Parameter "InjectedNbrOfConversion" is discarded. */
/* * Injected context register JSQR setting is simple: register is fully */
- /* defined on one call of this function (for injected rank 1) and can */
+ /* defined on one call of this function (for injected rank 1U) and can */
/* be entered into queue directly. */
/* - if scan mode is enabled: */
/* * Injected channels sequence length is set to parameter */
@@ -5962,7 +5962,7 @@
/* by software for alignment over all STM32 devices. */
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
- (sConfigInjected->InjectedNbrOfConversion == 1) )
+ (sConfigInjected->InjectedNbrOfConversion == 1U) )
{
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer: fixed to 1st rank */
@@ -6023,13 +6023,13 @@
/* 1. Start new context and set parameters related to all injected */
/* channels: injected sequence length and trigger */
- if (hadc->InjectionConfig.ChannelCount == 0)
+ if (hadc->InjectionConfig.ChannelCount == 0U)
{
/* Initialize number of channels that will be configured on the context */
/* being built */
hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
/* Initialize value that will be set into register JSQR */
- hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
+ hadc->InjectionConfig.ContextQueue = 0x00000000U;
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer */
@@ -6043,13 +6043,13 @@
/* software start. */
if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
- SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) |
ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) |
sConfigInjected->ExternalTrigInjecConvEdge );
}
else
{
- SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
+ SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) );
}
}
@@ -6067,7 +6067,7 @@
/* 3. End of context setting: If last channel set, then write context */
/* into register JSQR and make it enter into queue */
- if (hadc->InjectionConfig.ChannelCount == 0)
+ if (hadc->InjectionConfig.ChannelCount == 0U)
{
/* Update ADC register JSQR */
MODIFY_REG(hadc->Instance->JSQR ,
@@ -6160,14 +6160,14 @@
/* Channel sampling time configuration */
- /* For channels 10 to 18 */
+ /* For channels 10 to 18U */
if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
{
MODIFY_REG(hadc->Instance->SMPR2 ,
ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) ,
ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
}
- else /* For channels 1 to 9 */
+ else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1 ,
ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) ,
@@ -6177,7 +6177,7 @@
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset in function of the selected ADC resolution. */
- /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set */
+ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
/* to 0. */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
@@ -6188,7 +6188,7 @@
switch (sConfigInjected->InjectedOffsetNumber)
{
case ADC_OFFSET_1:
- /* Configure offset register 1 */
+ /* Configure offset register 1U */
MODIFY_REG(hadc->Instance->OFR1 ,
ADC_OFR1_OFFSET1_CH |
ADC_OFR1_OFFSET1 ,
@@ -6198,7 +6198,7 @@
break;
case ADC_OFFSET_2:
- /* Configure offset register 2 */
+ /* Configure offset register 2U */
MODIFY_REG(hadc->Instance->OFR2 ,
ADC_OFR2_OFFSET2_CH |
ADC_OFR2_OFFSET2 ,
@@ -6208,7 +6208,7 @@
break;
case ADC_OFFSET_3:
- /* Configure offset register 3 */
+ /* Configure offset register 3U */
MODIFY_REG(hadc->Instance->OFR3 ,
ADC_OFR3_OFFSET3_CH |
ADC_OFR3_OFFSET3 ,
@@ -6218,7 +6218,7 @@
break;
case ADC_OFFSET_4:
- /* Configure offset register 4 */
+ /* Configure offset register 4U */
MODIFY_REG(hadc->Instance->OFR4 ,
ADC_OFR4_OFFSET4_CH |
ADC_OFR4_OFFSET4 ,
@@ -6276,18 +6276,18 @@
/* Channel sampling time configuration (channel ADC_INx +1 */
/* corresponding to differential negative input). */
- /* For channels 10 to 18 */
+ /* For channels 10 to 18U */
if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
{
MODIFY_REG(hadc->Instance->SMPR2,
- ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1),
- ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
+ ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U),
+ ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
}
- else /* For channels 1 to 9 */
+ else /* For channels 1 to 9U */
{
MODIFY_REG(hadc->Instance->SMPR1,
- ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1),
- ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1) );
+ ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U),
+ ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) );
}
}
@@ -6332,8 +6332,8 @@
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -6404,7 +6404,7 @@
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -6426,7 +6426,7 @@
/* Configuration of injected group sequencer: */
/* - if scan mode is disabled, injected channels sequence length is set to */
- /* 0x00: 1 channel converted (channel on regular rank 1) */
+ /* 0x00: 1 channel converted (channel on regular rank 1U) */
/* Parameter "InjectedNbrOfConversion" is discarded. */
/* Note: Scan mode is present by hardware on this device and, if */
/* disabled, discards automatically nb of conversions. Anyway, nb of */
@@ -6446,7 +6446,7 @@
ADC_JSQR_JSQ1 ,
ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
ADC_INJECTED_RANK_1,
- 0x01) );
+ 0x01U) );
}
/* If another injected rank than rank1 was intended to be set, and could */
/* not due to ScanConvMode disabled, error is reported. */
@@ -6607,8 +6607,8 @@
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -6692,7 +6692,7 @@
/* - Set the analog watchdog enable mode: regular and/or injected */
/* groups, one or overall group of channels. */
/* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
MODIFY_REG(hadc->Instance->CFGR ,
ADC_CFGR_AWD1SGL |
ADC_CFGR_JAWD1EN |
@@ -6702,7 +6702,7 @@
ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) );
/* Shift the offset in function of the selected ADC resolution: */
- /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
+ /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */
/* are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
@@ -6736,7 +6736,7 @@
else
{
/* Shift the threshold in function of the selected ADC resolution */
- /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
+ /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */
tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
@@ -6889,7 +6889,7 @@
/* - Set the analog watchdog enable mode: regular and/or injected groups, */
/* one or all channels. */
/* - Set the Analog watchdog channel (is not used if watchdog */
- /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
+ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */
MODIFY_REG(hadc->Instance->CR1 ,
ADC_CR1_AWDSGL |
ADC_CR1_JAWDEN |
@@ -7071,7 +7071,7 @@
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
- /* Note: On STM32F1 devices, in case of sequencer enabled */
+ /* Note: On STM32F3 devices, in case of sequencer enabled */
/* (several ranks selected), end of conversion flag is raised */
/* at the end of the sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
@@ -7143,7 +7143,7 @@
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@@ -7197,7 +7197,7 @@
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
@@ -7256,9 +7256,9 @@
*/
static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
{
- uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
- uint32_t tickstart = 0;
- uint32_t Conversion_Timeout_CPU_cycles = 0;
+ uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -7272,7 +7272,7 @@
/* auto-delay mode. */
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
/* injected group stop ADC_CR_JADSTP). */
- /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
+ /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */
/* (see reference manual). */
if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) &&
(hadc->Init.ContinuousConvMode==ENABLE) &&
@@ -7284,7 +7284,7 @@
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
{
- if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
+ if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U))
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -7304,7 +7304,7 @@
/* Stop potential conversion on going on regular group */
if (ConversionGroup != ADC_INJECTED_GROUP)
{
- /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+ /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
{
@@ -7316,7 +7316,7 @@
/* Stop potential conversion on going on injected group */
if (ConversionGroup != ADC_REGULAR_GROUP)
{
- /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+ /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
{
@@ -7377,8 +7377,8 @@
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
- __IO uint32_t wait_loop_index = 0;
+ uint32_t tickstart = 0U;
+ __IO uint32_t wait_loop_index = 0U;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@@ -7391,8 +7391,8 @@
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -7430,7 +7430,7 @@
*/
static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Verification if ADC is not already disabled: */
if (ADC_IS_ENABLE(hadc) != RESET)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
@@ -89,14 +89,14 @@
Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
uint32_t Resolution; /*!< Configures the ADC resolution.
This parameter can be a value of @ref ADCEx_Resolution */
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4, if offset enabled: MSB on register bit 14 and LSB on register bit 3).
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting)
+ or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U).
See reference manual for alignments with other resolutions.
This parameter can be a value of @ref ADCEx_Data_align */
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
Scan direction is upward: from rank1 to rank 'n'.
This parameter can be a value of @ref ADCEx_Scan_mode */
@@ -177,7 +177,7 @@
This parameter must be a value of @ref ADCEx_SingleDifferential
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
@@ -186,7 +186,7 @@
Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
}ADC_ChannelConfTypeDef;
@@ -228,7 +228,7 @@
This parameter must be a value of @ref ADCEx_SingleDifferential
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
+ Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
@@ -237,8 +237,8 @@
Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
@@ -315,11 +315,11 @@
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
}ADC_AnalogWDGConfTypeDef;
@@ -365,17 +365,17 @@
*/
typedef struct
{
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
+ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting)
+ or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U).
This parameter can be a value of @ref ADCEx_Data_align */
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+ If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U).
+ Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
Scan direction is upward: from rank1 to rank 'n'.
This parameter can be a value of @ref ADCEx_Scan_mode
- Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
+ Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U)
or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
the last conversion of the sequence. All previous conversions would be overwritten by the last one.
Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
@@ -452,8 +452,8 @@
Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
+ Depending of ADC resolution selected (12U, 10U, 8 or 6 bits),
+ this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
@@ -502,7 +502,7 @@
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
+ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */
}ADC_AnalogWDGConfTypeDef;
#endif /* STM32F373xC || STM32F378xx */
/**
@@ -518,12 +518,12 @@
/** @defgroup ADCEx_Error_Code ADC Extended Error Code
* @{
*/
-#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
+#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
-#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
+#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
/**
* @}
*/
@@ -535,22 +535,22 @@
/** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
* @{
*/
-#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
+#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
-#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
+#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */
+#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */
#endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
@@ -564,7 +564,7 @@
/** @defgroup ADCEx_Resolution ADC Extended Resolution
* @{
*/
-#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
+#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
@@ -575,7 +575,7 @@
/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
* @{
*/
-#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT (0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
/**
* @}
@@ -584,8 +584,8 @@
/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
* @{
*/
-#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
-#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
+#define ADC_SCAN_DISABLE (0x00000000U)
+#define ADC_SCAN_ENABLE (0x00000001U)
/**
* @}
*/
@@ -593,7 +593,7 @@
/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
@@ -641,12 +641,12 @@
#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#if defined(STM32F303xE) || defined(STM32F398xx)
/* ADC external triggers specific to device STM303xE: mask to differentiate */
-/* standard triggers from specific timer 20, needed for reallocation of */
-/* triggers common to ADC1&2/ADC3&4 and to avoid mixing with standard */
+/* standard triggers from specific timer 20U, needed for reallocation of */
+/* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */
/* triggers without remap. */
#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
@@ -657,8 +657,8 @@
/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
-#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
/*!< External triggers of regular group for ADC3&ADC4 only, specific to */
/* device STM303xE: : using Timer20 with ADC trigger input remap */
@@ -669,7 +669,7 @@
/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
/* ADC3_4 by driver when needed. */
#define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */
#define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
/*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
#define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
@@ -700,11 +700,11 @@
#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#if defined(STM32F302xE)
/* ADC external triggers specific to device STM302xE: mask to differentiate */
-/* standard triggers from specific timer 20, needed for reallocation of */
+/* standard triggers from specific timer 20U, needed for reallocation of */
/* triggers common to ADC1&2 and to avoind mixing with standard */
/* triggers without remap. */
#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
@@ -716,8 +716,8 @@
/*!< External triggers of regular group for ADC1&ADC2 only, specific to */
/* device STM302xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
-#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
+#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */
+#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */
#endif /* STM32F302xE */
#endif /* STM32F302xE || */
@@ -745,7 +745,7 @@
#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#endif /* STM32F303x8 || STM32F328xx */
@@ -769,7 +769,7 @@
#define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
#define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#endif /* STM32F334x8 */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
@@ -786,7 +786,7 @@
#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
/**
* @}
@@ -805,8 +805,8 @@
/** @defgroup ADCEx_Overrun ADC Extended overrun
* @{
*/
-#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) /*!< Default setting, to be used for compatibility with other STM32 devices */
-#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001)
+#define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */
+#define ADC_OVR_DATA_PRESERVED (0x00000001U)
/**
* @}
*/
@@ -840,7 +840,7 @@
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
#define ADC_CHANNEL_VBAT ADC_CHANNEL_17
-/* Note: Vopamp2/3/4 internal channels available on ADC2/3/4 respectively */
+/* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */
#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
#define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
@@ -855,7 +855,7 @@
/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
#define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
@@ -870,8 +870,8 @@
/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
* @{
*/
-#define ADC_SINGLE_ENDED ((uint32_t)0x00000000)
-#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001)
+#define ADC_SINGLE_ENDED (0x00000000U)
+#define ADC_DIFFERENTIAL_ENDED (0x00000001U)
/**
* @}
*/
@@ -879,11 +879,11 @@
/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
* @{
*/
-#define ADC_OFFSET_NONE ((uint32_t)0x00)
-#define ADC_OFFSET_1 ((uint32_t)0x01)
-#define ADC_OFFSET_2 ((uint32_t)0x02)
-#define ADC_OFFSET_3 ((uint32_t)0x03)
-#define ADC_OFFSET_4 ((uint32_t)0x04)
+#define ADC_OFFSET_NONE (0x00U)
+#define ADC_OFFSET_1 (0x01U)
+#define ADC_OFFSET_2 (0x02U)
+#define ADC_OFFSET_3 (0x03U)
+#define ADC_OFFSET_4 (0x04U)
/**
* @}
*/
@@ -891,22 +891,22 @@
/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
* @{
*/
-#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+#define ADC_REGULAR_RANK_1 (0x00000001U)
+#define ADC_REGULAR_RANK_2 (0x00000002U)
+#define ADC_REGULAR_RANK_3 (0x00000003U)
+#define ADC_REGULAR_RANK_4 (0x00000004U)
+#define ADC_REGULAR_RANK_5 (0x00000005U)
+#define ADC_REGULAR_RANK_6 (0x00000006U)
+#define ADC_REGULAR_RANK_7 (0x00000007U)
+#define ADC_REGULAR_RANK_8 (0x00000008U)
+#define ADC_REGULAR_RANK_9 (0x00000009U)
+#define ADC_REGULAR_RANK_10 (0x0000000AU)
+#define ADC_REGULAR_RANK_11 (0x0000000BU)
+#define ADC_REGULAR_RANK_12 (0x0000000CU)
+#define ADC_REGULAR_RANK_13 (0x0000000DU)
+#define ADC_REGULAR_RANK_14 (0x0000000EU)
+#define ADC_REGULAR_RANK_15 (0x0000000FU)
+#define ADC_REGULAR_RANK_16 (0x00000010U)
/**
* @}
*/
@@ -914,10 +914,10 @@
/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
* @{
*/
-#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+#define ADC_INJECTED_RANK_1 (0x00000001U)
+#define ADC_INJECTED_RANK_2 (0x00000002U)
+#define ADC_INJECTED_RANK_3 (0x00000003U)
+#define ADC_INJECTED_RANK_4 (0x00000004U)
/**
* @}
*/
@@ -925,7 +925,7 @@
/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
* @{
*/
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
@@ -971,7 +971,7 @@
#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
#if defined(STM32F303xE) || defined(STM32F398xx)
/*!< List of external triggers specific to device STM303xE: using Timer20 */
@@ -981,11 +981,11 @@
/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
/*!< External triggers of injected group for ADC3&ADC4 only, specific to */
/* device STM303xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */
/*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
/* device STM303xE: : using Timer20 with ADC trigger input remap */
@@ -994,7 +994,7 @@
#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
/*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
- /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11) */
+ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */
#endif /* STM32F303xE || STM32F398xx */
#if defined(STM32F303xC) || defined(STM32F358xx)
@@ -1079,7 +1079,7 @@
#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
#if defined(STM32F302xE)
/*!< List of external triggers specific to device STM302xE: using Timer20 */
@@ -1089,7 +1089,7 @@
/*!< External triggers of injected group for ADC1&ADC2 only, specific to */
/* device STM302xE: : using Timer20 with ADC trigger input remap */
-#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
+#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */
#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
#endif /* STM32F302xE */
@@ -1120,7 +1120,7 @@
#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
#endif /* STM32F303x8 || STM32F328xx */
#if defined(STM32F334x8)
@@ -1144,7 +1144,7 @@
#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
#endif /* STM32F334x8 */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
@@ -1155,11 +1155,13 @@
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
+#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1
+#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_INJECTED_SOFTWARE_START (0x00000001U)
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
/**
* @}
@@ -1169,7 +1171,7 @@
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
* @{
*/
-#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
+#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U))
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
@@ -1185,7 +1187,7 @@
/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
* @{
*/
-#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
+#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
/**
@@ -1195,7 +1197,7 @@
/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
* @{
*/
-#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
+#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U))
#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
@@ -1214,9 +1216,9 @@
/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
* @{
*/
-#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
-#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
-#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
+#define ADC_ANALOGWATCHDOG_1 (0x00000001U)
+#define ADC_ANALOGWATCHDOG_2 (0x00000002U)
+#define ADC_ANALOGWATCHDOG_3 (0x00000003U)
/**
* @}
*/
@@ -1224,7 +1226,7 @@
/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
@@ -1310,7 +1312,7 @@
/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
* @{
*/
-#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT (0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@@ -1319,7 +1321,7 @@
/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
* @{
*/
-#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_DISABLE (0x00000000U)
#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
/**
* @}
@@ -1328,7 +1330,7 @@
/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
/**
* @}
@@ -1358,7 +1360,7 @@
*/
/* Note: Depending on devices, some channels may not be available on package */
/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_0 (0x00000000U)
#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
@@ -1388,7 +1390,7 @@
/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
@@ -1403,22 +1405,22 @@
/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
* @{
*/
-#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+#define ADC_REGULAR_RANK_1 (0x00000001U)
+#define ADC_REGULAR_RANK_2 (0x00000002U)
+#define ADC_REGULAR_RANK_3 (0x00000003U)
+#define ADC_REGULAR_RANK_4 (0x00000004U)
+#define ADC_REGULAR_RANK_5 (0x00000005U)
+#define ADC_REGULAR_RANK_6 (0x00000006U)
+#define ADC_REGULAR_RANK_7 (0x00000007U)
+#define ADC_REGULAR_RANK_8 (0x00000008U)
+#define ADC_REGULAR_RANK_9 (0x00000009U)
+#define ADC_REGULAR_RANK_10 (0x0000000AU)
+#define ADC_REGULAR_RANK_11 (0x0000000BU)
+#define ADC_REGULAR_RANK_12 (0x0000000CU)
+#define ADC_REGULAR_RANK_13 (0x0000000DU)
+#define ADC_REGULAR_RANK_14 (0x0000000EU)
+#define ADC_REGULAR_RANK_15 (0x0000000FU)
+#define ADC_REGULAR_RANK_16 (0x00000010U)
/**
* @}
*/
@@ -1426,10 +1428,10 @@
/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
* @{
*/
-#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+#define ADC_INJECTED_RANK_1 (0x00000001U)
+#define ADC_INJECTED_RANK_2 (0x00000002U)
+#define ADC_INJECTED_RANK_3 (0x00000003U)
+#define ADC_INJECTED_RANK_4 (0x00000004U)
/**
* @}
*/
@@ -1437,7 +1439,7 @@
/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
* @{
*/
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
/**
* @}
@@ -1463,7 +1465,7 @@
/** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
@@ -1543,7 +1545,7 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of regular group for ADC1 & ADC2 */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
@@ -1561,7 +1563,7 @@
#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
/* External triggers of regular group for ADC3 & ADC4 */
-#define ADC3_4_EXTERNALTRIG_T3_CC1 ((uint32_t)0x00000000)
+#define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U)
#define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
@@ -1584,7 +1586,7 @@
defined(STM32F302xC)
/* List of external triggers of common group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
@@ -1604,7 +1606,7 @@
#if defined(STM32F303x8) || defined(STM32F328xx)
/* List of external triggers of common group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
@@ -1625,7 +1627,7 @@
#if defined(STM32F334x8)
/* List of external triggers of common group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
@@ -1644,7 +1646,7 @@
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/* List of external triggers of regular group for ADC1: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
+#define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U)
#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
@@ -1653,7 +1655,7 @@
#define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
-#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
+#define ADC_SOFTWARE_START (0x00000001U)
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
/**
* @}
@@ -1669,7 +1671,7 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers for injected groups of ADC1 & ADC2 */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
@@ -1694,9 +1696,9 @@
/* differentiation between similar triggers of common groups ADC1&ADC2, */
/* ADC3&ADC4 (Differentiation processed into macro */
/* ADC_JSQR_JEXTSEL_SET) */
-#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
-#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000)
+#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U)
#define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
@@ -1721,7 +1723,7 @@
defined(STM32F302xC)
/* List of external triggers of group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
@@ -1740,7 +1742,7 @@
#if defined(STM32F303x8) || defined(STM32F328xx)
/* List of external triggers of group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
@@ -1761,7 +1763,7 @@
#if defined(STM32F334x8)
/* List of external triggers of group ADC1&ADC2: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
@@ -1780,8 +1782,10 @@
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/* List of external triggers of injected group for ADC1: */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
-#define ADC1_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
+#define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U)
#define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
+#define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
+#define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
#define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
#define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
#define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
@@ -1815,7 +1819,7 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T19_TRGO ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U)
#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -1834,7 +1838,7 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of injected group for ADC1 */
-#define ADC_EXTERNALTRIGINJEC_T19_CC1 ((uint32_t) 0x00000000)
+#define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U)
#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@@ -1873,7 +1877,7 @@
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
-#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U)
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
@@ -1882,7 +1886,7 @@
#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U)
#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
@@ -1947,7 +1951,7 @@
do{ \
SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \
__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the ADC end of conversion interrupt.
@@ -2275,7 +2279,7 @@
* @param _CHANNELNB_: Channel number.
* @retval None
*/
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
/**
* @brief Set the ADC's sample time for Channels numbers between 10 and 18.
@@ -2283,7 +2287,7 @@
* @param _CHANNELNB_: Channel number.
* @retval None
*/
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
/**
* @brief Set the selected regular Channel rank for rank between 1 and 4.
@@ -2291,7 +2295,7 @@
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_)))
+#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
/**
* @brief Set the selected regular Channel rank for rank between 5 and 9.
@@ -2299,7 +2303,7 @@
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 5)))
+#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
/**
* @brief Set the selected regular Channel rank for rank between 10 and 14.
@@ -2307,7 +2311,7 @@
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 10)))
+#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
/**
* @brief Set the selected regular Channel rank for rank between 15 and 16.
@@ -2315,7 +2319,7 @@
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 15)))
+#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
/**
* @brief Set the selected injected Channel rank.
@@ -2323,7 +2327,7 @@
* @param _RANKNB_: Rank number.
* @retval None
*/
-#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_) +2))
+#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
/**
@@ -2331,7 +2335,7 @@
* @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
* @retval None
*/
-#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26)
+#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U)
/**
* @brief Configure the channel number into Analog Watchdog 2 or 3.
@@ -2345,49 +2349,49 @@
* @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion.
* @retval None
*/
-#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25)
+#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U)
/**
* @brief Enable ADC injected context queue
* @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode.
* @retval None
*/
-#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21)
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U)
/**
* @brief Enable ADC discontinuous conversion mode for injected group
* @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode.
* @retval None
*/
-#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20)
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U)
/**
* @brief Enable ADC discontinuous conversion mode for regular group
* @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
* @retval None
*/
-#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
+#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
/**
* @brief Configures the number of discontinuous conversions for regular group.
* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
* @retval None
*/
-#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
+#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
/**
* @brief Enable the ADC auto delay mode.
* @param _AUTOWAIT_: Auto delay bit enable or disable.
* @retval None
*/
-#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
+#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
/**
* @brief Enable ADC continuous conversion mode.
* @param _CONTINUOUS_MODE_: Continuous mode.
* @retval None
*/
-#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
+#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
/**
* @brief Enable ADC overrun mode.
@@ -2395,11 +2399,11 @@
* @retval Overrun bit setting to be programmed into CFGR register
*/
/* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
-/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */
/* as the default case to be compliant with other STM32 devices. */
#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
- )? (ADC_CFGR_OVRMOD) : (0x00000000) \
+ )? (ADC_CFGR_OVRMOD) : (0x00000000U) \
)
/**
@@ -2407,7 +2411,7 @@
* @param _DMACONTREQ_MODE_: DMA continuous request mode.
* @retval None
*/
-#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
+#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
/**
* @brief For devices with 3 ADCs or more: Defines the external trigger source
@@ -2598,7 +2602,7 @@
* @param _CHANNEL_: ADC Channel
* @retval None
*/
-#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26)
+#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U)
/**
* @brief Configure the channel number into differential mode selection register
@@ -2612,28 +2616,28 @@
* @param _Calibration_Factor_: Calibration factor value
* @retval None
*/
-#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16)
+#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
/**
* @brief Calibration factor in differential mode to be retrieved from calibration register
* @param _Calibration_Factor_: Calibration factor value
* @retval None
*/
-#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16)
+#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
/**
* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
* @param _Threshold_: Threshold value
* @retval None
*/
-#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
+#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
/**
* @brief Enable the ADC DMA continuous request for ADC multimode.
* @param _DMAContReq_MODE_: DMA continuous request mode.
* @retval None
*/
-#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13)
+#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
/**
* @brief Verification of hardware constraints before ADC can be disabled
@@ -2659,7 +2663,7 @@
* @retval None
*/
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
- ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+ ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
@@ -2674,7 +2678,7 @@
* @retval None
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
- ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
+ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))
/**
* @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
@@ -2689,8 +2693,8 @@
*/
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
- ((_Threshold_) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
- (_Threshold_) << 2 )
+ ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \
+ (_Threshold_) << 2U )
/**
* @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
@@ -2872,7 +2876,7 @@
#else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
(RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif
/**
* @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
@@ -3456,10 +3460,10 @@
* @{
*/
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
- ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
- (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
+ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \
+ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) )
/**
* @}
*/
@@ -3467,7 +3471,7 @@
/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
* @{
*/
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
/**
* @}
*/
@@ -3475,7 +3479,7 @@
/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
* @{
*/
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
/**
* @}
*/
@@ -3483,7 +3487,7 @@
/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
* @{
*/
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
/**
* @}
*/
@@ -3496,7 +3500,7 @@
* @param _Calibration_Factor_: Calibration factor value
* @retval None
*/
-#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
+#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
/**
* @}
*/
@@ -3559,7 +3563,7 @@
* @retval None
*/
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
- (((_NbrOfConversion_) - (uint8_t)1) << 20)
+ (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
/**
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -3568,7 +3572,7 @@
* @retval None
*/
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
+ ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
/**
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -3577,7 +3581,7 @@
* @retval None
*/
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
+ ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
/**
* @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -3586,7 +3590,7 @@
* @retval None
*/
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U)))
/**
* @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -3595,7 +3599,7 @@
* @retval None
*/
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U)))
/**
* @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -3604,7 +3608,7 @@
* @retval None
*/
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
+ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U)))
/**
* @brief Set the injected sequence length.
@@ -3612,7 +3616,7 @@
* @retval None
*/
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
- (((_JSQR_JL_) -1) << 20)
+ (((_JSQR_JL_) -1U) << 20U)
/**
* @brief Set the selected injected channel rank
@@ -3625,7 +3629,7 @@
* @retval None
*/
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
- ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+ ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U)))
/**
* @brief Enable ADC continuous conversion mode.
@@ -3633,7 +3637,7 @@
* @retval None
*/
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
- ((_CONTINUOUS_MODE_) << 1)
+ ((_CONTINUOUS_MODE_) << 1U)
/**
* @brief Configures the number of discontinuous conversions for the regular group channels.
@@ -3641,7 +3645,7 @@
* @retval None
*/
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
- (((_NBR_DISCONTINUOUS_CONV_) - 1) << 13)
+ (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U)
/**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@@ -3661,7 +3665,7 @@
* @retval None
*/
#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \
- ((_Calibration_Factor_) << 16)
+ ((_Calibration_Factor_) << 16U)
/**
* @brief Calibration factor in differential mode to be retrieved from calibration register
@@ -3669,7 +3673,7 @@
* @retval None
*/
#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \
- ((_Calibration_Factor_) >> 16)
+ ((_Calibration_Factor_) >> 16U)
/**
@@ -3712,16 +3716,16 @@
*/
#define ADC_CLOCK_PRESCALER_RANGE() \
(( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \
- (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32 ) \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \
: \
- (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128 ) \
+ (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \
)
/**
* @brief Get the ADC clock prescaler from system clock configuration register.
* @retval None
*/
-#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14) +1)
+#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
((ALIGN) == ADC_DATAALIGN_LEFT) )
@@ -3822,7 +3826,7 @@
* For a unique ADC resolution: 12 bits
* @{
*/
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU))
/**
* @}
*/
@@ -3830,7 +3834,7 @@
/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
* @{
*/
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
/**
* @}
*/
@@ -3838,7 +3842,7 @@
/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
* @{
*/
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U)))
/**
* @}
*/
@@ -3846,7 +3850,7 @@
/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
* @{
*/
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_can.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_can.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_can.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -170,7 +170,7 @@
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check CAN handle */
if(hcan == NULL)
@@ -292,7 +292,7 @@
((uint32_t)hcan->Init.SJW) | \
((uint32_t)hcan->Init.BS1) | \
((uint32_t)hcan->Init.BS2) | \
- ((uint32_t)hcan->Init.Prescaler - 1);
+ ((uint32_t)hcan->Init.Prescaler - 1U);
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
@@ -351,7 +351,7 @@
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
- uint32_t filternbrbitpos = 0;
+ uint32_t filternbrbitpos = 0U;
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
@@ -360,7 +360,7 @@
assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
- filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
/* Initialisation mode for the filter */
hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
@@ -377,14 +377,14 @@
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
@@ -393,12 +393,12 @@
hcan->Instance->FS1R |= filternbrbitpos;
/* 32-bit identifier or First 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
@@ -535,75 +535,78 @@
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Select one empty transmit mailbox */
- if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmitmailbox = 0;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = 1;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmitmailbox = 2;
- }
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ }
- if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
- {
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = 0U;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = 1U;
+ }
+ else
+ {
+ transmitmailbox = 2U;
+ }
+
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
/* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[0]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[4]));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0] ) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4] ) );
+
/* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
/* Get tick */
tickstart = HAL_GetTick();
@@ -614,9 +617,13 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ /* Cancel transmission */
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
@@ -644,9 +651,6 @@
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
/* Return function status */
return HAL_ERROR;
@@ -667,101 +671,100 @@
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
/* Select one empty transmit mailbox */
- if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
{
- transmitmailbox = 0;
+ transmitmailbox = 0U;
}
- else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = 1U;
+ }
+ else
{
- transmitmailbox = 1;
+ transmitmailbox = 2U;
}
- else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
- transmitmailbox = 2;
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
}
- if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
- {
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0] ) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4] ) );
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[2] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[1] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[0]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
- ((uint32_t)hcan->pTxMsg->Data[6] << 16) |
- ((uint32_t)hcan->pTxMsg->Data[5] << 8) |
- ((uint32_t)hcan->pTxMsg->Data[4]));
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Enable Error warning Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-
- /* Enable Error passive Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-
- /* Enable Bus-off Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-
- /* Enable Last error code Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-
- /* Enable Error Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
-
- /* Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
}
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
else
{
- return HAL_BUSY;
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
}
return HAL_OK;
@@ -778,7 +781,7 @@
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
@@ -801,12 +804,12 @@
tickstart = HAL_GetTick();
/* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
@@ -817,30 +820,30 @@
}
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
- hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
@@ -951,7 +954,7 @@
*/
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -1006,7 +1009,7 @@
*/
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -1072,7 +1075,7 @@
/* Check End of reception flag for FIFO0 */
if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0U))
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO0);
@@ -1080,7 +1083,7 @@
/* Check End of reception flag for FIFO1 */
if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0U))
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO1);
@@ -1329,30 +1332,30 @@
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
if (hcan->pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
- hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_can.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_can.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_can.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@@ -69,13 +69,13 @@
*/
typedef enum
{
- HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
}HAL_CAN_StateTypeDef;
@@ -144,7 +144,7 @@
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
@@ -255,16 +255,16 @@
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
-#define HAL_CAN_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_CAN_ERROR_EWG ((uint32_t)0x00000001) /*!< EWG error */
-#define HAL_CAN_ERROR_EPV ((uint32_t)0x00000002) /*!< EPV error */
-#define HAL_CAN_ERROR_BOF ((uint32_t)0x00000004) /*!< BOF error */
-#define HAL_CAN_ERROR_STF ((uint32_t)0x00000008) /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR ((uint32_t)0x00000010) /*!< Form error */
-#define HAL_CAN_ERROR_ACK ((uint32_t)0x00000020) /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
/**
* @}
*/
@@ -272,8 +272,8 @@
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
-#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
@@ -281,7 +281,7 @@
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
-#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@@ -293,7 +293,7 @@
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
-#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@@ -304,7 +304,7 @@
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
-#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -327,7 +327,7 @@
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
-#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -342,8 +342,8 @@
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
/**
* @}
*/
@@ -351,8 +351,8 @@
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
/**
* @}
*/
@@ -360,8 +360,8 @@
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
@@ -369,8 +369,8 @@
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
@@ -378,8 +378,8 @@
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
@@ -387,8 +387,8 @@
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{
*/
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
@@ -402,34 +402,34 @@
CAN_GetFlagStatus() function. */
/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
-#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
-#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
-#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
@@ -468,9 +468,9 @@
* @{
*/
/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
/**
* @}
*/
@@ -513,7 +513,7 @@
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: specifies the CAN Handle.
@@ -543,10 +543,10 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
@@ -576,10 +576,10 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
@@ -718,8 +718,8 @@
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
@@ -741,9 +741,9 @@
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
@@ -754,12 +754,12 @@
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
+#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_cec.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@@ -11,37 +11,38 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
+ *
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
- The CEC HAL driver can be used as follows:
+ The CEC HAL driver can be used as follow:
(#) Declare a CEC_HandleTypeDef handle structure.
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
- (++) Enable the CEC interface clock.
- (++) CEC pins configuration:
- (+++) Enable the clock for the CEC GPIOs.
- (+++) Configure these CEC pins as alternate function pull-up.
- (++) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+ (##) Enable the CEC interface clock.
+ (##) CEC pins configuration:
+ (+) Enable the clock for the CEC GPIOs.
+ (+) Configure these CEC pins as alternate function pull-up.
+ (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
- (+++) Configure the CEC interrupt priority.
- (+++) Enable the NVIC CEC IRQ handle.
+ (+) Configure the CEC interrupt priority.
+ (+) Enable the NVIC CEC IRQ handle.
+ (@) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_CEC_MspInit() API.
- -@@- The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
@endverbatim
******************************************************************************
@@ -83,34 +84,31 @@
#ifdef HAL_CEC_MODULE_ENABLED
-#if defined(STM32F373xC) || defined(STM32F378xx)
-/** @defgroup CEC CEC
+#if defined(STM32F373xC) || defined(STM32F378xx)
+/** @defgroup CEC CEC
* @brief HAL CEC module driver
* @{
- */
-
+ */
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
-#define CEC_CFGR_FIELDS (CEC_CFGR_SFT | CEC_CFGR_RXTOL | CEC_CFGR_BRESTP \
- | CEC_CFGR_BREGEN | CEC_CFGR_LBPEGEN | CEC_CFGR_SFTOPT \
- | CEC_CFGR_BRDNOGEN | CEC_CFGR_OAR | CEC_CFGR_LSTN)
/**
- * @}
- */
+ * @}
+ */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
/**
* @}
- */
+ */
+
/* Exported functions ---------------------------------------------------------*/
/** @defgroup CEC_Exported_Functions CEC Exported Functions
@@ -120,7 +118,7 @@
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@@ -142,17 +140,15 @@
*/
/**
- * @brief Initialize the CEC mode according to the specified
- * parameters in the CEC_InitTypeDef and creates the associated handle.
- * @param hcec: CEC handle.
+ * @brief Initializes the CEC mode according to the specified
+ * parameters in the CEC_InitTypeDef and creates the associated handle .
+ * @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
- uint32_t tmpreg = 0x0;
-
+{
/* Check the CEC handle allocation */
- if(hcec == NULL)
+ if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
@@ -166,51 +162,57 @@
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
- assert_param(IS_CEC_OAR_ADDRESS(hcec->Init.OwnAddress));
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
- assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+ assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
-
- if(hcec->State == HAL_CEC_STATE_RESET)
- {
+ if(hcec->gState == HAL_CEC_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
-
- hcec->State = HAL_CEC_STATE_BUSY;
+ hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
- tmpreg = hcec->Init.SignalFreeTime;
- tmpreg |= hcec->Init.Tolerance;
- tmpreg |= hcec->Init.BRERxStop;
- tmpreg |= hcec->Init.BREErrorBitGen;
- tmpreg |= hcec->Init.LBPEErrorBitGen;
- tmpreg |= hcec->Init.BroadcastMsgNoErrorBitGen;
- tmpreg |= hcec->Init.SignalFreeTimeOption;
- tmpreg |= (hcec->Init.OwnAddress << CEC_CFGR_OAR_LSB_POS);
- tmpreg |= hcec->Init.ListenMode;
+ /* Write to CEC Control Register */
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
+ hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Init.ListenMode;
- /* Write to CEC Control Register */
- MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, tmpreg);
-
- /* Enable the Peripheral */
+ /* Enable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
+ /* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
- hcec->State = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
-
-
/**
- * @brief DeInitialize the CEC peripheral.
- * @param hcec: CEC handle.
+ * @brief DeInitializes the CEC peripheral
+ * @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
@@ -224,15 +226,36 @@
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
- hcec->State = HAL_CEC_STATE_BUSY;
+ hcec->gState = HAL_CEC_STATE_BUSY;
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
+ /* Clear Flags */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
+
+ /* Disable the following CEC Transmission/Reception interrupts as
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
+
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->State = HAL_CEC_STATE_RESET;
+ hcec->gState = HAL_CEC_STATE_RESET;
+ hcec->RxState = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
@@ -241,31 +264,76 @@
}
/**
- * @brief CEC MSP Init.
- * @param hcec: CEC handle.
+ * @brief Initializes the Own Address of the CEC device
+ * @param hcec: CEC handle
+ * @param CEC_OwnAddress: The CEC own address.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+ if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ {
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
+ }
+ else
+ {
+ hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
+ }
+
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief CEC MSP Init
+ * @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
-
- /* NOTE : This function should not be modified; when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspInit can be implemented in the user file
*/
}
/**
- * @brief CEC MSP DeInit.
- * @param hcec: CEC handle.
+ * @brief CEC MSP DeInit
+ * @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
-
- /* NOTE : This function should not be modified; when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspDeInit can be implemented in the user file
*/
}
@@ -279,19 +347,14 @@
*
@verbatim
===============================================================================
- ##### IO operation function #####
- ===============================================================================
- [..]
+ ##### IO operation functions #####
+ ===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
- (+) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
- (+) There are two mode of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) Non Blocking mode: The communication is performed using Interrupts.
+ (#) The communication is performed using Interrupts.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
@@ -299,592 +362,207 @@
will be executed respectivelly at the end of the transmit or Receive process
The HAL_CEC_ErrorCallback()user callback will be executed when a communication
error is detected
+
+ (#) API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_IRQHandler()
- (+) Blocking mode API's are :
- (++) HAL_CEC_Transmit()
- (++) HAL_CEC_Receive()
-
- (+) Non-Blocking mode API's with Interrupt are :
- (++) HAL_CEC_Transmit_IT()
- (++) HAL_CEC_Receive_IT()
- (++) HAL_CEC_IRQHandler()
-
- (+) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (++) HAL_CEC_TxCpltCallback()
- (++) HAL_CEC_RxCpltCallback()
- (++) HAL_CEC_ErrorCallback()
+ (#) A set of User Callbacks are provided:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
@endverbatim
* @{
*/
/**
- * @brief Send data in blocking mode.
- * @param hcec: CEC handle.
- * @param DestinationAddress: destination logical address.
- * @param pData: pointer to input byte data buffer.
+ * @brief Send data in interrupt mode
+ * @param hcec: CEC handle
+ * @param InitiatorAddress: Initiator address
+ * @param DestinationAddress: destination logical address
+ * @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @param Timeout: Timeout duration.
+ * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
{
- uint8_t temp = 0;
- uint32_t tempisr = 0;
- uint32_t tickstart = 0;
-
- if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
- {
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- if((pData == NULL) && (Size > 0))
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ if((pData == NULL ) && (Size > 0U))
{
- hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress));
assert_param(IS_CEC_MSGSIZE(Size));
-
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->State = HAL_CEC_STATE_BUSY_TX;
-
- hcec->TxXferCount = Size;
-
- /* case no data to be sent, sender is only pinging the system */
- if (Size == 0)
- {
- /* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
-
- /* send header block */
- temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
- hcec->Instance->TXDR = temp;
- /* Set TX Start of Message (TXSOM) bit */
- __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
- while (hcec->TxXferCount > 0)
- {
- hcec->TxXferCount--;
-
- tickstart = HAL_GetTick();
- while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
-
- /* check whether error occured while waiting for TXBR to be set:
- * has Tx underrun occurred ?
- * has Tx error occurred ?
- * has Tx Missing Acknowledge error occurred ?
- * has Arbitration Loss error occurred ? */
- tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
- {
- /* copy ISR for error handling purposes */
- hcec->ErrorCode = tempisr;
- /* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
- hcec->State = HAL_CEC_STATE_ERROR;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- }
- /* TXBR to clear BEFORE writing TXDR register */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- if (hcec->TxXferCount == 0)
- {
- /* if last byte transmission, set TX End of Message (TXEOM) bit */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
- hcec->Instance->TXDR = *pData++;
-
- /* error check after TX byte write up */
- tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
- {
- /* copy ISR for error handling purposes */
- hcec->ErrorCode = tempisr;
- /* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
- hcec->State = HAL_CEC_STATE_ERROR;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- } /* end while (while (hcec->TxXferCount > 0)) */
-
-
- /* if no error up to this point, check that transmission is
- * complete, that is wait until TXEOM is reset */
- tickstart = HAL_GetTick();
-
- while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_ERROR;
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Final error check once all bytes have been transmitted */
- tempisr = hcec->Instance->ISR;
- if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
- {
- /* copy ISR for error handling purposes */
- hcec->ErrorCode = tempisr;
- /* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
- hcec->State = HAL_CEC_STATE_ERROR;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
- * @param hcec: CEC handle
- * @param pData: pointer to received data buffer.
- * @param Timeout: Timeout duration.
- * @note The received data size is not known beforehand, the latter is known
- * when the reception is complete and is stored in hcec->RxXferSize.
- * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
- * If only a header is received, hcec->RxXferSize = 0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
-{
- uint32_t temp;
- uint32_t tickstart = 0;
-
- if (hcec->State == HAL_CEC_STATE_READY)
- {
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- if (pData == NULL)
- {
- hcec->State = HAL_CEC_STATE_ERROR;
- return HAL_ERROR;
- }
-
- hcec->RxXferSize = 0;
- /* Process Locked */
- __HAL_LOCK(hcec);
-
-
- /* Rx loop until CEC_FLAG_RXEND is set */
- while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
- {
- tickstart = HAL_GetTick();
- /* Wait for next byte to be received */
- while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
- /* any error so far ?
- * has Rx Missing Acknowledge occurred ?
- * has Rx Long Bit Period error occurred ?
- * has Rx Short Bit Period error occurred ?
- * has Rx Bit Rising error occurred ?
- * has Rx Overrun error occurred ? */
- temp = (uint32_t) (hcec->Instance->ISR);
- if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
- {
- /* copy ISR for error handling purposes */
- hcec->ErrorCode = temp;
- /* clear all error flags by default */
- __HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
- hcec->State = HAL_CEC_STATE_ERROR;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR)) */
-
-
- /* read received data */
- *pData++ = hcec->Instance->RXDR;
- temp = (uint32_t) (hcec->Instance->ISR);
- /* end of message ? */
- if ((temp & CEC_FLAG_RXEND) != 0)
- {
- assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_OK;
- }
-
- /* clear Rx-Byte Received flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
- /* increment payload byte counter */
- hcec->RxXferSize++;
- } /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND)) */
-
- /* if the instructions below are executed, it means RXEND was set when RXBR was
- * set for the first time:
- * the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))"
- * loop has not been executed and this means a single byte has been sent */
- *pData++ = hcec->Instance->RXDR;
- /* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
- hcec->RxXferSize = 0;
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Send data in interrupt mode.
- * @param hcec: CEC handle.
- * @param DestinationAddress: destination logical address.
- * @param pData: pointer to input byte data buffer.
- * @param Size: amount of data to be sent in bytes (without counting the header).
- * 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
-{
- uint8_t temp = 0;
- /* if the IP isn't already busy and if there is no previous transmission
- already pending due to arbitration lost */
- if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
- && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
- {
- if((pData == NULL) && (Size > 0))
- {
- hcec->State = HAL_CEC_STATE_ERROR;
- return HAL_ERROR;
- }
-
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
- assert_param(IS_CEC_MSGSIZE(Size));
-
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
- hcec->State = HAL_CEC_STATE_BUSY_TX;
+ hcec->gState = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Disable Peripheral to write CEC_IER register */
- __HAL_CEC_DISABLE(hcec);
-
- /* Enable the following two CEC Transmission interrupts as
- * well as the following CEC Transmission Errors interrupts:
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* in case of no payload (Size = 0), sender is only pinging the system;
- * Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
- if (Size == 0)
+ /* in case of no payload (Size = 0U), sender is only pinging the system;
+ Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+ if (Size == 0U)
{
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
-
+
/* send header block */
- temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
- hcec->Instance->TXDR = temp;
+ hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
return HAL_OK;
- }
- /* if the IP is already busy or if there is a previous transmission
- already pending due to arbitration loss */
- else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
- || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
- {
- __HAL_LOCK(hcec);
- /* set state to BUSY TX, in case it wasn't set already (case
- * of transmission new attempt after arbitration loss) */
- if (hcec->State != HAL_CEC_STATE_BUSY_TX)
- {
- hcec->State = HAL_CEC_STATE_BUSY_TX;
- }
- /* if all data have been sent */
- if(hcec->TxXferCount == 0)
- {
- /* Disable Peripheral to write CEC_IER register */
- __HAL_CEC_DISABLE(hcec);
-
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
- /* Disable the CEC Transmission Error Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
-
- hcec->State = HAL_CEC_STATE_READY;
- /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
- start again the Transmission under the Tx call back API */
- __HAL_UNLOCK(hcec);
-
- HAL_CEC_TxCpltCallback(hcec);
-
- return HAL_OK;
- }
- else
- {
- if (hcec->TxXferCount == 1)
- {
- /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
- /* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- hcec->TxXferCount--;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
- }
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
-
-/**
- * @brief Receive data in interrupt mode.
- * @param hcec: CEC handle.
- * @param pData: pointer to received data buffer.
- * @note The received data size is not known beforehand, the latter is known
- * when the reception is complete and is stored in hcec->RxXferSize.
- * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
- * If only a header is received, hcec->RxXferSize = 0.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
-{
- if(hcec->State == HAL_CEC_STATE_READY)
- {
- if(pData == NULL)
- {
- hcec->State = HAL_CEC_STATE_ERROR;
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hcec);
- hcec->RxXferSize = 0;
- hcec->pRxBuffPtr = pData;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- /* the IP is moving to a ready to receive state */
- hcec->State = HAL_CEC_STATE_STANDBY_RX;
-
- /* Disable Peripheral to write CEC_IER register */
- __HAL_CEC_DISABLE(hcec);
-
- /* Enable the following CEC Reception Error Interrupts:
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IER_RX_ALL_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* Enable the following two CEC Reception interrupts:
- * Rx Byte Received IT
- * End of Reception IT */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND);
-
- __HAL_CEC_ENABLE(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-
/**
* @brief Get size of the received frame.
- * @param hcec: CEC handle.
+ * @param hcec: CEC handle
* @retval Frame size
*/
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
{
return hcec->RxXferSize;
}
-
/**
+ * @brief Change Rx Buffer.
+ * @param hcec: CEC handle
+ * @param Rxbuffer: Rx Buffer
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
+ * @retval Frame size
+ */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+{
+ hcec->Init.RxBuffer = Rxbuffer;
+}
+
+/**
* @brief This function handles CEC interrupt requests.
- * @param hcec: CEC handle.
+ * @param hcec: CEC handle
* @retval None
*/
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
+
/* save interrupts register for further error or interrupts handling purposes */
- hcec->ErrorCode = hcec->Instance->ISR;
- /* CEC TX missing acknowledge error interrupt occurred -------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXACKE) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXACKE);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
+ uint32_t reg = 0U;
+ reg = hcec->Instance->ISR;
+
- /* CEC transmit error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET))
+ /* ----------------------------Arbitration Lost Management----------------------------------*/
+ /* CEC TX arbitration error interrupt occurred --------------------------------------*/
+ if((reg & CEC_FLAG_ARBLST) != RESET)
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC TX underrun error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC TX arbitration error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET))
- {
+ hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
- hcec->State = HAL_CEC_STATE_ERROR;
}
- /* CEC RX overrun error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC RX bit rising error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC RX short bit period error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET))
+ /* ----------------------------Rx Management----------------------------------*/
+ /* CEC RX byte received interrupt ---------------------------------------------------*/
+ if((reg & CEC_FLAG_RXBR) != RESET)
{
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC RX long bit period error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET))
- {
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE);
- hcec->State = HAL_CEC_STATE_ERROR;
- }
-
- if ((hcec->ErrorCode & CEC_ISR_ALL_ERROR) != 0)
- {
- HAL_CEC_ErrorCallback(hcec);
- }
-
- /* CEC RX byte received interrupt ---------------------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXBR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXBR) != RESET))
- {
- /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
- CEC_Receive_IT(hcec);
+ /* reception is starting */
+ hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+ hcec->RxXferSize++;
+ /* read received byte */
+ *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
}
/* CEC RX end received interrupt ---------------------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXEND) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXEND) != RESET))
+ if((reg & CEC_FLAG_RXEND) != RESET)
{
- /* RXBR IT is cleared during HAL_CEC_Transmit_IT processing */
- CEC_Receive_IT(hcec);
+ /* clear IT */
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+ /* Rx process is completed, restore hcec->RxState to Ready */
+ hcec->RxState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+ hcec->RxXferSize = 0U;
}
-
+ /* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXBR) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXBR) != RESET))
+ if((reg & CEC_FLAG_TXBR) != RESET)
{
- /* TXBR IT is cleared during HAL_CEC_Transmit_IT processing */
- CEC_Transmit_IT(hcec);
+ if (hcec->TxXferCount == 0U)
+ {
+ /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+ __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ }
+ else
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->TxXferCount--;
+ }
+ /* clear Tx-Byte request flag */
+ __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXEND) != RESET) &&(__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXEND) != RESET))
- {
- /* TXEND IT is cleared during HAL_CEC_Transmit_IT processing */
- CEC_Transmit_IT(hcec);
+ if((reg & CEC_FLAG_TXEND) != RESET)
+ {
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
+
+ /* Tx process is ended, restore hcec->gState to Ready */
+ hcec->gState = HAL_CEC_STATE_READY;
+ /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+ start again the Transmission under the Tx call back API */
+ __HAL_UNLOCK(hcec);
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ HAL_CEC_TxCpltCallback(hcec);
}
+ /* ----------------------------Rx/Tx Error Management----------------------------------*/
+ if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
+ {
+ hcec->ErrorCode = reg;
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+
+
+ if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+ {
+ hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
+ hcec->RxState = HAL_CEC_STATE_READY;
+ }
+ else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
+ {
+ /* Set the CEC state ready to be able to start again the process */
+ hcec->gState = HAL_CEC_STATE_READY;
+ }
+
+ /* Error Call Back */
+ HAL_CEC_ErrorCallback(hcec);
+ }
+
}
-
/**
* @brief Tx Transfer completed callback
* @param hcec: CEC handle
@@ -893,8 +571,7 @@
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
-
+ UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
*/
@@ -903,68 +580,71 @@
/**
* @brief Rx Transfer completed callback
* @param hcec: CEC handle
+ * @param RxFrameSize: Size of frame
* @retval None
*/
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CEC_TxCpltCallback can be implemented in the user file.
+ UNUSED(RxFrameSize);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_RxCpltCallback can be implemented in the user file
*/
}
/**
- * @brief CEC error callback.
- * @param hcec: CEC handle.
+ * @brief CEC error callbacks
+ * @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
-
- /* NOTE : This function should not be modified; when the callback is needed,
- the HAL_CEC_ErrorCallback can be implemented in the user file.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_CEC_ErrorCallback can be implemented in the user file
*/
}
-
/**
* @}
*/
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
* @brief CEC control functions
*
@verbatim
===============================================================================
- ##### Peripheral Control functions #####
+ ##### Peripheral Control function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the CEC.
- (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API report the CEC handle error code.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
-
/**
- * @brief Return the CEC state.
- * @param hcec: CEC handle.
+ * @brief return the CEC state
+ * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC module.
* @retval HAL state
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
- return hcec->State;
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ temp1 = hcec->gState;
+ temp2 = hcec->RxState;
+
+ return (HAL_CEC_StateTypeDef)(temp1 | temp2);
}
/**
-* @brief Return the CEC error code.
-* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * @brief Return the CEC error code
+ * @param hcec : pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
-* @retval CEC Error Code
-*/
+ * @retval CEC Error Code
+ */
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
{
return hcec->ErrorCode;
@@ -977,162 +657,7 @@
/**
* @}
*/
-
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-
- /**
- * @brief Send data in interrupt mode.
- * @param hcec: CEC handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_CEC_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
-{
- /* if the IP is already busy or if there is a previous transmission
- already pending due to arbitration loss */
- if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
- || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
- {
-
- /* set state to BUSY TX, in case it wasn't set already (case
- * of transmission new attempt after arbitration loss) */
- if (hcec->State != HAL_CEC_STATE_BUSY_TX)
- {
- hcec->State = HAL_CEC_STATE_BUSY_TX;
- }
-
- /* if all data have been sent */
- if(hcec->TxXferCount == 0)
- {
- /* Disable Peripheral to write CEC_IER register */
- __HAL_CEC_DISABLE(hcec);
-
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
- /* Disable the CEC Transmission Error Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
-
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
-
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
-
- /* If RX interruptions are enabled, return to HAL_CEC_STATE_STANDBY_RX state */
- if (__HAL_CEC_GET_IT_SOURCE(hcec, (CEC_IT_RXBR|CEC_IT_RXEND) ) != RESET)
- {
- hcec->State = HAL_CEC_STATE_STANDBY_RX;
- }
- else
- {
- hcec->State = HAL_CEC_STATE_READY;
- }
-
- HAL_CEC_TxCpltCallback(hcec);
-
- return HAL_OK;
- }
- else
- {
- if (hcec->TxXferCount == 1)
- {
- /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
- __HAL_CEC_LAST_BYTE_TX_SET(hcec);
- }
- /* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
- hcec->TxXferCount--;
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
- * @brief Receive data in interrupt mode.
- * @param hcec: CEC handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_CEC_Receive_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
-{
- uint32_t tempisr;
-
- /* Three different conditions are tested to carry out the RX IT processing:
- * - the IP is in reception stand-by (the IP state is HAL_CEC_STATE_STANDBY_RX) and
- * the reception of the first byte is starting
- * - a message reception is already on-going (the IP state is HAL_CEC_STATE_BUSY_RX)
- * and a new byte is being received
- * - a transmission has just been started (the IP state is HAL_CEC_STATE_BUSY_TX)
- * but has been interrupted by a new message reception or discarded due to
- * arbitration loss: the reception of the first or higher priority message
- * (the arbitration winner) is starting */
- if ((hcec->State == HAL_CEC_STATE_STANDBY_RX)
- || (hcec->State == HAL_CEC_STATE_BUSY_RX)
- || (hcec->State == HAL_CEC_STATE_BUSY_TX))
- {
- /* reception is starting */
- hcec->State = HAL_CEC_STATE_BUSY_RX;
- tempisr = (uint32_t) (hcec->Instance->ISR);
- if ((tempisr & CEC_FLAG_RXBR) != 0)
- {
- /* read received byte */
- *hcec->pRxBuffPtr++ = hcec->Instance->RXDR;
- /* if last byte has been received */
- if ((tempisr & CEC_FLAG_RXEND) != 0)
- {
- /* clear IT */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR|CEC_FLAG_RXEND);
- /* RX interrupts are not disabled at this point.
- * Indeed, to disable the IT, the IP must be disabled first
- * which resets the TXSOM flag. In case of arbitration loss,
- * this leads to a transmission abort.
- * Therefore, RX interruptions disabling if so required,
- * is done in HAL_CEC_RxCpltCallback */
-
- /* IP state is moved to READY.
- * If the IP must remain in standby mode to listen
- * any new message, it is up to HAL_CEC_RxCpltCallback
- * to move it again to HAL_CEC_STATE_STANDBY_RX */
- hcec->State = HAL_CEC_STATE_READY;
-
- HAL_CEC_RxCpltCallback(hcec);
-
- return HAL_OK;
- }
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
-
- hcec->RxXferSize++;
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
#endif /* defined(STM32F373xC) || defined(STM32F378xx) */
@@ -1141,4 +666,8 @@
* @}
*/
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_cec.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
@@ -51,14 +51,14 @@
* @{
*/
-/** @addtogroup CEC CEC
+/** @addtogroup CEC
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
- */
+ */
/**
* @brief CEC Init Structure definition
@@ -67,78 +67,120 @@
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
- and belongs to the set {0,...,7} where
+ and belongs to the set {0U,...,7} where
0x0 is the default configuration
- else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
+ else means 0.5U + (SignalFreeTime - 1U) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance :
- @arg CEC_STANDARD_TOLERANCE
- @arg CEC_EXTENDED_TOLERANCE */
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
- @arg CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
- @arg CEC_RX_STOP_ON_BRE: reception is stopped. */
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
- @arg CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
- @arg CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
+ CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
- @arg CEC line upon Long Bit Period Error detection.
- @arg CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
- @arg CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+ CEC line upon Long Bit Period Error detection.
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
- @arg 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- @arg __ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ 1U) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
- @arg __ b) LBPE detection: error-bit generation on the CEC line
+ b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
- @arg 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
+ 2U) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
- @arg CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- @arg CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
-
- uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
+ CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
- @arg CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
- @arg CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
- uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of @ref CEC_OWN_ADDRESS */
+
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+
}CEC_InitTypeDef;
/**
- * @brief HAL CEC State structures definition
+ * @brief HAL CEC State structures definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains CEC state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6 Error information
+ * 0 : No Error
+ * 1 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized. HAL CEC Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
*/
typedef enum
{
- HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
- HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
- HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
- HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
- HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
- HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+ HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
}HAL_CEC_StateTypeDef;
/**
@@ -154,31 +196,33 @@
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */
-
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
-
HAL_LockTypeDef Lock; /*!< Locking object */
+
+ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
- HAL_CEC_StateTypeDef State; /*!< CEC communication state */
-
+ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
}CEC_HandleTypeDef;
/**
- * @}
- */
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
-#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< No error */
+#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@@ -191,27 +235,27 @@
/**
* @}
*/
-
+
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
-#define CEC_DEFAULT_SFT ((uint32_t)0x00000000) /*!< Transmission history-based signal free time (ruled by hardware) */
-#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001) /*!< 0.5 nominal data bit period */
-#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002) /*!< 1.5 nominal data bit periods */
-#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003) /*!< 2.5 nominal data bit periods */
-#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004) /*!< 3.5 nominal data bit periods */
-#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005) /*!< 4.5 nominal data bit periods */
-#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006) /*!< 5.5 nominal data bit periods */
-#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007) /*!< 6.5 nominal data bit periods */
-/**
- * @}
+#define CEC_DEFAULT_SFT (0x00000000U)
+#define CEC_0_5_BITPERIOD_SFT (0x00000001U)
+#define CEC_1_5_BITPERIOD_SFT (0x00000002U)
+#define CEC_2_5_BITPERIOD_SFT (0x00000003U)
+#define CEC_3_5_BITPERIOD_SFT (0x00000004U)
+#define CEC_4_5_BITPERIOD_SFT (0x00000005U)
+#define CEC_5_5_BITPERIOD_SFT (0x00000006U)
+#define CEC_6_5_BITPERIOD_SFT (0x00000007U)
+/**
+ * @}
*/
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
-#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000) /*!< Standard tolerance margin */
-#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) /*!< Extended Tolerance */
+#define CEC_STANDARD_TOLERANCE (0x00000000U)
+#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
*/
@@ -219,8 +263,8 @@
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
-#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000) /*!< CEC reception not stopped by BRE detection */
-#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) /*!< CEC reception stopped by BRE detection */
+#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
+#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
*/
@@ -228,8 +272,8 @@
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
-#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of BRE detection */
-#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) /*!< Error-Bit on CEC line in case of BRE detection */
+#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
+#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
*/
@@ -237,8 +281,8 @@
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
-#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000) /*!< No Error-Bit on CEC line in case of LBPE detection */
-#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) /*!< Error-Bit on CEC line in case of LBPE detection */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
+#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
*/
@@ -246,10 +290,8 @@
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000) /*!< Error-Bit on CEC line for specific error conditions
- on a broadcast message (cf Reference Manual) */
-#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) /*!< No Error-Bit on CEC line for specific error conditions
- on a broadcast message (cf Reference Manual) */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
@@ -257,8 +299,8 @@
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
-#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000) /*!< SFT timer starts when TXSOM is set by software */
-#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) /*!< SFT timer starts automatically at the end of message transmission/reception */
+#define CEC_SFT_START_ON_TXSOM (0x00000000U)
+#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
@@ -266,18 +308,16 @@
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
-#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000) /*!< CEC peripheral receives only message addressed to its own address (OAR). */
-#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) /*!< CEC peripheral receives messages addressed to its own address (OAR) with
- positive acknowledge. Messages addressed to different destination are
- received, but without interfering with the CEC bus: no acknowledge sent. */
+#define CEC_REDUCED_LISTENING_MODE (0x00000000U)
+#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
-
+
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
-#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16) /*!< CEC Device Own Address position in CEC CFGR register */
+#define CEC_CFGR_OAR_LSB_POS (16U)
/**
* @}
*/
@@ -285,56 +325,79 @@
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
-#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) /*!< CEC Initiator logical address position in message header */
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupts_Definitions CEC interrupts definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE /*!< Tx missing acknowledge error interruption */
-#define CEC_IT_TXERR CEC_IER_TXERRIE /*!< Tx error interruption */
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE /*!< Tx underrun interruption */
-#define CEC_IT_TXEND CEC_IER_TXENDIE /*!< Tx end of message interruption */
-#define CEC_IT_TXBR CEC_IER_TXBRIE /*!< Tx byte request interruption */
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE /*!< Arbitration lost interruption */
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE /*!< Rx missing acknowledge error interruption */
-#define CEC_IT_LBPE CEC_IER_LBPEIE /*!< Long bit period error interruption */
-#define CEC_IT_SBPE CEC_IER_SBPEIE /*!< Short bit period error interruption */
-#define CEC_IT_BRE CEC_IER_BREIE /*!< Bit rising error interruption */
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE /*!< Rx overrun interruption */
-#define CEC_IT_RXEND CEC_IER_RXENDIE /*!< End of reception interruption */
-#define CEC_IT_RXBR CEC_IER_RXBRIE /*!< RX byte received interruption */
+#define CEC_INITIATOR_LSB_POS (4U)
/**
* @}
*/
-/** @defgroup CEC_Flags_Definitions CEC flags definition
+/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE /*!< Tx missing acknowledge error flag */
-#define CEC_FLAG_TXERR CEC_ISR_TXERR /*!< Tx error flag */
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR /*!< Tx underrun flag */
-#define CEC_FLAG_TXEND CEC_ISR_TXEND /*!< Tx end of message flag */
-#define CEC_FLAG_TXBR CEC_ISR_TXBR /*!< Tx byte request flag */
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST /*!< Arbitration lost flag */
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE /*!< Rx missing acknowledge error flag */
-#define CEC_FLAG_LBPE CEC_ISR_LBPE /*!< Long bit period error flag */
-#define CEC_FLAG_SBPE CEC_ISR_SBPE /*!< Short bit period error flag */
-#define CEC_FLAG_BRE CEC_ISR_BRE /*!< Bit rising error flag */
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR /*!< Rx overrun flag */
-#define CEC_FLAG_RXEND CEC_ISR_RXEND /*!< End of reception flag */
-#define CEC_FLAG_RXBR CEC_ISR_RXBR /*!< RX byte received flag */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0U */
+#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1U */
+#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2U */
+#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3U */
+#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4U */
+#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5U */
+#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6U */
+#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7U */
+#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9U */
+#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10U */
+#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11U */
+#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12U */
+#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13U */
+#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14U */
+#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15U */
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
+ * @{
+ */
+#define CEC_IT_TXACKE CEC_IER_TXACKEIE
+#define CEC_IT_TXERR CEC_IER_TXERRIE
+#define CEC_IT_TXUDR CEC_IER_TXUDRIE
+#define CEC_IT_TXEND CEC_IER_TXENDIE
+#define CEC_IT_TXBR CEC_IER_TXBRIE
+#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
+#define CEC_IT_RXACKE CEC_IER_RXACKEIE
+#define CEC_IT_LBPE CEC_IER_LBPEIE
+#define CEC_IT_SBPE CEC_IER_SBPEIE
+#define CEC_IT_BRE CEC_IER_BREIE
+#define CEC_IT_RXOVR CEC_IER_RXOVRIE
+#define CEC_IT_RXEND CEC_IER_RXENDIE
+#define CEC_IT_RXBR CEC_IER_RXBRIE
/**
* @}
*/
+/** @defgroup CEC_Flags_Definitions CEC Flags definition
+ * @{
+ */
+#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
+#define CEC_FLAG_TXERR CEC_ISR_TXERR
+#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
+#define CEC_FLAG_TXEND CEC_ISR_TXEND
+#define CEC_FLAG_TXBR CEC_ISR_TXBR
+#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
+#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
+#define CEC_FLAG_LBPE CEC_ISR_LBPE
+#define CEC_FLAG_SBPE CEC_ISR_SBPE
+#define CEC_FLAG_BRE CEC_ISR_BRE
+#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
+#define CEC_FLAG_RXEND CEC_ISR_RXEND
+#define CEC_FLAG_RXBR CEC_ISR_RXBR
+/**
+ * @}
+ */
+
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /*!< All Rx or Tx errors flags concatenation */
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -342,7 +405,7 @@
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /*!< All Rx errors interruptions concatenation */
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
@@ -350,10 +413,10 @@
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /*!< All Tx errors interruptions concatenation */
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
- */
+ */
/**
* @}
@@ -364,16 +427,18 @@
* @{
*/
-/** @brief Reset CEC handle state
+/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__: CEC handle.
* @retval None
*/
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0U)
-/** @brief Check whether or not the specified CEC interrupt flag is set.
+/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the interrupt to check.
- * This parameter can be one of the following values:
+ * @param __FLAG__: specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -383,15 +448,15 @@
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval IT Status
+ * @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
-/** @brief Clear the interrupt or status flag when raised (write at 1)
+/** @brief Clears the interrupt or status flag when raised (write at 1U)
* @param __HANDLE__: specifies the CEC Handle.
* @param __FLAG__: specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
@@ -404,15 +469,15 @@
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
+ * @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
-/** @brief Enable the specified CEC interrupt.
+/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
@@ -433,7 +498,7 @@
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
-/** @brief Disable the specified CEC interrupt.
+/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
@@ -449,12 +514,12 @@
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-/** @brief Check whether or not the specified CEC interrupt is enabled.
+/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to check.
* This parameter can be one of the following values:
@@ -470,59 +535,58 @@
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval Flag Status
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
-/** @brief Enable the CEC device.
+/** @brief Enables the CEC device
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
-/** @brief Disable the CEC device.
+/** @brief Disables the CEC device
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
-/** @brief Set Transmission Start flag.
+/** @brief Set Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
-/** @brief Set Transmission End flag.
- * @param __HANDLE__: specifies the CEC Handle.
- * @note If the CEC message consists of only one byte, TXEOM must be set before TXSOM.
+/** @brief Set Transmission End flag
+ * @param __HANDLE__: specifies the CEC Handle.
* @retval none
- *
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
-/** @brief Get Transmission Start flag.
+/** @brief Get Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
-/** @brief Get Transmission End flag.
+/** @brief Get Transmission End flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
-/** @brief Clear OAR register.
+/** @brief Clear OAR register
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
-/** @brief Set OAR register (without resetting previously set address in case of multi-address mode).
+/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
+ * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__: specifies the CEC Handle.
- * @param __ADDRESS__: own address value (CEC logical address is identified by bit position)
- * @note To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand.
+ * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@@ -532,46 +596,42 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions CEC Exported Functions
+/** @addtogroup CEC_Exported_Functions
* @{
*/
-
-/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+
+/** @addtogroup CEC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
/**
* @}
*/
-/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
+/** @addtogroup CEC_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
-/** @addtogroup CEC_Exported_Functions_Group3 Peripheral Control functions
- * @brief CEC control functions
+/** @addtogroup CEC_Exported_Functions_Group3
* @{
*/
-/* Peripheral State and Error functions ***************************************/
+/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
@@ -581,19 +641,46 @@
/**
* @}
*/
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
-#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
-#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
- ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
+#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
+ ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
@@ -610,20 +697,6 @@
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
-/** @brief Check CEC device Own Address Register (OAR) setting.
- * OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__: CEC own address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
-
-/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
@@ -631,11 +704,33 @@
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
/**
* @}
- */
-
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_comp.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@@ -132,27 +132,27 @@
+------------------------------------------------------------------------------------------+
| | | COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|-----------------|----------------|---------------|---------------------------------------|
- | | 1/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 1/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
- | | 3/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 1U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 1U/2 VREFINT | OK | OK | OK | OK | OK | OK | OK |
+ | | 3U/4 VREFINT | OK | OK | OK | OK | OK | OK | OK |
| Inverting Input | VREFINT | OK | OK | OK | OK | OK | OK | OK |
| | DAC1 OUT (PA4) | OK | OK | OK | OK | OK | OK | OK |
| | DAC2 OUT (PA5) | OK | OK | OK | OK | OK | OK | OK |
- | | IO1 | PA0 | PA2 | PD15 | PE8 | PD13 | PD10 | PC0 |
- | | IO2 | --- | --- | PB12 | PB2 | PB10 | PB15 | --- |
+ | | IO1 | PA0 | PA2 | PD15U | PE8 | PD13U | PD10U | PC0 |
+ | | IO2 | --- | --- | PB12U | PB2 | PB10U | PB15U | --- |
|-----------------|----------------|-------|-------|-------|-------|-------|-------|-------|
- | Non Inverting | IO1 | PA1 | PA7 | PB14 | PB0 | PD12 | PD11 | PA0 |
- | Input | IO2 | --- | PA3 | PD14 | PE7 | PB13 | PB11 | PC1 |
+ | Non Inverting | IO1 | PA1 | PA7 | PB14U | PB0 | PD12U | PD11U | PA0 |
+ | Input | IO2 | --- | PA3 | PD14U | PE7 | PB13U | PB11U | PC1 |
+------------------------------------------------------------------------------------------+
Table 2. COMP Outputs for the STM32F303xB/STM32F303xC/STM32F303xE devices
+-------------------------------------------------------+
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|-------|-------|-------|-------|-------|-------|-------|
- | PA0 | PA2 | PB1 | PC8 | PC7 | PA10 | PC2 |
+ | PA0 | PA2 | PB1 | PC8 | PC7 | PA10U | PC2 |
| PF4 | PA7 | --- | PA8 | PA9 | PC6 | --- |
- | PA6 | PA12 | --- | --- | --- | --- | --- |
- | PA11 | PB9 | --- | --- | --- | --- | --- |
+ | PA6 | PA12U | --- | --- | --- | --- | --- |
+ | PA11U | PB9 | --- | --- | --- | --- | --- |
| PB8 | --- | --- | --- | --- | --- | --- |
+-------------------------------------------------------+
@@ -189,11 +189,11 @@
+----------------------------------------------------------------------------------------------------------------------+
| COMP1 | COMP2 | COMP3 | COMP4 | COMP5 | COMP6 | COMP7 |
|----------------|----------------|----------------|----------------|----------------|----------------|----------------|
- | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1) |
+ | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) | TIM1 BKIN | TIM1 BKIN | TIM1 BKIN (1U) |
| | | | | | | |
| TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 | TIM1 BKIN2 |
| | | | | | | |
- | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1) |
+ | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) | TIM8 BKIN | TIM8 BKIN | TIM8 BKIN (1U) |
| | | | | | | |
| TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 | TIM8 BKIN2 |
| | | | | | | |
@@ -213,7 +213,7 @@
| | | | | | | |
| TIM3 OCREFCLR | TIM3 OCREFCLR | TIM15 BKIN | TIM15 IC2 | TIM17 IC1 | TIM4 IC4 | TIM17 BKIN |
| | | | | | | |
- | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1)|
+ | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)| TIM20 BKIN | TIM20 BKIN | TIM20 BKIN (1U)|
| | | | | | | |
| TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
| | | | | | | |
@@ -224,8 +224,8 @@
| TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 | TIM20 BKIN2 |
| | | | | | | |
+----------------------------------------------------------------------------------------------------------------------+
- (1): This connection consists of connecting both GPIO and COMP output to TIM1/8/20 BRK input through an OR gate, instead
- of connecting the GPIO to the TIM1/8/20 BRK input and the COMP output to the TIM1/8/20 BRK_ACTH input. The aim is to
+ (1U): This connection consists of connecting both GPIO and COMP output to TIM1/8U/20 BRK input through an OR gate, instead
+ of connecting the GPIO to the TIM1/8U/20 BRK input and the COMP output to the TIM1/8U/20 BRK_ACTH input. The aim is to
add a digital filter (3 bits) on the COMP output.
Table 5. COMP Outputs blanking sources for the STM32F303xB/STM32F303xC/STM32F303xE devices
@@ -261,7 +261,7 @@
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
-#define COMP_LOCK_DISABLE ((uint32_t)0x00000000)
+#define COMP_LOCK_DISABLE (0x00000000U)
#define COMP_LOCK_ENABLE COMP_CSR_COMPxLOCK
/**
* @}
@@ -456,7 +456,7 @@
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t extiline = 0;
+ uint32_t extiline = 0U;
/* Check the COMP handle allocation and lock status */
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
@@ -563,7 +563,7 @@
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t extiline = 0;
+ uint32_t extiline = 0U;
/* Check the COMP handle allocation and lock status */
if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
@@ -763,14 +763,14 @@
*/
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
{
- uint32_t level=0;
+ uint32_t level=0U;
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
level = READ_BIT(hcomp->Instance->CSR, COMP_CSR_COMPxOUT);
- if(level != 0)
+ if(level != 0U)
{
return(COMP_OUTPUTLEVEL_HIGH);
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_comp.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
@@ -90,7 +90,7 @@
This parameter can be a value of @ref COMPEx_Mode
Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
- uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2, 4 or 6 if available).
+ uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
This parameter can be a value of @ref COMPEx_WindowMode */
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
@@ -103,10 +103,10 @@
*/
typedef enum
{
- HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized or disabled */
- HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
- HAL_COMP_STATE_READY_LOCKED = 0x11, /*!< COMP initialized but the configuration is locked */
- HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
+ HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */
+ HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
+ HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */
+ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
}HAL_COMP_StateTypeDef;
@@ -133,7 +133,7 @@
/** @defgroup COMP_OutputPolarity COMP Output Polarity
* @{
*/
-#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
+#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
/**
* @}
@@ -144,7 +144,7 @@
*/
/* When output polarity is not inverted, comparator output is low when
the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000)
+#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
/* When output polarity is not inverted, comparator output is high when
the non-inverting input is at a higher voltage than the inverting input */
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
@@ -155,13 +155,13 @@
/** @defgroup COMP_TriggerMode COMP Trigger Mode
* @{
*/
-#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< No External Interrupt trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_RISING ((uint32_t)0x00000010) /*!< Event Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_FALLING ((uint32_t)0x00000020) /*!< Event Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_EVENT_RISING_FALLING ((uint32_t)0x00000030) /*!< Event Mode with Rising/Falling edge trigger detection */
+#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -169,7 +169,7 @@
/** @defgroup COMP_State_Lock COMP State Lock
* @{
*/
-#define COMP_STATE_BIT_LOCK ((uint32_t)0x00000010) /* Lock bit in COMP handle state */
+#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_comp_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of COMP HAL Extended module.
******************************************************************************
* @attention
@@ -65,9 +65,9 @@
/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F302xE/STM32F303xE/STM32F398xx/STM32F302xC/STM32F303xC/STM32F358xx Product devices)
* @{
*/
-#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
@@ -86,9 +86,9 @@
/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
* @{
*/
-#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
#define COMP_INVERTINGINPUT_IO1 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_1) /*!< IO1 (PA2 for COMP2, PB2 for COMP4, PB15 for COMP6)
@@ -106,9 +106,9 @@
/* connected to a GPIO. */
/* It must be chosen among the 2 literals COMP_INVERTINGINPUT_IOx */
/* depending on comparator instance COMPx. */
-#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3U/4 VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_VREFINT (COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0) /*!< VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH2 (COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
@@ -128,9 +128,9 @@
/** @defgroup COMPEx_InvertingInput COMP Extended InvertingInput (STM32F373xC/STM32F378xx Product devices)
* @{
*/
-#define COMP_INVERTINGINPUT_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_4VREFINT (0x00000000U) /*!< 1U/4 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_1_2VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_0) /*!< 1U/2 VREFINT connected to comparator inverting input */
+#define COMP_INVERTINGINPUT_3_4VREFINT ((uint32_t)COMP_CSR_COMPxINSEL_1) /*!< 3U/4 VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_VREFINT ((uint32_t)(COMP_CSR_COMPxINSEL_1|COMP_CSR_COMPxINSEL_0)) /*!< VREFINT connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH1 ((uint32_t)COMP_CSR_COMPxINSEL_2) /*!< DAC1_CH1_OUT (PA4) connected to comparator inverting input */
#define COMP_INVERTINGINPUT_DAC1_CH2 ((uint32_t)(COMP_CSR_COMPxINSEL_2|COMP_CSR_COMPxINSEL_0)) /*!< DAC1_CH2_OUT (PA5) connected to comparator inverting input */
@@ -150,7 +150,7 @@
/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
* @{
*/
-#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
PA0 for COMP7) connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
@@ -163,7 +163,7 @@
/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F301x8/STM32F302x8/STM32F318xx Product devices)
* @{
*/
-#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */
/**
@@ -173,7 +173,7 @@
/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F373xC/STM32F378xx Product devices)
* @{
*/
-#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
/**
@@ -183,7 +183,7 @@
/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
* @{
*/
-#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
PA0 for COMP7) connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
@@ -194,7 +194,7 @@
/** @defgroup COMPEx_NonInvertingInput COMP Extended NonInvertingInput (Other Product devices)
* @{
*/
-#define COMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
+#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
connected to comparator non inverting input */
/**
* @}
@@ -209,23 +209,23 @@
* @{
*/
/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
-#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000142AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
-#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
/**
* @}
*/
@@ -237,26 +237,26 @@
* @{
*/
/* Output Redirection values common to all comparators COMP2, COMP4 and COMP6 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0000002A) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000082A) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_NONE (0x0000002AU) /*!< COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000082AU) /*!< COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
/* Output Redirection common to COMP2 and COMP4 */
-#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0A) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0AU) /*!< COMP2 or COMP4 output connected to TIM3 OCREF Clear */
/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001802) /*!< COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C02) /*!< COMP2 output connected to TIM1 Input Capture 1 */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002002) /*!< COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002402) /*!< COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002802) /*!< COMP2 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001802U) /*!< COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C02U) /*!< COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002002U) /*!< COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002402U) /*!< COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 (0x00002802U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
-#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
-#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
/**
* @}
*/
@@ -268,29 +268,29 @@
* @{
*/
/* Output Redirection values common to all comparators COMP1, COMP2, COMP4, COMP6 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0000002B) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000042B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2_BRK2 ((uint32_t)0x0000082B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
-#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000142B) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_NONE (0x0000002BU) /*!< COMP1, COMP2, COMP4 or COMP6 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000042BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2_BRK2 (0x0000082BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BRK2) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000142BU) /*!< COMP1, COMP2, COMP4 or COMP6 output connected to TIM1 Break Input 2 (BKIN2) */
/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001803) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
-#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002403) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001803U) /*!< COMP1 or COMP2 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002403U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
/* Output Redirection common to COMP1,COMP2 and COMP4 */
-#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C0B) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C0BU) /*!< COMP1, COMP2 or COMP4 output connected to TIM3 OCREF Clear */
/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
-#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
-#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
-#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
-#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
/**
* @}
*/
@@ -302,50 +302,50 @@
* @{
*/
/* Output Redirection values common to all comparators COMP1...COMP7 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
+#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
/* Output Redirection common to COMP1, COMP2 and COMP3 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
-#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
/* Output Redirection specific to COMP3 */
-#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */
-#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */
-#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */
-#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
+#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
+#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
-#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
-#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
-#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
/* Output Redirection specific to COMP5 */
-#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */
-#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */
-#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */
-#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
+#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
+#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
-#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
/* Output Redirection specific to COMP7 */
-#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */
-#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */
-#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */
-#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
+#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
+#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
/**
* @}
*/
@@ -357,55 +357,55 @@
* @{
*/
/* Output Redirection values common to all comparators COMP1...COMP7 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0000007F) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM1BKIN ((uint32_t)0x0000047F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM1BKIN2 ((uint32_t)0x0000087F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM8BKIN ((uint32_t)0x00000C7F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM8BKIN2 ((uint32_t)0x0000107F) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x0000147F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
-#define COMP_OUTPUT_TIM20BKIN ((uint32_t)0x0000307F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
-#define COMP_OUTPUT_TIM20BKIN2 ((uint32_t)0x0000347F) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
-#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 ((uint32_t)0x0000387F) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2, TIM8 Break Input 2 and TIM20 Break Input 2 */
+#define COMP_OUTPUT_NONE (0x0000007FU) /*!< COMP1, COMP2... or COMP7 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM1BKIN (0x0000047FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM1BKIN2 (0x0000087FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM8BKIN (0x00000C7FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM8BKIN2 (0x0000107FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM8 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2 (0x0000147FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2 and TIM8 Break Input 2U */
+#define COMP_OUTPUT_TIM20BKIN (0x0000307FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM20BKIN2 (0x0000347FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM20 Break Input 2 (BKIN2) */
+#define COMP_OUTPUT_TIM1BKIN2_TIM8BKIN2_TIM20BKIN2 (0x0000387FU) /*!< COMP1, COMP2... or COMP7 output connected to TIM1 Break Input 2U, TIM8 Break Input 2 and TIM20 Break Input 2 */
/* Output Redirection common to COMP1, COMP2, COMP3 and COMP7 */
-#define COMP_OUTPUT_TIM1OCREFCLR ((uint32_t)0x00001847) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
+#define COMP_OUTPUT_TIM1OCREFCLR (0x00001847U) /*!< COMP1, COMP2, COMP3 or COMP7 output connected to TIM1 OCREF Clear */
/* Output Redirection common to COMP1, COMP2 and COMP3 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x00002407) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x00002407U) /*!< COMP1, COMP2 or COMP3 output connected to TIM2 OCREF Clear */
/* Output Redirection common to COMP1, COMP2, COMP4 and COMP5 */
-#define COMP_OUTPUT_TIM3OCREFCLR ((uint32_t)0x00002C1B) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM3OCREFCLR (0x00002C1BU) /*!< COMP1, COMP2, COMP4 or COMP5 output connected to TIM3 OCREF Clear */
/* Output Redirection common to COMP4, COMP5, COMP6 and COMP7 */
-#define COMP_OUTPUT_TIM8OCREFCLR ((uint32_t)0x00001C78) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
+#define COMP_OUTPUT_TIM8OCREFCLR (0x00001C78U) /*!< COMP4, COMP5, COMP6 or COMP7 output connected to TIM8 OCREF Clear */
/* Output Redirection common to COMP1 and COMP2 */
-#define COMP_OUTPUT_TIM1IC1 ((uint32_t)0x00001C03) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1 */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x00002003) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM3IC1 ((uint32_t)0x00002803) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1 */
+#define COMP_OUTPUT_TIM1IC1 (0x00001C03U) /*!< COMP1 or COMP2 output connected to TIM1 Input Capture 1U */
+#define COMP_OUTPUT_TIM2IC4 (0x00002003U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM3IC1 (0x00002803U) /*!< COMP1 or COMP2 output connected to TIM3 Input Capture 1U */
/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM20OCREFCLR ((uint32_t)0x00003C04) /*!< COMP2 output connected to TIM20 OCREF Clear */
+#define COMP_OUTPUT_TIM20OCREFCLR (0x00003C04U) /*!< COMP2 output connected to TIM20 OCREF Clear */
/* Output Redirection specific to COMP3 */
-#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x00001C04) /*!< COMP3 output connected to TIM4 Input Capture 1 */
-#define COMP_OUTPUT_TIM3IC2 ((uint32_t)0x00002004) /*!< COMP3 output connected to TIM3 Input Capture 2 */
-#define COMP_OUTPUT_TIM15IC1 ((uint32_t)0x00002804) /*!< COMP3 output connected to TIM15 Input Capture 1 */
-#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x00002C04) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM4IC1 (0x00001C04U) /*!< COMP3 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM3IC2 (0x00002004U) /*!< COMP3 output connected to TIM3 Input Capture 2U */
+#define COMP_OUTPUT_TIM15IC1 (0x00002804U) /*!< COMP3 output connected to TIM15 Input Capture 1U */
+#define COMP_OUTPUT_TIM15BKIN (0x00002C04U) /*!< COMP3 output connected to TIM15 Break Input (BKIN) */
/* Output Redirection specific to COMP4 */
-#define COMP_OUTPUT_TIM3IC3 ((uint32_t)0x00001808) /*!< COMP4 output connected to TIM3 Input Capture 3 */
-#define COMP_OUTPUT_TIM15IC2 ((uint32_t)0x00002008) /*!< COMP4 output connected to TIM15 Input Capture 2 */
-#define COMP_OUTPUT_TIM4IC2 ((uint32_t)0x00002408) /*!< COMP4 output connected to TIM4 Input Capture 2 */
-#define COMP_OUTPUT_TIM15OCREFCLR ((uint32_t)0x00002808) /*!< COMP4 output connected to TIM15 OCREF Clear */
+#define COMP_OUTPUT_TIM3IC3 (0x00001808U) /*!< COMP4 output connected to TIM3 Input Capture 3U */
+#define COMP_OUTPUT_TIM15IC2 (0x00002008U) /*!< COMP4 output connected to TIM15 Input Capture 2U */
+#define COMP_OUTPUT_TIM4IC2 (0x00002408U) /*!< COMP4 output connected to TIM4 Input Capture 2U */
+#define COMP_OUTPUT_TIM15OCREFCLR (0x00002808U) /*!< COMP4 output connected to TIM15 OCREF Clear */
/* Output Redirection specific to COMP5 */
-#define COMP_OUTPUT_TIM2IC1 ((uint32_t)0x00001810) /*!< COMP5 output connected to TIM2 Input Capture 1 */
-#define COMP_OUTPUT_TIM17IC1 ((uint32_t)0x00002010) /*!< COMP5 output connected to TIM17 Input Capture 1 */
-#define COMP_OUTPUT_TIM4IC3 ((uint32_t)0x00002410) /*!< COMP5 output connected to TIM4 Input Capture 3 */
-#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x00002810) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM2IC1 (0x00001810U) /*!< COMP5 output connected to TIM2 Input Capture 1U */
+#define COMP_OUTPUT_TIM17IC1 (0x00002010U) /*!< COMP5 output connected to TIM17 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC3 (0x00002410U) /*!< COMP5 output connected to TIM4 Input Capture 3U */
+#define COMP_OUTPUT_TIM16BKIN (0x00002810U) /*!< COMP5 output connected to TIM16 Break Input (BKIN) */
/* Output Redirection specific to COMP6 */
-#define COMP_OUTPUT_TIM2IC2 ((uint32_t)0x00001820) /*!< COMP6 output connected to TIM2 Input Capture 2 */
-#define COMP_OUTPUT_COMP6_TIM2OCREFCLR ((uint32_t)0x00002020) /*!< COMP6 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM16OCREFCLR ((uint32_t)0x00002420) /*!< COMP6 output connected to TIM16 OCREF Clear */
-#define COMP_OUTPUT_TIM16IC1 ((uint32_t)0x00002820) /*!< COMP6 output connected to TIM16 Input Capture 1 */
-#define COMP_OUTPUT_TIM4IC4 ((uint32_t)0x00002C20) /*!< COMP6 output connected to TIM4 Input Capture 4 */
+#define COMP_OUTPUT_TIM2IC2 (0x00001820U) /*!< COMP6 output connected to TIM2 Input Capture 2U */
+#define COMP_OUTPUT_COMP6_TIM2OCREFCLR (0x00002020U) /*!< COMP6 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_TIM16OCREFCLR (0x00002420U) /*!< COMP6 output connected to TIM16 OCREF Clear */
+#define COMP_OUTPUT_TIM16IC1 (0x00002820U) /*!< COMP6 output connected to TIM16 Input Capture 1U */
+#define COMP_OUTPUT_TIM4IC4 (0x00002C20U) /*!< COMP6 output connected to TIM4 Input Capture 4U */
/* Output Redirection specific to COMP7 */
-#define COMP_OUTPUT_TIM2IC3 ((uint32_t)0x00002040) /*!< COMP7 output connected to TIM2 Input Capture 3 */
-#define COMP_OUTPUT_TIM1IC2 ((uint32_t)0x00002440) /*!< COMP7 output connected to TIM1 Input Capture 2 */
-#define COMP_OUTPUT_TIM17OCREFCLR ((uint32_t)0x00002840) /*!< COMP7 output connected to TIM17 OCREF Clear */
-#define COMP_OUTPUT_TIM17BKIN ((uint32_t)0x00002C40) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
+#define COMP_OUTPUT_TIM2IC3 (0x00002040U) /*!< COMP7 output connected to TIM2 Input Capture 3U */
+#define COMP_OUTPUT_TIM1IC2 (0x00002440U) /*!< COMP7 output connected to TIM1 Input Capture 2U */
+#define COMP_OUTPUT_TIM17OCREFCLR (0x00002840U) /*!< COMP7 output connected to TIM17 OCREF Clear */
+#define COMP_OUTPUT_TIM17BKIN (0x00002C40U) /*!< COMP7 output connected to TIM17 Break Input (BKIN) */
/**
* @}
*/
@@ -417,21 +417,21 @@
* @{
*/
/* Output Redirection values common to all comparators COMP1 and COMP2 */
-#define COMP_OUTPUT_NONE ((uint32_t)0x0003) /*!< COMP1 or COMP2 output isn't connected to other peripherals */
-#define COMP_OUTPUT_TIM2IC4 ((uint32_t)0x0403) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR ((uint32_t)0x0503) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
+#define COMP_OUTPUT_NONE (0x0003U) /*!< COMP1 or COMP2 output isn't connected to other peripherals */
+#define COMP_OUTPUT_TIM2IC4 (0x0403U) /*!< COMP1 or COMP2 output connected to TIM2 Input Capture 4U */
+#define COMP_OUTPUT_TIM2OCREFCLR (0x0503U) /*!< COMP1 or COMP2 output connected to TIM2 OCREF Clear */
/* Output Redirection specific to COMP1 */
-#define COMP_OUTPUT_TIM15BKIN ((uint32_t)0x0101) /*!< COMP1 output connected to TIM15 Break Input */
-#define COMP_OUTPUT_COMP1_TIM3IC1 ((uint32_t)0x0201) /*!< COMP1 output connected to TIM3 Input Capture 1 */
-#define COMP_OUTPUT_COMP1_TIM3OCREFCLR ((uint32_t)0x0301) /*!< COMP1 output connected to TIM3 OCREF Clear */
-#define COMP_OUTPUT_TIM5IC4 ((uint32_t)0x0601) /*!< COMP1 output connected to TIM5 Input Capture 4 */
-#define COMP_OUTPUT_TIM5OCREFCLR ((uint32_t)0x0701) /*!< COMP1 output connected to TIM5 OCREF Clear */
+#define COMP_OUTPUT_TIM15BKIN (0x0101U) /*!< COMP1 output connected to TIM15 Break Input */
+#define COMP_OUTPUT_COMP1_TIM3IC1 (0x0201U) /*!< COMP1 output connected to TIM3 Input Capture 1U */
+#define COMP_OUTPUT_COMP1_TIM3OCREFCLR (0x0301U) /*!< COMP1 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM5IC4 (0x0601U) /*!< COMP1 output connected to TIM5 Input Capture 4U */
+#define COMP_OUTPUT_TIM5OCREFCLR (0x0701U) /*!< COMP1 output connected to TIM5 OCREF Clear */
/* Output Redirection specific to COMP2 */
-#define COMP_OUTPUT_TIM16BKIN ((uint32_t)0x0102) /*!< COMP2 output connected to TIM16 Break Input */
-#define COMP_OUTPUT_TIM4IC1 ((uint32_t)0x0202) /*!< COMP2 output connected to TIM4 Input Capture 1 */
-#define COMP_OUTPUT_TIM4OCREFCLR ((uint32_t)0x0302) /*!< COMP2 output connected to TIM4 OCREF Clear */
-#define COMP_OUTPUT_COMP2_TIM3IC1 ((uint32_t)0x0602) /*!< COMP2 output connected to TIM3 Input Capture 1 */
-#define COMP_OUTPUT_COMP2_TIM3OCREFCLR ((uint32_t)0x0702) /*!< COMP2 output connected to TIM3 OCREF Clear */
+#define COMP_OUTPUT_TIM16BKIN (0x0102U) /*!< COMP2 output connected to TIM16 Break Input */
+#define COMP_OUTPUT_TIM4IC1 (0x0202U) /*!< COMP2 output connected to TIM4 Input Capture 1U */
+#define COMP_OUTPUT_TIM4OCREFCLR (0x0302U) /*!< COMP2 output connected to TIM4 OCREF Clear */
+#define COMP_OUTPUT_COMP2_TIM3IC1 (0x0602U) /*!< COMP2 output connected to TIM3 Input Capture 1U */
+#define COMP_OUTPUT_COMP2_TIM3OCREFCLR (0x0702U) /*!< COMP2 output connected to TIM3 OCREF Clear */
/**
* @}
*/
@@ -441,9 +441,9 @@
/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xC/STM32F303xC/STM32F358xx Product devices)
* @{
*/
-#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6)
- is connected to the non inverting input of comparator X-1 */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
+ is connected to the non inverting input of comparator X-1U */
/**
* @}
*/
@@ -451,9 +451,9 @@
/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F302xE/STM32F303xE/STM32F398xx Product devices)
* @{
*/
-#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
-#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2,4,6)
- is connected to the non inverting input of comparator X-1 */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMPxWNDWEN /*!< Window mode enabled: non inverting input of comparator X (x=2U,4,6U)
+ is connected to the non inverting input of comparator X-1U */
/**
* @}
*/
@@ -461,7 +461,7 @@
/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (STM32F373xC/STM32F378xx Product devices)
* @{
*/
-#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled */
#define COMP_WINDOWMODE_ENABLE ((uint32_t)COMP_CSR_COMPxWNDWEN) /*!< Window mode enabled: non inverting input of comparator 2
is connected to the non inverting input of comparator 1 (PA1) */
/**
@@ -471,7 +471,7 @@
/** @defgroup COMPEx_WindowMode COMP Extended WindowMode (Other Product devices)
* @{
*/
-#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled (not available) */
+#define COMP_WINDOWMODE_DISABLE (0x00000000U) /*!< Window mode disabled (not available) */
/**
* @}
*/
@@ -485,7 +485,7 @@
/* Please refer to the electrical characteristics in the device datasheet for
the power consumption values */
-#define COMP_MODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */
+#define COMP_MODE_HIGHSPEED (0x00000000U) /*!< High Speed */
#define COMP_MODE_MEDIUMSPEED COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
#define COMP_MODE_LOWPOWER COMP_CSR_COMPxMODE_1 /*!< Low power mode */
#define COMP_MODE_ULTRALOWPOWER COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
@@ -502,14 +502,14 @@
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH COMP_CSR_COMPxHYST /*!< Hysteresis level high */
#else
-#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
+#define COMP_HYSTERESIS_NONE (0x00000000U) /*!< No hysteresis */
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
@@ -523,7 +523,7 @@
* @{
*/
/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
/* Blanking source for COMP2 */
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP2 */
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC3 selected as blanking source for COMP2 */
@@ -547,7 +547,7 @@
* @{
*/
/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
/* Blanking source common for COMP1 and COMP2 */
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1 and COMP2 */
/* Blanking source common for COMP1 and COMP2 */
@@ -573,7 +573,7 @@
* @{
*/
/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
/* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for COMP1, COMP2, COMP3 and COMP7 */
/* Blanking source common for COMP1 and COMP2 */
@@ -601,7 +601,7 @@
* @{
*/
/* No blanking source can be selected for all comparators */
-#define COMP_BLANKINGSRCE_NONE ((uint32_t)0x00000000) /*!< No blanking source */
+#define COMP_BLANKINGSRCE_NONE (0x00000000U) /*!< No blanking source */
/**
* @}
*/
@@ -645,7 +645,7 @@
regshift = COMP_CSR_COMP2_SHIFT; \
} \
SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the specified comparator.
@@ -661,7 +661,7 @@
regshift = COMP_CSR_COMP2_SHIFT; \
} \
CLEAR_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxEN << regshift); \
- } while(0)
+ } while(0U)
/**
* @brief Lock a comparator instance
@@ -677,7 +677,7 @@
regshift = COMP_CSR_COMP2_SHIFT; \
} \
SET_BIT(COMP->CSR, (uint32_t)COMP_CSR_COMPxLOCK << regshift); \
- } while(0)
+ } while(0U)
/** @brief Check whether the specified COMP flag is set or not.
* @param __HANDLE__ COMP Handle.
@@ -759,7 +759,7 @@
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
@@ -768,7 +768,7 @@
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
@@ -847,7 +847,7 @@
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
@@ -856,7 +856,7 @@
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP2 EXTI line in interrupt mode.
@@ -934,7 +934,7 @@
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP3 EXTI line rising & falling edge trigger.
@@ -943,7 +943,7 @@
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP3 EXTI line in interrupt mode.
@@ -1026,7 +1026,7 @@
#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP4 EXTI line rising & falling edge trigger.
@@ -1035,7 +1035,7 @@
#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP4 EXTI line in interrupt mode.
@@ -1118,7 +1118,7 @@
#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP5 EXTI line rising & falling edge trigger.
@@ -1127,7 +1127,7 @@
#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP5 EXTI line in interrupt mode.
@@ -1210,7 +1210,7 @@
#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP6 EXTI line rising & falling edge trigger.
@@ -1219,7 +1219,7 @@
#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP6 EXTI line in interrupt mode.
@@ -1301,7 +1301,7 @@
#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable the COMP7 EXTI line rising & falling edge trigger.
@@ -1310,7 +1310,7 @@
#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0)
+ } while(0U)
/**
* @brief Enable the COMP7 EXTI line in interrupt mode.
@@ -1431,30 +1431,30 @@
#define COMP_CSR_COMPxPOL_MASK COMP_CSR_COMPxPOL /*!< COMP_CSR_COMPxPOL Mask */
#if defined(STM32F373xC) || defined(STM32F378xx)
/* CSR register reset value */
-#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
-#define COMP_CSR_RESET_PARAMETERS_MASK ((uint32_t)0x00003FFF)
-#define COMP_CSR_UPDATE_PARAMETERS_MASK ((uint32_t)0x00003FFE)
+#define COMP_CSR_RESET_VALUE (0x00000000U)
+#define COMP_CSR_RESET_PARAMETERS_MASK (0x00003FFFU)
+#define COMP_CSR_UPDATE_PARAMETERS_MASK (0x00003FFEU)
/* CSR COMP1/COMP2 shift */
#define COMP_CSR_COMP1_SHIFT 0U
#define COMP_CSR_COMP2_SHIFT 16U
#else
/* CSR register reset value */
-#define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+#define COMP_CSR_RESET_VALUE (0x00000000U)
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define COMP_CSR_COMPxNONINSEL_MASK (COMP2_CSR_COMP2INPDAC) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define COMP_CSR_COMPxNONINSEL_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxWNDWEN_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxNONINSEL_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
@@ -1468,9 +1468,9 @@
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define COMP_CSR_COMPxNONINSEL_MASK (COMP1_CSR_COMP1SW1) /*!< COMP_CSR_COMPxNONINSEL mask */
-#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
-#define COMP_CSR_COMPxMODE_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
-#define COMP_CSR_COMPxHYST_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxWNDWEN_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxMODE_MASK (0x00000000U) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxHYST_MASK (0x00000000U) /*!< Mask empty: feature not available */
#define COMP_CSR_COMPxBLANKING_MASK COMP_CSR_COMPxBLANKING /*!< COMP_CSR_COMPxBLANKING mask */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
@@ -1479,7 +1479,7 @@
#define COMP_CSR_COMPxWNDWEN_MASK COMP_CSR_COMPxWNDWEN /*!< COMP_CSR_COMPxWNDWEN mask */
#define COMP_CSR_COMPxMODE_MASK COMP_CSR_COMPxMODE /*!< COMP_CSR_COMPxMODE Mask */
#define COMP_CSR_COMPxHYST_MASK COMP_CSR_COMPxHYST /*!< COMP_CSR_COMPxHYST Mask */
-#define COMP_CSR_COMPxBLANKING_MASK ((uint32_t)0x00000000) /*!< Mask empty: feature not available */
+#define COMP_CSR_COMPxBLANKING_MASK (0x00000000U) /*!< Mask empty: feature not available */
#endif /* STM32F373xC || STM32F378xx */
/**
@@ -1592,7 +1592,7 @@
{ \
COMP->CSR |= COMP_CSR_WNDWEN; \
} \
- } while(0)
+ } while(0U)
/**
* @brief DeInit a comparator instance
@@ -1610,7 +1610,7 @@
MODIFY_REG(COMP->CSR, \
COMP_CSR_RESET_PARAMETERS_MASK << regshift, \
COMP_CSR_RESET_VALUE << regshift); \
- } while(0)
+ } while(0U)
/**
@@ -1703,7 +1703,7 @@
*/
#define COMP_INIT(__HANDLE__) \
do { \
- __IO uint32_t csrreg = 0; \
+ __IO uint32_t csrreg = 0U; \
\
csrreg = READ_REG((__HANDLE__)->Instance->CSR); \
MODIFY_REG(csrreg, COMP_CSR_COMPxINSEL_MASK, (__HANDLE__)->Init.InvertingInput); \
@@ -1715,7 +1715,7 @@
MODIFY_REG(csrreg, COMP_CSR_COMPxMODE_MASK, (__HANDLE__)->Init.Mode); \
MODIFY_REG(csrreg, COMP_CSR_COMPxWNDWEN_MASK, (__HANDLE__)->Init.WindowMode); \
WRITE_REG((__HANDLE__)->Instance->CSR, csrreg); \
- } while(0)
+ } while(0U)
/**
* @brief DeInit a comparator instance
@@ -1933,7 +1933,7 @@
((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
((((INSTANCE) == COMP2) && \
(((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
@@ -2032,7 +2032,7 @@
((SOURCE) == COMP_BLANKINGSRCE_TIM15OC1) || \
((SOURCE) == COMP_BLANKINGSRCE_TIM15OC2))
-/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6/8, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
+/* STM32F301x6/x8, STM32F302x6/x8, STM32F303x6/x8, STM32F334x4/6U/8U, STM32F318xx/STM32F328xx devices comparator instances blanking source values */
#define IS_COMP_BLANKINGSRCE_INSTANCE(INSTANCE, BLANKINGSRCE) \
((((INSTANCE) == COMP2) && \
(((BLANKINGSRCE) == COMP_BLANKINGSRCE_NONE) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_conf.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_conf.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_conf.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief HAL configuration file.
******************************************************************************
* @attention
@@ -92,7 +92,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
@@ -100,7 +100,7 @@
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -109,7 +109,7 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@@ -117,14 +117,14 @@
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
- #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
+ #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
- #define LSI_VALUE ((uint32_t)40000)
+ #define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -132,14 +132,14 @@
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+ #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+ #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
@@ -150,7 +150,7 @@
* - External clock not generated on EVAL 373
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+ #define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -160,8 +160,8 @@
/**
* @brief This is the HAL system configuration section
*/
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
+#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 0
@@ -172,7 +172,7 @@
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
-/*#define USE_FULL_ASSERT 1*/
+/*#define USE_FULL_ASSERT 1U*/
/* Includes ------------------------------------------------------------------*/
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -46,7 +46,7 @@
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
@@ -105,19 +105,19 @@
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
==========================================================================================================================
@@ -208,7 +208,7 @@
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t prioritygroup = 0x00;
+ uint32_t prioritygroup = 0x00U;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
@@ -294,8 +294,42 @@
* @{
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
+
+/**
+ * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU */
+ MPU->CTRL = 0U;
+}
+
/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+
+ /**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
@@ -335,8 +369,8 @@
}
else
{
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
+ MPU->RBAR = 0x00U;
+ MPU->RASR = 0x00U;
}
}
#endif /* __MPU_PRESENT */
@@ -404,7 +438,7 @@
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- /* Return 1 if pending else 0 */
+ /* Return 1 if pending else 0U */
return NVIC_GetPendingIRQ(IRQn);
}
@@ -431,7 +465,7 @@
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
- /* Return 1 if active else 0 */
+ /* Return 1 if active else 0U */
return NVIC_GetActive(IRQn);
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
@@ -58,7 +58,7 @@
* @{
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@@ -105,15 +105,15 @@
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
+#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
@@ -122,20 +122,20 @@
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
+#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
/**
* @}
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
-#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
-#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
-#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
-#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
+#define MPU_HARDFAULT_NMI (0x00000002U)
+#define MPU_PRIVILEGED_DEFAULT (0x00000004U)
+#define MPU_HFNMI_PRIVDEF (0x00000006U)
/**
* @}
*/
@@ -143,8 +143,8 @@
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
+#define MPU_REGION_ENABLE ((uint8_t)0x01U)
+#define MPU_REGION_DISABLE ((uint8_t)0x00U)
/**
* @}
*/
@@ -152,8 +152,8 @@
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
+#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
+#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
@@ -161,8 +161,8 @@
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
+#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
/**
* @}
*/
@@ -170,8 +170,8 @@
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
+#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
/**
* @}
*/
@@ -179,8 +179,8 @@
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
+#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
+#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
/**
* @}
*/
@@ -188,9 +188,9 @@
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
+#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
+#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
+#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
/**
* @}
*/
@@ -198,34 +198,34 @@
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
* @}
*/
@@ -233,12 +233,12 @@
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
+#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
/**
* @}
*/
@@ -246,14 +246,14 @@
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
+#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
+#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
+#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
/**
* @}
*/
@@ -289,7 +289,7 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
@@ -322,9 +322,9 @@
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
@@ -337,7 +337,7 @@
* @}
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
@@ -402,7 +402,7 @@
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */
/**
@@ -415,39 +415,11 @@
* @{
*/
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU */
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
+#if (__MPU_PRESENT == 1U)
-/**
- * @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
+void HAL_MPU_Disable(void);
+void HAL_MPU_Enable(uint32_t MPU_Control);
+
#endif /* __MPU_PRESENT */
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_crc.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -276,12 +276,12 @@
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
using the combination of the previous CRC value and the new one
[..] or
- (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
@@ -305,8 +305,8 @@
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+ uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
@@ -318,7 +318,7 @@
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@@ -365,8 +365,8 @@
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0; /* CRC input data buffer index */
- uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
+ uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
@@ -382,7 +382,7 @@
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@@ -464,27 +464,27 @@
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0; /* input data buffer index */
+ uint32_t i = 0U; /* input data buffer index */
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the IP */
- for(i = 0; i < (BufferLength/4); i++)
+ for(i = 0U; i < (BufferLength/4U); i++)
{
- hcrc->Instance->DR = ((uint32_t)pBuffer[4*i]<<24) | ((uint32_t)pBuffer[4*i+1]<<16) | ((uint32_t)pBuffer[4*i+2]<<8) | (uint32_t)pBuffer[4*i+3];
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
}
/* last bytes specific handling */
- if ((BufferLength%4) != 0)
+ if ((BufferLength%4U) != 0U)
{
- if (BufferLength%4 == 1)
+ if (BufferLength%4U == 1U)
{
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
}
- if (BufferLength%4 == 2)
+ if (BufferLength%4U == 2U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
}
- if (BufferLength%4 == 3)
+ if (BufferLength%4U == 3U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
*(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
@@ -507,16 +507,16 @@
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0; /* input data buffer index */
+ uint32_t i = 0U; /* input data buffer index */
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the IP */
- for(i = 0; i < (BufferLength/2); i++)
+ for(i = 0U; i < (BufferLength/2U); i++)
{
- hcrc->Instance->DR = ((uint32_t)pBuffer[2*i]<<16) | (uint32_t)pBuffer[2*i+1];
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
}
- if ((BufferLength%2) != 0)
+ if ((BufferLength%2U) != 0U)
{
*(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_crc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@@ -63,10 +63,10 @@
*/
typedef enum
{
- HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
}HAL_CRC_StateTypeDef;
@@ -78,7 +78,7 @@
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+ X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
@@ -87,9 +87,9 @@
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
- uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
- e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7U, 8U, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7U, 8U, 16 or 32. This field is written in normal representation,
+ e.g., for a polynomial of degree 7U, X^7U + X^6U + X^5U + X^2U + 1 is written 0x65.
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
@@ -107,12 +107,12 @@
@arg CRC_INPUTDATA_INVERSION_NONE, no input data inversion
@arg CRC_INPUTDATA_INVERSION_BYTE, byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
@arg CRC_INPUTDATA_INVERSION_HALFWORD, halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+ @arg CRC_INPUTDATA_INVERSION_WORD, word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458U */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion,
- @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488 */
+ @arg CRC_OUTPUTDATA_INVERSION_ENABLE: CRC 0x11223344 is converted into 0x22CC4488U */
}CRC_InitTypeDef;
@@ -149,7 +149,7 @@
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
-#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+#define DEFAULT_CRC32_POLY 0x04C11DB7 /*!< X^32U + X^26U + X^23U + X^22U + X^16U + X^12U + X^11U + X^10U +X^8U + X^7U + X^5U + X^4U + X^2U+ X +1U */
/**
* @}
@@ -167,8 +167,8 @@
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) /*!< Enable default generating polynomial 0x04C11DB7 */
-#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) /*!< Disable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7U */
/**
* @}
*/
@@ -176,8 +176,8 @@
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
-#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) /*!< Enable initial CRC default value */
-#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) /*!< Disable initial CRC default value */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
@@ -185,7 +185,7 @@
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{
*/
-#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_32B (0x00000000U) /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) /*!< Resort to a 7-bit long generating polynomial */
@@ -212,10 +212,10 @@
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000) /*!< Undefined input data format */
-#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) /*!< Input data in byte format */
-#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) /*!< Input data in half-word format */
-#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) /*!< Input data in word format */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U) /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U) /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U) /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U) /*!< Input data in word format */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_crc_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
@@ -106,7 +106,7 @@
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
- uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
@@ -118,7 +118,7 @@
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while (((Pol & (1U << msb)) == 0) && (msb-- > 0)){}
+ while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U)){}
switch (PolyLength)
{
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
@@ -63,7 +63,7 @@
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended Input Data Inversion Modes
* @{
*/
-#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U) /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) /*!< Word-wise input data inversion */
@@ -74,7 +74,7 @@
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended Output Data Inversion Modes
* @{
*/
-#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U) /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) /*!< Bit-wise output data inversion */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dac.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -105,7 +105,7 @@
VEF+ is the input voltage reference (refer to the device datasheet)
[..]
e.g. To set DAC_OUT1 to 0.7V, use
- (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+ (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
*** DMA requests ***
=====================
@@ -490,8 +490,8 @@
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
- /* For all products including channel 2 */
- /* DAC channel 2 is available on top of DAC channel 1 */
+ /* For all products including channel 2U */
+ /* DAC channel 2 is available on top of DAC channel 1U */
else /* Channel2 is used for */
{
/* Disable the DMA channel */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dac.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@@ -65,10 +65,10 @@
*/
typedef enum
{
- HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
+ HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
}HAL_DAC_StateTypeDef;
@@ -104,9 +104,9 @@
HAL_LockTypeDef Lock; /*!< DAC locking object */
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
+ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
+ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */
__IO uint32_t ErrorCode; /*!< DAC Error code */
@@ -134,7 +134,7 @@
/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
* @{
*/
-#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@@ -146,18 +146,18 @@
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */
+#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
+#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
+#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
+#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
+#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
+#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
+#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
+#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
+#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
+#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
+#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
/**
* @}
@@ -166,7 +166,7 @@
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
-#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
@@ -177,7 +177,7 @@
/** @defgroup DAC_output_switch DAC output switch
* @{
*/
-#define DAC_OUTPUTSWITCH_DISABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U)
#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
/**
@@ -188,9 +188,9 @@
/** @defgroup DAC_data_alignement DAC data alignement
* @{
*/
-#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+#define DAC_ALIGN_12B_R (0x00000000U)
+#define DAC_ALIGN_12B_L (0x00000004U)
+#define DAC_ALIGN_8B_R (0x00000008U)
/**
* @}
@@ -251,19 +251,19 @@
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt
* @param __HANDLE__: specifies the DAC handle
@@ -362,7 +362,7 @@
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief DACEx HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
@@ -81,7 +81,7 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1 */
+/* DAC channel 2 is available on top of DAC channel 1U */
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
@@ -108,7 +108,7 @@
[..] This section provides functions allowing to:
(+) Set the specified data holding register value for DAC channel.
(+) Set the specified data holding register value for dual DAC channel
- (when DAC channel 2 is present in DAC 1)
+ (when DAC channel 2 is present in DAC 1U)
@endverbatim
* @{
@@ -129,7 +129,7 @@
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -139,7 +139,7 @@
tmp = (uint32_t) (hdac->Instance);
/* DAC 1 has 1 or 2 channels - no DAC2 */
-/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
if(Channel == DAC_CHANNEL_1)
{
@@ -169,7 +169,7 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is present in DAC 1 */
+/* DAC channel 2 is present in DAC 1U */
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -187,7 +187,7 @@
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
- uint32_t data = 0, tmp = 0;
+ uint32_t data = 0U, tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
@@ -197,11 +197,11 @@
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
- data = ((uint32_t)Data2 << 8) | Data1;
+ data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
- data = ((uint32_t)Data2 << 16) | Data1;
+ data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t) (hdac->Instance);
@@ -246,7 +246,7 @@
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -307,7 +307,7 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channels 1 */
+/* DAC 1 has 1 channels 1U */
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -352,12 +352,12 @@
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC 1 has 2 channels 1 & 2 */
+/* DAC 1 has 2 channels 1U & 2U */
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -377,7 +377,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
@@ -403,7 +403,7 @@
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
- /* Case of use of channel 1 */
+ /* Case of use of channel 1U */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
@@ -436,7 +436,7 @@
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
- /* Case of use of channel 2 */
+ /* Case of use of channel 2U */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
@@ -491,7 +491,7 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channel (channel 1) */
+/* DAC 1 has 1 channel (channel 1U) */
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -510,7 +510,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
@@ -534,7 +534,7 @@
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
- /* Case of use of channel 1 */
+ /* Case of use of channel 1U */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
@@ -573,12 +573,12 @@
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
-/* DAC 1 has 2 channels 1 & 2 - DAC 2 has one channel 1 */
+/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC 1 has 2 channels 1 & 2 */
+/* DAC 1 has 2 channels 1U & 2U */
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -612,7 +612,7 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/* DAC 1 has 1 channel (channel 1) */
+/* DAC 1 has 1 channel (channel 1U) */
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -642,7 +642,7 @@
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
tmp |= hdac->Instance->DOR1;
@@ -650,8 +650,8 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is present in DAC 1 */
- tmp |= hdac->Instance->DOR2 << 16;
+/* DAC channel 2 is present in DAC 1U */
+ tmp |= hdac->Instance->DOR2 << 16U;
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -665,7 +665,7 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1 */
+/* DAC channel 2 is available on top of DAC channel 1U */
/**
* @brief Handles DAC interrupt request
* This function uses the interruption of DMA
@@ -678,7 +678,7 @@
{
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
{
- /* Check underrun flag of DAC channel 1 */
+ /* Check underrun flag of DAC channel 1U */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
@@ -700,7 +700,7 @@
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
- /* Check underrun flag of DAC channel 1 */
+ /* Check underrun flag of DAC channel 1U */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{
/* Change DAC state to error state */
@@ -741,7 +741,7 @@
{
if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
{
- /* Check underrun flag of DAC channel 1 */
+ /* Check underrun flag of DAC channel 1U */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
@@ -780,7 +780,7 @@
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
@@ -791,7 +791,7 @@
/* Output Buffer (BOFF1) control */
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
}
- else /* DAC1 channel 2 & DAC2 channel 1 */
+ else /* DAC1 channel 2U & DAC2 channel 1U */
{
/* Output Switch (OUTEN) control */
assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
@@ -823,7 +823,7 @@
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
}
- else /* DAC1 channel 2 & DAC2 channel 1 */
+ else /* DAC1 channel 2U & DAC2 channel 1U */
{
/* Output Switch (OUTEN) control */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
@@ -955,7 +955,7 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1 */
+/* DAC channel 2 is available on top of DAC channel 1U */
/**
* @brief Conversion complete callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
@@ -1086,7 +1086,7 @@
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-/* DAC channel 2 is available on top of DAC channel 1 */
+/* DAC channel 2 is available on top of DAC channel 1U */
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to DMA handle.
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
@@ -65,7 +65,7 @@
*/
#if defined(STM32F301x8) || defined(STM32F318xx)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@@ -85,7 +85,7 @@
defined(STM32F302xC) || \
defined(STM32F302x8)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
@@ -111,7 +111,7 @@
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
@@ -141,7 +141,7 @@
#if defined(STM32F303x8) || defined(STM32F328xx)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
@@ -166,7 +166,7 @@
#if defined(STM32F373xC) || defined(STM32F378xx)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
@@ -194,7 +194,7 @@
#if defined(STM32F334x8)
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
@@ -237,7 +237,7 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#endif /* STM32F302xE || */
/* STM32F302xC || */
@@ -246,8 +246,8 @@
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
+#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
@@ -255,8 +255,8 @@
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC Channel 1 */
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC Channel 2 */
+#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
+#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_def.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@@ -56,9 +56,9 @@
*/
typedef enum
{
- HAL_OK = 0x00,
- HAL_ERROR = 0x01,
- HAL_BUSY = 0x02,
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
@@ -67,7 +67,7 @@
*/
typedef enum
{
- HAL_UNLOCKED = 0x00,
+ HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
@@ -81,7 +81,7 @@
do{ \
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
(__DMA_HANDLE_).Parent = (__HANDLE__); \
- } while(0)
+ } while(0U)
#define UNUSED(x) ((void)(x))
@@ -100,9 +100,9 @@
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-#if (USE_RTOS == 1)
+#if (USE_RTOS == 1U)
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
@@ -115,12 +115,12 @@
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
- }while (0)
+ }while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
+ }while (0U)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dma.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -18,7 +18,7 @@
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
- necessary) please refer to Reference manual for connection between peripherals
+ necessary). Please refer to Reference manual for connection between peripherals
and DMA requests .
(#) For a given Channel, program the required configuration through the following parameters:
@@ -48,7 +48,7 @@
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
- (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and
XferErrorCallback (i.e a member of DMA handle structure).
@@ -58,14 +58,6 @@
[..]
Below the list of most used macros in DMA HAL driver.
- (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
- (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
- (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
- (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
- (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
-
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros
@@ -116,14 +108,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
- * @{
- */
-#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
-/**
- * @}
- */
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -131,6 +115,7 @@
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
/**
* @}
*/
@@ -141,7 +126,7 @@
* @{
*/
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
@@ -161,18 +146,18 @@
*/
/**
- * @brief Initializes the DMA according to the specified
- * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check the DMA handle allocation */
- if(hdma == NULL)
+ if(NULL == hdma)
{
return HAL_ERROR;
}
@@ -187,12 +172,6 @@
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
- if(hdma->State == HAL_DMA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
- }
-
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
@@ -213,17 +192,30 @@
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
+ /* Initialize DmaBaseAddress and ChannelIndex parameters used
+ by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+ DMA_CalcBaseAndBitshift(hdma);
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
return HAL_OK;
}
/**
- * @brief DeInitializes the DMA peripheral
+ * @brief DeInitialize the DMA peripheral
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
@@ -231,33 +223,34 @@
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
- if(hdma == NULL)
+ if(NULL == hdma)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Channelx */
- __HAL_DMA_DISABLE(hdma);
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Reset DMA Channel control register */
- hdma->Instance->CCR = 0;
+ hdma->Instance->CCR = 0U;
/* Reset DMA Channel Number of Data to Transfer register */
- hdma->Instance->CNDTR = 0;
+ hdma->Instance->CNDTR = 0U;
/* Reset DMA Channel peripheral address register */
- hdma->Instance->CPAR = 0;
+ hdma->Instance->CPAR = 0U;
+
+ /* Reset DMA Channel memory address register */
+ hdma->Instance->CMAR = 0U;
- /* Reset DMA Channel memory address register */
- hdma->Instance->CMAR = 0;
+ /* Get DMA Base Address */
+ DMA_CalcBaseAndBitshift(hdma);
/* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -295,8 +288,8 @@
*/
/**
- * @brief Starts the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @brief Start the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
@@ -304,26 +297,41 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
- /* Process locked */
- __HAL_LOCK(hdma);
+{
+ HAL_StatusTypeDef status = HAL_OK;
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
+ /* Process locked */
+ __HAL_LOCK(hdma);
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
-
- return HAL_OK;
+ return status;
}
/**
@@ -337,87 +345,82 @@
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
- /* Process locked */
- __HAL_LOCK(hdma);
+ HAL_StatusTypeDef status = HAL_OK;
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ /* Process locked */
+ __HAL_LOCK(hdma);
- /* Enable the transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
- /* Enable the Half transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
- /* Enable the transfer Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Configure the source, destination address and the data length */
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete, & transfer error interrupts */
+ /* Half transfer interrupt is optional: enable it only if associated callback is available */
+ if(NULL != hdma->XferHalfCpltCallback )
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+ }
+ else
+ {
+ hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Enable the Peripheral */
+ hdma->Instance->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
- return HAL_OK;
+ return status;
}
/**
- * @brief Aborts the DMA Transfer.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- *
- * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
- * effectively disabled is added. If a Channel is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Channel will be effectively disabled only after the transfer of
- * this single data is finished.
+ * @brief Abort the DMA Transfer.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- uint32_t tickstart = 0x00;
-
- /* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the DMA Channel is effectively disabled */
- while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
- {
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_TIMEOUT;
- }
- }
- /* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
+ /* Disable DMA IT */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
+ /* Disable the channel */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
+
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
}
/**
- * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @brief Abort the DMA Transfer in Interrupt mode.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
@@ -435,14 +438,15 @@
}
else
{
+
/* Disable DMA IT */
- __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
/* Disable the channel */
- __HAL_DMA_DISABLE(hdma);
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
@@ -470,35 +474,52 @@
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
- uint32_t tickstart = 0x00;
+ uint32_t tickstart = 0U;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode */
+ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
/* Get the level transfer complete flag */
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Transfer Complete flag */
- temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
}
else
{
/* Half Transfer Complete flag */
- temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+ temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
/* Get tick */
tickstart = HAL_GetTick();
- while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+ while(RESET == (hdma->DmaBaseAddress->ISR & temp))
{
- if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+ if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
{
- /* Clear the transfer error flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
- hdma->State= HAL_DMA_STATE_ERROR;
+ hdma->State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
@@ -508,40 +529,35 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
+ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
+ hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
- if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+ if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
-
}
else
{
/* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers of half buffer are complete) */
- hdma->State = HAL_DMA_STATE_READY_HALF;
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
}
/* Process unlocked */
@@ -551,98 +567,205 @@
}
/**
- * @brief Handles DMA interrupt request.
+ * @brief Handle DMA interrupt request.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- /* Transfer Error Interrupt management ***************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+{
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t source_it = hdma->Instance->CCR;
+
+ /* Half Transfer Complete Interrupt management ******************************/
+ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
{
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
- {
- /* Disable the transfer error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
- /* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-
- /* Half Transfer Complete Interrupt management ******************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
- {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF;
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the half transfer interrupt */
+ hdma->Instance->CCR &= ~DMA_IT_HT;
+ }
+
+ /* Clear the half transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* State is updated only in Transfer Complete case */
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
}
/* Transfer Complete Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
{
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
- {
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
- {
- /* Disable the transfer complete interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
- }
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete & transfer error interrupts */
+ /* if the DMA mode is not CIRCULAR */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+ }
+
+ /* Clear the transfer complete flag */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Error Interrupt management ***************************************/
+ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Then, disable all DMA interrupts */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_READY;
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
}
}
}
/**
+ * @brief Register callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback: pointer to private callback function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
* @}
*/
@@ -675,8 +798,8 @@
/**
* @brief Return the DMA error code
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
* @retval DMA Error Code
*/
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
@@ -692,12 +815,12 @@
* @}
*/
-/** @addtogroup DMA_Private_Functions DMA Private Functions
+/** @addtogroup DMA_Private_Functions
* @{
*/
/**
- * @brief Sets the DMA Transfer parameter.
+ * @brief Set the DMA Transfer parameters.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
@@ -706,7 +829,10 @@
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
+{
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
+
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
@@ -731,10 +857,35 @@
}
/**
- * @}
+ * @brief Set the DMA base address and channel index depending on DMA instance
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Stream.
+ * @retval None
*/
+static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+#if defined (DMA2)
+ /* calculation of the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA1;
+ }
+ else
+ {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA2;
+ }
+#else
+ /* calculation of the channel index */
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
+ hdma->DmaBaseAddress = DMA1;
+#endif
+}
-#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
@@ -742,5 +893,14 @@
/**
* @}
*/
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_dma.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -84,33 +84,21 @@
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
+ data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
-/**
- * @brief DMA Configuration enumeration values definition
- */
-typedef enum
-{
- DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
- DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
-
-} DMA_ControlTypeDef;
-
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
- HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
@@ -118,10 +106,22 @@
*/
typedef enum
{
- HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
+}HAL_DMA_CallbackIDTypeDef;
+
/**
* @brief DMA handle Structure definition
*/
@@ -143,9 +143,13 @@
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
@@ -160,10 +164,11 @@
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
-#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoin transfer */
-#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
+#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
+#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
/**
* @}
*/
@@ -171,19 +176,19 @@
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
-
+
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
/**
* @}
*/
@@ -192,7 +197,7 @@
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
/**
* @}
*/
@@ -200,7 +205,7 @@
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
+#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
@@ -210,7 +215,7 @@
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
+#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
/**
@@ -220,8 +225,8 @@
/** @defgroup DMA_mode DMA mode
* @{
*/
-#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
+#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
+#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
/**
* @}
*/
@@ -229,7 +234,7 @@
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
+#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
@@ -251,34 +256,34 @@
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
-#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+#define DMA_FLAG_GL1 (0x00000001U)
+#define DMA_FLAG_TC1 (0x00000002U)
+#define DMA_FLAG_HT1 (0x00000004U)
+#define DMA_FLAG_TE1 (0x00000008U)
+#define DMA_FLAG_GL2 (0x00000010U)
+#define DMA_FLAG_TC2 (0x00000020U)
+#define DMA_FLAG_HT2 (0x00000040U)
+#define DMA_FLAG_TE2 (0x00000080U)
+#define DMA_FLAG_GL3 (0x00000100U)
+#define DMA_FLAG_TC3 (0x00000200U)
+#define DMA_FLAG_HT3 (0x00000400U)
+#define DMA_FLAG_TE3 (0x00000800U)
+#define DMA_FLAG_GL4 (0x00001000U)
+#define DMA_FLAG_TC4 (0x00002000U)
+#define DMA_FLAG_HT4 (0x00004000U)
+#define DMA_FLAG_TE4 (0x00008000U)
+#define DMA_FLAG_GL5 (0x00010000U)
+#define DMA_FLAG_TC5 (0x00020000U)
+#define DMA_FLAG_HT5 (0x00040000U)
+#define DMA_FLAG_TE5 (0x00080000U)
+#define DMA_FLAG_GL6 (0x00100000U)
+#define DMA_FLAG_TC6 (0x00200000U)
+#define DMA_FLAG_HT6 (0x00400000U)
+#define DMA_FLAG_TE6 (0x00800000U)
+#define DMA_FLAG_GL7 (0x01000000U)
+#define DMA_FLAG_TC7 (0x02000000U)
+#define DMA_FLAG_HT7 (0x04000000U)
+#define DMA_FLAG_TE7 (0x08000000U)
/**
* @}
*/
@@ -302,16 +307,16 @@
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
+#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
@@ -326,7 +331,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA Channel interrupts.
@@ -338,7 +343,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
@@ -350,7 +355,7 @@
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
@@ -368,7 +373,7 @@
#include "stm32f3xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+/** @addtogroup DMA_Exported_Functions
* @{
*/
@@ -385,13 +390,15 @@
/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
-/* IO operation functions *****************************************************/
+/* Input and Output operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
@@ -415,7 +422,7 @@
* @{
*/
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_flash.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -176,18 +176,18 @@
* @note FLASH should be previously erased before new programmation (only exception to this
* is when 0x0000 is programmed)
*
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
+ * @param Address Specifie the address to be programmed.
+ * @param Data Specifie the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
- uint8_t index = 0;
- uint8_t nbiterations = 0;
+ uint8_t index = 0U;
+ uint8_t nbiterations = 0U;
/* Process Locked */
__HAL_LOCK(&pFlash);
@@ -204,22 +204,22 @@
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/* Program halfword (16-bit) at a specified address. */
- nbiterations = 1;
+ nbiterations = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
- nbiterations = 2;
+ nbiterations = 2U;
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
- nbiterations = 4;
+ nbiterations = 4U;
}
- for (index = 0; index < nbiterations; index++)
+ for (index = 0U; index < nbiterations; index++)
{
- FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+ FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@@ -248,10 +248,10 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: Specifies the address to be programmed.
- * @param Data: Specifies the data to be programmed
+ * @param Address Specifie the address to be programmed.
+ * @param Data Specifie the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
@@ -276,19 +276,19 @@
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
/* Program halfword (16-bit) at a specified address. */
- pFlash.DataRemaining = 1;
+ pFlash.DataRemaining = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
/* Program word (32-bit : 2*16-bit) at a specified address. */
- pFlash.DataRemaining = 2;
+ pFlash.DataRemaining = 2U;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
/* Program double word (64-bit : 4*16-bit) at a specified address. */
- pFlash.DataRemaining = 4;
+ pFlash.DataRemaining = 4U;
}
/* Program halfword (16-bit) at a specified address. */
@@ -303,7 +303,7 @@
*/
void HAL_FLASH_IRQHandler(void)
{
- uint32_t addresstmp = 0;
+ uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
@@ -338,7 +338,7 @@
pFlash.DataRemaining--;
/* Check if there are still pages to erase */
- if(pFlash.DataRemaining != 0)
+ if(pFlash.DataRemaining != 0U)
{
addresstmp = pFlash.Address;
/*Indicate user which sector has been erased */
@@ -370,7 +370,7 @@
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0);
+ HAL_FLASH_EndOfOperationCallback(0U);
/* Stop Mass Erase procedure*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
@@ -381,14 +381,14 @@
pFlash.DataRemaining--;
/* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0)
+ if(pFlash.DataRemaining != 0U)
{
/* Increment address to 16-bit */
- pFlash.Address += 2;
+ pFlash.Address += 2U;
addresstmp = pFlash.Address;
/* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16);
+ pFlash.Data = (pFlash.Data >> 16U);
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
@@ -406,11 +406,11 @@
}
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
}
else
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
}
/* Reset Address and stop Program procedure */
@@ -644,7 +644,7 @@
{
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
@@ -677,7 +677,7 @@
*/
static void FLASH_SetErrorCode(void)
{
- uint32_t flags = 0;
+ uint32_t flags = 0U;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_flash.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@@ -57,7 +57,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
+#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
/**
* @}
*/
@@ -88,12 +88,12 @@
*/
typedef enum
{
- FLASH_PROC_NONE = 0,
- FLASH_PROC_PAGEERASE = 1,
- FLASH_PROC_MASSERASE = 2,
- FLASH_PROC_PROGRAMHALFWORD = 3,
- FLASH_PROC_PROGRAMWORD = 4,
- FLASH_PROC_PROGRAMDOUBLEWORD = 5
+ FLASH_PROC_NONE = 0U,
+ FLASH_PROC_PAGEERASE = 1U,
+ FLASH_PROC_MASSERASE = 2U,
+ FLASH_PROC_PROGRAMHALFWORD = 3U,
+ FLASH_PROC_PROGRAMWORD = 4U,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef;
/**
@@ -139,9 +139,9 @@
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
-#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!<Program a double word (64-bit) at a specified address*/
+#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
/**
* @}
@@ -150,7 +150,7 @@
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
-#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -177,7 +177,7 @@
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t address = 0;
+ uint32_t address = 0U;
/* Process Locked */
__HAL_LOCK(&pFlash);
@@ -482,7 +482,7 @@
*/
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
{
- uint32_t value = 0;
+ uint32_t value = 0U;
if (DATAAdress == OB_DATA_ADDRESS_DATA0)
{
@@ -539,15 +539,15 @@
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
+ uint16_t WRP0_Data = 0xFFFFU;
#if defined(OB_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
+ uint16_t WRP1_Data = 0xFFFFU;
#endif /* OB_WRP1_WRP1 */
#if defined(OB_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
+ uint16_t WRP2_Data = 0xFFFFU;
#endif /* OB_WRP2_WRP2 */
#if defined(OB_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
+ uint16_t WRP3_Data = 0xFFFFU;
#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
@@ -561,17 +561,17 @@
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#endif /* OB_WRP_PAGES48TO63MASK */
/* Wait for last operation to be completed */
@@ -590,7 +590,7 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(OB_WRP0_WRP0)
- if(WRP0_Data != 0xFF)
+ if(WRP0_Data != 0xFFU)
{
OB->WRP0 &= WRP0_Data;
@@ -600,7 +600,7 @@
#endif /* OB_WRP0_WRP0 */
#if defined(OB_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 &= WRP1_Data;
@@ -610,7 +610,7 @@
#endif /* OB_WRP1_WRP1 */
#if defined(OB_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 &= WRP2_Data;
@@ -620,7 +620,7 @@
#endif /* OB_WRP2_WRP2 */
#if defined(OB_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 &= WRP3_Data;
@@ -651,15 +651,15 @@
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
{
HAL_StatusTypeDef status = HAL_OK;
- uint16_t WRP0_Data = 0xFFFF;
+ uint16_t WRP0_Data = 0xFFFFU;
#if defined(OB_WRP1_WRP1)
- uint16_t WRP1_Data = 0xFFFF;
+ uint16_t WRP1_Data = 0xFFFFU;
#endif /* OB_WRP1_WRP1 */
#if defined(OB_WRP2_WRP2)
- uint16_t WRP2_Data = 0xFFFF;
+ uint16_t WRP2_Data = 0xFFFFU;
#endif /* OB_WRP2_WRP2 */
#if defined(OB_WRP3_WRP3)
- uint16_t WRP3_Data = 0xFFFF;
+ uint16_t WRP3_Data = 0xFFFFU;
#endif /* OB_WRP3_WRP3 */
/* Check the parameters */
@@ -673,17 +673,17 @@
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#endif /* OB_WRP_PAGES48TO63MASK */
@@ -702,7 +702,7 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(OB_WRP0_WRP0)
- if(WRP0_Data != 0xFF)
+ if(WRP0_Data != 0xFFU)
{
OB->WRP0 |= WRP0_Data;
@@ -712,7 +712,7 @@
#endif /* OB_WRP0_WRP0 */
#if defined(OB_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 |= WRP1_Data;
@@ -722,7 +722,7 @@
#endif /* OB_WRP1_WRP1 */
#if defined(OB_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 |= WRP2_Data;
@@ -732,7 +732,7 @@
#endif /* OB_WRP2_WRP2 */
#if defined(OB_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 |= WRP3_Data;
@@ -836,9 +836,9 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
- OB->USER = (UserConfig | 0x08);
+ OB->USER = (UserConfig | 0x08U);
#else
- OB->USER = (UserConfig | 0x88);
+ OB->USER = (UserConfig | 0x88U);
#endif
/* Wait for last operation to be completed */
@@ -913,7 +913,7 @@
static uint32_t FLASH_OB_GetRDP(void)
{
uint32_t readstatus = OB_RDP_LEVEL_0;
- uint32_t tmp_reg = 0;
+ uint32_t tmp_reg = 0U;
/* Read RDP level bits */
#if defined(FLASH_OBR_RDPRT)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
@@ -58,7 +58,7 @@
* @{
*/
-#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7CC)
+#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
/**
* @}
@@ -99,45 +99,45 @@
((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
- ((ADDRESS) <= 0x0803FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
- ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
+ ((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+ ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFF))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
- ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
- ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
+ ((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+ ((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU))))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF)
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
@@ -199,7 +199,7 @@
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
} FLASH_OBProgramInitTypeDef;
/**
* @}
@@ -221,8 +221,8 @@
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
-#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!<Flash mass erase activation*/
+#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
/**
* @}
@@ -235,10 +235,10 @@
/** @defgroup FLASHEx_OB_Type Option Bytes Type
* @{
*/
-#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
-#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
+#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
/**
* @}
@@ -247,8 +247,8 @@
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
* @{
*/
-#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
-#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
/**
* @}
@@ -257,96 +257,96 @@
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
* @{
*/
-#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
-#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
-#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
-#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
-#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
-#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
-#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
-#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
-#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
-#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
-#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
-#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
-#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
-#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
-#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
-#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
+#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
+#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
+#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
+#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
+#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
+#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
+#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
+#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
+#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
+#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
+#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
+#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
+#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
+#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
+#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000U) /* Write protection of page 62 to 127 */
+#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
+#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
+#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
+#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
+#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
+#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
+#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
+#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
+#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
+#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
+#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
+#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
+#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
+#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
+#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
+#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000U) /* Write protection of page 62 to 255 */
+#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
+#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
+#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
+#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
+#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
+#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
+#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
+#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
+#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
+#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
+#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
+#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
+#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
+#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
+#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
+#define OB_WRP_PAGES62TO255 (0x80000000U) /* Write protection of page 62 to 255 */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FFU)
-#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00U)
+#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
+#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
-#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000U)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
-#define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000U)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO255MASK (0xFF000000U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000U)
-#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000U)
+#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
+#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
-#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< Write protection of all pages */
+#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define OB_WRP_ALLPAGES ((uint32_t)0x0000FFFF) /*!< Write protection of all pages */
+#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
@@ -357,10 +357,10 @@
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
* @{
*/
-#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
-#define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
-#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
+#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
+#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
+#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0U */
/**
* @}
*/
@@ -368,8 +368,8 @@
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
* @{
*/
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
/**
* @}
*/
@@ -377,8 +377,8 @@
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
* @{
*/
-#define OB_STOP_NO_RST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
@@ -386,8 +386,8 @@
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
* @{
*/
-#define OB_STDBY_NO_RST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
@@ -395,8 +395,8 @@
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
* @{
*/
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
/**
* @}
*/
@@ -404,8 +404,8 @@
/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
* @{
*/
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
/**
* @}
*/
@@ -413,8 +413,8 @@
/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
* @{
*/
-#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity check enable set */
-#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity check enable reset */
+#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
+#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
/**
* @}
*/
@@ -424,8 +424,8 @@
/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
* @{
*/
-#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00) /*!< SDADC VDD Monitor reset */
-#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80) /*!< SDADC VDD Monitor set */
+#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U) /*!< SDADC VDD Monitor reset */
+#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U) /*!< SDADC VDD Monitor set */
/**
* @}
@@ -435,8 +435,8 @@
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
* @{
*/
-#define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
-#define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
+#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
+#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -82,7 +82,7 @@
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
- (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+ (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
@@ -139,15 +139,15 @@
/** @defgroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
-#define GPIO_MODE ((uint32_t)0x00000003)
-#define EXTI_MODE ((uint32_t)0x10000000)
-#define GPIO_MODE_IT ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT ((uint32_t)0x00020000)
-#define RISING_EDGE ((uint32_t)0x00100000)
-#define FALLING_EDGE ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
+#define GPIO_MODE (0x00000003U)
+#define EXTI_MODE (0x10000000U)
+#define GPIO_MODE_IT (0x00010000U)
+#define GPIO_MODE_EVT (0x00020000U)
+#define RISING_EDGE (0x00100000U)
+#define FALLING_EDGE (0x00200000U)
+#define GPIO_OUTPUT_TYPE (0x00000010U)
-#define GPIO_NUMBER ((uint32_t)16)
+#define GPIO_NUMBER (16U)
/**
* @}
*/
@@ -189,9 +189,9 @@
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- uint32_t position = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t temp = 0x00;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t temp = 0x00U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -217,15 +217,15 @@
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
- temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
- temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+ temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- temp &= ~(GPIO_MODER_MODER0 << (position * 2));
- temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
@@ -236,21 +236,21 @@
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
- temp |= (GPIO_Init->Speed << (position * 2));
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+ temp |= (GPIO_Init->Speed << (position * 2U));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
- temp |= ((GPIO_Init->Pull) << (position * 2));
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
@@ -261,8 +261,8 @@
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
- temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
- temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+ temp &= ~((0x0FU) << (4U * (position & 0x03U)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
@@ -314,9 +314,9 @@
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
- uint32_t position = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t tmp = 0x00;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -332,29 +332,29 @@
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
/* Configure the default Alternate Function in current IO */
- GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+ GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
/* Configure the default value for IO Speed */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2];
- tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
- if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ tmp &= ((0x0FU) << (4U * (position & 0x03U)));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+ tmp = (0x0FU) << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
/* Clear EXTI line configuration */
@@ -464,7 +464,7 @@
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32L4 family
+ * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
* @param GPIO_Pin: specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
@@ -479,11 +479,11 @@
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
GPIOx->LCKR = tmp;
- /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+ /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */
GPIOx->LCKR = GPIO_Pin;
- /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+ /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@@ -85,7 +85,7 @@
*/
typedef enum
{
- GPIO_PIN_RESET = 0,
+ GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
/**
@@ -99,25 +99,25 @@
/** @defgroup GPIO_pins GPIO pins
* @{
*/
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
+#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
+#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
+#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
+#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
+#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
+#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
+#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
+#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
+#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
+#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
+#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
+#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
+#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
+#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
+#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
+#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
+#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
-#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
@@ -132,18 +132,18 @@
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
-#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
-#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
-#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
+#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -152,9 +152,9 @@
* @brief GPIO Output Maximum frequency
* @{
*/
-#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 2 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
-#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000003) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
+#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
/**
* @}
*/
@@ -163,9 +163,9 @@
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
-#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
-#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
+#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
+#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
@@ -229,8 +229,8 @@
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
- (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
@@ -70,116 +70,116 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
-#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F302xC */
@@ -188,129 +188,129 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
-#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F303xC */
@@ -319,141 +319,141 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
/**
* @brief AF 14 selection
*/
-#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F303xE */
@@ -462,125 +462,125 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
/**
* @brief AF 14 selection
*/
-#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F302xE */
@@ -589,136 +589,136 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
-#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#define GPIO_AF12_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
+#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F398xx */
@@ -727,124 +727,124 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
-#define GPIO_AF3_COMP7 ((uint8_t)0x03) /* COMP7 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_I2S ((uint8_t)0x05) /* I2S Alternate Function mapping */
-#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext Alternate Function mapping */
-#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
-#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
-#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */
+#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */
+#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
+#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */
+#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext Alternate Function mapping */
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_COMP3 ((uint8_t)0x07) /* COMP3 Alternate Function mapping */
-#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
-#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
-#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
-#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
-#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
-#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */
+#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */
+#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */
+#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM8 ((uint8_t)0xA) /* TIM8 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
-#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0xC) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F358xx */
@@ -853,102 +853,102 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
-#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
-#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
-#define GPIO_AF14_USB ((uint8_t)0x0E) /* USB Alternate Function mapping */
+#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0E) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F373xC */
@@ -958,100 +958,100 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM13 ((uint8_t)0x02) /* TIM13 Alternate Function mapping */
-#define GPIO_AF2_TIM14 ((uint8_t)0x02) /* TIM14 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM19 ((uint8_t)0x02) /* TIM19 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
+#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_CEC ((uint8_t)0x06) /* CEC Alternate Function mapping */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
-#define GPIO_AF7_CEC ((uint8_t)0x07) /* CEC Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
+#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
-#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
+#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */
+#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM4 ((uint8_t)0xA) /* TIM4 Alternate Function mapping */
-#define GPIO_AF10_TIM12 ((uint8_t)0xA) /* TIM12 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */
+#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM19 ((uint8_t)0x0B) /* TIM19 Alternate Function mapping */
+#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0B) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F378xx */
@@ -1060,98 +1060,98 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
-#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F303x8 */
@@ -1160,101 +1160,101 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
+#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_HRTIM1 ((uint8_t)0x03U) /* HRTIM1 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM3 ((uint8_t)0xA) /* TIM3 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
-#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_HRTIM1 ((uint8_t)0x0CU) /* HRTIM1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
-#define GPIO_AF13_OPAMP2 ((uint8_t)0x0D) /* OPAMP2 Alternate Function mapping */
-#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
+#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */
+#define GPIO_AF13_HRTIM1 ((uint8_t)0x0DU) /* HRTIM1 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0D) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F334x8 || STM32F328xx */
@@ -1263,103 +1263,103 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F301x8 || STM32F318xx */
@@ -1368,105 +1368,105 @@
/**
* @brief AF 0 selection
*/
-#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC Alternate Function mapping */
-#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */
+#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
-#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
-#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
-#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */
/**
* @brief AF 2 selection
*/
-#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
-#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
-#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
-#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
-#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */
-#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
-#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
+#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */
+#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
-#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
-#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
-#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
+#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */
+#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
-#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
-#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
+#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
+#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */
/**
* @brief AF 6 selection
*/
-#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
-#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
+#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */
+#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
-#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
-#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
-#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
-#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07) /* GPCOMP6 Alternate Function mapping */
-#define GPIO_AF7_CAN ((uint8_t)0x07) /* CAN Alternate Function mapping */
+#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
+#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
+#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
+#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */
/**
* @brief AF 8 selection
*/
-#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08) /* GPCOMP2 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08) /* GPCOMP4 Alternate Function mapping */
-#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08) /* GPCOMP6 Alternate Function mapping */
+#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */
+#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
-#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
-#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
-#define GPIO_AF9_CAN ((uint8_t)0x09) /* CAN Alternate Function mapping */
+#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */
+#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */
+#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */
/**
* @brief AF 10 selection
*/
-#define GPIO_AF10_TIM2 ((uint8_t)0xA) /* TIM2 Alternate Function mapping */
-#define GPIO_AF10_TIM17 ((uint8_t)0xA) /* TIM17 Alternate Function mapping */
+#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */
+#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */
/**
* @brief AF 11 selection
*/
-#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
+#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
-#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
+#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
-#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
+#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0C) || ((AF) == (uint8_t)0x0F))
+#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU))
/*------------------------------------------------------------------------------------------*/
#endif /* STM32F302x8 */
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_hrtim.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Resolution Timer (HRTIM) peripheral:
@@ -565,8 +565,8 @@
hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
- hhrtim->TimerParam[timer_idx].DMASrcAddress = 0;
- hhrtim->TimerParam[timer_idx].DMASize = 0;
+ hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
+ hhrtim->TimerParam[timer_idx].DMASize = 0U;
}
return HAL_OK;
@@ -746,7 +746,7 @@
HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
uint32_t Timeout)
{
- uint32_t tickstart=0;
+ uint32_t tickstart=0U;
tickstart = HAL_GetTick();
@@ -755,7 +755,7 @@
{
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hhrtim->State = HAL_HRTIM_STATE_ERROR;
return HAL_TIMEOUT;
@@ -1046,7 +1046,7 @@
}
if((hhrtim->State == HAL_HRTIM_STATE_READY))
{
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1264,7 +1264,7 @@
CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
+ CompareCfg.AutoDelayedTimeout = 0U;
HRTIM_CompareUnitConfig(hhrtim,
TimerIdx,
@@ -1609,7 +1609,7 @@
}
if((hhrtim->State == HAL_HRTIM_STATE_READY))
{
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1832,7 +1832,7 @@
CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
+ CompareCfg.AutoDelayedTimeout = 0U;
HRTIM_CompareUnitConfig(hhrtim,
TimerIdx,
@@ -2174,7 +2174,7 @@
}
if((hhrtim->State == HAL_HRTIM_STATE_READY))
{
- if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
+ if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2956,7 +2956,7 @@
CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
- CompareCfg.AutoDelayedTimeout = 0;
+ CompareCfg.AutoDelayedTimeout = 0U;
HRTIM_CompareUnitConfig(hhrtim,
TimerIdx,
@@ -3508,28 +3508,28 @@
case HRTIM_FAULT_2:
{
hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 8);
- hrtim_fltinr1 |= (pFaultCfg->Source << 8);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 8);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 8);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 8U);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 8U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 8U);
}
break;
case HRTIM_FAULT_3:
{
hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 16);
- hrtim_fltinr1 |= (pFaultCfg->Source << 16);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 16);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 16);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 16U);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 16U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 16U);
}
break;
case HRTIM_FAULT_4:
{
hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
- hrtim_fltinr1 |= (pFaultCfg->Polarity << 24);
- hrtim_fltinr1 |= (pFaultCfg->Source << 24);
- hrtim_fltinr1 |= (pFaultCfg->Filter << 24);
- hrtim_fltinr1 |= (pFaultCfg->Lock << 24);
+ hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U);
+ hrtim_fltinr1 |= (pFaultCfg->Source << 24U);
+ hrtim_fltinr1 |= (pFaultCfg->Filter << 24U);
+ hrtim_fltinr1 |= (pFaultCfg->Lock << 24U);
}
break;
case HRTIM_FAULT_5:
@@ -3643,17 +3643,17 @@
if ((Faults & HRTIM_FAULT_2) != RESET)
{
hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
- hrtim_fltinr1 |= (Enable << 8);
+ hrtim_fltinr1 |= (Enable << 8U);
}
if ((Faults & HRTIM_FAULT_3) != RESET)
{
hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
- hrtim_fltinr1 |= (Enable << 16);
+ hrtim_fltinr1 |= (Enable << 16U);
}
if ((Faults & HRTIM_FAULT_4) != RESET)
{
hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
- hrtim_fltinr1 |= (Enable << 24);
+ hrtim_fltinr1 |= (Enable << 24U);
}
if ((Faults & HRTIM_FAULT_5) != RESET)
{
@@ -3717,7 +3717,7 @@
case HRTIM_ADCTRIGGER_2:
{
hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
/* Set the ADC trigger 2 source */
hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
@@ -3726,7 +3726,7 @@
case HRTIM_ADCTRIGGER_3:
{
hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
/* Set the ADC trigger 3 source */
hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
@@ -3735,7 +3735,7 @@
case HRTIM_ADCTRIGGER_4:
{
hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
- hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC);
+ hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
/* Set the ADC trigger 4 source */
hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
@@ -3945,8 +3945,8 @@
{
case HRTIM_EVENT_NONE:
{
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0;
- hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U;
+ hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U;
}
break;
case HRTIM_EVENT_1:
@@ -3961,7 +3961,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
}
break;
@@ -3969,7 +3969,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
}
break;
@@ -3977,7 +3977,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
}
break;
@@ -3985,7 +3985,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
}
break;
@@ -4001,7 +4001,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
}
break;
@@ -4009,7 +4009,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
}
break;
@@ -4017,7 +4017,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
}
break;
@@ -4025,7 +4025,7 @@
{
hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
- hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
}
break;
@@ -4094,7 +4094,7 @@
hrtim_dtr |= pDeadTimeCfg->RisingSign;
hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
hrtim_dtr |= pDeadTimeCfg->RisingLock;
- hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16);
+ hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U);
hrtim_dtr |= pDeadTimeCfg->FallingSign;
hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
hrtim_dtr |= pDeadTimeCfg->FallingLock;
@@ -4398,7 +4398,7 @@
/* DELCMP4 bitfield must be reset when reprogrammed from one value */
/* to the other to reinitialize properly the auto-delayed mechanism */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
- hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2);
+ hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
/* Set the compare value for timeout compare unit (if any) */
if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
@@ -4772,12 +4772,12 @@
* @param hhrtim: pointer to HAL HRTIM handle
* @param Timers: Timer counter(s) to stop
* This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
* @retval HAL status
* @note The counter of a timer is stopped only if all timer outputs are disabled
*/
@@ -4873,12 +4873,12 @@
* @param hhrtim: pointer to HAL HRTIM handle
* @param Timers: Timer counter(s) to stop
* This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
* @retval HAL status
* @note The counter of a timer is stopped only if all timer outputs are disabled
* @note All enabled timer related interrupts are disabled.
@@ -4887,7 +4887,7 @@
uint32_t Timers)
{
/* ++ WA */
- __IO uint32_t delai = (uint32_t)(0x17F);
+ __IO uint32_t delai = (uint32_t)(0x17FU);
/* -- WA */
uint8_t timer_idx;
@@ -4922,7 +4922,7 @@
}
/* ++ WA */
- do { delai--; } while (delai != 0);
+ do { delai--; } while (delai != 0U);
/* -- WA */
/* Disable timer(s) counter */
@@ -4942,12 +4942,12 @@
* @param hhrtim: pointer to HAL HRTIM handle
* @param Timers: Timer counter(s) to start
* This parameter can be any combination of the following values:
- * HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
+ * HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
* @retval HAL status
* @note This function enables the dma request(s) mentionned in the timer
* configuration data structure for every timers to start.
@@ -4975,7 +4975,7 @@
__HAL_LOCK(hhrtim);
if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
{
/* Set the DMA error callback */
hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
@@ -4999,7 +4999,7 @@
timer_idx++)
{
if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0))
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
{
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
@@ -5040,12 +5040,12 @@
* @param hhrtim: pointer to HAL HRTIM handle
* @param Timers: Timer counter(s) to stop
* This parameter can be any combination of the following values:
- * @arg HRTIM_TIMER_MASTER
- * @arg HRTIM_TIMER_A
- * @arg HRTIM_TIMER_B
- * @arg HRTIM_TIMER_C
- * @arg HRTIM_TIMER_D
- * @arg HRTIM_TIMER_E
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_A
+ * @arg HRTIM_TIMERID_B
+ * @arg HRTIM_TIMERID_C
+ * @arg HRTIM_TIMERID_D
+ * @arg HRTIM_TIMERID_E
* @retval HAL status
* @note The counter of a timer is stopped only if all timer outputs are disabled
* @note All enabled timer related DMA requests are disabled.
@@ -5062,7 +5062,7 @@
hhrtim->State = HAL_HRTIM_STATE_BUSY;
if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
- (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
+ (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
{
/* Disable the DMA */
HAL_DMA_Abort(hhrtim->hdmaMaster);
@@ -5077,7 +5077,7 @@
timer_idx++)
{
if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
- (hhrtim->TimerParam[timer_idx].DMARequests != 0))
+ (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
{
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
@@ -5357,7 +5357,7 @@
}
if((hhrtim->State == HAL_HRTIM_STATE_READY))
{
- if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0))
+ if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
{
return HAL_ERROR;
}
@@ -5521,7 +5521,7 @@
uint32_t TimerIdx,
uint32_t CaptureUnit)
{
- uint32_t captured_value = 0;
+ uint32_t captured_value = 0U;
/* Check parameters */
assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
@@ -5652,7 +5652,7 @@
uint32_t TimerIdx,
uint32_t Output)
{
- uint32_t output_bit = 0;
+ uint32_t output_bit = 0U;
uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
/* Check parameters */
@@ -6608,7 +6608,7 @@
/* Master timer registers update handling */
hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
- hrtim_mcr |= (pTimerCfg->UpdateGating << 2);
+ hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
/* Enable/Disable registers update on repetition */
hrtim_mcr &= ~(HRTIM_MCR_MREPU);
@@ -6731,31 +6731,31 @@
case HRTIM_TIMERINDEX_TIMER_A:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 1);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
}
break;
case HRTIM_TIMERINDEX_TIMER_B:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 2);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
}
break;
case HRTIM_TIMERINDEX_TIMER_C:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 3);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
}
break;
case HRTIM_TIMERINDEX_TIMER_D:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 4);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
}
break;
case HRTIM_TIMERINDEX_TIMER_E:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
- hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
+ hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
}
break;
default:
@@ -6964,7 +6964,7 @@
hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
- shift = 0;
+ shift = 0U;
}
break;
case HRTIM_OUTPUT_TA2:
@@ -6977,7 +6977,7 @@
hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
- shift = 16;
+ shift = 16U;
}
break;
default:
@@ -7010,8 +7010,8 @@
/* Set the burst mode entry mode : deadtime insertion when entering the idle
state during a burst mode operation is allowed only under the following
conditions:
- - the outputs is active during the burst mode (IDLES=1)
- - positive deadtimes (SDTR/SDTF set to 0)
+ - the outputs is active during the burst mode (IDLES=1U)
+ - positive deadtimes (SDTR/SDTF set to 0U)
*/
if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
@@ -7062,52 +7062,52 @@
case HRTIM_EVENT_2:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 6);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
+ hrtim_eecr1 |= (pEventCfg->Source << 6U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U);
/* Update the HRTIM registers (all bitfields but EE2FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
/* Update the HRTIM registers (EE2FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 6);
+ hrtim_eecr1 |= (pEventCfg->FastMode << 6U);
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
}
break;
case HRTIM_EVENT_3:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 12);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
+ hrtim_eecr1 |= (pEventCfg->Source << 12U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U);
/* Update the HRTIM registers (all bitfields but EE3FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
/* Update the HRTIM registers (EE3FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 12);
+ hrtim_eecr1 |= (pEventCfg->FastMode << 12U);
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
}
break;
case HRTIM_EVENT_4:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 18);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
+ hrtim_eecr1 |= (pEventCfg->Source << 18U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U);
/* Update the HRTIM registers (all bitfields but EE4FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
/* Update the HRTIM registers (EE4FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 18);
+ hrtim_eecr1 |= (pEventCfg->FastMode << 18U);
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
}
break;
case HRTIM_EVENT_5:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
- hrtim_eecr1 |= (pEventCfg->Source << 24);
- hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL));
- hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
+ hrtim_eecr1 |= (pEventCfg->Source << 24U);
+ hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL));
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U);
/* Update the HRTIM registers (all bitfields but EE5FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
/* Update the HRTIM registers (EE5FAST bit) */
- hrtim_eecr1 |= (pEventCfg->FastMode << 24);
+ hrtim_eecr1 |= (pEventCfg->FastMode << 24U);
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
}
break;
@@ -7127,11 +7127,11 @@
case HRTIM_EVENT_7:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 6);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
+ hrtim_eecr2 |= (pEventCfg->Source << 6U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U);
hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
- hrtim_eecr3 |= (pEventCfg->Filter << 6);
+ hrtim_eecr3 |= (pEventCfg->Filter << 6U);
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
@@ -7140,11 +7140,11 @@
case HRTIM_EVENT_8:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 12);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
+ hrtim_eecr2 |= (pEventCfg->Source << 12U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U);
hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
- hrtim_eecr3 |= (pEventCfg->Filter << 12);
+ hrtim_eecr3 |= (pEventCfg->Filter << 12U);
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
@@ -7153,11 +7153,11 @@
case HRTIM_EVENT_9:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 18);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
+ hrtim_eecr2 |= (pEventCfg->Source << 18U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U);
hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
- hrtim_eecr3 |= (pEventCfg->Filter << 18);
+ hrtim_eecr3 |= (pEventCfg->Filter << 18U);
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
@@ -7166,11 +7166,11 @@
case HRTIM_EVENT_10:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
- hrtim_eecr2 |= (pEventCfg->Source << 24);
- hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL));
- hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
+ hrtim_eecr2 |= (pEventCfg->Source << 24U);
+ hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL));
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U);
hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
- hrtim_eecr3 |= (pEventCfg->Filter << 24);
+ hrtim_eecr3 |= (pEventCfg->Filter << 24U);
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
@@ -7274,7 +7274,7 @@
{
uint32_t hrtim_set;
uint32_t hrtim_reset;
- uint32_t interrupt = 0;
+ uint32_t interrupt = 0U;
switch (OCChannel)
{
@@ -7295,12 +7295,12 @@
interrupt = HRTIM_TIM_IT_CMP1;
}
else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0))
+ (hrtim_reset == 0U))
{
/* OC mode: HRTIM_BASICOCMODE_ACTIVE */
interrupt = HRTIM_TIM_IT_SET1;
}
- else if ((hrtim_set == 0) &&
+ else if ((hrtim_set == 0U) &&
((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
{
/* OC mode: HRTIM_BASICOCMODE_INACTIVE */
@@ -7325,12 +7325,12 @@
interrupt = HRTIM_TIM_IT_CMP2;
}
else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0))
+ (hrtim_reset == 0U))
{
/* OC mode: HRTIM_BASICOCMODE_ACTIVE */
interrupt = HRTIM_TIM_IT_SET2;
}
- else if ((hrtim_set == 0) &&
+ else if ((hrtim_set == 0U) &&
((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
{
/* OC mode: HRTIM_BASICOCMODE_INACTIVE */
@@ -7370,7 +7370,7 @@
{
uint32_t hrtim_set;
uint32_t hrtim_reset;
- uint32_t dma_request = 0;
+ uint32_t dma_request = 0U;
switch (OCChannel)
{
@@ -7391,12 +7391,12 @@
dma_request = HRTIM_TIM_DMA_CMP1;
}
else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
- (hrtim_reset == 0))
+ (hrtim_reset == 0U))
{
/* OC mode: HRTIM_BASICOCMODE_ACTIVE */
dma_request = HRTIM_TIM_DMA_SET1;
}
- else if ((hrtim_set == 0) &&
+ else if ((hrtim_set == 0U) &&
((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
{
/* OC mode: HRTIM_BASICOCMODE_INACTIVE */
@@ -7421,12 +7421,12 @@
dma_request = HRTIM_TIM_DMA_CMP2;
}
else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
- (hrtim_reset == 0))
+ (hrtim_reset == 0U))
{
/* OC mode: HRTIM_BASICOCMODE_ACTIVE */
dma_request = HRTIM_TIM_DMA_SET2;
}
- else if ((hrtim_set == 0) &&
+ else if ((hrtim_set == 0U) &&
((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
{
/* OC mode: HRTIM_BASICOCMODE_INACTIVE */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_hrtim.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of HRTIM HAL module.
******************************************************************************
* @attention
@@ -63,7 +63,7 @@
/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
* @{
*/
-#define MAX_HRTIM_TIMER 6
+#define MAX_HRTIM_TIMER 6U
/**
* @}
*/
@@ -102,10 +102,10 @@
*/
typedef enum
{
- HAL_HRTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_HRTIM_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_HRTIM_STATE_TIMEOUT = 0x06, /*!< Timeout state */
- HAL_HRTIM_STATE_ERROR = 0x07, /*!< Error state */
+ HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
+ HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
} HAL_HRTIM_StateTypeDef;
/**
@@ -155,7 +155,7 @@
typedef struct {
uint32_t Period; /*!< Specifies the timer period.
The period value must be above 3 periods of the fHRTIM clock.
- Maximum value is = 0xFFDF */
+ Maximum value is = 0xFFDFU */
uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
@@ -299,11 +299,11 @@
typedef struct {
uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
- The maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
+ The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
- CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
+ CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
} HRTIM_CompareCfgTypeDef;
/**
@@ -353,7 +353,7 @@
uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler.
This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge.
- This parameter can be a number between 0x0 and 0x1FF */
+ This parameter can be a number between 0x0 and 0x1FFU */
uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
@@ -361,7 +361,7 @@
uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge.
- This parameter can be a number between 0x0 and 0x1FF */
+ This parameter can be a number between 0x0 and 0x1FFU */
uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
@@ -455,13 +455,13 @@
* @{
* @brief Constants defining the timer indexes
*/
-#define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index used to access timer A registers */
-#define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index used to access timer B registers */
-#define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index used to access timer C registers */
-#define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index used to access timer D registers */
-#define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index used to access timer E registers */
-#define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index used to access master registers */
-#define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /*!< Index used to access HRTIM common registers */
+#define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */
+#define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */
+#define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */
+#define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */
+#define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */
+#define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */
+#define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */
/**
* @}
*/
@@ -484,10 +484,10 @@
* @{
* @brief Constants defining compare unit identifiers
*/
-#define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
-#define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
-#define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
-#define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
+#define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */
+#define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */
+#define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */
+#define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */
/**
* @}
*/
@@ -496,8 +496,8 @@
* @{
* @brief Constants defining capture unit identifiers
*/
-#define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
-#define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
+#define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */
+#define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */
/**
* @}
*/
@@ -506,16 +506,16 @@
* @{
* @brief Constants defining timer output identifiers
*/
-#define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Output 1 identifier */
-#define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Output 2 identifier */
-#define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Output 1 identifier */
-#define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Output 2 identifier */
-#define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Output 1 identifier */
-#define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Output 2 identifier */
-#define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Output 1 identifier */
-#define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Output 2 identifier */
-#define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Output 1 identifier */
-#define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Output 2 identifier */
+#define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */
+#define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */
+#define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */
+#define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */
+#define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */
+#define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */
+#define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */
+#define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */
+#define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */
+#define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */
/**
* @}
*/
@@ -524,10 +524,10 @@
* @{
* @brief Constants defining ADC triggers identifiers
*/
-#define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
-#define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 2 identifier */
-#define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 3 identifier */
-#define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 4 identifier */
+#define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
+#define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
+#define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
@@ -542,17 +542,17 @@
* @{
* @brief Constants defining external event channel identifiers
*/
-#define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
-#define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
-#define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
-#define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
-#define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
-#define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
-#define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
-#define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
-#define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
-#define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
-#define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
+#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */
+#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */
+#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */
+#define HRTIM_EVENT_3 (0x00000004U) /*!< External event channel 3 identifier */
+#define HRTIM_EVENT_4 (0x00000008U) /*!< External event channel 4 identifier */
+#define HRTIM_EVENT_5 (0x00000010U) /*!< External event channel 5 identifier */
+#define HRTIM_EVENT_6 (0x00000020U) /*!< External event channel 6 identifier */
+#define HRTIM_EVENT_7 (0x00000040U) /*!< External event channel 7 identifier */
+#define HRTIM_EVENT_8 (0x00000080U) /*!< External event channel 8 identifier */
+#define HRTIM_EVENT_9 (0x00000100U) /*!< External event channel 9 identifier */
+#define HRTIM_EVENT_10 (0x00000200U) /*!< External event channel 10 identifier */
/**
* @}
*/
@@ -561,11 +561,11 @@
* @{
* @brief Constants defining fault channel identifiers
*/
-#define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
-#define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
-#define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
-#define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
-#define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
+#define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */
+#define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */
+#define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */
+#define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */
+#define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */
/**
* @}
*/
@@ -575,14 +575,14 @@
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
-#define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
-#define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
/**
* @}
*/
@@ -591,9 +591,9 @@
* @{
* @brief Constants defining timer counter operating mode.
*/
-#define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
-#define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
-#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
+#define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
+#define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
/**
* @}
*/
@@ -602,8 +602,8 @@
* @{
* @brief Constants defining half mode enabling status.
*/
-#define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
-#define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
+#define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */
+#define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */
/**
* @}
*/
@@ -612,7 +612,7 @@
* @{
* @brief Constants defining the timer behavior following the synchronization event
*/
-#define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
/**
* @}
@@ -622,7 +622,7 @@
* @{
* @brief Constants defining the timer behavior following the synchronization event
*/
-#define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
/**
* @}
@@ -632,7 +632,7 @@
* @{
* @brief Constants defining on which output the DAC synchronization event is sent
*/
-#define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
+#define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */
#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
@@ -645,7 +645,7 @@
* @brief Constants defining whether a write access into a preloadable
* register is done into the active or the preload register.
*/
-#define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
+#define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
/**
* @}
@@ -656,15 +656,15 @@
* @brief Constants defining how the update occurs relatively to the burst DMA
* transaction and the external update request on update enable inputs 1 to 3.
*/
-#define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
+#define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
-#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
-#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
-#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
-#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
-#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
-#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
/**
* @}
*/
@@ -674,7 +674,7 @@
* @brief Constants defining how the timer behaves during a burst
mode operation.
*/
-#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U /*!< Timer counter clock is maintained and the timer operates normally */
#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
/**
* @}
@@ -686,7 +686,7 @@
* repetition period is completed (either due to roll-over or
* reset events)
*/
-#define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
+#define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */
#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
/**
* @}
@@ -698,7 +698,7 @@
* @brief Constants defining whether or not the puhs-pull mode is enabled for
* a timer.
*/
-#define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
+#define HRTIM_TIMPUSHPULLMODE_DISABLED (0x00000000U) /*!< Push-Pull mode disabled */
#define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
/**
* @}
@@ -708,7 +708,7 @@
* @{
* @brief Constants defining whether a faut channel is enabled for a timer
*/
-#define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
+#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */
#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
@@ -723,7 +723,7 @@
* @brief Constants defining whether or not fault enabling bits are write
* protected for a timer
*/
-#define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
+#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
/**
* @}
@@ -734,8 +734,8 @@
* @brief Constants defining whether or not fault the dead time insertion
* feature is enabled for a timer
*/
-#define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
-#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2U */
/**
* @}
*/
@@ -746,25 +746,25 @@
* for a timer. Also definethe source and outputs on which the delayed
* protection schemes are applied
*/
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
-
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7 */
-#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7 */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
+
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
/**
* @}
*/
@@ -774,7 +774,7 @@
* @brief Constants defining whether the registers update is done synchronously
* with any other timer or master update
*/
-#define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
+#define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
@@ -790,7 +790,7 @@
* @brief Constants defining the events that can be selected to trigger the reset
* of the timer counter
*/
-#define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
+#define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
@@ -799,16 +799,16 @@
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
-#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
-#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
-#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
-#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
-#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
-#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
-#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
-#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
-#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
-#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
+#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
+#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
+#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
+#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
+#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
+#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
+#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
+#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
+#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
+#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
@@ -831,7 +831,7 @@
* counter reset or roll-over to 0 after reaching the period value
* in continuous mode
*/
-#define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / roll-over disabled */
+#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
/**
* @}
@@ -843,7 +843,7 @@
* regular mode (compare match issued as soon as counter equal compare),
* or in auto-delayed mode
*/
-#define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
+#define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
@@ -872,7 +872,7 @@
* @{
* @brief Constants defining the polarity of a timer output
*/
-#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
+#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */
#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
@@ -883,7 +883,7 @@
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
-#define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
@@ -924,7 +924,7 @@
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
-#define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
@@ -965,7 +965,7 @@
* @brief Constants defining whether or not the timer output transition to its
IDLE state when burst mode is entered
*/
-#define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
+#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
/**
* @}
@@ -975,7 +975,7 @@
* @{
* @brief Constants defining the output level when output is in IDLE state
*/
-#define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
+#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
/**
* @}
@@ -985,7 +985,7 @@
* @{
* @brief Constants defining the output level when output is in FAULT state
*/
-#define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
@@ -998,7 +998,7 @@
* @brief Constants defining whether or not chopper mode is enabled for a timer
output
*/
-#define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< Output signal is not altered */
+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
/**
* @}
@@ -1009,7 +1009,7 @@
* @brief Constants defining the idle mode entry is delayed by forcing a
deadtime insertion before switching the outputs to their idle state
*/
-#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
/**
* @}
@@ -1020,7 +1020,7 @@
* @brief Constants defining the events that can be selected to trigger the
* capture of the timing unit counter
*/
-#define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
+#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */
#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
@@ -1061,11 +1061,11 @@
* @brief Constants defining the event filtering apploed to external events
* by a timer
*/
-#define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
+#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
@@ -1074,8 +1074,8 @@
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
@@ -1087,7 +1087,7 @@
* memorized (latched) and generated as soon as the blanking period
* is completed or the window ends
*/
-#define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
/**
* @}
@@ -1098,14 +1098,14 @@
* @brief Constants defining division ratio between the timer clock frequency
* (fHRTIM) and the deadtime generator clock (fDTG)
*/
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /*!< fDTG = fHRTIM * 8 */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
/**
* @}
*/
@@ -1115,7 +1115,7 @@
* @brief Constants defining whether the deadtime is positive or negative
* (overlapping signal) on rising edge
*/
-#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on rising edge */
#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
/**
* @}
@@ -1126,7 +1126,7 @@
* @brief Constants defining whether or not the deadtime (rising sign and
* value) is write protected
*/
-#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Deadtime rising value and sign is writeable */
#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
/**
* @}
@@ -1137,7 +1137,7 @@
* @brief Constants defining whether or not the deadtime rising sign is write
* protected
*/
-#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime rising sign is writeable */
#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
/**
* @}
@@ -1148,7 +1148,7 @@
* @brief Constants defining whether the deadtime is positive or negative
* (overlapping signal) on falling edge
*/
-#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */
#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
/**
* @}
@@ -1159,7 +1159,7 @@
* @brief Constants defining whether or not the deadtime (falling sign and
* value) is write protected
*/
-#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */
#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
/**
* @}
@@ -1170,7 +1170,7 @@
* @brief Constants defining whether or not the deadtime falling sign is write
* protected
*/
-#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */
#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
/**
* @}
@@ -1180,7 +1180,7 @@
* @{
* @brief Constants defining the frequency of the generated high frequency carrier
*/
-#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /*!< fCHPFRQ = fHRTIM / 16 */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
@@ -1205,14 +1205,14 @@
* @brief Constants defining the duty cycle of the generated high frequency carrier
* Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
*/
-#define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /*!< Only 1st pulse is present */
-#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
-#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
+#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */
+#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
/**
* @}
*/
@@ -1222,7 +1222,7 @@
* @brief Constants defining the pulse width of the first pulse of the generated
* high frequency carrier
*/
-#define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /*!< tSTPW = tHRTIM x 16 */
+#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */
#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
@@ -1248,9 +1248,9 @@
* instances, as a master unit (generating a synchronization signal)
* or as a slave (waiting for a trigger to be synchronized)
*/
-#define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
-#define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
-#define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
+#define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
+#define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
+#define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
/**
* @}
*/
@@ -1259,7 +1259,7 @@
* @{
* @brief Constants defining defining the synchronization input source
*/
-#define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
+#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
/**
@@ -1271,7 +1271,7 @@
* @brief Constants defining the source and event to be sent on the
* synchronization outputs
*/
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
@@ -1283,7 +1283,7 @@
* @{
* @brief Constants defining the routing and conditioning of the synchronization output event
*/
-#define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
+#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
/**
@@ -1294,10 +1294,10 @@
* @{
* @brief Constants defining available sources associated to external events
*/
-#define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
-#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
-#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
-#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
+#define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */
+#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */
+#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */
+#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */
/**
* @}
*/
@@ -1306,7 +1306,7 @@
* @{
* @brief Constants defining the polarity of an external event
*/
-#define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
+#define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */
#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
/**
* @}
@@ -1317,7 +1317,7 @@
* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
* of an external event
*/
-#define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
+#define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */
#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
@@ -1330,7 +1330,7 @@
* @brief Constants defining whether or not an external event is programmed in
fast mode
*/
-#define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+#define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is acting asynchronously on outputs (low latency mode) */
#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
/**
* @}
@@ -1341,22 +1341,22 @@
* @brief Constants defining the frequency used to sample an external event 6
* input and the length (N) of the digital filter applied
*/
-#define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
-#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
-#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
-#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
-#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
-#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
-#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
-#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
-#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
-#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
-#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
-#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
-#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
-#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
-#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
-#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
+#define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */
+#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */
+#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
+#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
+#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
+#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */
+#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
+#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
+#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
+#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
+#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
+#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
+#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
/**
* @}
*/
@@ -1367,10 +1367,10 @@
* fHRTIM) and the external event signal sampling clock (fEEVS)
* used by the digital filters
*/
-#define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
-#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
-#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
-#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
+#define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */
+#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */
+#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */
+#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
/**
* @}
*/
@@ -1380,7 +1380,7 @@
* @brief Constants defining whether a faults is be triggered by any external
* or internal fault source
*/
-#define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
+#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */
#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
/**
* @}
@@ -1390,7 +1390,7 @@
* @{
* @brief Constants defining the polarity of a fault event
*/
-#define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
+#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */
#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
/**
* @}
@@ -1401,22 +1401,22 @@
* @ brief Constants defining the frequency used to sample the fault input and
* the length (N) of the digital filter applied
*/
-#define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
-#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
-#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
-#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
-#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
-#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
-#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
-#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
-#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
-#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
-#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
-#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
-#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
-#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
-#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
-#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
+#define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */
+#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */
+#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
+#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
+#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
+#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */
+#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
+#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
+#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
+#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
+#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
+#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
+#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
/**
* @}
*/
@@ -1426,7 +1426,7 @@
* @brief Constants defining whether or not the fault programming bits are
write protected
*/
-#define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
+#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */
#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
/**
* @}
@@ -1438,10 +1438,10 @@
* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
* by the digital filters.
*/
-#define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
-#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
-#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
-#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
+#define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */
+#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */
+#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */
+#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
/**
* @}
*/
@@ -1451,7 +1451,7 @@
* @brief Constants defining if the burst mode is entered once or if it is
* continuously operating
*/
-#define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
+#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
/**
* @}
@@ -1461,7 +1461,7 @@
* @{
* @brief Constants defining the clock source for the burst mode counter
*/
-#define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
@@ -1480,22 +1480,22 @@
* @brief Constants defining the prescaling ratio of the fHRTIM clock
* for the burst mode controller
*/
-#define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
-#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
-#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
-#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
-#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
-#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
-#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
-#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
-#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
-#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
-#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
-#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
-#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
-#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
-#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
-#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
+#define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */
+#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */
+#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
+#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
+#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
+#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */
+#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
+#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
+#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
+#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
/**
* @}
*/
@@ -1506,7 +1506,7 @@
mechanism is enabled, i.e. a write access into a preloadable register
(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
*/
-#define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
+#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
/**
* @}
@@ -1517,13 +1517,13 @@
* @brief Constants defining the events that can be used tor trig the burst
* mode operation
*/
-#define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /*!< No trigger */
+#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */
#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
-#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */
#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
@@ -1558,7 +1558,7 @@
* @brief constants defining the source triggering the update of the
HRTIM_ADCxR register (transfer from preload to active register).
*/
-#define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
+#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
@@ -1574,72 +1574,72 @@
* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
*/
-#define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
-#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
-#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
-#define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
-#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
-#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
/**
@@ -1651,10 +1651,10 @@
* @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
-#define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
-#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 ms) */
-#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 ms) */
-#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 ms) */
+#define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
+#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
+#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
+#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
/**
* @}
*/
@@ -1664,7 +1664,7 @@
* @brief Constants defining the registers that can be written during a burst
* DMA operation
*/
-#define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
@@ -1694,7 +1694,7 @@
* @{
* @brief Constants used to enable or disable the burst mode controller
*/
-#define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
+#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
/**
* @}
@@ -1704,8 +1704,8 @@
* @{
* @brief Constants used to enable or disable a fault channel
*/
-#define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Fault channel is disabled */
-#define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /*!< Fault channel is enabled */
+#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
+#define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */
#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
@@ -1774,7 +1774,7 @@
* @{
* @brief Constants defining the operating state of the burst mode controller
*/
-#define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
+#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */
#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
/**
* @}
@@ -1785,7 +1785,7 @@
* @brief Constants defining on which output the signal is currently applied
* in push-pull mode
*/
-#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
/**
* @}
@@ -1797,7 +1797,7 @@
* push-pull mode balanced fault mode or delayed idle mode, when the
* protection was triggered
*/
-#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
/**
* @}
@@ -1806,7 +1806,7 @@
/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
* @{
*/
-#define HRTIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
@@ -1822,7 +1822,7 @@
/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
* @{
*/
-#define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
@@ -1837,7 +1837,7 @@
/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
* @{
*/
-#define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
+#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
@@ -1909,7 +1909,7 @@
/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
* @{
*/
-#define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
+#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */
#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
@@ -1924,7 +1924,7 @@
/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
* @{
*/
-#define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
+#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */
#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
@@ -1967,7 +1967,7 @@
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
-#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000)
+#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
@@ -1979,7 +1979,7 @@
(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
-#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000)
+#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
@@ -2091,7 +2091,7 @@
(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
-#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000)
+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
@@ -2119,9 +2119,9 @@
(((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
-#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000)
-
-#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000)
+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
@@ -2134,7 +2134,7 @@
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
-/* Auto delayed mode is only available for compare units 2 and 4 */
+/* Auto delayed mode is only available for compare units 2 and 4U */
#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
@@ -2659,38 +2659,38 @@
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
- ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000)) \
+ ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
|| \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)) \
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
|| \
- (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000)))
+ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
-#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000)
-
-#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000)
-
-#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000)
+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
+
+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
+
+#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
-#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000)
-
-
-#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000)
+#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
+
+
+#define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
-#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000)
-
-#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000)
+#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
/**
* @}
*/
@@ -2768,7 +2768,7 @@
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
}\
}\
- } while(0)
+ } while(0U)
/** @brief Enables or disables the specified HRTIM common interrupts.
* @param __HANDLE__: specifies the HRTIM Handle.
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,24 +2,24 @@
******************************************************************************
* @file stm32f3xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief I2C HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The I2C HAL driver can be used as follows:
-
+
(#) Declare a I2C_HandleTypeDef handle structure, for example:
- I2C_HandleTypeDef hi2c;
+ I2C_HandleTypeDef hi2c;
(#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
@@ -35,13 +35,13 @@
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx channel
(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx or Rx channel
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+ (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
@@ -98,6 +98,9 @@
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
@@ -195,13 +198,13 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -234,8 +237,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -273,7 +276,7 @@
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
@@ -291,9 +294,12 @@
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
+
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
/**
* @}
- */
+ */
/* Private macro -------------------------------------------------------------*/
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
@@ -351,7 +357,7 @@
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
@@ -366,13 +372,13 @@
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
+ [..] This subsection provides a set of functions allowing to initialize and
deinitialize the I2Cx peripheral:
- (+) User must Implement HAL_I2C_MspInit() function in which he configures
+ (+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
- (+) Call the function HAL_I2C_Init() to configure the selected device with
+ (+) Call the function HAL_I2C_Init() to configure the selected device with
the selected configuration:
(++) Clock Timing
(++) Own Address 1
@@ -383,15 +389,15 @@
(++) General call mode
(++) Nostretch mode
- (+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx peripheral.
+ (+) Call the function HAL_I2C_DeInit() to restore the default configuration
+ of the selected I2Cx peripheral.
@endverbatim
* @{
*/
/**
- * @brief Initializes the I2C according to the specified parameters
+ * @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and initialize the associated handle.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -419,7 +425,7 @@
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
}
@@ -434,18 +440,17 @@
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ /* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if(hi2c->Init.OwnAddress1 != 0U)
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
@@ -458,6 +463,9 @@
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
@@ -477,7 +485,7 @@
}
/**
- * @brief DeInitialize the I2C peripheral.
+ * @brief DeInitialize the I2C peripheral.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
@@ -518,14 +526,14 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -534,39 +542,39 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the I2C data
+ This subsection provides a set of functions allowing to manage the I2C data
transfers.
(#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
+ (++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
@@ -577,7 +585,7 @@
(++) HAL_I2C_Mem_Write()
(++) HAL_I2C_Mem_Read()
(++) HAL_I2C_IsDeviceReady()
-
+
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2C_Master_Transmit_IT()
(++) HAL_I2C_Master_Receive_IT()
@@ -635,9 +643,9 @@
return HAL_TIMEOUT;
}
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
@@ -683,7 +691,7 @@
{
return HAL_TIMEOUT;
}
-
+
if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -696,7 +704,7 @@
}
}
}
-
+
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
@@ -718,8 +726,8 @@
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -732,7 +740,7 @@
}
/**
- * @brief Receives in master mode an amount of data in blocking mode.
+ * @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -750,7 +758,7 @@
{
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -759,15 +767,15 @@
return HAL_TIMEOUT;
}
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
-
+
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if(hi2c->XferCount > MAX_NBYTE_SIZE)
@@ -808,7 +816,7 @@
{
return HAL_TIMEOUT;
}
-
+
if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -835,7 +843,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -843,11 +851,11 @@
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
+
return HAL_OK;
}
else
@@ -870,21 +878,21 @@
uint32_t tickstart = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
@@ -944,7 +952,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
@@ -967,10 +975,10 @@
return HAL_TIMEOUT;
}
}
-
+
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
+
/* Wait until BUSY flag is reset */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -983,7 +991,7 @@
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -997,7 +1005,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in blocking mode
+ * @brief Receive in slave mode an amount of data in blocking mode
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1010,7 +1018,7 @@
uint32_t tickstart = 0U;
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
@@ -1021,9 +1029,9 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
@@ -1077,7 +1085,7 @@
return HAL_ERROR;
}
}
-
+
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
hi2c->XferCount--;
@@ -1102,7 +1110,7 @@
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
- /* Wait until BUSY flag is reset */
+ /* Wait until BUSY flag is reset */
if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
@@ -1114,7 +1122,7 @@
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1151,16 +1159,16 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -1179,7 +1187,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -1193,7 +1201,7 @@
else
{
return HAL_BUSY;
- }
+ }
}
/**
@@ -1220,16 +1228,16 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -1244,11 +1252,11 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -1261,12 +1269,12 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1280,24 +1288,24 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -1310,8 +1318,8 @@
}
else
{
- return HAL_BUSY;
- }
+ return HAL_BUSY;
+ }
}
/**
@@ -1329,24 +1337,24 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -1354,12 +1362,12 @@
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
@@ -1387,13 +1395,13 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
@@ -1472,7 +1480,7 @@
}
/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -1494,17 +1502,17 @@
/* Process Locked */
__HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
- hi2c->pBuffPtr = pData;
- hi2c->XferCount = Size;
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
+
if(hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -1579,7 +1587,7 @@
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1593,14 +1601,14 @@
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
- __HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
@@ -1645,7 +1653,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1658,15 +1666,15 @@
{
if((pData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
@@ -1700,7 +1708,7 @@
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
return HAL_OK;
}
@@ -1728,9 +1736,9 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
@@ -1843,12 +1851,12 @@
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
+
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2434,7 +2442,7 @@
}
/**
- * @brief Checks if target device is ready for communication.
+ * @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -2447,9 +2455,9 @@
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
uint32_t tickstart = 0U;
-
+
__IO uint32_t I2C_Trials = 0U;
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
@@ -2473,8 +2481,8 @@
tickstart = HAL_GetTick();
while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
- {
+ if(Timeout != HAL_MAX_DELAY)
+ {
if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
@@ -2483,7 +2491,7 @@
__HAL_UNLOCK(hi2c);
return HAL_TIMEOUT;
}
- }
+ }
}
/* Check if the NACKF flag has not been set */
@@ -2597,7 +2605,6 @@
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
}
-
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
@@ -2699,7 +2706,7 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
{
@@ -2711,6 +2718,14 @@
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ }
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
@@ -2765,7 +2780,7 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
if((pData == NULL) || (Size == 0U))
{
@@ -2777,7 +2792,15 @@
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2993,14 +3016,14 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -3024,14 +3047,14 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -3092,14 +3115,14 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemTxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -3124,14 +3147,14 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
@@ -3157,12 +3180,12 @@
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @brief Peripheral State, Mode and Error functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -3196,7 +3219,7 @@
* @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @retval I2C Error Code
+* @retval I2C Error Code
*/
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
@@ -3205,16 +3228,16 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @addtogroup I2C_Private_Functions
* @{
*/
-
+
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3736,6 +3759,9 @@
uint16_t ownadd1code = 0U;
uint16_t ownadd2code = 0U;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
/* In case of Listen state, need to inform upper layer of address match code event */
if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
@@ -4263,7 +4289,7 @@
* @param hdma DMA handle
* @retval None
*/
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4301,12 +4327,15 @@
}
/**
- * @brief DMA I2C slave transmit process complete callback.
+ * @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
* @retval None
*/
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
@@ -4317,7 +4346,7 @@
* @param hdma DMA handle
* @retval None
*/
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
@@ -4359,8 +4388,11 @@
* @param hdma DMA handle
* @retval None
*/
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
+static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
@@ -4807,7 +4839,7 @@
/**
* @}
- */
+ */
#endif /* HAL_I2C_MODULE_ENABLED */
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -245,8 +245,8 @@
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
-#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
@@ -658,6 +658,7 @@
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,25 +2,25 @@
******************************************************************************
* @file stm32f3xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
-
+
[..] Comparing to other previous devices, the I2C interface for STM32F3xx
devices contains the following additional features
-
+
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode
-
+
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
@@ -31,7 +31,7 @@
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
- (++) HAL_I2CEx_DisbleFastModePlus()
+ (++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
@@ -60,7 +60,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -90,11 +90,11 @@
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
- *
-@verbatim
+ *
+@verbatim
===============================================================================
##### Extended features functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
@@ -102,9 +102,9 @@
@endverbatim
* @{
*/
-
+
/**
- * @brief Configure I2C Analog noise filter.
+ * @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
@@ -115,31 +115,31 @@
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
hi2c->State = HAL_I2C_STATE_BUSY;
-
+
/* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
+ __HAL_I2C_DISABLE(hi2c);
+
/* Reset I2Cx ANOFF bit */
- hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
-
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
-
- __HAL_I2C_ENABLE(hi2c);
-
+
+ __HAL_I2C_ENABLE(hi2c);
+
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
- return HAL_OK;
+
+ return HAL_OK;
}
else
{
@@ -148,56 +148,56 @@
}
/**
- * @brief Configure I2C Digital noise filter.
+ * @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
- * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg = 0U;
-
+
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
hi2c->State = HAL_I2C_STATE_BUSY;
-
+
/* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
+ __HAL_I2C_DISABLE(hi2c);
+
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
-
+
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
-
+
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
-
+
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
-
- __HAL_I2C_ENABLE(hi2c);
-
+
+ __HAL_I2C_ENABLE(hi2c);
+
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
+
return HAL_OK;
}
else
{
return HAL_BUSY;
}
-}
+}
/**
* @brief Enable I2C wakeup from stop mode.
@@ -209,35 +209,34 @@
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
hi2c->State = HAL_I2C_STATE_BUSY;
-
+
/* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
+ __HAL_I2C_DISABLE(hi2c);
+
/* Enable wakeup from stop mode */
- hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
-
- __HAL_I2C_ENABLE(hi2c);
-
+ hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+ __HAL_I2C_ENABLE(hi2c);
+
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
+
return HAL_OK;
}
else
{
return HAL_BUSY;
}
-}
-
+}
/**
* @brief Disable I2C wakeup from stop mode.
@@ -249,49 +248,58 @@
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
-
+
if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ {
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
hi2c->State = HAL_I2C_STATE_BUSY;
-
+
/* Disable the selected I2C peripheral */
- __HAL_I2C_DISABLE(hi2c);
-
+ __HAL_I2C_DISABLE(hi2c);
+
/* Enable wakeup from stop mode */
- hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
-
+ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
__HAL_I2C_ENABLE(hi2c);
-
+
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
-
- return HAL_OK;
+
+ return HAL_OK;
}
else
{
return HAL_BUSY;
}
-}
+}
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be enabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be enabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
+
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
-
+
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
@@ -300,13 +308,22 @@
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
+ * @note For I2C1, fast mode plus driving capability can be disabled on all selected
+ * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+ * on each one of the following pins PB6, PB7, PB8 and PB9.
+ * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+ * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+ * @note For all I2C2 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C2 parameter.
+ * @note For all I2C3 pins fast mode plus driving capability can be disabled
+ * only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
-
+
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
@@ -316,7 +333,7 @@
/**
* @}
- */
+ */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2C_EX_H
@@ -44,17 +44,17 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f3xx_hal_def.h"
+#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
-/** @addtogroup I2CEx I2CEx
+/** @addtogroup I2CEx
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
@@ -64,8 +64,8 @@
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
-#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
-#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+#define I2C_ANALOGFILTER_ENABLE 0x00000000U
+#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
@@ -73,41 +73,30 @@
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
-#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
-#define I2C_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast Mode Plus on PB6 */
-#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
-#define I2C_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast Mode Plus on PB7 */
-#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
-#define I2C_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast Mode Plus on PB8 */
-#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
-#define I2C_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast Mode Plus on PB9 */
-#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
-
-#if defined(SYSCFG_CFGR1_I2C1_FMP)
-#define I2C_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< Enable Fast Mode Plus on I2C1 pins */
-#endif /* SYSCFG_CFGR1_I2C1_FMP */
-
+#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
+#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
+#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
+#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
+#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
+#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
-#define I2C_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< Enable Fast Mode Plus on I2C2 pins */
-#endif /* SYSCFG_CFGR1_I2C2_FMP */
-
+#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
+#endif
#if defined(SYSCFG_CFGR1_I2C3_FMP)
-#define I2C_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< Enable Fast Mode Plus on I2C3 pins */
-#endif /* SYSCFG_CFGR1_I2C3_FMP */
+#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
+#endif
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -119,12 +108,12 @@
* @brief Extended features functions
* @{
*/
-
+
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
@@ -135,69 +124,53 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-#if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
-#elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
-#elif defined(SYSCFG_CFGR1_I2C1_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
- (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
-#endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+ ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
/**
* @}
- */
-
+ */
+
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
- */
+ */
/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
/**
* @}
*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
/**
* @}
*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}
@@ -205,5 +178,4 @@
#endif /* __STM32F3xx_HAL_I2C_EX_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -356,7 +356,7 @@
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -366,8 +366,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
@@ -388,7 +388,7 @@
__HAL_I2S_ENABLE(hi2s);
}
- while(hi2s->TxXferCount > 0)
+ while(hi2s->TxXferCount > 0U)
{
hi2s->Instance->DR = (*pData++);
hi2s->TxXferCount--;
@@ -449,7 +449,7 @@
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -459,8 +459,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -489,7 +489,7 @@
}
/* Receive data */
- while(hi2s->RxXferCount > 0)
+ while(hi2s->RxXferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
@@ -551,7 +551,7 @@
{
if(hi2s->State == HAL_I2S_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -560,8 +560,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
@@ -616,7 +616,7 @@
{
if(hi2s->State == HAL_I2S_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -625,8 +625,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -678,7 +678,7 @@
{
uint32_t *tmp;
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -689,8 +689,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
@@ -756,7 +756,7 @@
{
uint32_t *tmp;
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -767,8 +767,8 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -874,7 +874,7 @@
}
/* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
@@ -1141,12 +1141,12 @@
{
I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable Tx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- hi2s->TxXferCount = 0;
+ hi2s->TxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
HAL_I2S_TxCpltCallback(hi2s);
@@ -1175,11 +1175,11 @@
{
I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable Rx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0;
+ hi2s->RxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
HAL_I2S_RxCpltCallback(hi2s);
@@ -1210,8 +1210,8 @@
/* Disable Rx and Tx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0;
- hi2s->RxXferCount = 0;
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
hi2s->State= HAL_I2S_STATE_READY;
@@ -1232,7 +1232,7 @@
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1253,7 +1253,7 @@
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
@@ -1283,7 +1283,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@@ -1302,7 +1302,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@@ -100,13 +100,13 @@
*/
typedef enum
{
- HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
}HAL_I2S_StateTypeDef;
@@ -159,12 +159,12 @@
/** @defgroup I2S_Error I2S Error
* @{
*/
-#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
-#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */
-#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
/**
* @}
*/
@@ -172,8 +172,8 @@
/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
-#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
-#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
+#define I2S_CLOCK_EXTERNAL (0x00000001U)
+#define I2S_CLOCK_SYSCLK (0x00000002U)
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_SYSCLK))
@@ -184,10 +184,10 @@
/** @defgroup I2S_Mode I2S Mode
* @{
*/
-#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
-#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
-#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
-#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+#define I2S_MODE_SLAVE_TX (0x00000000U)
+#define I2S_MODE_SLAVE_RX (0x00000100U)
+#define I2S_MODE_MASTER_TX (0x00000200U)
+#define I2S_MODE_MASTER_RX (0x00000300U)
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
@@ -200,11 +200,11 @@
/** @defgroup I2S_Standard I2S Standard
* @{
*/
-#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
-#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
-#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
-#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
-#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+#define I2S_STANDARD_PHILIPS (0x00000000U)
+#define I2S_STANDARD_MSB (0x00000010U)
+#define I2S_STANDARD_LSB (0x00000020U)
+#define I2S_STANDARD_PCM_SHORT (0x00000030U)
+#define I2S_STANDARD_PCM_LONG (0x000000B0U)
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
@@ -218,10 +218,10 @@
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
-#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
-#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
-#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+#define I2S_DATAFORMAT_16B (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
+#define I2S_DATAFORMAT_24B (0x00000003U)
+#define I2S_DATAFORMAT_32B (0x00000005U)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
@@ -235,7 +235,7 @@
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
@@ -246,16 +246,16 @@
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
-#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+#define I2S_AUDIOFREQ_192K (192000U)
+#define I2S_AUDIOFREQ_96K (96000U)
+#define I2S_AUDIOFREQ_48K (48000U)
+#define I2S_AUDIOFREQ_44K (44100U)
+#define I2S_AUDIOFREQ_32K (32000U)
+#define I2S_AUDIOFREQ_22K (22050U)
+#define I2S_AUDIOFREQ_16K (16000U)
+#define I2S_AUDIOFREQ_11K (11025U)
+#define I2S_AUDIOFREQ_8K (8000U)
+#define I2S_AUDIOFREQ_DEFAULT (2U)
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
@@ -267,8 +267,8 @@
/** @defgroup I2S_FullDuplex_Mode I2S Full Duplex Mode
* @{
*/
-#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
-#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
+#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
+#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
@@ -279,7 +279,7 @@
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
@@ -384,7 +384,7 @@
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
- }while(0)
+ }while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
@@ -393,7 +393,7 @@
__IO uint32_t tmpreg;\
tmpreg = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg); \
- }while(0)
+ }while(0U)
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief I2S Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S Extended peripheral:
@@ -19,7 +19,21 @@
called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
(#) The Extended block is not a full SPI IP, it is used only as I2S slave to
implement full duplex mode. The Extended block uses the same clock sources
- as its master.
+ as its master (refer to the following Figure).
+
+ +-----------------------+
+ I2Sx_SCK | |
+ ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
+ +--|-->| |
+ | | +-----------------------+
+ | |
+ I2S_WS | |
+ ------>| |
+ | | +-----------------------+
+ | +-->| |
+ | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+ +----->| |
+ +-----------------------+
(#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
@@ -101,26 +115,6 @@
******************************************************************************
*/
-/*
- Additional Figure: The Extended block uses the same clock sources as its master.
- (refer to the following Figure).
-
- +-----------------------+
- I2Sx_SCK | |
- ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
- +--|-->| |
- | | +-----------------------+
- | |
- I2S_WS | |
- ------>| |
- | | +-----------------------+
- | +-->| |
- | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
- +----->| |
- +-----------------------+
-
-*/
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -148,7 +142,7 @@
*/
typedef enum
{
- I2S_USE_I2S = 0x00, /*!< I2Sx should be used */
+ I2S_USE_I2S = 0x00U, /*!< I2Sx should be used */
I2S_USE_I2SEXT = 0x01 /*!< I2Sx_ext should be used */
}I2S_UseTypeDef;
/**
@@ -223,8 +217,8 @@
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
+ uint16_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U, i2sclk = 0U;
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
RCC_PeriphCLKInitTypeDef rccperiphclkinit;
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
@@ -256,7 +250,7 @@
hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- hi2s->Instance->I2SPR = 0x0002;
+ hi2s->Instance->I2SPR = 0x0002U;
/* Get the I2SCFGR register value */
tmpreg = hi2s->Instance->I2SCFGR;
@@ -264,8 +258,8 @@
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
{
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
+ i2sodd = (uint16_t)0U;
+ i2sdiv = (uint16_t)2U;
}
/* If the requested audio frequency is not the default, compute the prescaler */
else
@@ -274,12 +268,12 @@
if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
- packetlength = 1;
+ packetlength = 1U;
}
else
{
/* Packet length is 32 bits */
- packetlength = 2;
+ packetlength = 2U;
}
/* Get I2S source Clock frequency ****************************************/
@@ -323,33 +317,33 @@
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint16_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
- tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint16_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
- tmp = tmp / 10;
+ tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
+ i2sodd = (uint16_t) (i2sodd << 8U);
}
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ /* Test if the divider is 1 or 0 or greater than 0xFFU */
+ if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
+ i2sdiv = 2U;
+ i2sodd = 0U;
}
/* Write to SPIx I2SPR register the computed value */
@@ -370,7 +364,7 @@
I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
- I2SxEXT(hi2s->Instance)->I2SPR = 0x0002;
+ I2SxEXT(hi2s->Instance)->I2SPR = 0x0002U;
/* Get the I2SCFGR register value */
tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
@@ -629,7 +623,7 @@
I2SxEXT(hi2s->Instance)->CR2 |= (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
/* If the I2Sext peripheral is still not enabled, enable it */
- if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
{
/* Enable I2Sext peripheral */
__HAL_I2SEXT_ENABLE(hi2s);
@@ -638,7 +632,7 @@
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
@@ -781,7 +775,7 @@
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -796,10 +790,10 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -838,7 +832,7 @@
__HAL_I2S_ENABLE(hi2s);
}
- while(hi2s->RxXferCount > 0)
+ while(hi2s->RxXferCount > 0U)
{
/* Wait until TXE flag is set */
if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2S) != HAL_OK)
@@ -849,7 +843,7 @@
return HAL_TIMEOUT;
}
- if (hi2s->TxXferCount > 0)
+ if (hi2s->TxXferCount > 0U)
{
/* Check if an underrun occurs */
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
@@ -925,7 +919,7 @@
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
- while(hi2s->RxXferCount > 0)
+ while(hi2s->RxXferCount > 0U)
{
/* Wait until TXE flag is set */
if (I2S_FullDuplexWaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout, I2S_USE_I2SEXT) != HAL_OK)
@@ -936,7 +930,7 @@
return HAL_TIMEOUT;
}
- if (hi2s->TxXferCount > 0)
+ if (hi2s->TxXferCount > 0U)
{
/* Check if an underrun occurs */
if(__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
@@ -1020,7 +1014,7 @@
{
if(hi2s->State == HAL_I2S_STATE_READY)
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1035,10 +1029,10 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -1069,18 +1063,18 @@
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
{
/* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0)
+ if(hi2s->TxXferCount != 0U)
{
/* Transmit First data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
/* Disable I2Sext RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
@@ -1111,18 +1105,18 @@
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Prepare the First Data before enabling the I2S */
- if(hi2s->TxXferCount != 0)
+ if(hi2s->TxXferCount != 0U)
{
/* Transmit First data */
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
/* Disable I2Sext TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE| I2S_IT_ERR));
@@ -1168,7 +1162,7 @@
{
uint32_t *tmp;
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1185,10 +1179,10 @@
if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
@@ -1322,9 +1316,9 @@
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
- hi2s->RxXferCount = 0;
+ hi2s->RxXferCount = 0U;
- if (hi2s->TxXferCount == 0)
+ if (hi2s->TxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
@@ -1344,9 +1338,9 @@
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
- hi2s->TxXferCount = 0;
+ hi2s->TxXferCount = 0U;
- if (hi2s->RxXferCount == 0)
+ if (hi2s->RxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
@@ -1368,8 +1362,8 @@
hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0;
- hi2s->RxXferCount = 0;
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
hi2s->State= HAL_I2S_STATE_READY;
@@ -1392,12 +1386,12 @@
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
HAL_I2S_TxRxCpltCallback(hi2s);
@@ -1410,12 +1404,12 @@
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
/* Disable I2Sext TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
HAL_I2S_TxRxCpltCallback(hi2s);
@@ -1438,12 +1432,12 @@
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
HAL_I2S_TxRxCpltCallback(hi2s);
@@ -1456,12 +1450,12 @@
(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
hi2s->RxXferCount--;
- if(hi2s->RxXferCount == 0)
+ if(hi2s->RxXferCount == 0U)
{
/* Disable I2Sext RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- if(hi2s->TxXferCount == 0)
+ if(hi2s->TxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
HAL_I2S_TxRxCpltCallback(hi2s);
@@ -1493,7 +1487,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@@ -1513,7 +1507,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@@ -1536,7 +1530,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
@@ -1556,7 +1550,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2s_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of I2S HAL Extended module.
******************************************************************************
* @attention
@@ -119,7 +119,7 @@
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
- (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0)
+ (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_irda.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -51,6 +51,10 @@
(++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_IRDA_MspInit() API.
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
@@ -137,8 +141,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
-#ifdef HAL_IRDA_MODULE_ENABLED
-
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
@@ -148,14 +150,14 @@
* @{
*/
+#ifdef HAL_IRDA_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
-#define IRDA_TXDMA_TIMEOUTVALUE 22000
-#define IRDA_TIMEOUT_VALUE 22000
+#define IRDA_TEACK_REACK_TIMEOUT 1000 /*!< IRDA TX or RX enable acknowledge time-out value */
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
/**
@@ -165,20 +167,27 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+/** @addtogroup IRDA_Private_Functions
* @{
*/
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
@@ -222,7 +231,7 @@
frame length is either defined by the M bit (8-bits or 9-bits)
or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
Possible IRDA frame formats are as listed in the following table:
-
+
Table 1. IRDA frame format.
+-----------------------------------------------------------------------+
| M bit | PCE bit | IRDA frame |
@@ -253,9 +262,9 @@
*/
/**
- * @brief Initialize the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and initialize the associated handle.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -293,8 +302,8 @@
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
- hirda->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP);
- hirda->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
hirda->Instance->CR3 |= USART_CR3_IREN;
@@ -307,8 +316,8 @@
}
/**
- * @brief DeInitialize the IRDA peripheral.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -331,8 +340,8 @@
__HAL_IRDA_DISABLE(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_RESET;
- hirda->RxState = HAL_IRDA_STATE_RESET;
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hirda);
@@ -341,12 +350,12 @@
}
/**
- * @brief Initialize the IRDA MSP.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Initialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -357,12 +366,12 @@
}
/**
- * @brief DeInitialize the IRDA MSP.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -380,9 +389,9 @@
* @brief IRDA Transmit and Receive functions
*
@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
@@ -393,11 +402,11 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
- (#) There are two modes of transfer:
+ (#) There are two mode of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode: the communication is performed using Interrupts
+ (++) Non-Blocking mode: the communication is performed using Interrupts
or DMA, these API's return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
@@ -429,27 +438,52 @@
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
* @brief Send an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Specify timeout value.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
+ uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -458,32 +492,34 @@
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0)
+ while(hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pData +=2;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pData += 2U;
}
else
{
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
}
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -504,22 +540,23 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @param Timeout: Specify timeout value.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
uint16_t uhMask;
+ uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -528,23 +565,25 @@
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
- /* Computation of the mask to apply to the RDR register
+ /* Computation of the mask to apply to RDR register
of the UART associated to the IRDA */
IRDA_MASK_COMPUTATION(hirda);
uhMask = hirda->Mask;
/* Check data remaining to be received */
- while(hirda->RxXferCount > 0)
+ while(hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -552,7 +591,7 @@
{
tmp = (uint16_t*) pData ;
*tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2;
+ pData +=2U;
}
else
{
@@ -576,10 +615,10 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -587,7 +626,7 @@
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -600,14 +639,13 @@
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Transmit Data Register Empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -619,10 +657,10 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -630,13 +668,13 @@
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hirda);
+ __HAL_LOCK(hirda);
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
@@ -647,20 +685,16 @@
IRDA_MASK_COMPUTATION(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Data Register not empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
- /* Enable the IRDA Parity Error Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
@@ -672,23 +706,21 @@
/**
* @brief Send an amount of data in DMA mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
/* Check that a Tx process is not already ongoing */
if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -701,7 +733,6 @@
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Set the IRDA DMA transfer complete callback */
@@ -713,19 +744,21 @@
/* Set the DMA error callback */
hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
/* Enable the IRDA transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
+ HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
/* Clear the TC flag in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
- hirda->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -737,25 +770,23 @@
/**
* @brief Receive an amount of data in DMA mode.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @note When the IRDA parity is enabled (PCE = 1) the received data contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check if USART/UART instance associated to the IRDA handle supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(hirda->Instance));
/* Check that a Rx process is not already ongoing */
if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -767,7 +798,6 @@
hirda->RxXferSize = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Set the IRDA DMA transfer complete callback */
@@ -779,16 +809,24 @@
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
- hirda->Instance->CR3 |= USART_CR3_DMAR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -800,44 +838,50 @@
/**
- * @brief Pause the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Pause the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
{
/* Process Locked */
__HAL_LOCK(hirda);
-
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
{
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
/* Disable the IRDA DMA Rx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resume the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @brief Resume the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
{
/* Process Locked */
__HAL_LOCK(hirda);
-
+
if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
@@ -847,165 +891,670 @@
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
/* Enable the IRDA DMA Rx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
/**
- * @brief Stop the DMA Transfer.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @brief Stop the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
- HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
- generated if the DMA transfer interruption occurs at the middle or at the end of the stream
- and the corresponding call back is executed.
- */
+ HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
- /* Disable the IRDA Tx/Rx DMA requests */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA tx channel */
- if(hirda->hdmatx != NULL)
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
- HAL_DMA_Abort(hirda->hdmatx);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
}
- /* Abort the IRDA DMA rx channel */
- if(hirda->hdmarx != NULL)
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
- HAL_DMA_Abort(hirda->hdmarx);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
}
-
- hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
/**
* @brief Handle IRDA interrupt request.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
- /* IRDA parity error interrupt occurred -------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+ uint32_t isrflags = READ_REG(hirda->Instance->ISR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
- /* Set the IRDA Rx state ready to be able to start again the process */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(hirda->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
- /* IRDA frame error interrupt occurred --------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- /* Set the IRDA Rx state ready to be able to start again the process */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
- /* IRDA noise error interrupt occurred --------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- /* Set the IRDA Rx state ready to be able to start again the process */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
- /* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- /* Set the IRDA Rx state ready to be able to start again the process */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
- /* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
- {
- HAL_IRDA_ErrorCallback(hirda);
- }
-
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_RXNE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
-
+ } /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TXE) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE) != RESET))
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
IRDA_Transmit_IT(hirda);
+ return;
}
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET))
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
IRDA_EndTransmit_IT(hirda);
+ return;
}
}
/**
* @brief Tx Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Tx Half Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Transfer completed callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -1013,8 +1562,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
*/
}
@@ -1036,17 +1585,65 @@
/**
* @brief IRDA error callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
@@ -1059,7 +1656,7 @@
*
@verbatim
==============================================================================
- ##### Peripheral State and Errors functions #####
+ ##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of IrDA
@@ -1075,24 +1672,24 @@
/**
* @brief Return the IRDA handle state.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
- uint32_t temp1= 0x00, temp2 = 0x00;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
temp1 = hirda->gState;
temp2 = hirda->RxState;
-
+
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the IRDA handle error code.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
@@ -1108,20 +1705,19 @@
* @}
*/
-/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
-
/**
- * @brief Configure the IRDA peripheral.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval None
+ * @retval HAL status
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
- uint32_t tmpreg = 0x00000000;
+ uint32_t tmpreg = 0x00000000U;
IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
@@ -1153,19 +1749,19 @@
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_PCLK2:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_SYSCLK:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2U)) / hirda->Init.BaudRate);
break;
case IRDA_CLOCKSOURCE_UNDEFINED:
default:
@@ -1177,17 +1773,21 @@
}
/**
- * @brief Check the IRDA Idle State.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
{
+ uint32_t tickstart = 0U;
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* TEACK bits in ISR is checked only when available.
Bit is defined and available only for UART instances supporting WakeUp from Stop Mode feature.
*/
@@ -1197,7 +1797,7 @@
if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@@ -1208,7 +1808,8 @@
/* Check if the Receiver is enabled */
if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ /* Wait until REACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout Occured */
return HAL_TIMEOUT;
@@ -1216,8 +1817,8 @@
}
/* Initialize the IRDA state*/
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -1227,111 +1828,114 @@
/**
* @brief Handle IRDA Communication Timeout.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param Flag: specifies the IRDA flag to check.
- * @param Status: the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
- * @param Timeout: Timeout duration
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag Specifies the IRDA flag to check.
+ * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
- while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
/**
* @brief DMA IRDA transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
- hirda->TxXferCount = 0;
+ hirda->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the IRDA CR3 register */
- hirda->Instance->CR3 &= ~(USART_CR3_DMAT);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
{
HAL_IRDA_TxCpltCallback(hirda);
}
+
}
/**
- * @brief DMA IRDA transmit process half complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
HAL_IRDA_TxHalfCpltCallback(hirda);
}
@@ -1344,16 +1948,20 @@
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the IRDA CR3 register */
- hirda->Instance->CR3 &= ~(USART_CR3_DMAR);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
@@ -1370,37 +1978,191 @@
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
HAL_IRDA_RxHalfCpltCallback(hirda);
}
/**
- * @brief DMA IRDA communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
- hirda->RxXferCount = 0;
- hirda->TxXferCount = 0;
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
HAL_IRDA_ErrorCallback(hirda);
}
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmarx != NULL)
+ {
+ if(hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
/**
- * @brief Send an amount of data in non-blocking mode.
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmatx != NULL)
+ {
+ if(hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ hirda->TxXferCount = 0U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_IRDA_Transmit_IT().
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
@@ -1410,13 +2172,13 @@
/* Check that a Tx process is ongoing */
if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- if(hirda->TxXferCount == 0)
+ if(hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
/* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
return HAL_OK;
}
@@ -1425,12 +2187,12 @@
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- hirda->pTxBuffPtr += 2;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ hirda->pTxBuffPtr += 2U;
}
else
{
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
}
hirda->TxXferCount--;
@@ -1445,14 +2207,14 @@
/**
* @brief Wrap up transmission in non-blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
@@ -1462,44 +2224,42 @@
return HAL_OK;
}
-
/**
- * @brief Receive an amount of data in non-blocking mode.
- * Function is called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Receive_IT().
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
uint16_t* tmp;
- uint16_t uhMask = hirda->Mask;
+ uint16_t uhMask = hirda->Mask;
+ uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
-
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t*) hirda->pRxBuffPtr ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- hirda->pRxBuffPtr +=2;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ hirda->pRxBuffPtr +=2U;
}
else
{
- *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
}
- if(--hirda->RxXferCount == 0)
+ if(--hirda->RxXferCount == 0U)
{
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
+ /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
@@ -1524,6 +2284,7 @@
* @}
*/
+#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
@@ -1532,6 +2293,4 @@
* @}
*/
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_irda.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file contains all the functions prototypes for the IRDA
* firmware library.
******************************************************************************
@@ -55,7 +55,7 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
@@ -155,12 +155,12 @@
*/
typedef enum
{
- IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
}IRDA_ClockSourceTypeDef;
/**
@@ -168,7 +168,7 @@
*/
typedef struct
{
- USART_TypeDef *Instance; /*!< USART registers base address */
+ USART_TypeDef *Instance; /*!< IRDA registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
@@ -176,15 +176,15 @@
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
- uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
- uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
- uint16_t Mask; /*!< USART RX RDR register mask */
+ uint16_t Mask; /*!< IRDA RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
@@ -209,12 +209,12 @@
*/
typedef enum
{
- IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */
- IRDA_PARITY = 0x01, /*!< IRDA frame parity */
- IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */
- IRDA_MODE = 0x03, /*!< IRDA communication mode */
- IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */
- IRDA_POWERMODE = 0x05 /*!< IRDA power mode */
+ IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */
+ IRDA_PARITY = 0x01U, /*!< IRDA frame parity */
+ IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */
+ IRDA_MODE = 0x03U, /*!< IRDA communication mode */
+ IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */
+ IRDA_POWERMODE = 0x05U /*!< IRDA power mode */
}IRDA_ControlTypeDef;
/**
@@ -229,12 +229,13 @@
/** @defgroup IRDA_Error IRDA Error
* @{
*/
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
/**
* @}
*/
@@ -242,7 +243,7 @@
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
-#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
@@ -262,7 +263,7 @@
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
-#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
/**
* @}
@@ -271,7 +272,7 @@
/** @defgroup IRDA_State IRDA State
* @{
*/
-#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
+#define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */
#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
/**
* @}
@@ -280,7 +281,7 @@
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
-#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */
#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
/**
* @}
@@ -289,7 +290,7 @@
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
-#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
/**
* @}
@@ -298,7 +299,7 @@
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
-#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */
#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
/**
* @}
@@ -307,7 +308,7 @@
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
-#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */
#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
/**
* @}
@@ -316,8 +317,8 @@
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
* @{
*/
-#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
/**
* @}
@@ -328,18 +329,18 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */
-#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */
-#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */
-#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */
-#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */
-#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */
-#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */
-#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
-#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
-#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
-#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Noise error */
-#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
+#define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */
+#define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */
+#define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */
+#define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */
+#define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */
+#define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */
+#define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */
+#define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */
+#define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */
+#define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */
/**
* @}
*/
@@ -354,27 +355,15 @@
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */
-#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
-#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
-
-/** Elements values convention: 000000000XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- */
-#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
-
-/** Elements values convention: 0000ZZZZ00000000b
- * - ZZZZ : Flag position in the ISR register(4bits)
- */
-#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
-#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
+#define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */
+#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */
+#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */
/**
* @}
*/
@@ -382,10 +371,11 @@
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
-#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
@@ -394,7 +384,7 @@
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
-#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */
+#define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */
/**
* @}
*/
@@ -416,9 +406,9 @@
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0)
+ } while(0U)
-/** @brief Flush the IRDA Data registers.
+/** @brief Flush the IRDA DR register.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
@@ -426,18 +416,18 @@
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg IRDA_CLEAR_PEF
- * @arg IRDA_CLEAR_FEF
- * @arg IRDA_CLEAR_NEF
- * @arg IRDA_CLEAR_OREF
- * @arg IRDA_CLEAR_TCF
- * @arg IRDA_CLEAR_IDLEF
+ * @arg @ref IRDA_CLEAR_PEF
+ * @arg @ref IRDA_CLEAR_FEF
+ * @arg @ref IRDA_CLEAR_NEF
+ * @arg @ref IRDA_CLEAR_OREF
+ * @arg @ref IRDA_CLEAR_TCF
+ * @arg @ref IRDA_CLEAR_IDLEF
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -475,23 +465,20 @@
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
- * @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg IRDA_FLAG_BUSY: Busy flag
- * @arg IRDA_FLAG_ABRF: Auto Baud rate detection flag
- * @arg IRDA_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg IRDA_FLAG_TXE: Transmit data register empty flag
- * @arg IRDA_FLAG_TC: Transmission Complete flag
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
- * @arg IRDA_FLAG_IDLE: Idle Line detection flag
- * @arg IRDA_FLAG_ORE: OverRun Error flag
- * @arg IRDA_FLAG_NE: Noise Error flag
- * @arg IRDA_FLAG_FE: Framing Error flag
- * @arg IRDA_FLAG_PE: Parity Error flag
+ * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref IRDA_FLAG_BUSY Busy flag
+ * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
+ * @arg @ref IRDA_FLAG_TC Transmission Complete flag
+ * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref IRDA_FLAG_ORE OverRun Error flag
+ * @arg @ref IRDA_FLAG_NE Noise Error flag
+ * @arg @ref IRDA_FLAG_FE Framing Error flag
+ * @arg @ref IRDA_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
@@ -499,91 +486,79 @@
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
+ * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __IT__: specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ORE: OverRun Error interrupt
- * @arg IRDA_IT_NE: Noise Error interrupt
- * @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ORE OverRun Error interrupt
+ * @arg @ref IRDA_IT_NE Noise Error interrupt
+ * @arg @ref IRDA_IT_FE Framing Error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
+#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __IT__: specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ORE: OverRun Error interrupt
- * @arg IRDA_IT_NE: Noise Error interrupt
- * @arg IRDA_IT_FE: Framing Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
+ * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref IRDA_IT_TC Transmission complete interrupt
+ * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref IRDA_IT_IDLE Idle line detection interrupt
+ * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
- * @arg IRDA_CLEAR_FEF: Framing Error Clear Flag
- * @arg IRDA_CLEAR_NEF: Noise detected Clear Flag
- * @arg IRDA_CLEAR_OREF: OverRun Error Clear Flag
- * @arg IRDA_CLEAR_TCF: Transmission Complete Clear Flag
+ * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -591,13 +566,11 @@
/** @brief Set a specific IRDA request flag.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
- * @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg IRDA_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
@@ -605,32 +578,24 @@
/** @brief Enable the IRDA one bit sample method.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @retval None
- */
+ */
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the IRDA one bit sample method.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @retval None
- */
+ */
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -648,13 +613,13 @@
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
/**
* @brief Ensure that IRDA frame parity is valid.
@@ -670,7 +635,7 @@
* @param __MODE__: IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that IRDA power mode is valid.
@@ -717,8 +682,8 @@
* @param __DMARX__: IRDA DMA RX mode.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
- ((__DMARX__) == IRDA_DMA_RX_ENABLE))
+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
+ ((__DMARX__) == IRDA_DMA_RX_ENABLE))
/**
* @brief Ensure that IRDA request is valid.
@@ -768,12 +733,23 @@
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
/**
* @}
@@ -804,6 +780,7 @@
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f3xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
- * @brief Header file of IRDA HAL Extension module.
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
@@ -50,8 +50,7 @@
* @{
*/
-/** @defgroup IRDAEx IRDAEx
- * @brief IRDA Extension HAL module driver.
+/** @addtogroup IRDAEx
* @{
*/
@@ -68,10 +67,10 @@
defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
#else
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F334x8 || */
@@ -83,7 +82,7 @@
/**
* @}
*/
-
+
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -100,7 +99,7 @@
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -211,10 +210,10 @@
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -249,7 +248,7 @@
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#else
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -320,7 +319,7 @@
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
@@ -331,74 +330,74 @@
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
- * @param __HANDLE__: specifies the IRDA Handle
- * @retval None, the mask to apply to IRDA RDR register is stored in (__HANDLE__)->Mask field.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
defined(STM32F334x8)
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU ; \
} \
} \
-} while(0)
+} while(0U)
#else
-#define IRDA_MASK_COMPUTATION(__HANDLE__) \
+#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
-} while(0)
+} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F334x8 */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -22,8 +22,8 @@
if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
- disabled. The counter starts counting down from the reset value (0xFFF).
- When it reaches the end of count value (0x000) a reset signal is
+ disabled. The counter starts counting down from the reset value (0xFFFU).
+ When it reaches the end of count value (0x000U) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
@@ -41,7 +41,7 @@
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
[..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F3xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
@@ -127,7 +127,7 @@
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to HSI variation, we need to wait at
+ higher prescaler (256U), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@@ -68,10 +68,10 @@
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFFU */
} IWDG_InitTypeDef;
@@ -103,8 +103,8 @@
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128U */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256U */
/**
* @}
*/
@@ -250,6 +250,6 @@
}
#endif
-#endif /* __STM32L4xx_HAL_IWDG_H */
+#endif /* __STM32F3xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_nand.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -340,8 +340,8 @@
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
- __IO uint32_t data = 0;
- uint32_t deviceaddress = 0;
+ __IO uint32_t data = 0U;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -395,7 +395,7 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -444,10 +444,10 @@
*/
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
- __IO uint32_t index = 0;
- uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
+ __IO uint32_t index = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ uint32_t addressoffset = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -477,7 +477,7 @@
nandaddress.Zone = pAddress->Zone;
/* Page(s) read loop */
- while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
@@ -494,7 +494,7 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr >= 1024U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
@@ -538,11 +538,11 @@
*/
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ uint32_t addressoffset = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -572,7 +572,7 @@
nandaddress.Zone = pAddress->Zone;
/* Page(s) write loop */
- while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
@@ -590,7 +590,7 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr >= 1024U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
@@ -645,10 +645,10 @@
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
- __IO uint32_t index = 0;
- uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
+ __IO uint32_t index = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ uint32_t addressoffset = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -678,7 +678,7 @@
nandaddress.Zone = pAddress->Zone;
/* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
@@ -695,7 +695,7 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr >= 1024U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
@@ -738,11 +738,11 @@
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ uint32_t addressoffset = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -772,7 +772,7 @@
nandaddress.Zone = pAddress->Zone;
/* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
@@ -790,7 +790,7 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr >= 1024U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
@@ -843,8 +843,8 @@
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t deviceaddress = 0;
- uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0U;
+ uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -876,7 +876,7 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
/* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ if(hnand->Info.BlockNbr >= 1024U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
}
@@ -915,8 +915,8 @@
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
- uint32_t data = 0;
- uint32_t deviceaddress = 0;
+ uint32_t data = 0U;
+ uint32_t deviceaddress = 0U;
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
@@ -966,12 +966,12 @@
/* Check NAND address is valid */
if(pAddress->Page == hnand->Info.BlockSize)
{
- pAddress->Page = 0;
+ pAddress->Page = 0U;
pAddress->Block++;
if(pAddress->Block == hnand->Info.ZoneSize)
{
- pAddress->Block = 0;
+ pAddress->Block = 0U;
pAddress->Zone++;
if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
@@ -1145,12 +1145,12 @@
if(Address->Page == hnand->Info.BlockSize)
{
- Address->Page = 0;
+ Address->Page = 0U;
Address->Block++;
if(Address->Block == hnand->Info.ZoneSize)
{
- Address->Block = 0;
+ Address->Block = 0U;
Address->Zone++;
if(Address->Zone == hnand->Info.BlockNbr)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_nand.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
@@ -61,32 +61,32 @@
#define NAND_DEVICE1 FMC_BANK2
#define NAND_DEVICE2 FMC_BANK3
-#define NAND_WRITE_TIMEOUT ((uint32_t)1000)
+#define NAND_WRITE_TIMEOUT (1000U)
-#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16U = CLE high */
+#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17U = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+#define NAND_CMD_AREA_A ((uint8_t)0x00U)
+#define NAND_CMD_AREA_B ((uint8_t)0x01U)
+#define NAND_CMD_AREA_C ((uint8_t)0x50U)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
+#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
+#define NAND_CMD_READID ((uint8_t)0x90U)
+#define NAND_CMD_STATUS ((uint8_t)0x70U)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
+#define NAND_CMD_RESET ((uint8_t)0xFFU)
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
-#define NAND_BUSY ((uint32_t)0x00000000)
-#define NAND_ERROR ((uint32_t)0x00000001)
-#define NAND_READY ((uint32_t)0x00000040)
+#define NAND_VALID_ADDRESS (0x00000100U)
+#define NAND_INVALID_ADDRESS (0x00000200U)
+#define NAND_TIMEOUT_ERROR (0x00000400U)
+#define NAND_BUSY (0x00000000U)
+#define NAND_ERROR (0x00000001U)
+#define NAND_READY (0x00000040U)
/**
* @}
@@ -111,9 +111,9 @@
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
/**
* @}
@@ -130,9 +130,9 @@
*/
typedef enum
{
- HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
}HAL_NAND_StateTypeDef;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_nor.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -330,7 +330,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -390,7 +390,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -440,7 +440,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -499,7 +499,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -560,7 +560,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -598,10 +598,10 @@
NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
/* Read buffer */
- while( uwBufferSize > 0)
+ while( uwBufferSize > 0U)
{
*pData++ = *(__IO uint16_t *)uwAddress;
- uwAddress += 2;
+ uwAddress += 2U;
uwBufferSize--;
}
@@ -632,7 +632,7 @@
{
uint16_t * p_currentaddress = (uint16_t *)NULL;
uint16_t * p_endaddress = (uint16_t *)NULL;
- uint32_t lastloadedaddress = 0, deviceaddress = 0;
+ uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -666,7 +666,7 @@
/* Initialize variables */
p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
- p_endaddress = p_currentaddress + (uwBufferSize-1);
+ p_endaddress = p_currentaddress + (uwBufferSize-1U);
lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
@@ -675,7 +675,7 @@
/* Write Buffer Load Command */
NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
+ NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
/* Load Data into NOR Buffer */
while(p_currentaddress <= p_endaddress)
@@ -710,7 +710,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -769,7 +769,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -827,7 +827,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -987,8 +987,8 @@
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
- uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
- uint32_t tickstart = 0;
+ uint16_t tmp_sr1 = 0U, tmp_sr2 = 0U;
+ uint32_t tickstart = 0U;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
HAL_NOR_MspWait(hnor, Timeout);
@@ -1000,7 +1000,7 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
status = HAL_NOR_STATUS_TIMEOUT;
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_nor.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
@@ -61,20 +61,20 @@
*/
/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
+#define MC_ADDRESS ((uint16_t)0x0000U)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x10)
-#define CFI2_ADDRESS ((uint16_t)0x11)
-#define CFI3_ADDRESS ((uint16_t)0x12)
-#define CFI4_ADDRESS ((uint16_t)0x13)
+#define CFI1_ADDRESS ((uint16_t)0x10U)
+#define CFI2_ADDRESS ((uint16_t)0x11U)
+#define CFI3_ADDRESS ((uint16_t)0x12U)
+#define CFI4_ADDRESS ((uint16_t)0x13U)
/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0)
-#define NOR_MEMORY_16B ((uint8_t)0x1)
+#define NOR_MEMORY_8B ((uint8_t)0x0U)
+#define NOR_MEMORY_16B ((uint8_t)0x1U)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 FMC_BANK1_1
@@ -99,7 +99,7 @@
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
@@ -124,10 +124,10 @@
*/
typedef enum
{
- HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
}HAL_NOR_StateTypeDef;
@@ -136,7 +136,7 @@
*/
typedef enum
{
- HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_opamp.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
@@ -37,7 +37,7 @@
handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
(++) HAL_OPAMP_SelfCalibrate:
(++) Runs automatically the calibration in 2 steps.
- (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
+ (90U% of VDDA for NMOS transistors, 10U% of VDDA for PMOS transistors).
(As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
appropriate and enough in most cases).
(++) Enables the user trimming mode
@@ -71,7 +71,7 @@
(Resistor feedback output)
(++) The OPAMP(s) output(s) can be internally connected to resistor feedback
output.
- (++) OPAMP gain is either 2, 4, 8 or 16.
+ (++) OPAMP gain is either 2U, 4U, 8 or 16.
##### How to use this driver #####
@@ -170,14 +170,14 @@
|-----------------|--------|--------|--------|--------|--------|
| | No conn| X | X | X | X |
| Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
- | (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
+ | (1U) | VM1 | PA3 | PA5 | PB2 | PD8 |
|-----------------|--------|--------|--------|--------|--------|
| | VP0 | PA1 | PA7 | PB0 | PB13 |
| Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
| Input | VP2 | PA3 | PB0 | PA1 | PA4 |
| | VP3 | PA5 | PB14 | PA5 | PB11 |
+--------------------------------------------------------------+
- (1): NA in follower mode.
+ (1U): NA in follower mode.
Table 2. OPAMPs outputs for the STM32F3 devices:
+--------------------------------------------------------------+
@@ -213,7 +213,7 @@
* @{
*/
/* CSR register reset value */
-#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
+#define OPAMP_CSR_RESET_VALUE (0x00000000U)
/**
* @}
*/
@@ -570,8 +570,8 @@
HAL_StatusTypeDef status = HAL_OK;
- uint32_t trimmingvaluen = 0;
- uint32_t trimmingvaluep = 0;
+ uint32_t trimmingvaluen = 0U;
+ uint32_t trimmingvaluep = 0U;
uint32_t delta;
/* Check the OPAMP handle allocation */
@@ -600,7 +600,7 @@
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
- /* Select 90% VREF */
+ /* Select 90U% VREF */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
/* Enable the selected opamp */
@@ -608,10 +608,10 @@
/* Init trimming counter */
/* Medium value */
- trimmingvaluen = 16;
- delta = 8;
+ trimmingvaluen = 16U;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen<<OPAMP_INPUT_INVERTING);
@@ -619,7 +619,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -632,7 +632,7 @@
trimmingvaluen -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
/* Still need to check if righ calibration is current value or un step below */
@@ -642,7 +642,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -653,15 +653,15 @@
}
/* 2nd calibration - P */
- /* Select 10% VREF */
+ /* Select 10U% VREF */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
/* Init trimming counter */
/* Medium value */
- trimmingvaluep = 16;
- delta = 8;
+ trimmingvaluep = 16U;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
@@ -669,7 +669,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -681,18 +681,18 @@
trimmingvaluep -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
/* Still need to check if righ calibration is current value or un step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
/* Set candidate trimming */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep<<OPAMP_INPUT_NONINVERTING);
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -842,8 +842,8 @@
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
{
- uint32_t oldusertrimming = 0;
- OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0, oldtrimmingvaluen = 0, trimmingvalue = 0;
+ uint32_t oldusertrimming = 0U;
+ OPAMP_TrimmingValueTypeDef oldtrimmingvaluep = 0U, oldtrimmingvaluen = 0U, trimmingvalue = 0U;
/* Check the OPAMP handle allocation */
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_opamp.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
@@ -113,7 +113,7 @@
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
i.e. when mode is OPAMP_PGA_MODE.
- This parameter must be a value of @ref OPAMP_PgaGain (2, 4, 8 or 16 ) */
+ This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */
uint32_t UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref OPAMP_UserTrimming
@@ -121,11 +121,11 @@
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
}OPAMP_InitTypeDef;
@@ -135,13 +135,13 @@
typedef enum
{
- HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPMAP is not yet Initialized */
+ HAL_OPAMP_STATE_RESET = 0x00000000U, /*!< OPMAP is not yet Initialized */
- HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
- HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
+ HAL_OPAMP_STATE_READY = 0x00000001U, /*!< OPAMP is initialized and ready for use */
+ HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
- HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
- HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005, /*!< OPAMP is locked
+ HAL_OPAMP_STATE_BUSY = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
+ HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U, /*!< OPAMP is locked
only system reset allows reconfiguring the opamp. */
}HAL_OPAMP_StateTypeDef;
@@ -189,7 +189,7 @@
/** @defgroup OPAMP_Mode OPAMP Mode
* @{
*/
-#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */
+#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< standalone mode */
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
@@ -208,7 +208,7 @@
#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
+#define OPAMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4)
connected to OPAMPx non inverting input */
@@ -228,7 +228,7 @@
* @{
*/
-#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< inverting input connected to VM0 */
+#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< inverting input connected to VM0 */
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
@@ -241,7 +241,7 @@
/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
* @{
*/
- #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE ((uint32_t)0x00000000) /*!< Timer controlled Mux mode disabled */
+ #define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U) /*!< Timer controlled Mux mode disabled */
#define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
@@ -256,7 +256,7 @@
#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
connected to OPAMPx non inverting input */
-#define OPAMP_SEC_NONINVERTINGINPUT_IO1 ((uint32_t)0x00000000) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+#define OPAMP_SEC_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
connected to OPAMPx non inverting input */
@@ -276,7 +276,7 @@
* @{
*/
-#define OPAMP_SEC_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000U) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
connected to OPAMPx inverting input */
#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
connected to OPAMPx inverting input */
@@ -292,7 +292,7 @@
* @{
*/
-#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the non inverting input is not connected */
+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000U) /*!< In PGA mode, the non inverting input is not connected */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
@@ -308,10 +308,10 @@
* @{
*/
-#define OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000) /*!< PGA gain = 2 */
-#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
-#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
-#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
+#define OPAMP_PGA_GAIN_2 (0x00000000U) /*!< PGA gain = 2U */
+#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4U */
+#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8U */
+#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16U */
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
((GAIN) == OPAMP_PGA_GAIN_4) || \
@@ -325,7 +325,7 @@
* @{
*/
-#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
@@ -335,10 +335,10 @@
* @{
*/
-#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFFU) /*!< Dummy trimming value */
+#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy trimming value */
-#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
-#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
+#define OPAMP_FACTORYTRIMMING_N (0x00000000U) /*!< Offset trimming N */
+#define OPAMP_FACTORYTRIMMING_P (0x00000001U) /*!< Offset trimming P */
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
@@ -352,7 +352,7 @@
* @{
*/
-#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
/**
@@ -364,8 +364,8 @@
* @{
*/
-#define OPAMP_INPUT_INVERTING ((uint32_t) 24) /*!< Inverting input */
-#define OPAMP_INPUT_NONINVERTING ((uint32_t) 19) /*!< Non inverting input */
+#define OPAMP_INPUT_INVERTING ( 24U) /*!< Inverting input */
+#define OPAMP_INPUT_NONINVERTING ( 19U) /*!< Non inverting input */
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
((INPUT) == OPAMP_INPUT_NONINVERTING))
@@ -378,10 +378,10 @@
* @{
*/
-#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
-#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
-#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
-#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
+#define OPAMP_VREF_3VDDA (0x00000000U) /*!< OPMAP Vref = 3.3U% VDDA */
+#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10U% VDDA */
+#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50U% VDDA */
+#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90U% VDDA */
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
((VREF) == OPAMP_VREF_10VDDA) || \
@@ -395,8 +395,8 @@
/** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
*/
-#define OPAMP_VREF_NOTCONNECTEDTO_ADC ((uint32_t)0x00000000) /*!< VREF not connected to ADC */
-#define OPAMP_VREF_CONNECTEDTO_ADC ((uint32_t)0x00000001) /*!< VREF not connected to ADC */
+#define OPAMP_VREF_NOTCONNECTEDTO_ADC (0x00000000U) /*!< VREF not connected to ADC */
+#define OPAMP_VREF_CONNECTEDTO_ADC (0x00000001U) /*!< VREF not connected to ADC */
#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_opamp_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended OPAMP HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -105,10 +105,10 @@
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t trimmingvaluen1 = 0;
- uint32_t trimmingvaluep1 = 0;
- uint32_t trimmingvaluen2 = 0;
- uint32_t trimmingvaluep2 = 0;
+ uint32_t trimmingvaluen1 = 0U;
+ uint32_t trimmingvaluep1 = 0U;
+ uint32_t trimmingvaluen2 = 0U;
+ uint32_t trimmingvaluep2 = 0U;
uint32_t delta;
@@ -141,7 +141,7 @@
SET_BIT (hopamp2->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
- /* Select 90% VREF */
+ /* Select 90U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
@@ -151,11 +151,11 @@
/* Init trimming counter */
/* Medium value */
- trimmingvaluen1 = 16;
- trimmingvaluen2 = 16;
- delta = 8;
+ trimmingvaluen1 = 16U;
+ trimmingvaluen2 = 16U;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
@@ -164,7 +164,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
{
@@ -188,7 +188,7 @@
trimmingvaluen2 -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
// Still need to check if righ calibration is current value or un step below
@@ -199,7 +199,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
{
@@ -218,17 +218,17 @@
}
/* 2nd calibration - P */
- /* Select 10% VREF */
+ /* Select 10U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
/* Init trimming counter */
/* Medium value */
- trimmingvaluep1 = 16;
- trimmingvaluep2 = 16;
- delta = 8;
+ trimmingvaluep1 = 16U;
+ trimmingvaluep2 = 16U;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
@@ -237,7 +237,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
{
@@ -259,7 +259,7 @@
trimmingvaluep2 -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
// Still need to check if righ calibration is current value or un step below
@@ -271,7 +271,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if (hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL)
{
@@ -362,14 +362,14 @@
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t trimmingvaluen1 = 0;
- uint32_t trimmingvaluep1 = 0;
- uint32_t trimmingvaluen2 = 0;
- uint32_t trimmingvaluep2 = 0;
- uint32_t trimmingvaluen3 = 0;
- uint32_t trimmingvaluep3 = 0;
- uint32_t trimmingvaluen4 = 0;
- uint32_t trimmingvaluep4 = 0;
+ uint32_t trimmingvaluen1 = 0U;
+ uint32_t trimmingvaluep1 = 0U;
+ uint32_t trimmingvaluen2 = 0U;
+ uint32_t trimmingvaluep2 = 0U;
+ uint32_t trimmingvaluen3 = 0U;
+ uint32_t trimmingvaluep3 = 0U;
+ uint32_t trimmingvaluen4 = 0U;
+ uint32_t trimmingvaluep4 = 0U;
uint32_t delta;
@@ -413,7 +413,7 @@
SET_BIT (hopamp4->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
- /* Select 90% VREF */
+ /* Select 90U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
@@ -427,13 +427,13 @@
/* Init trimming counter */
/* Medium value */
- trimmingvaluen1 = 16;
- trimmingvaluen2 = 16;
- trimmingvaluen3 = 16;
- trimmingvaluen4 = 16;
- delta = 8;
+ trimmingvaluen1 = 16U;
+ trimmingvaluen2 = 16U;
+ trimmingvaluen3 = 16U;
+ trimmingvaluen4 = 16U;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
@@ -444,7 +444,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -490,11 +490,11 @@
trimmingvaluen4 -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
/* Still need to check if righ calibration is current value or un step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1<<OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2<<OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3<<OPAMP_INPUT_INVERTING);
@@ -503,7 +503,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -538,7 +538,7 @@
}
/* 2nd calibration - P */
- /* Select 10% VREF */
+ /* Select 10U% VREF */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
@@ -546,14 +546,14 @@
/* Init trimming counter */
/* Medium value */
- trimmingvaluep1 = 16;
- trimmingvaluep2 = 16;
- trimmingvaluep3 = 16;
- trimmingvaluep4 = 16;
+ trimmingvaluep1 = 16U;
+ trimmingvaluep2 = 16U;
+ trimmingvaluep3 = 16U;
+ trimmingvaluep4 = 16U;
- delta = 8;
+ delta = 8U;
- while (delta != 0)
+ while (delta != 0U)
{
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
@@ -564,7 +564,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
@@ -606,11 +606,11 @@
trimmingvaluep4 -= delta;
}
- delta >>= 1;
+ delta >>= 1U;
}
/* Still need to check if righ calibration is current value or un step below */
- /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
+ /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1<<OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2<<OPAMP_INPUT_NONINVERTING);
@@ -620,7 +620,7 @@
/* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
- HAL_Delay(2);
+ HAL_Delay(2U);
if ((hopamp1->Instance->CSR & OPAMP_CSR_OUTCAL) != RESET)
{
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f3xx_hal_opamp_ex.h * @author MCD Application Team - * @version V1.3.0 - * @date 01-July-2016 + * @version V1.4.0 + * @date 16-December-2016 * @brief Header file of OPAMP HAL Extended module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pccard.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pccard.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -95,9 +95,9 @@
* @{
*/
-#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
+#define PCCARD_TIMEOUT_READ_ID 0x0000FFFF
+#define PCCARD_TIMEOUT_SECTOR 0x0000FFFF
+#define PCCARD_TIMEOUT_STATUS 0x01000000
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
@@ -264,8 +264,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -294,14 +294,14 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
/* Read CF ID bytes */
- for(index = 0; index < 16; index++)
+ for(index = 0U; index < 16U; index++)
{
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
@@ -327,8 +327,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -352,17 +352,17 @@
do
{
- /* wait till the Status = 0x80 */
+ /* wait till the Status = 0x80U */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status == 0x80) && timeout);
+ }while((status == 0x80U) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
- timeout = 0xFFFF;
+ timeout = 0xFFFFU;
do
{
@@ -371,7 +371,7 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -403,8 +403,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -433,7 +433,7 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -451,7 +451,7 @@
timeout--;
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -476,8 +476,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0x400;
- uint8_t status = 0;
+ uint32_t timeout = 0x400U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -511,7 +511,7 @@
timeout--;
}
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -543,10 +543,10 @@
}
/* Provide an SW reset and Read and verify the:
- - CF Configuration Option Register at address 0x98000200 --> 0x80
- - Card Configuration and Status Register at address 0x98000202 --> 0x00
- - Pin Replacement Register at address 0x98000204 --> 0x0C
- - Socket and Copy Register at address 0x98000206 --> 0x00
+ - CF Configuration Option Register at address 0x98000200U --> 0x80
+ - Card Configuration and Status Register at address 0x98000202U --> 0x00
+ - Pin Replacement Register at address 0x98000204U --> 0x0C
+ - Socket and Copy Register at address 0x98000206U --> 0x00
*/
/* Check the PCCARD controller state */
@@ -671,7 +671,7 @@
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0U;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
@@ -687,7 +687,7 @@
timeout--;
}
- if(timeout == 0)
+ if(timeout == 0U)
{
status_cf = PCCARD_TIMEOUT_ERROR;
}
@@ -707,7 +707,7 @@
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0, status_cf = PCCARD_BUSY;
+ uint8_t data = 0U, status_cf = PCCARD_BUSY;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pccard.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pccard.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
@@ -60,36 +60,36 @@
*/
#define PCCARD_DEVICE_ADDRESS FMC_BANK4
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
/* Compact Flash-ATA registers description */
-#define ATA_DATA ((uint8_t)0x00) /* Data register */
-#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
-#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
-#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
-#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
-#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
-#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
-#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
-#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
+#define ATA_DATA ((uint8_t)0x00U) /* Data register */
+#define ATA_SECTOR_COUNT ((uint8_t)0x02U) /* Sector Count register */
+#define ATA_SECTOR_NUMBER ((uint8_t)0x03U) /* Sector Number register */
+#define ATA_CYLINDER_LOW ((uint8_t)0x04U) /* Cylinder low register */
+#define ATA_CYLINDER_HIGH ((uint8_t)0x05U) /* Cylinder high register */
+#define ATA_CARD_HEAD ((uint8_t)0x06U) /* Card/Head register */
+#define ATA_STATUS_CMD ((uint8_t)0x07U) /* Status(read)/Command(write) register */
+#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0EU) /* Alternate Status(read)/Command(write) register */
+#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400U) /* Start of data area (for Common access only!) */
+#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202U) /* Card Configuration and Status Register */
/* Compact Flash-ATA commands */
-#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
-#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
-#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
-#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
+#define ATA_READ_SECTOR_CMD ((uint8_t)0x20U)
+#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30U)
+#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0U)
+#define ATA_IDENTIFY_CMD ((uint8_t)0xECU)
/* Compact Flash status */
-#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
-#define PCCARD_BUSY ((uint8_t)0x80)
-#define PCCARD_PROGR ((uint8_t)0x01)
-#define PCCARD_READY ((uint8_t)0x40)
+#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60U)
+#define PCCARD_BUSY ((uint8_t)0x80U)
+#define PCCARD_PROGR ((uint8_t)0x01U)
+#define PCCARD_READY ((uint8_t)0x40U)
-#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+#define PCCARD_SECTOR_SIZE (255U) /* In half words */
/* Compact Flash redefinition */
@@ -136,15 +136,15 @@
*/
typedef enum
{
- HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
- HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
- HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
}HAL_PCCARD_StateTypeDef;
typedef enum
{
- HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_SUCCESS = 0U,
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -96,7 +96,7 @@
/** @defgroup PCD_Private_Define PCD Private Define
* @{
*/
-#define BTABLE_ADDRESS (0x000)
+#define BTABLE_ADDRESS (0x000U)
/**
* @}
*/
@@ -139,9 +139,9 @@
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
- uint32_t i = 0;
+ uint32_t i = 0U;
- uint32_t wInterrupt_Mask = 0;
+ uint32_t wInterrupt_Mask = 0U;
/* Check the PCD handle allocation */
if(hpcd == NULL)
@@ -165,50 +165,50 @@
hpcd->State = HAL_PCD_STATE_BUSY;
/* Init endpoints structures */
- for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
{
/* Init ep structure */
- hpcd->IN_ep[i].is_in = 1;
+ hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
/* Control until ep is actvated */
hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0;
- hpcd->IN_ep[i].xfer_buff = 0;
- hpcd->IN_ep[i].xfer_len = 0;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
}
- for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
+ for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
{
- hpcd->OUT_ep[i].is_in = 0;
+ hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
/* Control until ep is activated */
hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0;
- hpcd->OUT_ep[i].xfer_buff = 0;
- hpcd->OUT_ep[i].xfer_len = 0;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
}
/* Init Device */
- /*CNTR_FRES = 1*/
+ /*CNTR_FRES = 1U*/
hpcd->Instance->CNTR = USB_CNTR_FRES;
- /*CNTR_FRES = 0*/
- hpcd->Instance->CNTR = 0;
+ /*CNTR_FRES = 0U*/
+ hpcd->Instance->CNTR = 0U;
/*Clear pending interrupts*/
- hpcd->Instance->ISTR = 0;
+ hpcd->Instance->ISTR = 0U;
/*Set Btable Adress*/
hpcd->Instance->BTABLE = BTABLE_ADDRESS;
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+ | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
/*Set interrupt mask*/
hpcd->Instance->CNTR = wInterrupt_Mask;
- hpcd->USB_Address = 0;
+ hpcd->USB_Address = 0U;
hpcd->State= HAL_PCD_STATE_READY;
return HAL_OK;
@@ -297,7 +297,7 @@
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
/* DP Pull-Down is external */
- HAL_PCDEx_SetConnectionState (hpcd, 1);
+ HAL_PCDEx_SetConnectionState (hpcd, 1U);
return HAL_OK;
}
@@ -315,7 +315,7 @@
hpcd->Instance->CNTR = USB_CNTR_FRES;
/* clear interrupt status register */
- hpcd->Instance->ISTR = 0;
+ hpcd->Instance->ISTR = 0U;
/* switch-off device */
hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
@@ -342,28 +342,28 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count=0;
+ uint16_t count=0U;
uint8_t EPindex;
__IO uint16_t wIstr;
- __IO uint16_t wEPVal = 0;
+ __IO uint16_t wEPVal = 0U;
/* stay in loop while pending interrupts */
- while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
+ while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
{
/* extract highest priority endpoint number */
EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
- if (EPindex == 0)
+ if (EPindex == 0U)
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
- if ((wIstr & USB_ISTR_DIR) == 0)
+ if ((wIstr & USB_ISTR_DIR) == 0U)
{
- /* DIR = 0 */
+ /* DIR = 0U */
/* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
+ /* DIR = 0 implies that (EP_CTR_TX = 1U) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
ep = &hpcd->IN_ep[0];
@@ -371,54 +371,54 @@
ep->xfer_buff += ep->xfer_count;
/* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, 0);
+ HAL_PCD_DataInStageCallback(hpcd, 0U);
- if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
{
hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0;
+ hpcd->USB_Address = 0U;
}
}
else
{
- /* DIR = 1 */
+ /* DIR = 1U */
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
- /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+ /* DIR = 1U & CTR_RX => SETUP or OUT int */
+ /* DIR = 1U & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
- if ((wEPVal & USB_EP_SETUP) != 0)
+ if ((wEPVal & USB_EP_SETUP) != 0U)
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
+ /* SETUP bit kept frozen while CTR_RX = 1U*/
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Process SETUP Packet*/
HAL_PCD_SetupStageCallback(hpcd);
}
- else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
ep->xfer_buff+=ep->xfer_count;
}
/* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0);
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
}
}
}
@@ -429,28 +429,28 @@
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
- if ((wEPVal & USB_EP_CTR_RX) != 0)
+ if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
ep = &hpcd->OUT_ep[EPindex];
/* OUT double Buffering*/
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
else
{
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
{
/*read from endpoint BUF0Addr buffer*/
count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
@@ -459,18 +459,18 @@
{
/*read from endpoint BUF1Addr buffer*/
count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
}
/*multi-packet on the NON control OUT endpoint*/
ep->xfer_count+=count;
ep->xfer_buff+=count;
- if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
{
/* RX COMPLETE */
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
@@ -482,7 +482,7 @@
} /* if((wEPVal & EP_CTR_RX) */
- if ((wEPVal & USB_EP_CTR_TX) != 0)
+ if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
ep = &hpcd->IN_ep[EPindex];
@@ -490,21 +490,21 @@
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
/* IN double Buffering*/
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
}
}
else
{
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{
/*read from endpoint BUF0Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
}
@@ -513,19 +513,19 @@
{
/*read from endpoint BUF1Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
}
}
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
}
/*multi-packet on the NON control IN endpoint*/
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
ep->xfer_buff+=ep->xfer_count;
/* Zero Length Packet? */
- if (ep->xfer_len == 0)
+ if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
HAL_PCD_DataInStageCallback(hpcd, ep->num);
@@ -558,7 +558,7 @@
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- uint32_t wInterrupt_Mask = 0;
+ uint32_t wInterrupt_Mask = 0U;
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
{
@@ -571,7 +571,7 @@
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
HAL_PCD_ResetCallback(hpcd);
- HAL_PCD_SetAddress(hpcd, 0);
+ HAL_PCD_SetAddress(hpcd, 0U);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
@@ -585,7 +585,7 @@
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
{
- hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE));
/*set wInterrupt_Mask global variable*/
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
@@ -607,7 +607,7 @@
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
{
HAL_PCD_SuspendCallback(hpcd);
}
@@ -826,7 +826,7 @@
__HAL_LOCK(hpcd);
/* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
- HAL_PCDEx_SetConnectionState(hpcd, 1);
+ HAL_PCDEx_SetConnectionState(hpcd, 1U);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -842,7 +842,7 @@
__HAL_LOCK(hpcd);
/* Disable DP Pull-Down bit*/
- HAL_PCDEx_SetConnectionState(hpcd, 0);
+ HAL_PCDEx_SetConnectionState(hpcd, 0U);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -858,7 +858,7 @@
{
__HAL_LOCK(hpcd);
- if(address == 0)
+ if(address == 0U)
{
/* set device address and enable function */
hpcd->Instance->DADDR = USB_DADDR_EF;
@@ -884,17 +884,17 @@
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
}
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & 0x7FU;
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->is_in = (0x80U & ep_addr) != 0U;
ep->maxpacket = ep_mps;
ep->type = ep_type;
@@ -915,29 +915,31 @@
case PCD_EP_TYPE_ISOC:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
break;
+ default:
+ break;
}
PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
if (ep->is_in)
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Configure NAK status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
}
else
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
/* Configure VALID status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
}
}
/*Double Buffer*/
@@ -946,29 +948,29 @@
/*Set the endpoint as double buffered*/
PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
/*Set buffer address for double buffered mode*/
- PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+ PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
- if (ep->is_in==0)
+ if (ep->is_in==0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
@@ -987,7 +989,7 @@
{
PCD_EPTypeDef *ep;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
@@ -995,51 +997,51 @@
{
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & 0x7FU;
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->is_in = (0x80U & ep_addr) != 0U;
__HAL_LOCK(hpcd);
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
if (ep->is_in)
{
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
/* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
/*Double Buffer*/
else
{
- if (ep->is_in==0)
+ if (ep->is_in==0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
}
}
@@ -1066,9 +1068,9 @@
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 0;
- ep->num = ep_addr & 0x7F;
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
@@ -1081,22 +1083,22 @@
else
{
len=ep->xfer_len;
- ep->xfer_len =0;
+ ep->xfer_len =0U;
}
/* configure and validate Rx endpoint */
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
/*Set RX buffer count*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
+ PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
}
else
{
/*Set the Double buffer counter*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
}
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
__HAL_UNLOCK(hpcd);
@@ -1124,16 +1126,16 @@
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
- uint16_t pmabuffer = 0;
+ uint16_t pmabuffer = 0U;
ep = &hpcd->IN_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 1;
- ep->num = ep_addr & 0x7F;
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & 0x7FU;
__HAL_LOCK(hpcd);
@@ -1146,11 +1148,11 @@
else
{
len=ep->xfer_len;
- ep->xfer_len =0;
+ ep->xfer_len =0U;
}
/* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
@@ -1158,7 +1160,7 @@
else
{
/*Write the data to the USB endpoint*/
- if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
{
pmabuffer = ep->pmaaddr1;
}
@@ -1167,10 +1169,10 @@
pmabuffer = ep->pmaaddr0;
}
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
}
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
__HAL_UNLOCK(hpcd);
@@ -1189,7 +1191,7 @@
__HAL_LOCK(hpcd);
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
@@ -1198,24 +1200,24 @@
ep = &hpcd->OUT_ep[ep_addr];
}
- ep->is_stall = 1;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
+ ep->is_stall = 1U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
- if (ep->num == 0)
+ if (ep->num == 0U)
{
/* This macro sets STALL status for RX & TX*/
- PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
+ PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
}
else
{
if (ep->is_in)
{
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL);
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
}
else
{
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
}
}
__HAL_UNLOCK(hpcd);
@@ -1233,7 +1235,7 @@
{
PCD_EPTypeDef *ep;
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
@@ -1242,21 +1244,21 @@
ep = &hpcd->OUT_ep[ep_addr];
}
- ep->is_stall = 0;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
+ ep->is_stall = 0U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
if (ep->is_in)
{
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+ PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
}
else
{
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+ PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
}
__HAL_UNLOCK(hpcd);
@@ -1292,7 +1294,7 @@
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
+ hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME);
return HAL_OK;
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@@ -69,11 +69,11 @@
*/
typedef enum
{
- HAL_PCD_STATE_RESET = 0x00,
- HAL_PCD_STATE_READY = 0x01,
- HAL_PCD_STATE_ERROR = 0x02,
- HAL_PCD_STATE_BUSY = 0x03,
- HAL_PCD_STATE_TIMEOUT = 0x04
+ HAL_PCD_STATE_RESET = 0x00U,
+ HAL_PCD_STATE_READY = 0x01U,
+ HAL_PCD_STATE_ERROR = 0x02U,
+ HAL_PCD_STATE_BUSY = 0x03U,
+ HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
/**
@@ -209,8 +209,8 @@
/** @defgroup PCD_Core_Speed PCD Core Speed
* @{
*/
-#define PCD_SPEED_HIGH 0 /* Not Supported */
-#define PCD_SPEED_FULL 2
+#define PCD_SPEED_HIGH 0U /* Not Supported */
+#define PCD_SPEED_FULL 2U
/**
* @}
*/
@@ -218,7 +218,7 @@
/** @defgroup PCD_Core_PHY PCD Core PHY
* @{
*/
-#define PCD_PHY_EMBEDDED 2
+#define PCD_PHY_EMBEDDED 2U
/**
* @}
*/
@@ -232,7 +232,7 @@
* @{
*/
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
@@ -244,19 +244,19 @@
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
- } while(0)
+ } while(0U)
#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);\
EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
- } while(0)
+ } while(0U)
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE);\
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;\
- } while(0)
+ } while(0U)
/**
* @}
*/
@@ -351,10 +351,10 @@
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
-#define DEP0CTL_MPS_64 0
-#define DEP0CTL_MPS_32 1
-#define DEP0CTL_MPS_16 2
-#define DEP0CTL_MPS_8 3
+#define DEP0CTL_MPS_64 0U
+#define DEP0CTL_MPS_32 1U
+#define DEP0CTL_MPS_16 2U
+#define DEP0CTL_MPS_8 3U
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
@@ -367,10 +367,10 @@
/** @defgroup PCD_EP_Type PCD EP Type
* @{
*/
-#define PCD_EP_TYPE_CTRL 0
-#define PCD_EP_TYPE_ISOC 1
-#define PCD_EP_TYPE_BULK 2
-#define PCD_EP_TYPE_INTR 3
+#define PCD_EP_TYPE_CTRL 0U
+#define PCD_EP_TYPE_ISOC 1U
+#define PCD_EP_TYPE_BULK 2U
+#define PCD_EP_TYPE_INTR 3U
/**
* @}
*/
@@ -378,14 +378,14 @@
/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
-#define PCD_ENDP0 ((uint8_t)0)
-#define PCD_ENDP1 ((uint8_t)1)
-#define PCD_ENDP2 ((uint8_t)2)
-#define PCD_ENDP3 ((uint8_t)3)
-#define PCD_ENDP4 ((uint8_t)4)
-#define PCD_ENDP5 ((uint8_t)5)
-#define PCD_ENDP6 ((uint8_t)6)
-#define PCD_ENDP7 ((uint8_t)7)
+#define PCD_ENDP0 ((uint8_t)0U)
+#define PCD_ENDP1 ((uint8_t)1U)
+#define PCD_ENDP2 ((uint8_t)2U)
+#define PCD_ENDP3 ((uint8_t)3U)
+#define PCD_ENDP4 ((uint8_t)4U)
+#define PCD_ENDP5 ((uint8_t)5U)
+#define PCD_ENDP6 ((uint8_t)6U)
+#define PCD_ENDP7 ((uint8_t)7U)
/**
* @}
*/
@@ -393,8 +393,8 @@
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
-#define PCD_SNG_BUF 0
-#define PCD_DBL_BUF 1
+#define PCD_SNG_BUF 0U
+#define PCD_DBL_BUF 1U
/**
* @}
*/
@@ -410,10 +410,10 @@
*/
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
@@ -425,7 +425,7 @@
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+ ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -433,7 +433,7 @@
* @param bEpNum: Endpoint Number.
* @retval Endpoint Type
*/
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
/**
@@ -465,9 +465,9 @@
*/
#define PCD_GET_DB_DIR(USBx, bEpNum)\
{\
- if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
+ if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
return(PCD_EP_DBUF_OUT);\
- else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
+ else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
return(PCD_EP_DBUF_IN);\
else\
return(PCD_EP_DBUF_ERR);\
@@ -480,17 +480,20 @@
* @param wState: new state
* @retval None
*/
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) {\
- register uint16_t _wRegVal; \
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
\
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+ _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
/* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wState))!= 0) \
- _wRegVal ^= USB_EPTX_DTOG1; \
+ if((USB_EPTX_DTOG1 & (wState))!= 0U)\
+ { \
+ _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
+ } \
/* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wState))!= 0) \
- _wRegVal ^= USB_EPTX_DTOG2; \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
+ { \
+ _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
} /* PCD_SET_EP_TX_STATUS */
/**
@@ -503,14 +506,18 @@
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
register uint16_t _wRegVal; \
\
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+ _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
/* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & (wState))!= 0) \
- _wRegVal ^= USB_EPRX_DTOG1; \
+ if((USB_EPRX_DTOG1 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
+ } \
/* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wState))!= 0) \
- _wRegVal ^= USB_EPRX_DTOG2; \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+ if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
+ { \
+ _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} /* PCD_SET_EP_RX_STATUS */
/**
@@ -526,17 +533,25 @@
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
/* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
+ { \
_wRegVal ^= USB_EPRX_DTOG1; \
+ } \
/* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
+ { \
_wRegVal ^= USB_EPRX_DTOG2; \
+ } \
/* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG1; \
+ } \
/* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
+ { \
_wRegVal ^= USB_EPTX_DTOG2; \
+ } \
PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
} /* PCD_SET_EP_TXRX_STATUS */
@@ -547,9 +562,8 @@
* @param bEpNum: Endpoint Number.
* @retval status
*/
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
@@ -579,9 +593,9 @@
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+ (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
@@ -608,9 +622,9 @@
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -619,20 +633,24 @@
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+ USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx: USB peripheral instance register address.
* @param bEpNum: Endpoint Number.
* @retval None
- */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
- PCD_RX_DTOG((USBx), (bEpNum))
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
- PCD_TX_DTOG((USBx), (bEpNum))
+ */
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
+ { \
+ PCD_RX_DTOG((USBx),(bEpNum));\
+ }
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
+ {\
+ PCD_TX_DTOG((USBx),(bEpNum));\
+ }
/**
* @brief Sets address in an endpoint register.
@@ -642,7 +660,7 @@
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
- USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+ USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
/**
* @brief Gets address in an endpoint register.
@@ -659,8 +677,8 @@
* @param wAddr: address to be set (must be word aligned).
* @retval None
*/
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
/**
* @brief Gets address of the tx/rx buffer.
@@ -679,29 +697,41 @@
* @retval None
*/
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 5;\
- if(((wCount) & 0x1f) == 0)\
+ (wNBlocks) = (wCount) >> 5U;\
+ if(((wCount) & 0x1fU) == 0U)\
+ { \
(wNBlocks)--;\
- *pdwReg = (uint16_t)(((wNBlocks) << 10) | 0x8000);\
+ } \
+ *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
}/* PCD_CALC_BLK32 */
+
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 1;\
- if(((wCount) & 0x1) != 0)\
+ (wNBlocks) = (wCount) >> 1U;\
+ if(((wCount) & 0x1U) != 0U)\
+ { \
(wNBlocks)++;\
- *pdwReg = (uint16_t)((wNBlocks) << 10);\
+ } \
+ *pdwReg = (uint16_t)((wNBlocks) << 10U);\
}/* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
uint16_t wNBlocks;\
- if((wCount) > 62){PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);}\
- else {PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);}\
+ if((wCount) > 62U) \
+ { \
+ PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
+ } \
}/* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
- uint32_t *pdwReg = PCD_EP_TX_CNT(USBx, bEpNum); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
}
+
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx: USB peripheral instance register address.
@@ -717,8 +747,8 @@
* @param bEpNum: Endpoint Number.
* @retval Counter value
*/
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
@@ -727,8 +757,8 @@
* @param wBuf0Addr: buffer 0 address.
* @retval Counter value
*/
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
/**
* @brief Sets addresses in a double buffer endpoint.
@@ -764,25 +794,28 @@
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
if((bDir) == PCD_EP_DBUF_OUT)\
/* OUT endpoint */ \
- {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+ {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
else if((bDir) == PCD_EP_DBUF_IN)\
- /* IN endpoint */ \
+ { \
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+ } \
} /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
if((bDir) == PCD_EP_DBUF_OUT)\
- /* OUT endpoint */ \
- {PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));}\
+ {/* OUT endpoint */ \
+ PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
+ } \
else if((bDir) == PCD_EP_DBUF_IN)\
- /* IN endpoint */\
+ {/* IN endpoint */ \
*PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } /* SetEPDblBuf1Count */
+ } \
+ } /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
- PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- } /* PCD_SET_EP_DBUF_CNT */
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
+ } /
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -109,9 +109,9 @@
PCD_EPTypeDef *ep;
/* initialize ep structure*/
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
@@ -122,7 +122,7 @@
if (ep_kind == PCD_SNG_BUF)
{
/*Single Buffer*/
- ep->doublebuffer = 0;
+ ep->doublebuffer = 0U;
/*Configure the PMA*/
ep->pmaadress = (uint16_t)pmaadress;
}
@@ -131,8 +131,8 @@
/*Double Buffer Endpoint*/
ep->doublebuffer = 1;
/*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0xFFFF;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16;
+ ep->pmaaddr0 = pmaadress & 0xFFFFU;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
}
return HAL_OK;
@@ -164,15 +164,17 @@
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+
uint32_t i, temp1, temp2;
uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+
for (i = n; i != 0; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
- temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
*pdwVal++ = temp2;
pdwVal++;
pbUsrBuf++;
@@ -189,13 +191,19 @@
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = (wNBytes + 1) >> 1;/* /2*/
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i;
uint32_t *pdwVal;
- pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+
+ pdwVal = (uint32_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+ uint32_t tmp = *pdwVal++;
+ *pbUsrBuf++ = (uint16_t)((tmp >> 0) & 0xFF);
+ *pbUsrBuf++ = (uint16_t)((tmp >> 8) & 0xFF);
+
+
for (i = n; i != 0; i--)
{
- *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
pbUsrBuf++;
}
}
@@ -216,17 +224,16 @@
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i;
uint16_t temp1, temp2;
uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
-
- for (i = n; i != 0; i--)
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+ for (i = n; i != 0U; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
- temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
*pdwVal++ = temp2;
pbUsrBuf++;
}
@@ -242,13 +249,13 @@
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = (wNBytes + 1) >> 1;
+ uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i;
uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400);
- for (i = n; i != 0; i--)
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+ for (i = n; i != 0U; i--)
{
- *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
pbUsrBuf++;
}
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
@@ -75,15 +75,16 @@
#if defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F373xC)
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8)*2+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+2)*2+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+4)*2+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)((USBx->BTABLE+bEpNum*8+6)*2+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
+
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint32_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
- }
+ uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
+ PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
+ }
#endif /* STM32F302xC || STM32F303xC || */
/* STM32F373xC */
@@ -92,14 +93,14 @@
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302x8)
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8)+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+2)+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+4)+ ((uint32_t)USBx + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((USBx->BTABLE+bEpNum*8+6)+ ((uint32_t)USBx + 0x400)))
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg = PCD_EP_RX_CNT(USBx, bEpNum); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, wCount);\
+ uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\
+ PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
}
#endif /* STM32F302xE || STM32F303xE || */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -243,7 +243,7 @@
(+) Comparator auto-wakeup (AWU) from the Stop mode
(++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
- (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2)
+ (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
to be sensitive to to the selected edges (falling, rising or falling
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
(+++) Configure the comparator to generate the event.
@@ -255,7 +255,7 @@
* @brief Enables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be value of :
- * @ref PWREx_WakeUp_Pins
+ * @ref PWR_WakeUp_Pins
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
@@ -270,7 +270,7 @@
* @brief Disables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be values of :
- * @ref PWREx_WakeUp_Pins
+ * @ref PWR_WakeUp_Pins
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
@@ -342,7 +342,7 @@
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
@@ -64,9 +64,9 @@
* @{
*/
-#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1 */
-#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2 */
-#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3 */
+#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */
+#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */
+#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */
/**
* @}
*/
@@ -74,7 +74,7 @@
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
* @{
*/
-#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Voltage regulator on during STOP mode */
+#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */
/**
* @}
@@ -83,8 +83,8 @@
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter SLEEP mode */
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter SLEEP mode */
+#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */
+#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */
/**
* @}
*/
@@ -92,8 +92,8 @@
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter STOP mode */
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter STOP mode */
+#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */
+#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */
/**
* @}
*/
@@ -144,7 +144,7 @@
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
*/
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -59,10 +59,10 @@
/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
* @{
*/
-#define PVD_MODE_IT ((uint32_t)0x00010000)
-#define PVD_MODE_EVT ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+#define PVD_MODE_IT (0x00010000U)
+#define PVD_MODE_EVT (0x00020000U)
+#define PVD_RISING_EDGE (0x00000001U)
+#define PVD_FALLING_EDGE (0x00000002U)
/**
* @}
*/
@@ -109,7 +109,7 @@
In Stop mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the
- microcontroller must be powered from a nominal VDD = 1.8V +/-8% voltage.
+ microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage.
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pwr_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
@@ -114,13 +114,13 @@
/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
* @{
*/
-#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
-#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@@ -137,9 +137,9 @@
/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
* @{
*/
-#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_SDADC1EN) /*!< Enable SDADC1 */
-#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_SDADC2EN) /*!< Enable SDADC2 */
-#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_SDADC3EN) /*!< Enable SDADC3 */
+#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */
+#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */
+#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -120,10 +120,10 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
-const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
- 10, 11, 12, 13, 14, 15, 16, 16};
-const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
- 9,10, 11, 12, 13, 14, 15, 16};
+const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
+ 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
+const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
+ 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};
/**
* @}
*/
@@ -752,7 +752,7 @@
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
}
/* Update the SystemCoreClock global variable */
@@ -913,8 +913,8 @@
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
- uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
- uint32_t sysclockfreq = 0;
+ uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
+ uint32_t sysclockfreq = 0U;
tmpreg = RCC->CFGR;
@@ -939,7 +939,7 @@
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (HSI_VALUE >> 1) * pllmul;
+ pllclk = (HSI_VALUE >> 1U) * pllmul;
}
#else
if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
@@ -1118,7 +1118,7 @@
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
/* Get the APB2 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -68,9 +68,9 @@
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
+#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
+#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
/**
* @}
*/
@@ -102,63 +102,63 @@
/* --- CR Register ---*/
/* Alias word address of HSION bit */
#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
/* Alias word address of HSEON bit */
#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
/* Alias word address of CSSON bit */
#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
/* Alias word address of PLLON bit */
#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
/* --- CSR Register ---*/
/* Alias word address of LSION bit */
#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
/* Alias word address of RMVF bit */
#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
/* --- BDCR Registers ---*/
/* Alias word address of LSEON bit */
#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
+#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
/* Alias word address of LSEON bit */
#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
+#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
/* Alias word address of RTCEN bit */
#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
/* Alias word address of BDRST bit */
#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
/**
* @}
*/
/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1)
-#define BDCR_REG_INDEX ((uint8_t)2)
-#define CSR_REG_INDEX ((uint8_t)3)
-#define CFGR_REG_INDEX ((uint8_t)4)
+#define CR_REG_INDEX ((uint8_t)1U)
+#define BDCR_REG_INDEX ((uint8_t)2U)
+#define CSR_REG_INDEX ((uint8_t)3U)
+#define CFGR_REG_INDEX ((uint8_t)4U)
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
+#define RCC_FLAG_MASK ((uint8_t)0x1FU)
/**
* @}
@@ -179,7 +179,7 @@
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
@@ -307,7 +307,7 @@
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
@@ -365,11 +365,11 @@
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
-#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
/**
* @}
*/
@@ -377,7 +377,7 @@
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
-#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
/**
@@ -387,7 +387,7 @@
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
-#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
+#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
@@ -398,10 +398,10 @@
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
-#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
/**
* @}
@@ -410,7 +410,7 @@
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
-#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
/**
@@ -420,9 +420,9 @@
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
-#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
-#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
-#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
+#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
+#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
/**
* @}
@@ -431,10 +431,10 @@
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
/**
* @}
@@ -620,7 +620,7 @@
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
-#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO1 (0x00000000U)
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
/**
@@ -651,29 +651,29 @@
* @{
*/
/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
#if defined(RCC_CSR_V18PWRRSTF)
-#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
+#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF)))
#endif
-#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
/* Flags in the CFGR register */
#if defined(RCC_CFGR_MCOF)
-#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
+#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */
#endif /* RCC_CFGR_MCOF */
/**
@@ -703,70 +703,70 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TSC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
@@ -795,56 +795,56 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
@@ -871,35 +871,35 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
@@ -1167,7 +1167,7 @@
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1215,7 +1215,7 @@
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1679,10 +1679,10 @@
@endif
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX) ? RCC->CR : \
- (((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
- (((__FLAG__) >> 5) == CFGR_REG_INDEX)? RCC->CFGR : \
- RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
+ (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
+ (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \
+ RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
/**
* @}
@@ -1720,6 +1720,10 @@
/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
void HAL_RCC_DisableCSS(void);
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
@@ -1728,12 +1732,6 @@
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -120,8 +120,8 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t tickstart = 0;
- uint32_t temp_reg = 0;
+ uint32_t tickstart = 0U;
+ uint32_t temp_reg = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
@@ -959,14 +959,14 @@
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
- uint32_t frequency = 0;
- uint32_t srcclk = 0;
+ uint32_t frequency = 0U;
+ uint32_t srcclk = 0U;
#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
- uint16_t adc_pll_prediv_table[12] = { 1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256};
+ uint16_t adc_pll_prediv_table[12] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
-#if defined(RCC_CFGR_SDADCPRE)
- uint8_t sdadc_prescaler_table[16] = { 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32, 36, 40, 44, 48};
-#endif /* RCC_CFGR_SDADCPRE */
+#if defined(RCC_CFGR_SDPRE)
+ uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
+#endif /* RCC_CFGR_SDPRE */
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
@@ -991,12 +991,12 @@
/* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
{
- frequency = HSE_VALUE / 32;
+ frequency = HSE_VALUE / 32U;
}
/* Clock not enabled for RTC*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1035,7 +1035,7 @@
/* Clock not enabled for USART1*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1068,7 +1068,7 @@
/* Clock not enabled for USART2*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1102,7 +1102,7 @@
/* Clock not enabled for USART3*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1136,7 +1136,7 @@
/* Clock not enabled for UART4*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1170,7 +1170,7 @@
/* Clock not enabled for UART5*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1193,7 +1193,7 @@
/* Clock not enabled for I2C1*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1216,7 +1216,7 @@
/* Clock not enabled for I2C2*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1240,7 +1240,7 @@
/* Clock not enabled for I2C3*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1265,7 +1265,7 @@
/* Clock not enabled for I2S*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1287,13 +1287,13 @@
/* Check if USB clock selection is divided by 1.5 */
else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */
{
- frequency = (RCC_GetPLLCLKFreq() * 3) / 2;
+ frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
}
}
/* Clock not enabled for USB*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1315,18 +1315,18 @@
/* Check if PLL is ready */
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
- /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
- frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xF];
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
+ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
}
/* Clock not enabled for ADC1*/
else
{
- frequency = 0;
+ frequency = 0U;
}
}
#else /* RCC_CFGR_ADCPRE */
- /* ADC1 is set to PLCK2 frequency divided by 2/4/6/8 */
- frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1) * 2);
+ /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
+ frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U);
#endif /* RCC_CFGR2_ADC1PRES */
break;
}
@@ -1347,13 +1347,13 @@
/* Check if PLL is ready */
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
- /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
}
/* Clock not enabled for ADC12*/
else
{
- frequency = 0;
+ frequency = 0U;
}
}
break;
@@ -1375,13 +1375,13 @@
/* Check if PLL is ready */
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))
{
- /* Frequency is the PLL frequency divided by ADC prescaler (1/2/4/6/8/10/12/16/32/64/128/256) */
+ /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
}
/* Clock not enabled for ADC34*/
else
{
- frequency = 0;
+ frequency = 0U;
}
}
break;
@@ -1406,7 +1406,7 @@
/* Clock not enabled for TIM1*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1430,7 +1430,7 @@
/* Clock not enabled for TIM2*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1454,7 +1454,7 @@
/* Clock not enabled for TIM8*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1478,7 +1478,7 @@
/* Clock not enabled for TIM15*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1502,7 +1502,7 @@
/* Clock not enabled for TIM16*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1526,7 +1526,7 @@
/* Clock not enabled for TIM17*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1550,7 +1550,7 @@
/* Clock not enabled for TIM20*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1574,7 +1574,7 @@
/* Clock not enabled for TIM34*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1598,21 +1598,21 @@
/* Clock not enabled for HRTIM1*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
#endif /* RCC_CFGR3_HRTIM1SW */
-#if defined(RCC_CFGR_SDADCPRE)
+#if defined(RCC_CFGR_SDPRE)
case RCC_PERIPHCLK_SDADC:
{
/* Get the current SDADC source */
srcclk = __HAL_RCC_GET_SDADC_SOURCE();
- /* Frequency is the system frequency divided by SDADC prescaler (2/4/6/8/10/12/14/16/20/24/28/32/36/40/44/48) */
- frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDADCPRE)) & 0xF];
+ /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */
+ frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF];
break;
}
-#endif /* RCC_CFGR_SDADCPRE */
+#endif /* RCC_CFGR_SDPRE */
#if defined(RCC_CFGR3_CECSW)
case RCC_PERIPHCLK_CEC:
{
@@ -1632,7 +1632,7 @@
/* Clock not enabled for CEC*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
@@ -1664,25 +1664,25 @@
*/
static uint32_t RCC_GetPLLCLKFreq(void)
{
- uint32_t pllmul = 0, pllsource = 0, prediv = 0, pllclk = 0;
+ uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U;
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllmul = ( pllmul >> 18) + 2;
+ pllmul = ( pllmul >> 18U) + 2U;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if (pllsource != RCC_PLLSOURCE_HSI)
{
- prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (HSE_VALUE/prediv) * pllmul;
}
else
{
- /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (HSI_VALUE >> 1) * pllmul;
+ /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */
+ pllclk = (HSI_VALUE >> 1U) * pllmul;
}
#else
- prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U;
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rcc_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -983,213 +983,213 @@
* @{
*/
#if defined(STM32F301x8) || defined(STM32F318xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
-#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
-#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_I2C3 (0x00008000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_TIM15 (0x00040000U)
+#define RCC_PERIPHCLK_TIM16 (0x00080000U)
+#define RCC_PERIPHCLK_TIM17 (0x00100000U)
#endif /* STM32F301x8 || STM32F318xx */
#if defined(STM32F302x8)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
-#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
-#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_I2C3 (0x00008000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_TIM15 (0x00040000U)
+#define RCC_PERIPHCLK_TIM16 (0x00080000U)
+#define RCC_PERIPHCLK_TIM17 (0x00100000U)
#endif /* STM32F302x8 */
#if defined(STM32F302xC)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F302xC */
#if defined(STM32F303xC)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F303xC */
#if defined(STM32F302xE)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
-#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
-#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
-#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
-#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
-#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
#endif /* STM32F302xE */
#if defined(STM32F303xE)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
-#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
-#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
-#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
-#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
-#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
-#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
+#define RCC_PERIPHCLK_TIM20 (0x02000000U)
#endif /* STM32F303xE */
#if defined(STM32F398xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
-#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
-#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
-#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
-#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
-#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
-#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_I2C3 (0x00040000U)
+#define RCC_PERIPHCLK_TIM2 (0x00100000U)
+#define RCC_PERIPHCLK_TIM34 (0x00200000U)
+#define RCC_PERIPHCLK_TIM15 (0x00400000U)
+#define RCC_PERIPHCLK_TIM16 (0x00800000U)
+#define RCC_PERIPHCLK_TIM17 (0x01000000U)
+#define RCC_PERIPHCLK_TIM20 (0x02000000U)
#endif /* STM32F398xx */
#if defined(STM32F358xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
-#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
-#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_UART4 (0x00000008U)
+#define RCC_PERIPHCLK_UART5 (0x00000010U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_ADC34 (0x00000100U)
+#define RCC_PERIPHCLK_I2S (0x00000200U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_TIM8 (0x00002000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F358xx */
#if defined(STM32F303x8)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F303x8 */
#if defined(STM32F334x8)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_HRTIM1 (0x00004000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F334x8 */
#if defined(STM32F328xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_ADC12 (0x00000080U)
+#define RCC_PERIPHCLK_TIM1 (0x00001000U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F328xx */
#if defined(STM32F373xC)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
-#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_CEC (0x00000400U)
+#define RCC_PERIPHCLK_SDADC (0x00000800U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
+#define RCC_PERIPHCLK_USB (0x00020000U)
#endif /* STM32F373xC */
#if defined(STM32F378xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
-#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
-#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
-#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
-#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART1 (0x00000001U)
+#define RCC_PERIPHCLK_USART2 (0x00000002U)
+#define RCC_PERIPHCLK_USART3 (0x00000004U)
+#define RCC_PERIPHCLK_I2C1 (0x00000020U)
+#define RCC_PERIPHCLK_I2C2 (0x00000040U)
+#define RCC_PERIPHCLK_ADC1 (0x00000080U)
+#define RCC_PERIPHCLK_CEC (0x00000400U)
+#define RCC_PERIPHCLK_SDADC (0x00000800U)
+#define RCC_PERIPHCLK_RTC (0x00010000U)
#endif /* STM32F378xx */
/**
@@ -1711,23 +1711,23 @@
/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
* @{
*/
-#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
-#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
-#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
-#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
-#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
-#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
-#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
-#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
-#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
-#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
-#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
-#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
-#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
-#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
-#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
-#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
-#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
+#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1
+#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2
+#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4
+#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6
+#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8
+#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10
+#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12
+#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14
+#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16
+#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20
+#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24
+#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28
+#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32
+#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36
+#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40
+#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44
+#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48
/**
* @}
@@ -1761,18 +1761,18 @@
*/
#if defined(RCC_CFGR_MCOPRE)
-#define RCC_MCODIV_1 ((uint32_t)0x00000000)
-#define RCC_MCODIV_2 ((uint32_t)0x10000000)
-#define RCC_MCODIV_4 ((uint32_t)0x20000000)
-#define RCC_MCODIV_8 ((uint32_t)0x30000000)
-#define RCC_MCODIV_16 ((uint32_t)0x40000000)
-#define RCC_MCODIV_32 ((uint32_t)0x50000000)
-#define RCC_MCODIV_64 ((uint32_t)0x60000000)
-#define RCC_MCODIV_128 ((uint32_t)0x70000000)
+#define RCC_MCODIV_1 (0x00000000U)
+#define RCC_MCODIV_2 (0x10000000U)
+#define RCC_MCODIV_4 (0x20000000U)
+#define RCC_MCODIV_8 (0x30000000U)
+#define RCC_MCODIV_16 (0x40000000U)
+#define RCC_MCODIV_32 (0x50000000U)
+#define RCC_MCODIV_64 (0x60000000U)
+#define RCC_MCODIV_128 (0x70000000U)
#else
-#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+#define RCC_MCODIV_1 (0x00000000U)
#endif /* RCC_CFGR_MCOPRE */
@@ -1784,7 +1784,7 @@
* @{
*/
-#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */
+#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
@@ -1823,7 +1823,7 @@
do { \
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
- } while(0)
+ } while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
@@ -1897,7 +1897,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
@@ -1910,21 +1910,21 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
/* Aliases for STM32 F3 compatibility */
#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
@@ -1946,7 +1946,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
@@ -1958,7 +1958,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
/* Aliases for STM32 F3 compatibility */
#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
@@ -1976,14 +1976,14 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
@@ -1996,21 +1996,21 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
@@ -2034,28 +2034,28 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
@@ -2071,49 +2071,49 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
@@ -2132,14 +2132,14 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
@@ -2152,84 +2152,84 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM18_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CEC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
@@ -2255,7 +2255,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
#endif /* STM32F303xE || STM32F398xx || */
@@ -2273,7 +2273,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#endif /* STM32F302xE || STM32F303xE || */
@@ -2288,7 +2288,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
#endif /* STM32F301x8*/
@@ -2300,7 +2300,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
@@ -2323,7 +2323,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
@@ -2337,7 +2337,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#endif /* STM32F303xE || STM32F398xx || */
@@ -2350,7 +2350,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
@@ -2362,7 +2362,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
#endif /* STM32F334x8 */
@@ -2374,42 +2374,42 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM19_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
@@ -2429,7 +2429,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
@@ -2444,7 +2444,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
@@ -2456,7 +2456,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
#endif /* STM32F303xE || STM32F398xx */
@@ -3560,7 +3560,7 @@
* @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
*/
#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__))
/** @brief Macro to get the SDADCx clock prescaler.
* @retval The clock source can be one of the following values:
@@ -3582,7 +3582,7 @@
* @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
* @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
*/
-#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
+#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE)))
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
@@ -292,7 +292,7 @@
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
@@ -318,7 +318,7 @@
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -343,7 +343,7 @@
else
{
/* Reset TR, DR and CR registers */
- hrtc->Instance->TR = (uint32_t)0x00000000;
+ hrtc->Instance->TR = 0x00000000U;
hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= RTC_CR_WUCKSEL;
@@ -366,23 +366,23 @@
}
/* Reset all RTC CR register bits */
- hrtc->Instance->CR &= (uint32_t)0x00000000;
+ hrtc->Instance->CR &= 0x00000000U;
hrtc->Instance->WUTR = RTC_WUTR_WUT;
- hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF));
- hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
- hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
- hrtc->Instance->CALR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
- hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
+ hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMBR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->ALRMASSR = 0x00000000U;
+ hrtc->Instance->ALRMBSSR = 0x00000000U;
/* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = (uint32_t)0x00000000;
+ hrtc->Instance->ISR = 0x00000000U;
/* Reset Tamper and alternate functions configuration register */
- hrtc->Instance->TAFCR = (uint32_t)0x00000000;
+ hrtc->Instance->TAFCR = 0x00000000U;
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
@@ -471,7 +471,7 @@
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -492,16 +492,16 @@
}
else
{
- sTime->TimeFormat = 0x00;
+ sTime->TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sTime->Hours));
}
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
+ tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16));
+ (((uint32_t)sTime->TimeFormat) << 16U));
}
else
{
@@ -513,15 +513,15 @@
}
else
{
- sTime->TimeFormat = 0x00;
+ sTime->TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
- ((uint32_t)(sTime->Minutes) << 8) | \
+ tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
+ ((uint32_t)(sTime->Minutes) << 8U) | \
((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16));
+ ((uint32_t)(sTime->TimeFormat) << 16U));
}
/* Disable the write protection for RTC registers */
@@ -555,7 +555,7 @@
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
@@ -601,7 +601,7 @@
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -616,10 +616,10 @@
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@@ -645,7 +645,7 @@
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
- uint32_t datetmpreg = 0;
+ uint32_t datetmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -655,9 +655,9 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
+ if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
- sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
+ sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
@@ -668,10 +668,10 @@
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13));
+ ((uint32_t)sDate->WeekDay << 13U));
}
else
{
@@ -681,10 +681,10 @@
datetmpreg = RTC_Bcd2ToByte(sDate->Date);
assert_param(IS_RTC_DATE(datetmpreg));
- datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
- (((uint32_t)sDate->Month) << 8) | \
+ datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
+ (((uint32_t)sDate->Month) << 8U) | \
((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13));
+ (((uint32_t)sDate->WeekDay) << 13U));
}
/* Disable the write protection for RTC registers */
@@ -712,7 +712,7 @@
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
@@ -753,7 +753,7 @@
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
- uint32_t datetmpreg = 0;
+ uint32_t datetmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -762,10 +762,10 @@
datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13);
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@@ -807,8 +807,8 @@
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t tickstart = 0;
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -832,7 +832,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@@ -847,11 +847,11 @@
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -865,7 +865,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@@ -883,11 +883,11 @@
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -991,8 +991,8 @@
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t tickstart = 0;
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1016,7 +1016,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@@ -1030,11 +1030,11 @@
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -1048,7 +1048,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@@ -1065,11 +1065,11 @@
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -1176,7 +1176,7 @@
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
@@ -1270,7 +1270,7 @@
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1293,12 +1293,12 @@
}
/* Fill the structure with the read parameters */
- sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
- sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
+ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+ sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
- sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+ sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
@@ -1385,7 +1385,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -1437,7 +1437,7 @@
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
@@ -1508,7 +1508,7 @@
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check if the Initialization mode is set */
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
@@ -1538,15 +1538,15 @@
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
- uint32_t bcdhigh = 0;
+ uint32_t bcdhigh = 0U;
- while(Value >= 10)
+ while(Value >= 10U)
{
bcdhigh++;
- Value -= 10;
+ Value -= 10U;
}
- return ((uint8_t)(bcdhigh << 4) | Value);
+ return ((uint8_t)(bcdhigh << 4U) | Value);
}
/**
@@ -1556,9 +1556,9 @@
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
- uint32_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
+ uint32_t tmp = 0U;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
+ return (tmp + (Value & (uint8_t)0x0FU));
}
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@@ -64,10 +64,10 @@
*/
typedef enum
{
- HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
+ HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
}HAL_RTCStateTypeDef;
@@ -81,10 +81,10 @@
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FU */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
@@ -106,21 +106,21 @@
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59U */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59U */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
- This parameter corresponds to a time unit range between [0-1] Second
+ This parameter corresponds to a time unit range between [0U-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
- This parameter corresponds to a time unit range between [0-1] Second
+ This parameter corresponds to a time unit range between [0U-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
@@ -144,10 +144,10 @@
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99U */
}RTC_DateTypeDef;
@@ -168,7 +168,7 @@
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+ If the Alarm Date is selected, this parameter must be set to a value in the 1U-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
@@ -201,7 +201,7 @@
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
-#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_24 (0x00000000U)
#define RTC_HOURFORMAT_12 RTC_CR_FMT
/**
* @}
@@ -210,7 +210,7 @@
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
-#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
@@ -219,7 +219,7 @@
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
-#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
/**
* @}
@@ -228,8 +228,8 @@
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
-#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
/**
* @}
*/
@@ -237,7 +237,7 @@
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
* @{
*/
-#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
+#define RTC_DAYLIGHTSAVING_NONE (0x00000000U)
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
/**
@@ -247,7 +247,7 @@
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
* @{
*/
-#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_RESET (0x00000000U)
#define RTC_STOREOPERATION_SET RTC_CR_BCK
/**
* @}
@@ -256,8 +256,8 @@
/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
* @{
*/
-#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
-#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define RTC_FORMAT_BIN (0x000000000U)
+#define RTC_FORMAT_BCD (0x000000001U)
/**
* @}
*/
@@ -266,18 +266,18 @@
* @{
*/
/* Coded in BCD format */
-#define RTC_MONTH_JANUARY ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
-#define RTC_MONTH_MARCH ((uint8_t)0x03)
-#define RTC_MONTH_APRIL ((uint8_t)0x04)
-#define RTC_MONTH_MAY ((uint8_t)0x05)
-#define RTC_MONTH_JUNE ((uint8_t)0x06)
-#define RTC_MONTH_JULY ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
+#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
+#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
+#define RTC_MONTH_MARCH ((uint8_t)0x03U)
+#define RTC_MONTH_APRIL ((uint8_t)0x04U)
+#define RTC_MONTH_MAY ((uint8_t)0x05U)
+#define RTC_MONTH_JUNE ((uint8_t)0x06U)
+#define RTC_MONTH_JULY ((uint8_t)0x07U)
+#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
+#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
+#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
+#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
+#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
/**
* @}
*/
@@ -285,13 +285,13 @@
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
-#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
+#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
+#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
+#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
+#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
+#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
+#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
+#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
/**
* @}
*/
@@ -299,7 +299,7 @@
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
* @{
*/
-#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
* @}
@@ -308,7 +308,7 @@
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
* @{
*/
-#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_NONE (0x00000000U)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
@@ -334,7 +334,7 @@
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
-#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
+#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
@@ -378,10 +378,10 @@
#define RTC_IT_ALRB RTC_CR_ALRBIE
#define RTC_IT_ALRA RTC_CR_ALRAIE
#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000) /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP1 (0x00020000U) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP2 (0x00040000U) /*only for RTC_ISR flag check*/
#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /*only for RTC_ISR flag check*/
+#define RTC_IT_TAMP3 (0x00080000U) /*only for RTC_ISR flag check*/
#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
@@ -434,9 +434,9 @@
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
- (__HANDLE__)->Instance->WPR = 0xCA; \
- (__HANDLE__)->Instance->WPR = 0x53; \
- } while(0)
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
/**
* @brief Enable the write protection for RTC registers.
@@ -445,8 +445,8 @@
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
- (__HANDLE__)->Instance->WPR = 0xFF; \
- } while(0)
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -507,7 +507,7 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -703,10 +703,10 @@
* @{
*/
/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
+#define RTC_TR_RESERVED_MASK (0x007F7F7FU)
+#define RTC_DR_RESERVED_MASK (0x00FFFF3FU)
+#define RTC_INIT_MASK (0xFFFFFFFFU)
+#define RTC_RSF_MASK (0xFFFFFF5FU)
#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
@@ -739,12 +739,12 @@
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
+#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
((PM) == RTC_HOURFORMAT12_PM))
@@ -758,11 +758,11 @@
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@@ -772,7 +772,7 @@
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
@@ -785,11 +785,11 @@
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extended peripheral:
@@ -39,7 +39,7 @@
interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
function.
- (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13).
+ (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).
*** Tamper configuration ***
============================
@@ -49,7 +49,7 @@
value, sampling frequency, precharge or discharge and Pull-UP using the
HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
mode using HAL_RTCEx_SetTamper_IT() function.
- (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13).
+ (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).
*** Backup Data Registers configuration ***
===========================================
@@ -150,7 +150,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
@@ -204,7 +204,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
@@ -254,7 +254,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -297,7 +297,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
{
- uint32_t tmptime = 0, tmpdate = 0;
+ uint32_t tmptime = 0U, tmpdate = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -307,17 +307,17 @@
tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
/* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
/* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@@ -348,7 +348,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
@@ -366,14 +366,14 @@
if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
(uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
(uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
(uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
(uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
@@ -396,7 +396,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
@@ -415,14 +415,14 @@
/* Configure the tamper trigger */
if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
- sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1);
+ sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1U);
}
tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
(uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
(uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
(uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
(uint32_t)RTC_TAFCR_TAMPPUDIS);
@@ -631,7 +631,7 @@
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -660,7 +660,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -692,7 +692,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -725,7 +725,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -770,7 +770,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@@ -859,7 +859,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@@ -958,7 +958,7 @@
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1067,7 +1067,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
@@ -1127,13 +1127,13 @@
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4);
+ tmp += (BackupRegister * 4U);
/* Write the specified register */
*(__IO uint32_t *)tmp = (uint32_t)Data;
@@ -1149,13 +1149,13 @@
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)&(hrtc->Instance->BKP0R);
- tmp += (BackupRegister * 4);
+ tmp += (BackupRegister * 4U);
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
@@ -1182,7 +1182,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
@@ -1250,7 +1250,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
@@ -1289,7 +1289,7 @@
/* Configure the Shift settings */
hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
@@ -1613,7 +1613,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_rtc_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
@@ -98,7 +98,7 @@
/** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
* @{
*/
-#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000)
+#define RTC_OUTPUT_DISABLE (0x00000000U)
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
@@ -109,49 +109,49 @@
/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
* @{
*/
-#if RTC_BKP_NUMBER > 0
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#endif /* RTC_BKP_NUMBER > 0 */
+#if RTC_BKP_NUMBER > 0U
+#define RTC_BKP_DR0 (0x00000000U)
+#define RTC_BKP_DR1 (0x00000001U)
+#define RTC_BKP_DR2 (0x00000002U)
+#define RTC_BKP_DR3 (0x00000003U)
+#define RTC_BKP_DR4 (0x00000004U)
+#endif /* RTC_BKP_NUMBER > 0U */
-#if RTC_BKP_NUMBER > 5
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
-#endif /* RTC_BKP_NUMBER > 5 */
+#if RTC_BKP_NUMBER > 5U
+#define RTC_BKP_DR5 (0x00000005U)
+#define RTC_BKP_DR6 (0x00000006U)
+#define RTC_BKP_DR7 (0x00000007U)
+#define RTC_BKP_DR8 (0x00000008U)
+#define RTC_BKP_DR9 (0x00000009U)
+#define RTC_BKP_DR10 (0x0000000AU)
+#define RTC_BKP_DR11 (0x0000000BU)
+#define RTC_BKP_DR12 (0x0000000CU)
+#define RTC_BKP_DR13 (0x0000000DU)
+#define RTC_BKP_DR14 (0x0000000EU)
+#define RTC_BKP_DR15 (0x0000000FU)
+#endif /* RTC_BKP_NUMBER > 5U */
-#if RTC_BKP_NUMBER > 16
-#define RTC_BKP_DR16 ((uint32_t)0x00000010)
-#define RTC_BKP_DR17 ((uint32_t)0x00000011)
-#define RTC_BKP_DR18 ((uint32_t)0x00000012)
-#define RTC_BKP_DR19 ((uint32_t)0x00000013)
-#endif /* RTC_BKP_NUMBER > 16 */
+#if RTC_BKP_NUMBER > 16U
+#define RTC_BKP_DR16 (0x00000010U)
+#define RTC_BKP_DR17 (0x00000011U)
+#define RTC_BKP_DR18 (0x00000012U)
+#define RTC_BKP_DR19 (0x00000013U)
+#endif /* RTC_BKP_NUMBER > 16U */
-#if RTC_BKP_NUMBER > 20
-#define RTC_BKP_DR20 ((uint32_t)0x00000014)
-#define RTC_BKP_DR21 ((uint32_t)0x00000015)
-#define RTC_BKP_DR22 ((uint32_t)0x00000016)
-#define RTC_BKP_DR23 ((uint32_t)0x00000017)
-#define RTC_BKP_DR24 ((uint32_t)0x00000018)
-#define RTC_BKP_DR25 ((uint32_t)0x00000019)
-#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
-#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
-#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
-#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
-#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
-#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
-#endif /* RTC_BKP_NUMBER > 20 */
+#if RTC_BKP_NUMBER > 20U
+#define RTC_BKP_DR20 (0x00000014U)
+#define RTC_BKP_DR21 (0x00000015U)
+#define RTC_BKP_DR22 (0x00000016U)
+#define RTC_BKP_DR23 (0x00000017U)
+#define RTC_BKP_DR24 (0x00000018U)
+#define RTC_BKP_DR25 (0x00000019U)
+#define RTC_BKP_DR26 (0x0000001AU)
+#define RTC_BKP_DR27 (0x0000001BU)
+#define RTC_BKP_DR28 (0x0000001CU)
+#define RTC_BKP_DR29 (0x0000001DU)
+#define RTC_BKP_DR30 (0x0000001EU)
+#define RTC_BKP_DR31 (0x0000001FU)
+#endif /* RTC_BKP_NUMBER > 20U */
/**
* @}
*/
@@ -159,7 +159,7 @@
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
* @{
*/
-#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPEDGE_RISING (0x00000000U)
#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
* @}
@@ -168,7 +168,7 @@
/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000)
+#define RTC_TIMESTAMPPIN_DEFAULT (0x00000000U)
/**
* @}
*/
@@ -189,7 +189,7 @@
/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
* @{
*/
-#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000)
+#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U)
#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
@@ -200,7 +200,7 @@
/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
* @{
*/
-#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
consecutive samples at the active level */
@@ -215,10 +215,10 @@
/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
* @{
*/
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768U */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
+ with a frequency = RTCCLK / 16384U */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 8192 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
@@ -238,7 +238,7 @@
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
* @{
*/
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
@@ -254,7 +254,7 @@
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */
/**
* @}
*/
@@ -262,7 +262,7 @@
/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
* @{
*/
-#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
/**
* @}
@@ -271,7 +271,7 @@
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
* @{
*/
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000)
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U)
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
@@ -284,7 +284,7 @@
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK seconds */
#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 16s, else 2exp19 RTCCLK seconds */
@@ -297,11 +297,11 @@
/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
* @{
*/
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
+ with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */
/**
* @}
*/
@@ -309,7 +309,7 @@
/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
* @{
*/
-#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000)
+#define RTC_CALIBOUTPUT_512HZ (0x00000000U)
#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
@@ -318,7 +318,7 @@
/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
* @{
*/
-#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000)
+#define RTC_SHIFTADD1S_RESET (0x00000000U)
#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
@@ -379,7 +379,7 @@
* @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
@@ -542,7 +542,7 @@
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
@@ -659,7 +659,7 @@
* @note (*) RTC_IT_TAMP3 not present on all the devices
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
@@ -946,7 +946,7 @@
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6U) == 0x00) && ((TAMPER) != (uint32_t)RESET))
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
@@ -983,7 +983,7 @@
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
@@ -993,10 +993,10 @@
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
((SEL) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_sdadc.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Sigma-Delta Analog to Digital Converter
* (SDADC) peripherals:
@@ -286,8 +286,8 @@
/* Initialize SDADC variables with default values */
hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
- hsdadc->InjectedChannelsNbr = 1;
- hsdadc->InjConvRemaining = 1;
+ hsdadc->InjectedChannelsNbr = 1U;
+ hsdadc->InjConvRemaining = 1U;
hsdadc->RegularTrigger = SDADC_SOFTWARE_TRIGGER;
hsdadc->InjectedTrigger = SDADC_SOFTWARE_TRIGGER;
hsdadc->ExtTriggerEdge = SDADC_EXT_TRIG_RISING_EDGE;
@@ -317,14 +317,14 @@
SDADC1->CR1 |= hsdadc->Init.ReferenceVoltage;
/* Wait at least 2ms before setting ADON */
- HAL_Delay(2);
+ HAL_Delay(2U);
}
/* Enable SDADC */
hsdadc->Instance->CR2 |= SDADC_CR2_ADON;
/* Wait end of stabilization */
- while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0)
+ while((hsdadc->Instance->ISR & SDADC_ISR_STABIP) != 0U)
{
}
@@ -355,14 +355,14 @@
hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
/* Reset all registers */
- hsdadc->Instance->CR1 = 0x00000000;
- hsdadc->Instance->CR2 = 0x00000000;
- hsdadc->Instance->JCHGR = 0x00000001;
- hsdadc->Instance->CONF0R = 0x00000000;
- hsdadc->Instance->CONF1R = 0x00000000;
- hsdadc->Instance->CONF2R = 0x00000000;
- hsdadc->Instance->CONFCHR1 = 0x00000000;
- hsdadc->Instance->CONFCHR2 = 0x00000000;
+ hsdadc->Instance->CR1 = 0x00000000U;
+ hsdadc->Instance->CR2 = 0x00000000U;
+ hsdadc->Instance->JCHGR = 0x00000001U;
+ hsdadc->Instance->CONF0R = 0x00000000U;
+ hsdadc->Instance->CONF1R = 0x00000000U;
+ hsdadc->Instance->CONF2R = 0x00000000U;
+ hsdadc->Instance->CONFCHR1 = 0x00000000U;
+ hsdadc->Instance->CONFCHR2 = 0x00000000U;
/* Call MSP deinit function */
HAL_SDADC_MspDeInit(hsdadc);
@@ -445,7 +445,7 @@
SDADC_ConfParamTypeDef* ConfParamStruct)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
@@ -475,7 +475,7 @@
/* Program configuration register with parameters */
tmp = (uint32_t)((uint32_t)(hsdadc->Instance) + \
SDADC_CONFREG_OFFSET + \
- (uint32_t)(ConfIndex << 2));
+ (uint32_t)(ConfIndex << 2U));
*(__IO uint32_t *) (tmp) = (uint32_t) (ConfParamStruct->InputMode | \
ConfParamStruct->Gain | \
ConfParamStruct->CommonMode | \
@@ -505,7 +505,7 @@
uint32_t ConfIndex)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t channelnum = 0;
+ uint32_t channelnum = 0U;
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
@@ -532,11 +532,11 @@
if(Channel != SDADC_CHANNEL_8)
{
/* Get channel number */
- channelnum = (uint32_t)(Channel>>16);
+ channelnum = (uint32_t)(Channel>>16U);
/* Set the channel configuration */
- hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2));
- hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2));
+ hsdadc->Instance->CONFCHR1 &= (uint32_t) ~((uint32_t)SDADC_CONFCHR1_CONFCH0 << (channelnum << 2U));
+ hsdadc->Instance->CONFCHR1 |= (uint32_t) (ConfIndex << (channelnum << 2U));
}
else
{
@@ -1016,7 +1016,7 @@
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1150,7 +1150,7 @@
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1289,7 +1289,7 @@
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(pData != NULL);
- assert_param(Length != 0);
+ assert_param(Length != 0U);
/* Check that DMA is not enabled for injected conversion */
if((hsdadc->Instance->CR1 & SDADC_CR1_JDMAEN) == SDADC_CR1_JDMAEN)
@@ -1300,7 +1300,7 @@
else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length != 1))
+ (Length != 1U))
{
status = HAL_ERROR;
}
@@ -1465,7 +1465,7 @@
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
/* Return timeout status */
return HAL_TIMEOUT;
@@ -1484,7 +1484,7 @@
}
/* Update remaining injected conversions */
hsdadc->InjConvRemaining--;
- if(hsdadc->InjConvRemaining == 0)
+ if(hsdadc->InjConvRemaining == 0U)
{
/* end of injected sequence, reset the value */
hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
@@ -1614,7 +1614,7 @@
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(pData != NULL);
- assert_param(Length != 0);
+ assert_param(Length != 0U);
/* Check that DMA is not enabled for regular conversion */
if((hsdadc->Instance->CR1 & SDADC_CR1_RDMAEN) == SDADC_CR1_RDMAEN)
@@ -1722,7 +1722,7 @@
*/
uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
{
- uint32_t value = 0;
+ uint32_t value = 0U;
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
@@ -1754,7 +1754,7 @@
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(pData != NULL);
- assert_param(Length != 0);
+ assert_param(Length != 0U);
/* Check instance is SDADC1 */
if(hsdadc->Instance != SDADC1)
@@ -1770,7 +1770,7 @@
else if((hsdadc->RegularTrigger == SDADC_SOFTWARE_TRIGGER) && \
(hsdadc->RegularContMode == SDADC_CONTINUOUS_CONV_OFF) && \
(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length != 1))
+ (Length != 1U))
{
status = HAL_ERROR;
}
@@ -1879,7 +1879,7 @@
*/
uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
{
- uint32_t value = 0;
+ uint32_t value = 0U;
/* Check parameters and check instance is SDADC1 */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
@@ -1910,7 +1910,7 @@
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(pData != NULL);
- assert_param(Length != 0);
+ assert_param(Length != 0U);
/* Check instance is SDADC1 */
if(hsdadc->Instance != SDADC1)
@@ -1926,7 +1926,7 @@
else if((hsdadc->InjectedTrigger == SDADC_SOFTWARE_TRIGGER) && \
(hsdadc->InjectedContMode == SDADC_CONTINUOUS_CONV_OFF) && \
(hsdadc->hdma->Init.Mode == DMA_NORMAL) && \
- (Length > (hsdadc->InjectedChannelsNbr << 1)))
+ (Length > (hsdadc->InjectedChannelsNbr << 1U)))
{
status = HAL_ERROR;
}
@@ -2035,7 +2035,7 @@
*/
uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
{
- uint32_t value = 0;
+ uint32_t value = 0U;
/* Check parameters and check instance is SDADC1 */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
@@ -2084,7 +2084,7 @@
/* Update remaining injected conversions */
hsdadc->InjConvRemaining--;
- if(hsdadc->InjConvRemaining ==0)
+ if(hsdadc->InjConvRemaining ==0U)
{
/* end of injected sequence, reset the value */
hsdadc->InjConvRemaining = hsdadc->InjectedChannelsNbr;
@@ -2374,7 +2374,7 @@
*/
static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Set INIT bit on SDADC_CR1 register */
hsdadc->Instance->CR1 |= SDADC_CR1_INIT;
@@ -2411,18 +2411,18 @@
*/
static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
{
- uint32_t nbChannels = 0;
+ uint32_t nbChannels = 0U;
uint32_t tmp,i;
/* Get the number of channels from bitfield */
tmp = (uint32_t) (Channels & SDADC_LSB_MASK);
- for(i = 0 ; i < 9 ; i++)
+ for(i = 0U ; i < 9U ; i++)
{
- if((tmp & (uint32_t)0x00000001) != 0)
+ if((tmp & 0x00000001U) != 0U)
{
nbChannels++;
}
- tmp = (uint32_t) (tmp >> 1);
+ tmp = (uint32_t) (tmp >> 1U);
}
return nbChannels;
}
@@ -2492,7 +2492,7 @@
}
/* Wait for the end of regular conversion */
tickstart = HAL_GetTick();
- while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0)
+ while((hsdadc->Instance->ISR & SDADC_ISR_RCIP) != 0U)
{
if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
{
@@ -2616,7 +2616,7 @@
}
/* Wait for the end of injected conversion */
tickstart = HAL_GetTick();
- while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0)
+ while((hsdadc->Instance->ISR & SDADC_ISR_JCIP) != 0U)
{
if((HAL_GetTick()-tickstart) > SDADC_TIMEOUT)
{
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sdadc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_sdadc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file contains all the functions prototypes for the SDADC
* firmware library.
******************************************************************************
@@ -68,13 +68,13 @@
*/
typedef enum
{
- HAL_SDADC_STATE_RESET = 0x00, /*!< SDADC not initialized */
- HAL_SDADC_STATE_READY = 0x01, /*!< SDADC initialized and ready for use */
- HAL_SDADC_STATE_CALIB = 0x02, /*!< SDADC calibration in progress */
- HAL_SDADC_STATE_REG = 0x03, /*!< SDADC regular conversion in progress */
- HAL_SDADC_STATE_INJ = 0x04, /*!< SDADC injected conversion in progress */
- HAL_SDADC_STATE_REG_INJ = 0x05, /*!< SDADC regular and injected conversions in progress */
- HAL_SDADC_STATE_ERROR = 0xFF, /*!< SDADC state error */
+ HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */
+ HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */
+ HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */
+ HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */
+ HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */
+ HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */
+ HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */
}HAL_SDADC_StateTypeDef;
/**
@@ -123,10 +123,10 @@
This parameter can be any value of @ref SDADC_InputMode */
uint32_t Gain; /*!< Specifies the gain setting.
This parameter can be any value of @ref SDADC_Gain */
- uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2).
+ uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
This parameter can be any value of @ref SDADC_CommonMode */
uint32_t Offset; /*!< Specifies the 12-bit offset value.
- This parameter can be any value lower or equal to 0x00000FFF */
+ This parameter can be any value lower or equal to 0x00000FFFU */
}SDADC_ConfParamTypeDef;
/**
@@ -142,7 +142,7 @@
/** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
* @{
*/
-#define SDADC_LOWPOWER_NONE ((uint32_t)0x00000000)
+#define SDADC_LOWPOWER_NONE (0x00000000U)
#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
/**
@@ -152,7 +152,7 @@
/** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
* @{
*/
-#define SDADC_FAST_CONV_DISABLE ((uint32_t)0x00000000)
+#define SDADC_FAST_CONV_DISABLE (0x00000000U)
#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
/**
* @}
@@ -161,7 +161,7 @@
/** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
* @{
*/
-#define SDADC_SLOW_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define SDADC_SLOW_CLOCK_DISABLE (0x00000000U)
#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
/**
* @}
@@ -170,7 +170,7 @@
/** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
* @{
*/
-#define SDADC_VREF_EXT ((uint32_t)0x00000000) /*!< The reference voltage is forced externally using VREF pin */
+#define SDADC_VREF_EXT (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */
#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
@@ -182,9 +182,9 @@
* @{
*/
-#define SDADC_CONF_INDEX_0 ((uint32_t)0x00000000) /*!< Configuration 0 Register selected */
-#define SDADC_CONF_INDEX_1 ((uint32_t)0x00000001) /*!< Configuration 1 Register selected */
-#define SDADC_CONF_INDEX_2 ((uint32_t)0x00000002) /*!< Configuration 2 Register selected */
+#define SDADC_CONF_INDEX_0 (0x00000000U) /*!< Configuration 0 Register selected */
+#define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */
+#define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */
/**
* @}
*/
@@ -192,7 +192,7 @@
/** @defgroup SDADC_InputMode SDADC Input Mode
* @{
*/
-#define SDADC_INPUT_MODE_DIFF ((uint32_t)0x00000000) /*!< Conversions are executed in differential mode */
+#define SDADC_INPUT_MODE_DIFF (0x00000000U) /*!< Conversions are executed in differential mode */
#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
/**
@@ -202,13 +202,13 @@
/** @defgroup SDADC_Gain SDADC Gain
* @{
*/
-#define SDADC_GAIN_1 ((uint32_t)0x00000000) /*!< Gain equal to 1 */
-#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2 */
-#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4 */
-#define SDADC_GAIN_8 ((uint32_t)0x00300000) /*!< Gain equal to 8 */
-#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16 */
-#define SDADC_GAIN_32 ((uint32_t)0x00500000) /*!< Gain equal to 32 */
-#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1/2 */
+#define SDADC_GAIN_1 (0x00000000U) /*!< Gain equal to 1U */
+#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */
+#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */
+#define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */
+#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */
+#define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */
+#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */
/**
* @}
*/
@@ -216,7 +216,7 @@
/** @defgroup SDADC_CommonMode SDADC Common Mode
* @{
*/
-#define SDADC_COMMON_MODE_VSSA ((uint32_t)0x00000000) /*!< Select SDADC VSSA as common mode */
+#define SDADC_COMMON_MODE_VSSA (0x00000000U) /*!< Select SDADC VSSA as common mode */
#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
/**
@@ -236,16 +236,16 @@
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
- --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
-#define SDADC_CHANNEL_0 ((uint32_t)0x00000001)
-#define SDADC_CHANNEL_1 ((uint32_t)0x00010002)
-#define SDADC_CHANNEL_2 ((uint32_t)0x00020004)
-#define SDADC_CHANNEL_3 ((uint32_t)0x00030008)
-#define SDADC_CHANNEL_4 ((uint32_t)0x00040010)
-#define SDADC_CHANNEL_5 ((uint32_t)0x00050020)
-#define SDADC_CHANNEL_6 ((uint32_t)0x00060040)
-#define SDADC_CHANNEL_7 ((uint32_t)0x00070080)
-#define SDADC_CHANNEL_8 ((uint32_t)0x00080100)
+ --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */
+#define SDADC_CHANNEL_0 (0x00000001U)
+#define SDADC_CHANNEL_1 (0x00010002U)
+#define SDADC_CHANNEL_2 (0x00020004U)
+#define SDADC_CHANNEL_3 (0x00030008U)
+#define SDADC_CHANNEL_4 (0x00040010U)
+#define SDADC_CHANNEL_5 (0x00050020U)
+#define SDADC_CHANNEL_6 (0x00060040U)
+#define SDADC_CHANNEL_7 (0x00070080U)
+#define SDADC_CHANNEL_8 (0x00080100U)
/**
* @}
*/
@@ -253,7 +253,7 @@
/** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
* @{
*/
-#define SDADC_CALIBRATION_SEQ_1 ((uint32_t)0x00000000) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
+#define SDADC_CALIBRATION_SEQ_1 (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
/**
@@ -263,8 +263,8 @@
/** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
* @{
*/
-#define SDADC_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
-#define SDADC_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
+#define SDADC_CONTINUOUS_CONV_OFF (0x00000000U) /*!< Conversion are not continuous */
+#define SDADC_CONTINUOUS_CONV_ON (0x00000001U) /*!< Conversion are continuous */
/**
* @}
*/
@@ -272,9 +272,9 @@
/** @defgroup SDADC_Trigger SDADC Trigger
* @{
*/
-#define SDADC_SOFTWARE_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
-#define SDADC_SYNCHRONOUS_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
-#define SDADC_EXTERNAL_TRIGGER ((uint32_t)0x00000002) /*!< External trigger */
+#define SDADC_SOFTWARE_TRIGGER (0x00000000U) /*!< Software trigger */
+#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
+#define SDADC_EXTERNAL_TRIGGER (0x00000002U) /*!< External trigger */
/**
* @}
*/
@@ -282,26 +282,26 @@
/** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
* @{
*/
-#define SDADC_EXT_TRIG_TIM13_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM14_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM16_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM17_CC1 ((uint32_t)0x00000000) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM12_CC1 ((uint32_t)0x00000100) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM12_CC2 ((uint32_t)0x00000100) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM15_CC2 ((uint32_t)0x00000200) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM2_CC3 ((uint32_t)0x00000200) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM2_CC4 ((uint32_t)0x00000200) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM3_CC1 ((uint32_t)0x00000300) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM3_CC2 ((uint32_t)0x00000300) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM3_CC3 ((uint32_t)0x00000300) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM4_CC1 ((uint32_t)0x00000400) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM4_CC2 ((uint32_t)0x00000400) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM4_CC3 ((uint32_t)0x00000400) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_TIM19_CC2 ((uint32_t)0x00000500) /*!< Trigger source for SDADC1 */
-#define SDADC_EXT_TRIG_TIM19_CC3 ((uint32_t)0x00000500) /*!< Trigger source for SDADC2 */
-#define SDADC_EXT_TRIG_TIM19_CC4 ((uint32_t)0x00000500) /*!< Trigger source for SDADC3 */
-#define SDADC_EXT_TRIG_EXTI11 ((uint32_t)0x00000700) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
-#define SDADC_EXT_TRIG_EXTI15 ((uint32_t)0x00000600) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500U) /*!< Trigger source for SDADC1 */
+#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500U) /*!< Trigger source for SDADC2 */
+#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500U) /*!< Trigger source for SDADC3 */
+#define SDADC_EXT_TRIG_EXTI11 (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
+#define SDADC_EXT_TRIG_EXTI15 (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
/**
* @}
*/
@@ -319,7 +319,7 @@
/** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
* @{
*/
-#define SDADC_INJECTED_DELAY_NONE ((uint32_t)0x00000000) /*!< No delay on injected conversion */
+#define SDADC_INJECTED_DELAY_NONE (0x00000000U) /*!< No delay on injected conversion */
#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
/**
* @}
@@ -328,8 +328,8 @@
/** @defgroup SDADC_MultimodeType SDADC Multimode Type
* @{
*/
-#define SDADC_MULTIMODE_SDADC1_SDADC2 ((uint32_t)0x00000000) /*!< Get conversion values for SDADC1 and SDADC2 */
-#define SDADC_MULTIMODE_SDADC1_SDADC3 ((uint32_t)0x00000001) /*!< Get conversion values for SDADC1 and SDADC3 */
+#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */
+#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
/**
* @}
*/
@@ -337,10 +337,10 @@
/** @defgroup SDADC_ErrorCode SDADC Error Code
* @{
*/
-#define SDADC_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define SDADC_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
-#define SDADC_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
-#define SDADC_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
+#define SDADC_ERROR_NONE (0x00000000U) /*!< No error */
+#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001U) /*!< Overrun occurs during regular conversion */
+#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002U) /*!< Overrun occurs during injected conversion */
+#define SDADC_ERROR_DMA (0x00000003U) /*!< DMA error occurs */
/**
* @}
*/
@@ -501,7 +501,7 @@
((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
((MODE) == SDADC_COMMON_MODE_VDDA))
-#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFF)
+#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
/* Just one channel of the 9 channels can be selected for regular conversion */
#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
@@ -515,7 +515,7 @@
((CHANNEL) == SDADC_CHANNEL_8))
/* Any or all of the 9 channels can be selected for injected conversion */
-#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F01FF))
+#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State and Errors functions
* + Peripheral Control functions
+ * + Peripheral State and Error functions
*
@verbatim
==============================================================================
@@ -24,20 +24,20 @@
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(++) Enable the USARTx interface clock.
(++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
(++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
(++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -92,8 +92,6 @@
[..]
Below the list of most used macros in SMARTCARD HAL driver.
- (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
(+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
(+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
(+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
@@ -137,8 +135,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
@@ -148,14 +144,15 @@
* @{
*/
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-#define SMARTCARD_TXDMA_TIMEOUTVALUE 22000
-#define SMARTCARD_TIMEOUT_VALUE 22000
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000 /*!< SMARTCARD TX or RX enable acknowledge time-out value */
+
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
@@ -168,16 +165,23 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -195,9 +199,9 @@
* @brief Initialization and Configuration functions
*
@verbatim
- ===============================================================================
+ ==============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx
associated to the SmartCard.
@@ -241,12 +245,6 @@
Frame Length is fixed to 8 bits plus parity:
SMARTCARD frame format is given in the following table:
+---------------------------------------------------------------+
- | M bit | PCE bit | SMARTCARD frame |
- |---------------------|-----------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
- or
- +---------------------------------------------------------------+
| M1M0 bits | PCE bit | SMARTCARD frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
@@ -255,9 +253,9 @@
*/
/**
- * @brief Initialize the SMARTCARD mode according to the specified
- * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -269,7 +267,7 @@
return HAL_ERROR;
}
- /* Check the USART associated to the SmartCard */
+ /* Check the USART associated to the SMARTCARD handle */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
@@ -283,8 +281,17 @@
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
- /* Disable the Peripheral */
- __HAL_SMARTCARD_DISABLE(hsmartcard);
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
/* Set the SMARTCARD Communication parameters */
if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
@@ -297,26 +304,16 @@
SMARTCARD_AdvFeatureConfig(hsmartcard);
}
- /* In SmartCard mode, the following bits must be kept cleared:
- - LINEN in the USART_CR2 register,
- - HDSEL and IREN bits in the USART_CR3 register.*/
- hsmartcard->Instance->CR2 &= ~(USART_CR2_LINEN);
- hsmartcard->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
-
- /* set the USART in SMARTCARD mode */
- hsmartcard->Instance->CR3 |= USART_CR3_SCEN;
-
/* Enable the Peripheral */
- __HAL_SMARTCARD_ENABLE(hsmartcard);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
return (SMARTCARD_CheckIdleState(hsmartcard));
}
-
/**
- * @brief DeInitialize the SMARTCARD peripheral.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -328,26 +325,26 @@
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check the USART/UART associated to the SMARTCARD handle */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
/* Disable the Peripheral */
- __HAL_SMARTCARD_DISABLE(hsmartcard);
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- hsmartcard->Instance->CR1 = 0x0;
- hsmartcard->Instance->CR2 = 0x0;
- hsmartcard->Instance->CR3 = 0x0;
- hsmartcard->Instance->RTOR = 0x0;
- hsmartcard->Instance->GTPR = 0x0;
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0U);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0U);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0U);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsmartcard);
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hsmartcard);
@@ -356,12 +353,12 @@
}
/**
- * @brief Initialize the SMARTCARD MSP.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -372,12 +369,12 @@
}
/**
- * @brief DeInitialize the SMARTCARD MSP.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -409,11 +406,11 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (+) There are two modes of transfer:
+ (#) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
+ (++) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
@@ -423,68 +420,119 @@
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (+) Blocking mode APIs are :
+ (#) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
- (+) Non Blocking mode APIs with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (+) Non Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_SMARTCARD_Abort()
+ (++) HAL_SMARTCARD_AbortTransmit()
+ (++) HAL_SMARTCARD_AbortReceive()
+ (++) HAL_SMARTCARD_Abort_IT()
+ (++) HAL_SMARTCARD_AbortTransmit_IT()
+ (++) HAL_SMARTCARD_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_SMARTCARD_AbortCpltCallback()
+ (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Send an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @param Timeout : Timeout duration.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0U;
+
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsmartcard);
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
- while(hsmartcard->TxXferCount > 0)
+
+ while(hsmartcard->TxXferCount > 0U)
{
hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ {
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ }
+
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -500,20 +548,22 @@
}
/**
- * @brief Receive an amount of data in blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @param Timeout : Timeout duration.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0U;
+
/* Check that a Rx process is not already ongoing */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -524,13 +574,18 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
+
/* Check the remain data to be received */
- while(hsmartcard->RxXferCount > 0)
+ while(hsmartcard->RxXferCount > 0U)
{
hsmartcard->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -552,11 +607,11 @@
}
/**
- * @brief Send an amount of data in interrupt mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Send an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
@@ -564,7 +619,7 @@
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -572,21 +627,77 @@
/* Process Locked */
__HAL_LOCK(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
hsmartcard->pTxBuffPtr = pData;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
/* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
@@ -597,19 +708,19 @@
}
/**
- * @brief Receive an amount of data in interrupt mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
- /* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -617,24 +728,48 @@
/* Process Locked */
__HAL_LOCK(hsmartcard);
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
- hsmartcard->RxXferCount = Size;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
- /* Enable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_PE);
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- /* Enable the SMARTCARD Data Register not empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -645,21 +780,21 @@
}
/**
- * @brief Send an amount of data in DMA mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -667,34 +802,37 @@
/* Process Locked */
__HAL_LOCK(hsmartcard);
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
- hsmartcard->TxXferCount = Size;
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
/* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
- /* Set the SMARTCARD error callback */
- hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
- /* Enable the SMARTCARD transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsmartcard->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsmartcard->Instance->TDR, Size);
+ /* Set the DMA abort callback */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
- /* Clear the TC flag in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_TCF);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
return HAL_OK;
}
else
@@ -704,59 +842,458 @@
}
/**
- * @brief Receive an amount of data in DMA mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
- * the received data contain the parity bit (MSB position).
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t *tmp;
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
- /* Check that a Rx process is not already ongoing */
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
{
- return HAL_ERROR;
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
}
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
- hsmartcard->pRxBuffPtr = pData;
- hsmartcard->RxXferSize = Size;
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
- hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Set the SMARTCARD DMA transfer complete callback */
- hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
- /* Set the SMARTCARD DMA error callback */
- hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
- /* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
- return HAL_OK;
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+ }
}
else
{
- return HAL_BUSY;
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
}
/**
@@ -767,70 +1304,179 @@
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* SMARTCARD parity error interrupt occurred -------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_PE) != RESET))
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == RESET)
{
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- /* Set the SMARTCARD states ready to be able to start again the process */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- }
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+ return;
+ }
+ }
- /* SMARTCARD frame error interrupt occurred --------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
+ /* If some errors occur */
+ cr3its = READ_REG(hsmartcard->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
{
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
- /* Set the SMARTCARD states ready to be able to start again the process */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- }
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
- /* SMARTCARD noise error interrupt occurred --------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
- /* Set the SMARTCARD states ready to be able to start again the process */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- }
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsmartcard);
+ }
- /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_ERR) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
- /* Set the SMARTCARD states ready to be able to start again the process */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- }
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+ || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
- /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RTO) != RESET))
- {
- __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
- /* Set the SMARTCARD states ready to be able to start again the process */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- }
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
- /* Call SMARTCARD Error Call back function if need be --------------------------*/
- if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
- {
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
- }
+ /* Abort the SMARTCARD DMA Tx channel */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
- /* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_RXNE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_RXNE) != RESET))
- {
- SMARTCARD_Receive_IT(hsmartcard);
- }
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
/* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_EOB) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_EOB) != RESET))
+ if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
{
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
__HAL_UNLOCK(hsmartcard);
@@ -838,28 +1484,31 @@
/* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
* to be available during HAL_SMARTCARD_RxCpltCallback() processing */
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+ return;
}
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TXE) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TXE) != RESET))
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
SMARTCARD_Transmit_IT(hsmartcard);
+ return;
}
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
{
SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
}
}
/**
- * @brief Tx Transfer completed callback.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -870,8 +1519,8 @@
}
/**
- * @brief Rx Transfer completed callback.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -886,8 +1535,8 @@
}
/**
- * @brief SMARTCARD error callback.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -902,6 +1551,54 @@
}
/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -924,26 +1621,26 @@
* @{
*/
-
/**
* @brief Return the SMARTCARD handle state.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t temp1= 0x00, temp2 = 0x00;
+ /* Return SMARTCARD handle state */
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
temp1 = hsmartcard->gState;
temp2 = hsmartcard->RxState;
-
+
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the SMARTCARD handle error code.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
*/
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -959,257 +1656,19 @@
* @}
*/
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
* @{
*/
/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Tx process is ongoing */
- if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- {
-
- if(hsmartcard->TxXferCount == 0)
- {
- /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- return HAL_OK;
- }
- else
- {
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
- hsmartcard->TxXferCount--;
-
- return HAL_OK;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wrap up transmission in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- /* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
- }
-
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-
- return HAL_OK;
-}
-
-
-/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
- * @retval HAL status
- */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
- /* Check that a Rx process is ongoing */
- if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
-
- if(--hsmartcard->RxXferCount == 0)
- {
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
-
- /* Check if a transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
- }
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
-
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-
- return HAL_OK;
- }
-
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Handle SMARTCARD Communication Timeout.
+ * @brief Configure the SMARTCARD associated USART peripheral.
* @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param Flag: specifies the SMARTCARD flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TXE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_RXNE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief DMA SMARTCARD transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsmartcard->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-}
-
-/**
- * @brief DMA SMARTCARD receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsmartcard->RxXferCount = 0;
-
- /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hsmartcard->RxState to Ready */
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-}
-
-/**
- * @brief DMA SMARTCARD communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsmartcard->RxXferCount = 0;
- hsmartcard->TxXferCount = 0;
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
- HAL_SMARTCARD_ErrorCallback(hsmartcard);
-}
-
-/**
- * @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @retval None
- */
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tmpreg = 0x00000000;
+ uint32_t tmpreg = 0x00000000U;
SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
@@ -1235,19 +1694,10 @@
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
- the bidirectional line to detect a NACK signal in case of parity error.
- Therefore, the receiver block must be enabled as well (RE bit must be set). */
- if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
- && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
- {
- tmpreg |= USART_CR1_RE;
- }
tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
- /* Stop bits are forced to 1.5 (STOP = 11) */
tmpreg = hsmartcard->Init.StopBits;
/* Synchronous mode is activated by default */
tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
@@ -1271,7 +1721,7 @@
MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
/*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
@@ -1284,19 +1734,19 @@
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
- hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_UNDEFINED:
default:
@@ -1309,9 +1759,9 @@
/**
- * @brief Configure the SMARTCARD associated USART peripheral advanced features.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1371,23 +1821,28 @@
}
/**
- * @brief Check the SMARTCARD Idle State.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
{
+ uint32_t tickstart = 0U;
/* Initialize the SMARTCARD ErrorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Check if the Transmitter is enabled */
if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
+ /* Timeout occurred */
return HAL_TIMEOUT;
}
}
@@ -1396,13 +1851,14 @@
if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
+ /* Timeout occurred */
return HAL_TIMEOUT;
}
}
- /* Initialize the SMARTCARD state*/
+ /* Initialize the SMARTCARD states */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1413,9 +1869,422 @@
}
/**
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->TxXferCount = 0U;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if(hsmartcard->TxXferCount == 0U)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ return HAL_OK;
+ }
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ {
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ }
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ {
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0U)
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
@@ -1424,7 +2293,4 @@
* @}
*/
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -55,7 +55,6 @@
*/
/* Exported types ------------------------------------------------------------*/
-
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
*/
@@ -72,12 +71,12 @@
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
- uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
- Only 1.5 stop bits are authorized in SmartCard mode. */
+ uint32_t StopBits; /*!< Specifies the number of stop bits.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
uint16_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
- @note The parity is enabled by default (PCE is forced to 1).
+ @note The parity is enabled by default (PCE is forced to 1U).
Since the WordLength is forced to 8 bits + parity, M is
forced to 1 and the parity bit is the 9th bit. */
@@ -98,9 +97,9 @@
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
- uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler */
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */
- uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time */
+ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
@@ -114,10 +113,10 @@
Block Wait Time (BWT). It is coded over 24 bits. */
uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
- This parameter can be any value from 0x0 to 0xFF */
+ This parameter can be any value from 0x0 to 0xFFU */
uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
- receive and transmit mode). When set to 0, retransmission is
+ receive and transmit mode). When set to 0U, retransmission is
disabled. Otherwise, its maximum value is 7 (before signalling
an error) */
@@ -216,7 +215,7 @@
}HAL_SMARTCARD_StateTypeDef;
/**
- * @brief SMARTCARD handle Structure definition
+ * @brief SMARTCARD handle Structure definition
*/
typedef struct
{
@@ -230,13 +229,13 @@
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
@@ -256,17 +255,17 @@
}SMARTCARD_HandleTypeDef;
-/**
- * @brief SMARTCARD clock sources
- */
+/**
+ * @brief SMARTCARD clock sources
+ */
typedef enum
{
- SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- SMARTCARD_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
}SMARTCARD_ClockSourceTypeDef;
/**
@@ -281,13 +280,13 @@
/** @defgroup SMARTCARD_Error SMARTCARD Error
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020) /*!< Receiver TimeOut error */
+#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
/**
* @}
*/
@@ -295,12 +294,12 @@
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
/**
* @}
*/
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
@@ -312,8 +311,8 @@
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
/**
* @}
*/
@@ -321,9 +320,9 @@
/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
* @{
*/
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
+#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
/**
* @}
*/
@@ -331,8 +330,8 @@
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
-#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define SMARTCARD_POLARITY_LOW (0x00000000U) /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
/**
* @}
*/
@@ -340,8 +339,8 @@
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define SMARTCARD_PHASE_1EDGE (0x00000000U) /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
/**
* @}
*/
@@ -349,8 +348,8 @@
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define SMARTCARD_LASTBIT_DISABLE (0x00000000U) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
@@ -358,8 +357,8 @@
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
* @{
*/
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
/**
* @}
*/
@@ -368,8 +367,8 @@
/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE (0x00000000U) /*!< SMARTCARD NACK transmission enabled */
/**
* @}
*/
@@ -377,23 +376,23 @@
/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
* @{
*/
-#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN)
+#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U) /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
/**
* @}
*/
-/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
-#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001)
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002)
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004)
-#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008)
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010)
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080)
+#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -401,8 +400,8 @@
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV)
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -410,8 +409,8 @@
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV)
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
/**
* @}
*/
@@ -419,8 +418,8 @@
/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV)
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
/**
* @}
*/
@@ -428,8 +427,8 @@
/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
* @{
*/
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP)
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
/**
* @}
*/
@@ -437,8 +436,8 @@
/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
* @{
*/
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS)
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
/**
* @}
*/
@@ -446,8 +445,8 @@
/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
* @{
*/
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE)
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
/**
* @}
*/
@@ -455,8 +454,8 @@
/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
* @{
*/
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000)
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST)
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
/**
* @}
*/
@@ -466,24 +465,24 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define SMARTCARD_FLAG_REACK ((uint32_t)0x00400000)
-#define SMARTCARD_FLAG_TEACK ((uint32_t)0x00200000)
-#define SMARTCARD_FLAG_BUSY ((uint32_t)0x00010000)
-#define SMARTCARD_FLAG_EOBF ((uint32_t)0x00001000)
-#define SMARTCARD_FLAG_RTOF ((uint32_t)0x00000800)
-#define SMARTCARD_FLAG_TXE ((uint32_t)0x00000080)
-#define SMARTCARD_FLAG_TC ((uint32_t)0x00000040)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)0x00000020)
-#define SMARTCARD_FLAG_IDLE ((uint32_t)0x00000010)
-#define SMARTCARD_FLAG_ORE ((uint32_t)0x00000008)
-#define SMARTCARD_FLAG_NE ((uint32_t)0x00000004)
-#define SMARTCARD_FLAG_FE ((uint32_t)0x00000002)
-#define SMARTCARD_FLAG_PE ((uint32_t)0x00000001)
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
/**
* @}
*/
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
@@ -494,34 +493,34 @@
* @{
*/
-#define SMARTCARD_IT_PE ((uint16_t)0x0028)
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727)
-#define SMARTCARD_IT_TC ((uint16_t)0x0626)
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525)
-#define SMARTCARD_IT_IDLE ((uint16_t)0x0424)
+#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060)
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300)
-#define SMARTCARD_IT_NE ((uint16_t)0x0200)
-#define SMARTCARD_IT_FE ((uint16_t)0x0100)
+#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B)
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A)
+#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */
/**
* @}
*/
-/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
* @{
*/
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< Idle line detected clear flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
/**
* @}
*/
@@ -529,7 +528,7 @@
/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
* @{
*/
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
/**
* @}
*/
@@ -537,7 +536,7 @@
/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
* @{
*/
-#define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) /*!< SMARTCARD guard time value LSB position in GTPR register */
+#define SMARTCARD_GTPR_GT_LSB_POS ( 8U) /*!< SMARTCARD guard time value LSB position in GTPR register */
/**
* @}
*/
@@ -545,7 +544,7 @@
/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
* @{
*/
-#define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) /*!< SMARTCARD block length LSB position in RTOR register */
+#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U) /*!< SMARTCARD block length LSB position in RTOR register */
/**
* @}
*/
@@ -553,16 +552,16 @@
/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
* @{
*/
-#define SMARTCARD_IT_MASK ((uint16_t)0x001F) /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /*!< SMARTCARD interruptions flags mask */
/**
* @}
*/
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
* @{
*/
-#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */
/**
* @}
*/
@@ -583,7 +582,7 @@
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- } while(0)
+ } while(0U)
/** @brief Flush the Smartcard Data registers.
* @param __HANDLE__: specifies the SMARTCARD Handle.
@@ -593,20 +592,20 @@
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
- * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
- * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
- * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
- * @arg SMARTCARD_CLEAR_IDLEF: Idle line detected clear flag
- * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
- * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
- * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -644,22 +643,21 @@
/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
- * @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg SMARTCARD_FLAG_BUSY: Busy flag
- * @arg SMARTCARD_FLAG_EOBF: End of block flag
- * @arg SMARTCARD_FLAG_RTOF: Receiver timeout flag
- * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
- * @arg SMARTCARD_FLAG_TC: Transmission complete flag
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
- * @arg SMARTCARD_FLAG_IDLE: Idle line detection flag
- * @arg SMARTCARD_FLAG_ORE: Overrun error flag
- * @arg SMARTCARD_FLAG_NE: Noise error flag
- * @arg SMARTCARD_FLAG_FE: Framing error flag
- * @arg SMARTCARD_FLAG_PE: Parity error flag
+ * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref SMARTCARD_FLAG_BUSY Busy flag
+ * @arg @ref SMARTCARD_FLAG_EOBF End of block flag
+ * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
+ * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
+ * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
+ * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
+ * @arg @ref SMARTCARD_FLAG_NE Noise error flag
+ * @arg @ref SMARTCARD_FLAG_FE Framing error flag
+ * @arg @ref SMARTCARD_FLAG_PE Parity error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
@@ -667,109 +665,101 @@
/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOB: End of block interrupt
- * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
- * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOB: End of block interrupt
- * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
- * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT__: specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOB: End of block interrupt
- * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
- * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_ORE: Overrun error interrupt
- * @arg SMARTCARD_IT_NE: Noise error interrupt
- * @arg SMARTCARD_IT_FE: Framing error interrupt
- * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt
+ * @arg @ref SMARTCARD_IT_NE Noise error interrupt
+ * @arg @ref SMARTCARD_IT_FE Framing error interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT__: specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
- * @arg SMARTCARD_IT_EOB: End of block interrupt
- * @arg SMARTCARD_IT_RTO: Receive timeout interrupt
- * @arg SMARTCARD_IT_TXE: Transmit data register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_ORE: Overrun error interrupt
- * @arg SMARTCARD_IT_NE: Noise error interrupt
- * @arg SMARTCARD_IT_FE: Framing error interrupt
- * @arg SMARTCARD_IT_PE: Parity error interrupt
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__IT__)) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
- * to clear the corresponding interrupt
+ * to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg SMARTCARD_CLEAR_PEF: Parity error clear flag
- * @arg SMARTCARD_CLEAR_FEF: Framing error clear flag
- * @arg SMARTCARD_CLEAR_NEF: Noise detected clear flag
- * @arg SMARTCARD_CLEAR_OREF: OverRun error clear flag
- * @arg SMARTCARD_CLEAR_IDLEF: Idle line detection clear flag
- * @arg SMARTCARD_CLEAR_TCF: Transmission complete clear flag
- * @arg SMARTCARD_CLEAR_RTOF: Receiver timeout clear flag
- * @arg SMARTCARD_CLEAR_EOBF: End of block clear flag
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
- * @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive data flush Request
- * @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+ * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
@@ -789,14 +779,12 @@
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3 to select the USART peripheral
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -810,34 +798,34 @@
* @{
*/
-/** @brief Check the Baud rate range. The maximum Baud Rate is derived from the
- * maximum clock on F3 (i.e. 72 MHz) divided by the oversampling used
- * on the SMARTCARD (i.e. 16).
+/** @brief Check the Baud rate range.
+ * @note The maximum Baud Rate is derived from the maximum clock on F3 (72 MHz)
+ * divided by the oversampling used on the SMARTCARD (i.e. 16).
* @param __BAUDRATE__: Baud rate set by the configuration function.
* @retval Test result (TRUE or FALSE)
*/
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001U)
/** @brief Check the block length range.
* @note The maximum SMARTCARD block length is 0xFF.
* @param __LENGTH__: block length.
* @retval Test result (TRUE or FALSE)
*/
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
/** @brief Check the receiver timeout value.
* @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__: receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFF)
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/** @brief Check the SMARTCARD autoretry counter value.
* @note The maximum number of retransmissions is 0x7.
* @param __COUNT__: number of retransmissions.
* @retval Test result (TRUE or FALSE)
*/
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7)
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
/**
* @brief Ensure that SMARTCARD frame length is valid.
@@ -867,7 +855,7 @@
* @param __MODE__: SMARTCARD communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
/**
* @brief Ensure that SMARTCARD frame polarity is valid.
@@ -1001,15 +989,16 @@
#include "stm32f3xx_hal_smartcard_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
- * @{
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
+
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -1019,29 +1008,42 @@
* @}
*/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
-/* IO operation functions *****************************************************/
+
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
-/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
* @{
*/
-/* Peripheral State and Error functions ***************************************/
+
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,14 +2,13 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief SMARTCARD HAL module driver.
- *
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
- * + Initialization and de-initialization function
- * + Peripheral Control function
+ * + Initialization and de-initialization functions
+ * + Peripheral Control functions
*
*
@verbatim
@@ -59,8 +58,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
@@ -69,6 +66,7 @@
* @brief SMARTCARD Extension HAL module driver
* @{
*/
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -77,7 +75,7 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
+/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
* @{
*/
@@ -134,20 +132,27 @@
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
- /* Set the USART RTOEN bit */
- hsmartcard->Instance->CR2 |= USART_CR2_RTOEN;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
-
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
@@ -159,29 +164,28 @@
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Process Locked */
- __HAL_LOCK(hsmartcard);
-
- hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
- /* Clear the USART RTOEN bit */
- hsmartcard->Instance->CR2 &= ~(USART_CR2_RTOEN);
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
- hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- return HAL_OK;
-}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
-/**
- * @}
- */
-
-/**
- * @}
- */
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
/**
* @}
@@ -193,4 +197,12 @@
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smartcard_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
@@ -56,20 +56,20 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Extended_Exported_Macros SMARTCARDEx Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{
*/
-
-/** @brief Reports the SMARTCARD clock source.
- * @param __HANDLE__: specifies the SMARTCARD Handle
- * @param __CLOCKSOURCE__ : output variable
+
+/** @brief Report the SMARTCARD clock source.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __CLOCKSOURCE__: output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -104,9 +104,9 @@
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#else
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -175,9 +175,9 @@
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#endif
-
+
/**
* @}
*/
@@ -188,8 +188,9 @@
*/
/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
@@ -199,8 +200,6 @@
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-/* Peripheral State and Error functions ***************************************/
-
/**
* @}
*/
@@ -216,7 +215,7 @@
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smbus.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smbus.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief SMBUS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
@@ -13,7 +13,7 @@
* + Peripheral State and Errors functions
*
@verbatim
- ==============================================================================
+ ==============================================================================
##### How to use this driver #####
==============================================================================
[..]
@@ -41,8 +41,8 @@
(#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
- (#) For SMBUS IO operations, only one mode of operations is available within this driver :
-
+ (#) For SMBUS IO operations, only one mode of operations is available within this driver
+
*** Interrupt mode IO operation ***
===================================
[..]
@@ -141,22 +141,22 @@
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMBUS_Private_Define SMBUS Private Constants
- * @{
- */
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
-#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /*!< 10 s */
-#define HAL_TIMEOUT_BUSY ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_DIR ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_RXNE ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_STOPF ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_TC ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_TCR ((uint32_t)25) /*!< 25 ms */
-#define HAL_TIMEOUT_TXIS ((uint32_t)25) /*!< 25 ms */
-#define MAX_NBYTE_SIZE 255
+ * @{
+ */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
+#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define MAX_NBYTE_SIZE 255U
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -170,6 +170,8 @@
static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
@@ -273,16 +275,16 @@
/* Configure SMBUSx: Own Address1 and ack own address1 mode */
hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if(hsmbus->Init.OwnAddress1 != 0)
+ if(hsmbus->Init.OwnAddress1 != 0U)
{
if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
- }
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
+ }
else /* SMBUS_ADDRESSINGMODE_10BIT */
- {
- hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
- }
+ {
+ hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1);
+ }
}
/*---------------------------- SMBUSx CR2 Configuration ------------------------*/
@@ -297,7 +299,7 @@
/*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
/* Configure SMBUSx: Dual mode and Own Address2 */
- hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8));
+ hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
/*---------------------------- SMBUSx CR1 Configuration ------------------------*/
/* Configure SMBUSx: Generalcall and NoStretch mode */
@@ -357,11 +359,11 @@
/**
* @brief Initialize the SMBUS MSP.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
- __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
@@ -373,11 +375,11 @@
/**
* @brief DeInitialize the SMBUS MSP.
- * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval None
*/
- __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
@@ -477,7 +479,7 @@
{
hsmbus->XferSize = Size;
}
-
+
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
@@ -488,13 +490,17 @@
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
{
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
}
@@ -578,13 +584,17 @@
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
{
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
+ /* Handle Transfer */
SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
}
}
@@ -641,7 +651,7 @@
/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -682,7 +692,7 @@
if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -704,10 +714,12 @@
/* Prepare transfer parameters */
hsmbus->pBuffPtr = pData;
- hsmbus->XferSize = Size;
hsmbus->XferCount = Size;
hsmbus->XferOptions = XferOptions;
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
if(Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
@@ -720,12 +732,12 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
{
- SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
@@ -773,7 +785,7 @@
if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -798,19 +810,22 @@
hsmbus->XferSize = Size;
hsmbus->XferCount = Size;
hsmbus->XferOptions = XferOptions;
-
+
+ /* Convert OTHER_xxx XferOptions if any */
+ SMBUS_ConvertOtherXferOptions(hsmbus);
+
/* Set NBYTE to receive */
/* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
{
- SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else
{
- SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
}
/* Clear ADDR flag after prepare the transfer parameters */
@@ -922,9 +937,9 @@
*/
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
- __IO uint32_t SMBUS_Trials = 0;
+ __IO uint32_t SMBUS_Trials = 0U;
if(hsmbus->State == HAL_SMBUS_STATE_READY)
{
@@ -951,7 +966,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1043,7 +1058,7 @@
*/
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
- uint32_t tmpisrvalue = 0;
+ uint32_t tmpisrvalue = 0U;
/* Use a local variable to store the current ISR flags */
/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
@@ -1179,13 +1194,13 @@
* the configuration information for the specified SMBUS.
* @retval None
*/
- __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
*/
}
@@ -1201,7 +1216,7 @@
UNUSED(hsmbus);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file
*/
}
@@ -1210,13 +1225,13 @@
* the configuration information for the specified SMBUS.
* @retval None
*/
- __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
*/
}
@@ -1232,7 +1247,7 @@
UNUSED(hsmbus);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
+ the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file
*/
}
@@ -1267,7 +1282,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
- /* NOTE : This function should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
*/
}
@@ -1278,7 +1293,7 @@
* the configuration information for the specified SMBUS.
* @retval None
*/
- __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
+__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmbus);
@@ -1300,7 +1315,7 @@
##### Peripheral State and Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1310,7 +1325,7 @@
/**
* @brief Return the SMBUS handle state.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
- * the configuration information for the specified SMBUS.
+ * the configuration information for the specified SMBUS.
* @retval HAL state
*/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
@@ -1320,10 +1335,10 @@
}
/**
- * @brief Return the SMBUS error code.
+* @brief Return the SMBUS error code.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @retval SMBUS Error Code
+* @retval SMBUS Error Code
*/
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
{
@@ -1339,7 +1354,7 @@
*/
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
+ * @brief Data transfers Private functions
* @{
*/
@@ -1373,7 +1388,6 @@
}
else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
{
-
/* Call the corresponding callback to inform upper layer of End of Transfer */
if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
@@ -1403,6 +1417,19 @@
}
else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
+ /* Store Last receive data if any */
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+ if((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
@@ -1437,7 +1464,7 @@
}
else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
{
- if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
{
DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
@@ -1459,7 +1486,7 @@
}
}
}
- else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
+ else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
{
/* Call TxCpltCallback() if no stop mode is set */
if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
@@ -1493,7 +1520,7 @@
}
else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
{
- if(hsmbus->XferCount == 0)
+ if(hsmbus->XferCount == 0U)
{
/* Specific use case for Quick command */
if(hsmbus->pBuffPtr == NULL)
@@ -1548,8 +1575,8 @@
*/
static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
{
- uint8_t TransferDirection = 0;
- uint16_t SlaveAddrCode = 0;
+ uint8_t TransferDirection = 0U;
+ uint16_t SlaveAddrCode = 0U;
/* Process Locked */
__HAL_LOCK(hsmbus);
@@ -1560,7 +1587,7 @@
/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hsmbus->XferCount == 0)
+ if(hsmbus->XferCount == 0U)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1582,7 +1609,7 @@
/* Disable RX/TX Interrupts, keep only ADDR Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
@@ -1617,15 +1644,15 @@
hsmbus->XferSize--;
hsmbus->XferCount--;
- if(hsmbus->XferCount == 1)
+ if(hsmbus->XferCount == 1U)
{
/* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
- else if(hsmbus->XferCount == 0)
+ else if(hsmbus->XferCount == 0U)
{
/* Last Byte is received, disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
@@ -1643,7 +1670,7 @@
else
{
/* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -1651,17 +1678,17 @@
}
else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
+ if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
{
if(hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
@@ -1677,9 +1704,9 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hsmbus->XferCount > 0)
+ if(hsmbus->XferCount > 0U)
{
/* Write data to TXDR */
hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
@@ -1687,7 +1714,7 @@
hsmbus->XferSize--;
}
- if(hsmbus->XferCount == 0)
+ if(hsmbus->XferCount == 0U)
{
/* Last Byte is Transmitted */
/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
@@ -1708,6 +1735,19 @@
{
if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
+ /* Store Last receive data if any */
+ if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
+ /* Read data from RXDR */
+ (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+
+ if((hsmbus->XferSize > 0U))
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ }
+
/* Disable RX and TX Interrupts */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
@@ -1726,7 +1766,7 @@
/* Clear ADDR flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
- hsmbus->XferOptions = 0;
+ hsmbus->XferOptions = 0U;
hsmbus->PreviousState = hsmbus->State;
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1752,7 +1792,7 @@
*/
static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
{
- uint32_t tmpisr = 0;
+ uint32_t tmpisr = 0U;
if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
{
@@ -1794,7 +1834,7 @@
*/
static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
{
- uint32_t tmpisr = 0;
+ uint32_t tmpisr = 0U;
if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
{
@@ -1880,7 +1920,7 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
hsmbus->State= HAL_SMBUS_STATE_READY;
@@ -1900,7 +1940,7 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
hsmbus->State= HAL_SMBUS_STATE_READY;
@@ -1938,7 +1978,7 @@
*/
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -1952,12 +1992,51 @@
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
/* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request);
/* update CR2 register */
hsmbus->Instance->CR2 = tmpreg;
}
+
+/**
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+{
+ /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME */
+ if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
+ else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
+ else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
+ }
+ /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
+ else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ {
+ hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
+ }
+}
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smbus.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_smbus.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_SMBUS_H
@@ -57,8 +57,8 @@
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
* @{
- */
-
+ */
+
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
* @{
@@ -99,49 +99,49 @@
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
+ (Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
} SMBUS_InitTypeDef;
-/**
+/**
* @}
*/
/** @defgroup HAL_state_definition HAL state definition
* @brief HAL State definition
* @{
- */
-#define HAL_SMBUS_STATE_RESET ((uint32_t)0x00000000) /*!< SMBUS not yet initialized or disabled */
-#define HAL_SMBUS_STATE_READY ((uint32_t)0x00000001) /*!< SMBUS initialized and ready for use */
-#define HAL_SMBUS_STATE_BUSY ((uint32_t)0x00000002) /*!< SMBUS internal process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX ((uint32_t)0x00000012) /*!< Master Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX ((uint32_t)0x00000022) /*!< Master Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX ((uint32_t)0x00000032) /*!< Slave Data Transmission process is ongoing */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX ((uint32_t)0x00000042) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT ((uint32_t)0x00000003) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR ((uint32_t)0x00000004) /*!< Reception process is ongoing */
-#define HAL_SMBUS_STATE_LISTEN ((uint32_t)0x00000008) /*!< Address Listen Mode is ongoing */
-/**
+ */
+#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
+#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
+#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
+#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
+#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
+#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
+/**
* @}
*/
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
* @brief SMBUS Error Code definition
* @{
- */
-#define HAL_SMBUS_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_SMBUS_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
-#define HAL_SMBUS_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
-#define HAL_SMBUS_ERROR_ACKF ((uint32_t)0x00000004) /*!< ACKF error */
-#define HAL_SMBUS_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
-#define HAL_SMBUS_ERROR_HALTIMEOUT ((uint32_t)0x00000010) /*!< Timeout error */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT ((uint32_t)0x00000020) /*!< Bus Timeout error */
-#define HAL_SMBUS_ERROR_ALERT ((uint32_t)0x00000040) /*!< Alert error */
-#define HAL_SMBUS_ERROR_PECERR ((uint32_t)0x00000080) /*!< PEC error */
-/**
+ */
+#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
+#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
+#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
+#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
+#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+/**
* @}
*/
-
+
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
* @{
@@ -185,8 +185,8 @@
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
-#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
-#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
+#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
+#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
@@ -194,8 +194,8 @@
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
* @{
*/
-#define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
-#define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
+#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
+#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
@@ -204,43 +204,43 @@
* @{
*/
-#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
-#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
+#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
+#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
-/** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
* @{
*/
-#define SMBUS_OA2_NOMASK ((uint8_t)0x00)
-#define SMBUS_OA2_MASK01 ((uint8_t)0x01)
-#define SMBUS_OA2_MASK02 ((uint8_t)0x02)
-#define SMBUS_OA2_MASK03 ((uint8_t)0x03)
-#define SMBUS_OA2_MASK04 ((uint8_t)0x04)
-#define SMBUS_OA2_MASK05 ((uint8_t)0x05)
-#define SMBUS_OA2_MASK06 ((uint8_t)0x06)
-#define SMBUS_OA2_MASK07 ((uint8_t)0x07)
+#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
+#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
+#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
+#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
+#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
+#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
+#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
+#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
-/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
-#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000)
-#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
+#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
+#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
-#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
-#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
+#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
@@ -248,8 +248,8 @@
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
-#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000)
-#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
+#define SMBUS_PEC_DISABLE (0x00000000U)
+#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
@@ -257,18 +257,18 @@
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
* @{
*/
-#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
/**
* @}
*/
-/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
* @{
*/
-#define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000)
+#define SMBUS_SOFTEND_MODE (0x00000000U)
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
@@ -280,7 +280,7 @@
* @{
*/
-#define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000)
+#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP I2C_CR2_STOP
#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
@@ -288,16 +288,28 @@
* @}
*/
-/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
* @{
*/
-#define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE))
+/* List of XferOptions in usage of :
+ * 1- Restart condition when direction change
+ * 2- No Restart condition in other use cases
+ */
+#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
+#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
+#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
+#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
/**
* @}
*/
@@ -308,17 +320,17 @@
* - XXXXXXXX : Interrupt control mask
* @{
*/
-#define SMBUS_IT_ERRI I2C_CR1_ERRIE
-#define SMBUS_IT_TCI I2C_CR1_TCIE
-#define SMBUS_IT_STOPI I2C_CR1_STOPIE
-#define SMBUS_IT_NACKI I2C_CR1_NACKIE
-#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
-#define SMBUS_IT_RXI I2C_CR1_RXIE
-#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
-#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
-#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
-#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
+#define SMBUS_IT_ERRI I2C_CR1_ERRIE
+#define SMBUS_IT_TCI I2C_CR1_TCIE
+#define SMBUS_IT_STOPI I2C_CR1_STOPIE
+#define SMBUS_IT_NACKI I2C_CR1_NACKIE
+#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
+#define SMBUS_IT_RXI I2C_CR1_RXIE
+#define SMBUS_IT_TXI I2C_CR1_TXIE
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
+#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
* @}
*/
@@ -330,22 +342,22 @@
* @{
*/
-#define SMBUS_FLAG_TXE I2C_ISR_TXE
-#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
-#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
-#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
-#define SMBUS_FLAG_AF I2C_ISR_NACKF
-#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
-#define SMBUS_FLAG_TC I2C_ISR_TC
-#define SMBUS_FLAG_TCR I2C_ISR_TCR
-#define SMBUS_FLAG_BERR I2C_ISR_BERR
-#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
-#define SMBUS_FLAG_OVR I2C_ISR_OVR
-#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
-#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
-#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
-#define SMBUS_FLAG_DIR I2C_ISR_DIR
+#define SMBUS_FLAG_TXE I2C_ISR_TXE
+#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
+#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
+#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
+#define SMBUS_FLAG_AF I2C_ISR_NACKF
+#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
+#define SMBUS_FLAG_TC I2C_ISR_TC
+#define SMBUS_FLAG_TCR I2C_ISR_TCR
+#define SMBUS_FLAG_BERR I2C_ISR_BERR
+#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
+#define SMBUS_FLAG_OVR I2C_ISR_OVR
+#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
+#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
+#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
+#define SMBUS_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
@@ -399,7 +411,7 @@
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMBUS Handle.
- * @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
+ * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
@@ -436,7 +448,7 @@
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF)
+#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
@@ -521,6 +533,7 @@
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
((MODE) == SMBUS_AUTOEND_MODE) || \
((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
@@ -538,7 +551,13 @@
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
+ IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
@@ -546,8 +565,8 @@
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
-#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
+#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
@@ -555,31 +574,22 @@
#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
-#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
/**
* @}
*/
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
- * @{
- */
-/* Private functions are defined in stm32f3xx_hal_smbus.c file */
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
+ * @{
+ */
+
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
@@ -591,13 +601,22 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @{
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup Blocking_mode_Polling Blocking mode Polling
+ * @{
+ */
+/******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+/**
+ * @}
*/
-/* IO operation functions *****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
+ * @{
+ */
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
@@ -609,7 +628,13 @@
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
+/**
+ * @}
+ */
+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
@@ -626,8 +651,8 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
+ * @{
+ */
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
@@ -641,7 +666,14 @@
* @}
*/
-
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
+ * @{
+ */
+/* Private functions are defined in stm32f3xx_hal_smbus.c file */
+/**
+ * @}
+ */
/**
* @}
@@ -650,10 +682,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_spi.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -31,12 +31,12 @@
(+++) Configure the SPIx interrupt priority
(+++) Enable the NVIC SPI IRQ handle
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
+ (+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -52,13 +52,79 @@
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-
- @note
- (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
+ [..]
+ The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
+ modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
+ maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
+ the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
@endverbatim
+
+ Additional table :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
+
******************************************************************************
* @attention
*
@@ -89,40 +155,6 @@
******************************************************************************
*/
-/*
- Additional Table:
-
- Using the HAL it is not possible to reach all supported SPI frequency with the differents
- the following table resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
- +-----------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |--------------------|--------------------|--------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |=========================================================================================|
- | T | Polling | Fcpu/4 | Fcpu/8 | NA | NA | NA | NA |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA |
- | R |----------------|----------|---------|----------|---------|----------|---------|
- | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA |
- |=========|================|==========|=========|==========|=========|==========|=========|
- | | Polling | Fcpu/4 | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 |
- | |----------------|----------|---------|----------|---------|----------|---------|
- | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/2 | Fcpu/16 | Fcpu/2 | Fcpu/16 |
- |=========|================|==========|=========|==========|=========|==========|=========|
- | | Polling | Fcpu/8 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 |
- | |----------------|----------|---------|----------|---------|----------|---------|
- | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 |
- | X |----------------|----------|---------|----------|---------|----------|---------|
- | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 |
- +-----------------------------------------------------------------------------------------+
- @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling
-
-*/
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -141,7 +173,7 @@
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
-#define SPI_DEFAULT_TIMEOUT 50
+#define SPI_DEFAULT_TIMEOUT 100U
/**
* @}
*/
@@ -159,31 +191,39 @@
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
@@ -235,7 +275,7 @@
uint32_t frxth;
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
@@ -245,18 +285,28 @@
assert_param(IS_SPI_MODE(hspi->Init.Mode));
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
+#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
- assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
-
- if(hspi->State == HAL_SPI_STATE_RESET)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
@@ -271,7 +321,7 @@
__HAL_SPI_DISABLE(hspi);
/* Align by default the rs fifo threshold on the data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
}
@@ -281,17 +331,17 @@
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
- if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
/* Align the CRC Length on the data size */
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
{
/* CRC Length aligned on the data size : value set by default */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
}
@@ -301,35 +351,46 @@
}
}
- /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit, CRC calculation state, CRC Length */
- hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
-
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ Communication speed, First bit and CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
+#if (USE_SPI_CRC != 0U)
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- hspi->Instance->CR1|= SPI_CR1_CRCL;
+ hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
-
- /* Configure : NSS management */
- /* Configure : Rx Fifo Threshold */
- hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
- hspi->Init.DataSize ) | frxth;
-
- /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+#endif /* USE_SPI_CRC */
+
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+ hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
+
+#if (USE_SPI_CRC != 0U)
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
- hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
-
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
+
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitialize the SPI peripheral.
+ * @brief De-Initialize the SPI peripheral.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
@@ -337,13 +398,14 @@
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check SPI Instance parameter */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
hspi->State = HAL_SPI_STATE_BUSY;
/* Disable the SPI Peripheral Clock */
@@ -355,6 +417,7 @@
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
+ /* Release Lock */
__HAL_UNLOCK(hspi);
return HAL_OK;
@@ -371,13 +434,13 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_MspInit should be implemented in the user file
*/
}
/**
- * @brief DeInitialize the SPI MSP.
+ * @brief De-Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -440,21 +503,25 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -463,49 +530,61 @@
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
/* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0)
+ while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount--;
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -516,28 +595,43 @@
/* Transmit data in 8 Bit mode */
else
{
- while (hspi->TxXferCount > 0)
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ /* write on the data register in packing mode */
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ hspi->TxXferCount--;
+ }
+ }
+ while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- if(hspi->TxXferCount > 1)
+ if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
hspi->TxXferCount--;
}
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -545,26 +639,27 @@
}
}
}
-
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
-
+
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -587,52 +682,63 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- __IO uint16_t tmpreg;
- uint32_t tickstart = HAL_GetTick();
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the TransmitReceive process */
- /* Process Locked */
- return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
hspi->RxXferCount--;
}
+#endif /* USE_SPI_CRC */
/* Set the Rx Fido threshold */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -643,35 +749,37 @@
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Configure communication direction 1Line and enabled SPI if needed */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
- if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ /* Receive data in 8 Bit mode */
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
{
/* Transfer loop */
- while(hspi->RxXferCount > 0)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
- (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+ (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -682,19 +790,19 @@
else
{
/* Transfer loop */
- while(hspi->RxXferCount > 0)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -703,14 +811,15 @@
}
}
+#if (USE_SPI_CRC != 0U)
/* Handle the CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* freeze the CRC before the latest data */
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Read the latest data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
errorcode = HAL_TIMEOUT;
@@ -718,26 +827,26 @@
}
/* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)pData) = hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
- *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
}
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- /* Flag Error*/
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
/* To avoid GCC warning */
@@ -749,12 +858,12 @@
/* To avoid GCC warning */
UNUSED(tmpreg);
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
@@ -764,21 +873,24 @@
}
}
}
-
+#endif /* USE_SPI_CRC */
+
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -799,46 +911,72 @@
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
{
-__IO uint16_t tmpreg;
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Set the Rx Fido threshold */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -850,44 +988,56 @@
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
hspi->TxXferCount--;
-
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
}
/* Check RXNE flag */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -897,44 +1047,62 @@
/* Transmit and Receive data in 8 Bit mode */
else
{
- while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ {
+ if (hspi->TxXferCount > 1U)
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
+ }
+ else
+ {
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ hspi->TxXferCount--;
+ }
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* check TXE flag */
- if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- if(hspi->TxXferCount > 1)
+ if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
hspi->TxXferCount--;
}
-
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount <= 1)
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U)
{
/* set fiforxthresold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -942,11 +1110,13 @@
}
else
{
- (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
hspi->RxXferCount--;
}
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -954,19 +1124,20 @@
}
}
+#if (USE_SPI_CRC != 0U)
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
-
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
/* To avoid GCC warning */
@@ -978,12 +1149,12 @@
/* To avoid GCC warning */
UNUSED(tmpreg);
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
@@ -995,22 +1166,23 @@
}
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
errorcode = HAL_ERROR;
}
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -1032,36 +1204,40 @@
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- /* prepare the transfer */
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
- hspi->RxISR = NULL;
-
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
+
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->TxISR = SPI_TxISR_16BIT;
}
@@ -1071,23 +1247,25 @@
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1110,84 +1288,87 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- /* Configure communication */
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this we call the TransmitReceive process */
- return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
- }
-
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
- else
- {
- hspi->CRCSize = 0;
- }
-
- hspi->TxISR = NULL;
- /* check the data size to adapt Rx threshold and the set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- /* set fiforxthresold according the reception data length: 16 bit */
+ /* Set fiforxthresold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- /* set fiforxthresold according the reception data length: 8 bit */
+ /* Set fiforxthresold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_8BIT;
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
SPI_RESET_CRC(hspi);
}
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1210,75 +1391,84 @@
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- if(!((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- hspi->CRCSize = 0;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
-
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
SPI_RESET_CRC(hspi);
}
-
- /* check if packing mode is enabled and if there is more than 2 data to receive */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+ else
{
- /* set fiforxthresold according the reception data length: 16 bit */
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if packing mode is enabled and if there is more than 2 data to receive */
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+ {
+ /* Set fiforxthresold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8 bit */
+ /* Set fiforxthresold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -1286,7 +1476,7 @@
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1309,43 +1499,55 @@
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
@@ -1356,33 +1558,39 @@
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- /* packing mode is enabled only if the DMA setting is HALWORD */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ /* Packing mode is enabled only if the DMA setting is HALWORD */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Check the even/odd of the data size + crc if enabled */
- if((hspi->TxXferCount & 0x1) == 0)
+ if ((hspi->TxXferCount & 0x1U) == 0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
}
}
- /* Enable the Tx DMA channel */
+ /* Enable the Tx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1394,6 +1602,7 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
+ * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
@@ -1404,70 +1613,100 @@
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check rx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+
+ /* check tx dma handle */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the TransmitReceive process */
- return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
- }
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
+#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-
- /* packing mode management is enabled by the DMA settings */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+#endif /* USE_SPI_CRC */
+
+#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
+ /* Packing mode management is enabled by the DMA settings */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Restriction the DMA data received is not allowed in this mode */
errorcode = HAL_ERROR;
goto error;
}
+#endif
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthresold according the reception data length: 16bit */
+ /* Set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8bit */
+ /* Set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ {
+ /* set fiforxthresold according the reception data length: 16bit */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
+
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
+ {
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
+ }
+ else
+ {
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
+ }
+ }
}
/* Set the SPI RxDMA Half transfer complete callback */
@@ -1479,19 +1718,25 @@
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Enable the Rx DMA channel */
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
error:
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1508,33 +1753,44 @@
* @param Size: amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* check rx & tx dma handles */
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
+ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- if(!((hspi->State == HAL_SPI_STATE_READY) ||
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if (!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- /* check if the transmit Receive function is not called by a receive master */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
@@ -1543,99 +1799,119 @@
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- /* Reset CRC Calculation + increase the rxsize */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
+#endif /* USE_SPI_CRC */
+
+
+#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx)
+ /* packing mode management is enabled by the DMA settings */
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ {
+ /* Restriction the DMA data received is not allowed in this mode */
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+#endif
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
- /* the packing mode management is enabled by the DMA settings according the spi data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ /* The packing mode management is enabled by the DMA settings according the spi data size */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8bit */
+ /* Set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- if((hspi->TxXferSize & 0x1) == 0x0)
+ if ((hspi->TxXferSize & 0x1U) == 0x0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1;
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
}
}
- if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* set fiforxthresold according the reception data length: 16bit */
+ /* Set fiforxthresold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- if((hspi->RxXferCount & 0x1) == 0x0 )
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1;
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
}
}
}
- /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
- reception request (RXNE) */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
/* Set the SPI Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
}
else
{
- /* Set the SPI Rx DMA Half transfer complete callback */
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
- /* Enable the Rx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
-
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Enable the Tx DMA channel */
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1647,6 +1923,357 @@
}
/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+ __IO uint32_t count, resetcount;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+ resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ count = resetcount;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ /* Wait HAL_SPI_STATE_ABORT state */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ /* Reset Timeout Counter */
+ count = resetcount;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+ }
+
+ return errorcode;
+}
+
+/**
* @brief Pause the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
@@ -1700,13 +2327,13 @@
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
*/
- /* Abort the SPI DMA tx channel */
- if(hspi->hdmatx != NULL)
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
{
HAL_DMA_Abort(hspi->hdmatx);
}
- /* Abort the SPI DMA rx channel */
- if(hspi->hdmarx != NULL)
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
{
HAL_DMA_Abort(hspi->hdmarx);
}
@@ -1729,54 +2356,86 @@
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
- if(((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ if (((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
- /* SPI in mode Transmitter ---------------------------------------------------*/
- if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
- /* SPI in Error Treatment ---------------------------------------------------*/
- if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
{
- /* SPI Overrun error interrupt occurred -------------------------------------*/
- if((itflag & SPI_FLAG_OVR) != RESET)
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((itflag & SPI_FLAG_OVR) != RESET)
{
- if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
else
{
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
return;
}
}
- /* SPI Mode Fault error interrupt occurred -------------------------------------*/
- if((itflag & SPI_FLAG_MODF) != RESET)
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
- /* SPI Frame error interrupt occurred ----------------------------------------*/
- if((itflag & SPI_FLAG_FRE) != RESET)
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmarx);
+ }
+ /* Abort the SPI DMA Tx channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
return;
}
}
@@ -1883,7 +2542,7 @@
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -1897,6 +2556,21 @@
}
/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -1935,6 +2609,7 @@
*/
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI ErrorCode */
return hspi->ErrorCode;
}
@@ -1942,13 +2617,12 @@
* @}
*/
-
/**
* @}
*/
/** @addtogroup SPI_Private_Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
@@ -1960,29 +2634,37 @@
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- hspi->TxXferCount = 0;
+ hspi->TxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -1999,22 +2681,33 @@
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
- __IO uint16_t tmpreg;
-
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
tmpreg = hspi->Instance->DR;
/* To avoid GCC warning */
@@ -2026,12 +2719,12 @@
/* To avoid GCC warning */
UNUSED(tmpreg);
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
/* To avoid GCC warning */
@@ -2039,27 +2732,30 @@
}
}
}
+#endif /* USE_SPI_CRC */
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- hspi->RxXferCount = 0;
+ hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -2070,65 +2766,81 @@
/**
* @brief DMA SPI transmit receive process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
- __IO int16_t tmpreg;
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+#if (USE_SPI_CRC != 0U)
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
{
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
+ /* Read CRC to Flush DR and RXNE flag */
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
/* To avoid GCC warning */
UNUSED(tmpreg);
}
else
{
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
+ /* Read CRC to Flush DR and RXNE flag */
tmpreg = hspi->Instance->DR;
/* To avoid GCC warning */
UNUSED(tmpreg);
}
}
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
-
+
/* Disable Rx/Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -2139,13 +2851,13 @@
/**
* @brief DMA SPI half transmit process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_TxHalfCpltCallback(hspi);
}
@@ -2158,43 +2870,183 @@
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_RxHalfCpltCallback(hspi);
}
/**
* @brief DMA SPI half transmit receive process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
HAL_SPI_TxRxHalfCpltCallback(hspi);
}
/**
* @brief DMA SPI communication error callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
@@ -2203,12 +3055,12 @@
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in packing mode */
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount == 1)
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U)
{
/* set fiforxthresold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -2222,25 +3074,28 @@
}
/* check end of the reception */
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if(hspi->TxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2249,24 +3104,29 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
/* To avoid GCC warning */
UNUSED(tmpreg);
hspi->CRCSize--;
/* check end of the reception */
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if(hspi->TxXferCount == 0)
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#endif /* USE_SPI_CRC */
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
@@ -2277,11 +3137,11 @@
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in packing Bit mode */
- if(hspi->TxXferCount >= 2)
+ if (hspi->TxXferCount >= 2U)
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->TxXferCount -= 2U;
}
/* Transmit data in 8 Bit mode */
else
@@ -2291,18 +3151,23 @@
}
/* check the end of the transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ /* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
+#endif /* USE_SPI_CRC */
+
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2318,28 +3183,31 @@
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2349,7 +3217,11 @@
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = hspi->Instance->DR;
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
/* To avoid GCC warning */
UNUSED(tmpreg);
@@ -2358,6 +3230,7 @@
SPI_CloseRxTx_ISR(hspi);
}
+#endif /* USE_SPI_CRC */
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
@@ -2373,24 +3246,30 @@
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ /* Set CRC Next Bit to send CRC */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
return;
}
+#endif /* USE_SPI_CRC */
+
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
+#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 8-bit receive in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2399,17 +3278,22 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
/* To avoid GCC warning */
UNUSED(tmpreg);
hspi->CRCSize--;
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
SPI_CloseRx_ISR(hspi);
}
}
+#endif /* USE_SPI_CRC */
/**
* @brief Manage the receive 8-bit in Interrupt context.
@@ -2422,23 +3306,28 @@
*hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
hspi->RxXferCount--;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-
- if(hspi->RxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_8BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
+#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive in Interrupt context.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2447,9 +3336,11 @@
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg;
-
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
tmpreg = hspi->Instance->DR;
+
/* To avoid GCC warning */
UNUSED(tmpreg);
@@ -2458,6 +3349,7 @@
SPI_CloseRx_ISR(hspi);
}
+#endif /* USE_SPI_CRC */
/**
* @brief Manage the 16-bit receive in Interrupt context.
@@ -2471,19 +3363,23 @@
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-
- if(hspi->RxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
}
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
@@ -2499,13 +3395,15 @@
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
@@ -2523,13 +3421,15 @@
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
@@ -2537,21 +3437,21 @@
/**
* @brief Handle SPI Communication Timeout.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag : SPI flag to check
- * @param State : flag state to check
- * @param Timeout : Timeout duration
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param State: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
- while((hspi->Instance->SR & Flag) != State)
+ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2560,19 +3460,20 @@
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -2588,29 +3489,30 @@
/**
* @brief Handle SPI FIFO Communication Timeout.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo : Fifo to check
- * @param State : Fifo state to check
- * @param Timeout : Timeout duration
+ * the configuration information for SPI module.
+ * @param Fifo: Fifo to check
+ * @param State: Fifo state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
{
__IO uint8_t tmpreg;
- uint32_t tickstart = HAL_GetTick();
-
- while((hspi->Instance->SR & Fifo) != State)
+
+ while ((hspi->Instance->SR & Fifo) != State)
{
- if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
}
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2619,14 +3521,15 @@
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -2648,30 +3551,33 @@
* @brief Handle the check of the RX transaction complete.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout : Timeout duration
- * @retval None.
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
*/
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
-
+
/* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Empty the FRLVL fifo */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
}
@@ -2679,22 +3585,24 @@
}
/**
- * @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi: SPI handle
- * @param Timeout : Timeout duration
+ * @brief Handle the check of the RXTX or TX transaction complete.
+ * @param hspi: SPI handle
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
*/
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
/* Control if the TX fifo is empty */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
/* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
return HAL_OK;
@@ -2708,28 +3616,35 @@
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->State = HAL_SPI_STATE_READY;
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
HAL_SPI_ErrorCallback(hspi);
}
else
{
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_RxCpltCallback(hspi);
@@ -2745,7 +3660,9 @@
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
+#if (USE_SPI_CRC != 0U)
}
+#endif /* USE_SPI_CRC */
}
/**
@@ -2756,34 +3673,38 @@
*/
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
- }
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- HAL_SPI_ErrorCallback(hspi);
+ HAL_SPI_RxCpltCallback(hspi);
}
else
{
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- else
- {
- HAL_SPI_ErrorCallback(hspi);
- }
+ HAL_SPI_ErrorCallback(hspi);
}
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
}
/**
@@ -2794,23 +3715,28 @@
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
}
@@ -2821,6 +3747,93 @@
}
/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count;
+
+ count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Check TXEIE is disabled */
+ do
+ {
+ if (count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ }
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi.h Thu Feb 02 17:01:33 2017 +0000
@@ -1,9 +1,9 @@
- /**
+/**
******************************************************************************
* @file stm32f3xx_hal_spi.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@@ -40,7 +40,7 @@
#define __STM32F3xx_HAL_SPI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -92,14 +92,14 @@
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+ This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
@@ -114,18 +114,19 @@
} SPI_InitTypeDef;
/**
- * @brief HAL State structures definition
+ * @brief HAL SPI State structure definition
*/
typedef enum
{
- HAL_SPI_STATE_RESET = 0x00, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06 /*!< SPI error state */
-}HAL_SPI_StateTypeDef;
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
@@ -150,9 +151,9 @@
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx IRQ handler */
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx IRQ handler */
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
@@ -164,14 +165,13 @@
__IO uint32_t ErrorCode; /*!< SPI Error code */
-}SPI_HandleTypeDef;
+} SPI_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
@@ -179,23 +179,22 @@
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
-#define HAL_SPI_ERROR_NONE (uint32_t)0x00000000 /*!< No error */
-#define HAL_SPI_ERROR_MODF (uint32_t)0x00000001 /*!< MODF error */
-#define HAL_SPI_ERROR_CRC (uint32_t)0x00000002 /*!< CRC error */
-#define HAL_SPI_ERROR_OVR (uint32_t)0x00000004 /*!< OVR error */
-#define HAL_SPI_ERROR_FRE (uint32_t)0x00000008 /*!< FRE error */
-#define HAL_SPI_ERROR_DMA (uint32_t)0x00000010 /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG (uint32_t)0x00000020 /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040 /*!< Unknown error */
+#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
/**
* @}
*/
-
/** @defgroup SPI_Mode SPI Mode
* @{
*/
-#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
@@ -204,7 +203,7 @@
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
-#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
@@ -214,19 +213,19 @@
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_4BIT ((uint32_t)0x0300)
-#define SPI_DATASIZE_5BIT ((uint32_t)0x0400)
-#define SPI_DATASIZE_6BIT ((uint32_t)0x0500)
-#define SPI_DATASIZE_7BIT ((uint32_t)0x0600)
-#define SPI_DATASIZE_8BIT ((uint32_t)0x0700)
-#define SPI_DATASIZE_9BIT ((uint32_t)0x0800)
-#define SPI_DATASIZE_10BIT ((uint32_t)0x0900)
-#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00)
-#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00)
-#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00)
-#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00)
-#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00)
-#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00)
+#define SPI_DATASIZE_4BIT (0x00000300U)
+#define SPI_DATASIZE_5BIT (0x00000400U)
+#define SPI_DATASIZE_6BIT (0x00000500U)
+#define SPI_DATASIZE_7BIT (0x00000600U)
+#define SPI_DATASIZE_8BIT (0x00000700U)
+#define SPI_DATASIZE_9BIT (0x00000800U)
+#define SPI_DATASIZE_10BIT (0x00000900U)
+#define SPI_DATASIZE_11BIT (0x00000A00U)
+#define SPI_DATASIZE_12BIT (0x00000B00U)
+#define SPI_DATASIZE_13BIT (0x00000C00U)
+#define SPI_DATASIZE_14BIT (0x00000D00U)
+#define SPI_DATASIZE_15BIT (0x00000E00U)
+#define SPI_DATASIZE_16BIT (0x00000F00U)
/**
* @}
*/
@@ -234,7 +233,7 @@
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
-#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
+#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
@@ -243,18 +242,18 @@
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
-#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
*/
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
+#define SPI_NSS_HARD_INPUT (0x00000000U)
+#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
@@ -263,7 +262,7 @@
* @{
*/
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE ((uint32_t)0x00000000)
+#define SPI_NSS_PULSE_DISABLE (0x00000000U)
/**
* @}
*/
@@ -271,31 +270,31 @@
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
-#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
-#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
-#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
-#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
-#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
-#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
-#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
+#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
+#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
+#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
-#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
*/
-/** @defgroup SPI_TI_mode SPI TI mode
+/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
+#define SPI_TIMODE_DISABLE (0x00000000U)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
@@ -304,7 +303,7 @@
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
@@ -317,9 +316,9 @@
* SPI_CRC_LENGTH_8BIT : CRC 8bit
* SPI_CRC_LENGTH_16BIT : CRC 16bit
*/
-#define SPI_CRC_LENGTH_DATASIZE ((uint32_t)0x00000000)
-#define SPI_CRC_LENGTH_8BIT ((uint32_t)0x00000001)
-#define SPI_CRC_LENGTH_16BIT ((uint32_t)0x00000002)
+#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
+#define SPI_CRC_LENGTH_8BIT (0x00000001U)
+#define SPI_CRC_LENGTH_16BIT (0x00000002U)
/**
* @}
*/
@@ -334,16 +333,13 @@
* level is greater or equal to 1/4(8 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x00000000)
+#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
/**
* @}
*/
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
- * @brief SPI Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@@ -353,23 +349,18 @@
* @}
*/
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
- * @brief Flag definition
- * Elements values convention: 0xXXXXYYYY
- * - XXXX : Flag register Index
- * - YYYY : Flag mask
+/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
/**
* @}
*/
@@ -377,10 +368,10 @@
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
*/
-#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
-#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
-#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
-#define SPI_FTLVL_FULL ((uint32_t)0x1800)
+#define SPI_FTLVL_EMPTY (0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
+#define SPI_FTLVL_HALF_FULL (0x00001000U)
+#define SPI_FTLVL_FULL (0x00001800U)
/**
* @}
@@ -389,10 +380,10 @@
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
-#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
-#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
-#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
-#define SPI_FRLVL_FULL ((uint32_t)0x0600)
+#define SPI_FRLVL_EMPTY (0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
+#define SPI_FRLVL_HALF_FULL (0x00000400U)
+#define SPI_FRLVL_FULL (0x00000600U)
/**
* @}
*/
@@ -401,29 +392,41 @@
* @}
*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state.
- * @param __HANDLE__: SPI handle.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-/** @brief Enable or disable the specified SPI interrupts.
+/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: specifies the interrupt source to enable.
+ * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+
+/** @brief Disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI handle.
+ * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SPI Handle.
@@ -441,7 +444,7 @@
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
@@ -465,64 +468,61 @@
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_modf; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_ovr; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while(0)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while(0U)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg_fre; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
- } while(0)
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
+ }while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/**
* @}
*/
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
@@ -531,34 +531,34 @@
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
+ SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
- ((MODE) == SPI_DIRECTION_1LINE))
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
@@ -580,19 +580,19 @@
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
@@ -609,8 +609,9 @@
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT))
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0))
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
+#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
/**
* @}
@@ -624,34 +625,40 @@
* @{
*/
-/* Initialization and de-initialization functions ****************************/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/**
* @}
*/
-/* IO operation functions *****************************************************/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
+/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -661,14 +668,15 @@
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
-/* Peripheral State and Error functions ***************************************/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
+/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_spi_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :
@@ -72,8 +72,8 @@
*/
/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -98,13 +98,13 @@
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
- uint8_t count = 0;
- while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
+ uint8_t count = 0U;
+ while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
{
count++;
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg); /* To avoid GCC warning */
- if(count == SPI_FIFO_SIZE)
+ if (count == SPI_FIFO_SIZE)
{
return HAL_TIMEOUT;
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_spi_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -1,9 +1,9 @@
- /**
+/**
******************************************************************************
* @file stm32f3xx_hal_spi_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
@@ -40,7 +40,7 @@
#define __STM32F3xx_HAL_SPI_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,7 +56,7 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sram.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sram.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_sram.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -295,7 +295,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint8_t *)psramaddress;
pDstBuffer++;
@@ -337,7 +337,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint8_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
@@ -373,7 +373,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint16_t *)psramaddress;
pDstBuffer++;
@@ -415,7 +415,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint16_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
@@ -449,7 +449,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint32_t *)pAddress;
pDstBuffer++;
@@ -489,7 +489,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint32_t *)pAddress = *pSrcBuffer;
pSrcBuffer++;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sram.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_sram.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_sram.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
@@ -65,10 +65,10 @@
*/
typedef enum
{
- HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
+ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
}HAL_SRAM_StateTypeDef;
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tim.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -211,6 +211,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -394,7 +395,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -488,7 +489,8 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -787,7 +789,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -994,6 +996,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -1296,7 +1299,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1503,6 +1506,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -1778,7 +1782,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1979,7 +1983,8 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -2240,9 +2245,9 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Check the TIM handle allocation */
if(htim == NULL)
@@ -2252,6 +2257,9 @@
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2294,18 +2302,18 @@
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
- tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
@@ -2482,7 +2490,7 @@
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Enable the encoder interface channels */
- /* Enable the capture compare Interrupts 1 and/or 2 */
+ /* Enable the capture compare Interrupts 1 and/or 2U */
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2535,14 +2543,14 @@
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- /* Disable the capture compare Interrupts 1 */
+ /* Disable the capture compare Interrupts 1U */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
else if(Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- /* Disable the capture compare Interrupts 2 */
+ /* Disable the capture compare Interrupts 2U */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
else
@@ -2550,7 +2558,7 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- /* Disable the capture compare Interrupts 1 and 2 */
+ /* Disable the capture compare Interrupts 1 and 2U */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
@@ -2589,7 +2597,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -2706,14 +2714,14 @@
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- /* Disable the capture compare DMA Request 1 */
+ /* Disable the capture compare DMA Request 1U */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
}
else if(Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- /* Disable the capture compare DMA Request 2 */
+ /* Disable the capture compare DMA Request 2U */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
else
@@ -2721,7 +2729,7 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- /* Disable the capture compare DMA Request 1 and 2 */
+ /* Disable the capture compare DMA Request 1 and 2U */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
}
@@ -2769,7 +2777,7 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2791,7 +2799,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2812,7 +2820,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2833,7 +2841,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -3030,7 +3038,7 @@
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
/* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
}
else if (Channel == TIM_CHANNEL_3)
{
@@ -3062,7 +3070,7 @@
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
htim->State = HAL_TIM_STATE_READY;
@@ -3125,7 +3133,7 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
}
break;
@@ -3155,7 +3163,7 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
}
break;
@@ -3336,7 +3344,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0U ) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3356,7 +3364,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC1:
@@ -3368,7 +3376,7 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC2:
@@ -3380,7 +3388,7 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC3:
@@ -3392,7 +3400,7 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC4:
@@ -3404,7 +3412,7 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_COM:
@@ -3416,7 +3424,7 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
@@ -3428,7 +3436,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
default:
@@ -3559,7 +3567,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0U ) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3579,7 +3587,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC1:
@@ -3591,7 +3599,7 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC2:
@@ -3603,7 +3611,7 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC3:
@@ -3615,7 +3623,7 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC4:
@@ -3627,7 +3635,7 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_COM:
@@ -3639,7 +3647,7 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
@@ -3651,7 +3659,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
default:
@@ -3817,12 +3825,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 1 */
+ /* Enable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
+ /* Disable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
}
}
@@ -3832,12 +3840,12 @@
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 2 */
+ /* Enable the Ocref clear feature for Channel 2U */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 2 */
+ /* Disable the Ocref clear feature for Channel 2U */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
}
}
@@ -3847,12 +3855,12 @@
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 3 */
+ /* Enable the Ocref clear feature for Channel 3U */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 3 */
+ /* Disable the Ocref clear feature for Channel 3U */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
}
}
@@ -3862,12 +3870,12 @@
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 4 */
+ /* Enable the Ocref clear feature for Channel 4U */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 4 */
+ /* Disable the Ocref clear feature for Channel 4U */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
}
}
@@ -3892,7 +3900,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Process Locked */
__HAL_LOCK(htim);
@@ -3966,7 +3974,7 @@
case TIM_CLOCKSOURCE_TI1:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
@@ -3996,7 +4004,7 @@
break;
case TIM_CLOCKSOURCE_TI1ED:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
/* Check TI1 input conditioning related parameters */
@@ -4011,7 +4019,7 @@
break;
case TIM_CLOCKSOURCE_ITR0:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
@@ -4019,7 +4027,7 @@
break;
case TIM_CLOCKSOURCE_ITR1:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
@@ -4027,7 +4035,7 @@
break;
case TIM_CLOCKSOURCE_ITR2:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
@@ -4035,7 +4043,7 @@
break;
case TIM_CLOCKSOURCE_ITR3:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports external clock mode 1U */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
@@ -4066,7 +4074,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0U;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
@@ -4171,7 +4179,7 @@
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
__HAL_LOCK(htim);
@@ -4546,7 +4554,7 @@
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- uint32_t tmpcr1 = 0;
+ uint32_t tmpcr1 = 0U;
tmpcr1 = TIMx->CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
@@ -4564,6 +4572,9 @@
tmpcr1 |= (uint32_t)Structure->ClockDivision;
}
+ /* Set the auto-reload preload */
+ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+
TIMx->CR1 = tmpcr1;
/* Set the Autoreload value */
@@ -4591,9 +4602,9 @@
*/
void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -4665,9 +4676,9 @@
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -4685,12 +4696,12 @@
tmpccmrx &= ~TIM_CCMR1_CC2S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
+ tmpccer |= (OC_Config->OCPolarity << 4U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
{
@@ -4699,7 +4710,7 @@
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
@@ -4711,13 +4722,17 @@
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
- /* Reset the Output Compare and Output Compare N IDLE State */
+ /* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2N;
+#endif
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 2);
+ tmpcr2 |= (OC_Config->OCIdleState << 2U);
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 2);
+ tmpcr2 |= (OC_Config->OCNIdleState << 2U);
}
/* Write to TIMx CR2 */
@@ -4741,9 +4756,9 @@
*/
void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -4765,7 +4780,7 @@
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8);
+ tmpccer |= (OC_Config->OCPolarity << 8U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
@@ -4774,7 +4789,7 @@
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8);
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
}
@@ -4785,13 +4800,16 @@
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
tmpcr2 &= ~TIM_CR2_OIS3N;
+#endif
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4);
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
}
/* Write to TIMx CR2 */
@@ -4815,9 +4833,9 @@
*/
void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -4835,21 +4853,24 @@
tmpccmrx &= ~TIM_CCMR2_CC4S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12);
+ tmpccer |= (OC_Config->OCPolarity << 12U);
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
+#endif
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 6);
+ tmpcr2 |= (OC_Config->OCIdleState << 6U);
}
/* Write to TIMx CR2 */
@@ -4868,9 +4889,9 @@
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -4919,7 +4940,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
@@ -5012,8 +5033,8 @@
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -5033,7 +5054,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5058,8 +5079,8 @@
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
@@ -5068,7 +5089,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
+ tmpccmr1 |= (TIM_ICFilter << 4U);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5102,8 +5123,8 @@
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5112,15 +5133,15 @@
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8);
+ tmpccmr1 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -5141,8 +5162,8 @@
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5151,11 +5172,11 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
+ tmpccmr1 |= (TIM_ICFilter << 12U);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
+ tmpccer |= (TIM_ICPolarity << 4U);
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -5185,8 +5206,8 @@
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5199,11 +5220,11 @@
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -5233,8 +5254,8 @@
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5243,15 +5264,15 @@
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8);
+ tmpccmr2 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+ tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -5275,7 +5296,7 @@
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
@@ -5306,7 +5327,7 @@
void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
tmpsmcr = TIMx->SMCR;
@@ -5314,7 +5335,7 @@
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
@@ -5335,7 +5356,7 @@
*/
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tim.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -64,7 +64,7 @@
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
@@ -79,11 +79,14 @@
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
+ This means in PWM mode that (N+1U) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
@@ -95,7 +98,7 @@
This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -127,7 +130,7 @@
This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
@@ -151,7 +154,7 @@
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
} TIM_OnePulse_InitTypeDef;
@@ -170,7 +173,7 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
} TIM_IC_InitTypeDef;
/**
@@ -191,7 +194,7 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -203,7 +206,7 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
} TIM_Encoder_InitTypeDef;
@@ -219,7 +222,7 @@
uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
}TIM_ClockConfigTypeDef;
/**
@@ -236,7 +239,7 @@
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
This parameter can be a value of @ref TIM_ClearInput_Prescaler */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
}TIM_ClearInputConfigTypeDef;
/**
@@ -252,7 +255,7 @@
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
}TIM_SlaveConfigTypeDef;
@@ -261,10 +264,10 @@
*/
typedef enum
{
- HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
@@ -273,10 +276,10 @@
*/
typedef enum
{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
@@ -307,7 +310,7 @@
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
@@ -318,7 +321,7 @@
* @{
*/
#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
/**
* @}
*/
@@ -326,10 +329,10 @@
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2U */
+#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4U */
+#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8U */
/**
* @}
*/
@@ -337,7 +340,7 @@
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_UP (0x0000U)
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
@@ -349,17 +352,27 @@
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
/**
* @}
*/
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
+
+/**
+ * @}
+ */
+
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_DISABLE (0x0000U)
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
/**
* @}
@@ -368,7 +381,7 @@
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_HIGH (0x0000U)
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
/**
* @}
@@ -377,7 +390,7 @@
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_HIGH (0x0000U)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
/**
* @}
@@ -387,7 +400,7 @@
* @{
*/
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCIDLESTATE_RESET (0x0000U)
/**
* @}
*/
@@ -396,7 +409,7 @@
* @{
*/
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCNIDLESTATE_RESET (0x0000U)
/**
* @}
*/
@@ -414,11 +427,11 @@
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1U, 2U, 3 or 4 is selected to be connected to TRC */
/**
* @}
*/
@@ -426,7 +439,7 @@
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
@@ -438,7 +451,7 @@
* @{
*/
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+#define TIM_OPMODE_REPETITIVE (0x0000U)
/**
* @}
*/
@@ -472,7 +485,7 @@
* @{
*/
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+#define TIM_COMMUTATION_SOFTWARE (0x0000U)
/**
* @}
@@ -516,7 +529,7 @@
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
@@ -575,7 +588,7 @@
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSR_DISABLE (0x0000U)
/**
* @}
*/
@@ -584,7 +597,7 @@
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSI_DISABLE (0x0000U)
/**
* @}
*/
@@ -592,7 +605,7 @@
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_OFF (0x0000U)
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
@@ -604,7 +617,7 @@
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+#define TIM_BREAK_DISABLE (0x0000U)
/**
* @}
*/
@@ -612,7 +625,7 @@
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_LOW (0x0000U)
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
/**
* @}
@@ -621,7 +634,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
/**
* @}
*/
@@ -629,7 +642,7 @@
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_RESET (0x0000U)
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
@@ -644,8 +657,8 @@
/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
+#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
/**
* @}
*/
@@ -653,15 +666,15 @@
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-#define TIM_TS_ITR0 ((uint32_t)0x0000)
-#define TIM_TS_ITR1 ((uint32_t)0x0010)
-#define TIM_TS_ITR2 ((uint32_t)0x0020)
-#define TIM_TS_ITR3 ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
-#define TIM_TS_ETRF ((uint32_t)0x0070)
-#define TIM_TS_NONE ((uint32_t)0xFFFF)
+#define TIM_TS_ITR0 (0x0000U)
+#define TIM_TS_ITR1 (0x0010U)
+#define TIM_TS_ITR2 (0x0020U)
+#define TIM_TS_ITR3 (0x0030U)
+#define TIM_TS_TI1F_ED (0x0040U)
+#define TIM_TS_TI1FP1 (0x0050U)
+#define TIM_TS_TI2FP2 (0x0060U)
+#define TIM_TS_ETRF (0x0070U)
+#define TIM_TS_NONE (0xFFFFU)
/**
* @}
*/
@@ -692,7 +705,7 @@
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_CH1 (0x0000U)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
/**
* @}
@@ -701,24 +714,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
/**
* @}
*/
@@ -726,13 +739,13 @@
/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
@@ -740,10 +753,10 @@
/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
-#define TIM_CCx_ENABLE ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+#define TIM_CCx_ENABLE (0x0001U)
+#define TIM_CCx_DISABLE (0x0000U)
+#define TIM_CCxN_ENABLE (0x0004U)
+#define TIM_CCxN_DISABLE (0x0000U)
/**
* @}
*/
@@ -785,14 +798,14 @@
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
- } while(0)
+ } while(0U)
/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
channels have been disabled */
/**
@@ -803,14 +816,23 @@
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
- } while(0)
+ } while(0U)
+
+/* The Main Output Enable of a timer instance is disabled unconditionally */
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled uncondiotionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
/**
* @brief Enables the specified TIM interrupt.
@@ -979,7 +1001,7 @@
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Autoreload Register value on runtime
@@ -1005,7 +1027,7 @@
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Clock Division value on runtime
@@ -1037,7 +1059,7 @@
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Input Capture prescaler on runtime
@@ -1052,9 +1074,9 @@
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1100,7 +1122,7 @@
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1137,6 +1159,8 @@
((DIV) == TIM_CLOCKDIVISION_DIV2) || \
((DIV) == TIM_CLOCKDIVISION_DIV4))
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
((STATE) == TIM_OCFAST_ENABLE))
@@ -1174,7 +1198,7 @@
((MODE) == TIM_ENCODERMODE_TI2) || \
((MODE) == TIM_ENCODERMODE_TI12))
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
@@ -1199,7 +1223,7 @@
((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
@@ -1209,7 +1233,7 @@
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
((STATE) == TIM_OSSR_DISABLE))
@@ -1269,7 +1293,7 @@
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
@@ -1293,7 +1317,7 @@
((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
/** @brief Set TIM IC prescaler
* @param __HANDLE__: TIM handle
@@ -1303,9 +1327,9 @@
*/
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
/** @brief Reset TIM IC prescaler
* @param __HANDLE__: TIM handle
@@ -1326,9 +1350,9 @@
*/
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12))))
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
/** @brief Reset TIM IC polarity
* @param __HANDLE__: TIM handle
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
@@ -119,8 +119,8 @@
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define BDTR_BKF_SHIFT (16)
-#define BDTR_BK2F_SHIFT (20)
+#define BDTR_BKF_SHIFT (16U)
+#define BDTR_BK2F_SHIFT (20U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -199,6 +199,7 @@
assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -249,7 +250,7 @@
TIM_OC2_SetConfig(htim->Instance, &OC_Config);
/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
- register to 101 */
+ register to 101U */
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
@@ -347,7 +348,7 @@
/* Check the parameters */
assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1, 2 and 3
+ /* Disable the Input Capture channels 1U, 2 and 3
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
@@ -424,7 +425,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -442,7 +443,7 @@
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
- /* Enable the DMA channel for Capture 1*/
+ /* Enable the DMA channel for Capture 1U*/
HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
/* Enable the capture compare 1 Interrupt */
@@ -645,7 +646,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
+ uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -729,7 +730,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1061,7 +1062,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
+ uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1145,7 +1146,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U ) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1800,7 +1801,7 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
}
break;
@@ -1834,7 +1835,7 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
}
break;
@@ -1868,7 +1869,7 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
+ htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
}
break;
@@ -1912,7 +1913,7 @@
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
- /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+ /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2U */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
{
/* Check the parameters */
@@ -2005,7 +2006,7 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
{
- uint32_t tmpbdtr = 0;
+ uint32_t tmpbdtr = 0U;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@@ -2020,57 +2021,38 @@
/* Check input state */
__HAL_LOCK(htim);
-
+
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
+
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
- /* Clear the BDTR bits */
- tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
- TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
- TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
- TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
-
- /* Set the BDTR bits */
- tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
- tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
- tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
- tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
- tmpbdtr |= sBreakDeadTimeConfig->BreakState;
- tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
- tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
- tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
- tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
- tmpbdtr |= sBreakDeadTimeConfig->Break2State;
- tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
- }
- else
- {
- /* Clear the BDTR bits */
- tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK | TIM_BDTR_OSSI |
- TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
- TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
-
- /* Set the BDTR bits */
- tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
- tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
- tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
- tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
- tmpbdtr |= sBreakDeadTimeConfig->BreakState;
- tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
- tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
- tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
+ /* Set the BREAK2 input related BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
__HAL_UNLOCK(htim);
-
+
return HAL_OK;
}
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
@@ -2090,6 +2072,8 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
+ uint32_t tmpbdtr = 0U;
+
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
@@ -2107,15 +2091,20 @@
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
- htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
- sBreakDeadTimeConfig->OffStateIDLEMode |
- sBreakDeadTimeConfig->LockLevel |
- sBreakDeadTimeConfig->DeadTime |
- sBreakDeadTimeConfig->BreakState |
- sBreakDeadTimeConfig->BreakPolarity |
- sBreakDeadTimeConfig->AutomaticOutput;
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
-
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -2125,7 +2114,8 @@
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
+ defined(STM32F303xC) || defined(STM32F358xx) || \
+ defined(STM32F334x8)
#if defined(STM32F303xE) || defined(STM32F398xx)
/**
* @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
@@ -2165,7 +2155,7 @@
* @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
* @retval HAL status
*/
-#else /* STM32F303xC || STM32F358xx */
+#elif defined(STM32F303xC) || defined(STM32F358xx)
/**
* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
* @param htim: TIM handle.
@@ -2195,6 +2185,28 @@
* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
* @retval HAL status
*/
+#else /* STM32F334x8 */
+/**
+ * @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
+ * @param htim: TIM handle.
+ * @param Remap1: specifies the first TIM remapping source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
+ * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
+ * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
+ * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
+ * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
+ * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
+ * @param Remap2: specifies the second TIMremapping source (if any).
+ * This parameter can be one of the following values:
+ * @arg TIM_TIM1_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
+ * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1
+ * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2
+ * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3
+ * @retval HAL status
+ */
#endif /* STM32F303xE || STM32F398xx || */
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
{
@@ -2215,17 +2227,17 @@
return HAL_OK;
}
#endif /* STM32F303xE || STM32F398xx || */
- /* STM32F303xC || STM32F358xx || */
+ /* STM32F303xC || STM32F358xx || STM32F334x8 */
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Configures the TIM1 and TIM16 Remapping input capabilities.
@@ -2362,7 +2374,7 @@
TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
@@ -2424,12 +2436,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 1 */
+ /* Enable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
+ /* Disable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
}
}
@@ -2438,12 +2450,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 2 */
+ /* Enable the Ocref clear feature for Channel 2U */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 2 */
+ /* Disable the Ocref clear feature for Channel 2U */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
}
}
@@ -2452,12 +2464,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 3 */
+ /* Enable the Ocref clear feature for Channel 3U */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 3 */
+ /* Disable the Ocref clear feature for Channel 3U */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
}
}
@@ -2466,12 +2478,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 4 */
+ /* Enable the Ocref clear feature for Channel 4U */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 4 */
+ /* Disable the Ocref clear feature for Channel 4U */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
}
}
@@ -2480,12 +2492,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 1 */
+ /* Enable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
+ /* Disable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
}
}
@@ -2494,12 +2506,12 @@
{
if(sClearInputConfig->ClearInputState != RESET)
{
- /* Enable the Ocref clear feature for Channel 1 */
+ /* Enable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
}
else
{
- /* Disable the Ocref clear feature for Channel 1 */
+ /* Disable the Ocref clear feature for Channel 1U */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
}
}
@@ -2636,7 +2648,7 @@
*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
tmp = TIM_CCER_CC1NE << Channel;
@@ -2660,9 +2672,9 @@
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
@@ -2682,14 +2694,14 @@
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 16);
+ tmpccer |= (OC_Config->OCPolarity << 16U);
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 8);
+ tmpcr2 |= (OC_Config->OCIdleState << 8U);
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -2713,9 +2725,9 @@
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
@@ -2730,19 +2742,19 @@
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 20);
+ tmpccer |= (OC_Config->OCPolarity << 20U);
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 10);
+ tmpcr2 |= (OC_Config->OCIdleState << 10U);
}
/* Write to TIMx CR2 */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tim_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
@@ -73,9 +73,9 @@
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFU */
} TIM_HallSensor_InitTypeDef;
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -104,7 +104,7 @@
uint32_t LockLevel; /*!< TIM Lock level
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
uint32_t BreakState; /*!< TIM Break State
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity
@@ -133,19 +133,19 @@
uint32_t LockLevel; /*!< TIM Lock level
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
uint32_t BreakState; /*!< TIM Break State
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*!< Specifies the brek input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
uint32_t Break2State; /*!< TIM Break2 State
This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
uint32_t Break2Polarity; /*!< TIM Break2 input polarity
This parameter can be a value of @ref TIMEx_Break2_Polarity */
uint32_t Break2Filter; /*!< TIM break2 input filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xFU */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;
@@ -180,11 +180,11 @@
/** @defgroup TIMEx_Channel TIMEx Channel
* @{
*/
-#define TIM_CHANNEL_1 ((uint32_t)0x0000)
-#define TIM_CHANNEL_2 ((uint32_t)0x0004)
-#define TIM_CHANNEL_3 ((uint32_t)0x0008)
-#define TIM_CHANNEL_4 ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+#define TIM_CHANNEL_1 (0x0000U)
+#define TIM_CHANNEL_2 (0x0004U)
+#define TIM_CHANNEL_3 (0x0008U)
+#define TIM_CHANNEL_4 (0x000CU)
+#define TIM_CHANNEL_ALL (0x0018U)
/**
* @}
*/
@@ -192,7 +192,7 @@
/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
* @{
*/
-#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_TIMING (0x0000U)
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
@@ -207,8 +207,8 @@
/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
* @{
*/
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
-#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
+#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
/**
* @}
*/
@@ -216,7 +216,7 @@
/** @defgroup TIMEx_Slave_Mode TIMEx Slave Mode
* @{
*/
-#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_DISABLE (0x0000U)
#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
@@ -229,10 +229,10 @@
* @{
*/
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
@@ -243,26 +243,26 @@
/** @defgroup TIMEx_DMA_Base_address TIMEx DMA BAse Address
* @{
*/
-#define TIM_DMABASE_CR1 (0x00000000)
-#define TIM_DMABASE_CR2 (0x00000001)
-#define TIM_DMABASE_SMCR (0x00000002)
-#define TIM_DMABASE_DIER (0x00000003)
-#define TIM_DMABASE_SR (0x00000004)
-#define TIM_DMABASE_EGR (0x00000005)
-#define TIM_DMABASE_CCMR1 (0x00000006)
-#define TIM_DMABASE_CCMR2 (0x00000007)
-#define TIM_DMABASE_CCER (0x00000008)
-#define TIM_DMABASE_CNT (0x00000009)
-#define TIM_DMABASE_PSC (0x0000000A)
-#define TIM_DMABASE_ARR (0x0000000B)
-#define TIM_DMABASE_RCR (0x0000000C)
-#define TIM_DMABASE_CCR1 (0x0000000D)
-#define TIM_DMABASE_CCR2 (0x0000000E)
-#define TIM_DMABASE_CCR3 (0x0000000F)
-#define TIM_DMABASE_CCR4 (0x00000010)
-#define TIM_DMABASE_BDTR (0x00000011)
-#define TIM_DMABASE_DCR (0x00000012)
-#define TIM_DMABASE_OR (0x00000013)
+#define TIM_DMABASE_CR1 (0x00000000U)
+#define TIM_DMABASE_CR2 (0x00000001U)
+#define TIM_DMABASE_SMCR (0x00000002U)
+#define TIM_DMABASE_DIER (0x00000003U)
+#define TIM_DMABASE_SR (0x00000004U)
+#define TIM_DMABASE_EGR (0x00000005U)
+#define TIM_DMABASE_CCMR1 (0x00000006U)
+#define TIM_DMABASE_CCMR2 (0x00000007U)
+#define TIM_DMABASE_CCER (0x00000008U)
+#define TIM_DMABASE_CNT (0x00000009U)
+#define TIM_DMABASE_PSC (0x0000000AU)
+#define TIM_DMABASE_ARR (0x0000000BU)
+#define TIM_DMABASE_RCR (0x0000000CU)
+#define TIM_DMABASE_CCR1 (0x0000000DU)
+#define TIM_DMABASE_CCR2 (0x0000000EU)
+#define TIM_DMABASE_CCR3 (0x0000000FU)
+#define TIM_DMABASE_CCR4 (0x00000010U)
+#define TIM_DMABASE_BDTR (0x00000011U)
+#define TIM_DMABASE_DCR (0x00000012U)
+#define TIM_DMABASE_OR (0x00000013U)
/**
* @}
*/
@@ -275,13 +275,13 @@
/** @defgroup TIMEx_Channel TIMEx Channel
* @{
*/
-#define TIM_CHANNEL_1 ((uint32_t)0x0000)
-#define TIM_CHANNEL_2 ((uint32_t)0x0004)
-#define TIM_CHANNEL_3 ((uint32_t)0x0008)
-#define TIM_CHANNEL_4 ((uint32_t)0x000C)
-#define TIM_CHANNEL_5 ((uint32_t)0x0010)
-#define TIM_CHANNEL_6 ((uint32_t)0x0014)
-#define TIM_CHANNEL_ALL ((uint32_t)0x003C)
+#define TIM_CHANNEL_1 (0x0000U)
+#define TIM_CHANNEL_2 (0x0004U)
+#define TIM_CHANNEL_3 (0x0008U)
+#define TIM_CHANNEL_4 (0x000CU)
+#define TIM_CHANNEL_5 (0x0010U)
+#define TIM_CHANNEL_6 (0x0014U)
+#define TIM_CHANNEL_ALL (0x003CU)
/**
* @}
*/
@@ -289,7 +289,7 @@
/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
* @{
*/
-#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_TIMING (0x0000U)
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
@@ -312,9 +312,9 @@
/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
* @{
*/
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
-#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+#define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
+#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
+#define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
/**
* @}
*/
@@ -322,7 +322,7 @@
/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
* @{
*/
-#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
+#define TIM_BREAK2_DISABLE (0x00000000U)
#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
/**
* @}
@@ -331,7 +331,7 @@
/** @defgroup TIMEx_Break2_Polarity TIMEx Break Input 2 Polarity
* @{
*/
-#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
+#define TIM_BREAK2POLARITY_LOW (0x00000000U)
#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
/**
* @}
@@ -340,7 +340,7 @@
/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
* @{
*/
-#define TIM_TRGO2_RESET ((uint32_t)0x00000000)
+#define TIM_TRGO2_RESET (0x00000000U)
#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
@@ -363,7 +363,7 @@
/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
* @{
*/
-#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_SLAVEMODE_DISABLE (0x0000U)
#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
@@ -377,10 +377,10 @@
* @{
*/
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1U */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2U */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3U */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4U */
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
@@ -392,29 +392,29 @@
/** @defgroup TIM_DMA_Base_address TIMEx DMA Base Address
* @{
*/
-#define TIM_DMABASE_CR1 (0x00000000)
-#define TIM_DMABASE_CR2 (0x00000001)
-#define TIM_DMABASE_SMCR (0x00000002)
-#define TIM_DMABASE_DIER (0x00000003)
-#define TIM_DMABASE_SR (0x00000004)
-#define TIM_DMABASE_EGR (0x00000005)
-#define TIM_DMABASE_CCMR1 (0x00000006)
-#define TIM_DMABASE_CCMR2 (0x00000007)
-#define TIM_DMABASE_CCER (0x00000008)
-#define TIM_DMABASE_CNT (0x00000009)
-#define TIM_DMABASE_PSC (0x0000000A)
-#define TIM_DMABASE_ARR (0x0000000B)
-#define TIM_DMABASE_RCR (0x0000000C)
-#define TIM_DMABASE_CCR1 (0x0000000D)
-#define TIM_DMABASE_CCR2 (0x0000000E)
-#define TIM_DMABASE_CCR3 (0x0000000F)
-#define TIM_DMABASE_CCR4 (0x00000010)
-#define TIM_DMABASE_BDTR (0x00000011)
-#define TIM_DMABASE_DCR (0x00000012)
-#define TIM_DMABASE_CCMR3 (0x00000015)
-#define TIM_DMABASE_CCR5 (0x00000016)
-#define TIM_DMABASE_CCR6 (0x00000017)
-#define TIM_DMABASE_OR (0x00000018)
+#define TIM_DMABASE_CR1 (0x00000000U)
+#define TIM_DMABASE_CR2 (0x00000001U)
+#define TIM_DMABASE_SMCR (0x00000002U)
+#define TIM_DMABASE_DIER (0x00000003U)
+#define TIM_DMABASE_SR (0x00000004U)
+#define TIM_DMABASE_EGR (0x00000005U)
+#define TIM_DMABASE_CCMR1 (0x00000006U)
+#define TIM_DMABASE_CCMR2 (0x00000007U)
+#define TIM_DMABASE_CCER (0x00000008U)
+#define TIM_DMABASE_CNT (0x00000009U)
+#define TIM_DMABASE_PSC (0x0000000AU)
+#define TIM_DMABASE_ARR (0x0000000BU)
+#define TIM_DMABASE_RCR (0x0000000CU)
+#define TIM_DMABASE_CCR1 (0x0000000DU)
+#define TIM_DMABASE_CCR2 (0x0000000EU)
+#define TIM_DMABASE_CCR3 (0x0000000FU)
+#define TIM_DMABASE_CCR4 (0x00000010U)
+#define TIM_DMABASE_BDTR (0x00000011U)
+#define TIM_DMABASE_DCR (0x00000012U)
+#define TIM_DMABASE_CCMR3 (0x00000015U)
+#define TIM_DMABASE_CCR5 (0x00000016U)
+#define TIM_DMABASE_CCR6 (0x00000017U)
+#define TIM_DMABASE_OR (0x00000018U)
/**
* @}
*/
@@ -425,43 +425,40 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/** @defgroup TIMEx_Remap TIMEx Remapping
* @{
*/
-#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
-#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
/**
* @}
*/
#endif /* STM32F302xE || */
/* STM32F302xC || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F303x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
-#if defined(STM32F303xC) || defined(STM32F358xx)
+
+#if defined(STM32F334x8)
/** @defgroup TIMEx_Remap TIMEx Remapping 1
* @{
*/
-#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
-#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
/**
* @}
*/
@@ -469,15 +466,48 @@
/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
* @{
*/
-#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
-#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
+#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
+/**
+ * @}
+ */
+#endif /* STM32F334x8 */
+
+#if defined(STM32F303xC) || defined(STM32F358xx)
+/** @defgroup TIMEx_Remap TIMEx Remapping 1
+ * @{
+ */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+/**
+ * @}
+ */
+
+/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
+ * @{
+ */
+#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
/**
* @}
*/
@@ -487,22 +517,22 @@
/** @defgroup TIMEx_Remap TIMEx Remapping 1
* @{
*/
-#define TIM_TIM1_ADC1_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC1_AWD1 (0x00000001) /*!< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ADC1_AWD2 (0x00000002) /*!< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ADC1_AWD3 (0x00000003) /*!< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM8_ADC2_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC2_AWD1 (0x00000001) /*!< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ADC2_AWD2 (0x00000002) /*!< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ADC2_AWD3 (0x00000003) /*!< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM16_GPIO (0x00000000) /*!< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_RTC (0x00000001) /*!< TIM16 TI1 is connected to RTC_clock */
-#define TIM_TIM16_HSE (0x00000002) /*!< TIM16 TI1 is connected to HSE/32 */
-#define TIM_TIM16_MCO (0x00000003) /*!< TIM16 TI1 is connected to MCO */
-#define TIM_TIM20_ADC3_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM20_ADC3_AWD1 (0x00000001) /*!< TIM20_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM20_ADC3_AWD2 (0x00000002) /*!< TIM20_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM20_ADC3_AWD3 (0x00000003) /*!< TIM20_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
+#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32U */
+#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
+#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
/**
* @}
*/
@@ -510,19 +540,19 @@
/** @defgroup TIMEx_Remap2 TIMEx Remapping 2
* @{
*/
-#define TIM_TIM1_ADC4_NONE (0x00000000) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
-#define TIM_TIM1_ADC4_AWD1 (0x00000004) /*!< TIM1_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM1_ADC4_AWD2 (0x00000008) /*!< TIM1_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM1_ADC4_AWD3 (0x0000000C) /*!< TIM1_ETR is connected to ADC4 AWD3 */
-#define TIM_TIM8_ADC3_NONE (0x00000000) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM8_ADC3_AWD1 (0x00000004) /*!< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ADC3_AWD2 (0x00000008) /*!< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ADC3_AWD3 (0x0000000C) /*!< TIM8_ETR is connected to ADC3 AWD3 */
-#define TIM_TIM16_NONE (0x00000000) /*!< Non significant value for TIM16 */
-#define TIM_TIM20_ADC4_NONE (0x00000000) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
-#define TIM_TIM20_ADC4_AWD1 (0x00000004) /*!< TIM20_ETR is connected to ADC4 AWD1 */
-#define TIM_TIM20_ADC4_AWD2 (0x00000008) /*!< TIM20_ETR is connected to ADC4 AWD2 */
-#define TIM_TIM20_ADC4_AWD3 (0x0000000C) /*!< TIM20_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
+#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM16_NONE (0x00000000U) /*!< Non significant value for TIM16U */
+#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
+#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
+#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
+#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
/**
* @}
*/
@@ -533,14 +563,14 @@
/** @defgroup TIMEx_Remap TIMEx remapping
* @{
*/
-#define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
-#define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
-#define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
-#define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
-#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
-#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
-#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
-#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
+#define TIM_TIM2_TIM8_TRGO (0x00000000U) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
+#define TIM_TIM2_ETH_PTP (0x00000400U) /*!< PTP trigger output is connected to TIM2_ITR1 */
+#define TIM_TIM2_USBFS_SOF (0x00000800U) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM2_USBHS_SOF (0x00000C00U) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
+#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
+#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
+#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
+#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
/**
* @}
*/
@@ -550,10 +580,10 @@
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1U, 2 or 3
* @{
*/
-#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_NONE 0x00000000 /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
@@ -608,7 +638,7 @@
((MODE) == TIM_SLAVEMODE_TRIGGER) || \
((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
((BASE) == TIM_DMABASE_CR2) || \
@@ -675,7 +705,7 @@
((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
((MODE) == TIM_CLEARINPUTSOURCE_NONE))
-#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
+#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFU)
#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
((STATE) == TIM_BREAK2_DISABLE))
@@ -708,7 +738,7 @@
((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
((BASE) == TIM_DMABASE_CR2) || \
@@ -740,7 +770,7 @@
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
@@ -754,9 +784,27 @@
#endif /* STM32F302xE || */
/* STM32F302xC || */
- /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
+ /* STM32F303x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx || */
+#if defined(STM32F334x8)
+#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
+ ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
+ ((REMAP1) == TIM_TIM16_GPIO) ||\
+ ((REMAP1) == TIM_TIM16_RTC) ||\
+ ((REMAP1) == TIM_TIM16_HSE) ||\
+ ((REMAP1) == TIM_TIM16_MCO))
+
+#define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC2_NONE) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD1) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD2) ||\
+ ((REMAP2) == TIM_TIM1_ADC2_AWD3) ||\
+ ((REMAP2) == TIM_TIM16_NONE))
+
+#endif /* STM32F334x8 */
+
#if defined(STM32F303xC) || defined(STM32F358xx)
#define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
@@ -838,14 +886,14 @@
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
+#define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFFU) == 0x00000000U))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
/**
* @}
@@ -873,7 +921,7 @@
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
/**
* @brief Gets the TIM Capture Compare Register value on runtime
@@ -887,7 +935,42 @@
* @retval None
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
+
+/**
+ * @brief Sets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Resets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
+
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -937,6 +1020,49 @@
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
+
+/**
+ * @brief Sets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Resets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
@@ -1036,14 +1162,14 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(STM32F303xE) || defined(STM32F398xx) || \
- defined(STM32F303xC) || defined(STM32F358xx)
+ defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F334x8)
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
- defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
+ defined(STM32F303x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tsc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tsc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and De-initialization
@@ -253,7 +253,7 @@
/* Set all functions */
htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
htsc->Init.CTPulseLowLength |
- (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17) |
+ (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
htsc->Init.SpreadSpectrumPrescaler |
htsc->Init.PulseGeneratorPrescaler |
htsc->Init.MaxCountValue |
@@ -844,14 +844,14 @@
*/
static uint32_t TSC_extract_groups(uint32_t iomask)
{
- uint32_t groups = 0;
+ uint32_t groups = 0U;
uint32_t idx;
- for (idx = 0; idx < TSC_NB_OF_GROUPS; idx++)
+ for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
{
- if ((iomask & ((uint32_t)0x0F << (idx * 4))) != RESET)
+ if ((iomask & (0x0FU << (idx * 4U))) != RESET)
{
- groups |= ((uint32_t)1 << idx);
+ groups |= (1U << idx);
}
}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tsc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_tsc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_tsc.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of TSC HAL module.
******************************************************************************
* @attention
@@ -64,10 +64,10 @@
*/
typedef enum
{
- HAL_TSC_STATE_RESET = 0x00, /*!< TSC registers have their reset value */
- HAL_TSC_STATE_READY = 0x01, /*!< TSC registers are initialized or acquisition is completed with success */
- HAL_TSC_STATE_BUSY = 0x02, /*!< TSC initialization or acquisition is on-going */
- HAL_TSC_STATE_ERROR = 0x03 /*!< Acquisition is completed with max count error */
+ HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
} HAL_TSC_StateTypeDef;
/**
@@ -75,8 +75,8 @@
*/
typedef enum
{
- TSC_GROUP_ONGOING = 0x00, /*!< Acquisition on group is on-going or not started */
- TSC_GROUP_COMPLETED = 0x01 /*!< Acquisition on group is completed with success (no max count error) */
+ TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
} TSC_GroupStatusTypeDef;
/**
@@ -91,7 +91,7 @@
uint32_t SpreadSpectrum; /*!< Spread spectrum activation
This parameter can be a value of @ref TSC_CTPulseLL_Config */
uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
- This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 127U */
uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
@@ -144,22 +144,22 @@
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
-#define TSC_CTPH_1CYCLE ((uint32_t)((uint32_t) 0 << 28))
-#define TSC_CTPH_2CYCLES ((uint32_t)((uint32_t) 1 << 28))
-#define TSC_CTPH_3CYCLES ((uint32_t)((uint32_t) 2 << 28))
-#define TSC_CTPH_4CYCLES ((uint32_t)((uint32_t) 3 << 28))
-#define TSC_CTPH_5CYCLES ((uint32_t)((uint32_t) 4 << 28))
-#define TSC_CTPH_6CYCLES ((uint32_t)((uint32_t) 5 << 28))
-#define TSC_CTPH_7CYCLES ((uint32_t)((uint32_t) 6 << 28))
-#define TSC_CTPH_8CYCLES ((uint32_t)((uint32_t) 7 << 28))
-#define TSC_CTPH_9CYCLES ((uint32_t)((uint32_t) 8 << 28))
-#define TSC_CTPH_10CYCLES ((uint32_t)((uint32_t) 9 << 28))
-#define TSC_CTPH_11CYCLES ((uint32_t)((uint32_t)10 << 28))
-#define TSC_CTPH_12CYCLES ((uint32_t)((uint32_t)11 << 28))
-#define TSC_CTPH_13CYCLES ((uint32_t)((uint32_t)12 << 28))
-#define TSC_CTPH_14CYCLES ((uint32_t)((uint32_t)13 << 28))
-#define TSC_CTPH_15CYCLES ((uint32_t)((uint32_t)14 << 28))
-#define TSC_CTPH_16CYCLES ((uint32_t)((uint32_t)15 << 28))
+#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28U))
+#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28U))
+#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28U))
+#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28U))
+#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28U))
+#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28U))
+#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28U))
+#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28U))
+#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28U))
+#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28U))
+#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28U))
+#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28U))
+#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28U))
+#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28U))
+#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28U))
+#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28U))
/**
* @}
*/
@@ -167,22 +167,22 @@
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
-#define TSC_CTPL_1CYCLE ((uint32_t)((uint32_t) 0 << 24))
-#define TSC_CTPL_2CYCLES ((uint32_t)((uint32_t) 1 << 24))
-#define TSC_CTPL_3CYCLES ((uint32_t)((uint32_t) 2 << 24))
-#define TSC_CTPL_4CYCLES ((uint32_t)((uint32_t) 3 << 24))
-#define TSC_CTPL_5CYCLES ((uint32_t)((uint32_t) 4 << 24))
-#define TSC_CTPL_6CYCLES ((uint32_t)((uint32_t) 5 << 24))
-#define TSC_CTPL_7CYCLES ((uint32_t)((uint32_t) 6 << 24))
-#define TSC_CTPL_8CYCLES ((uint32_t)((uint32_t) 7 << 24))
-#define TSC_CTPL_9CYCLES ((uint32_t)((uint32_t) 8 << 24))
-#define TSC_CTPL_10CYCLES ((uint32_t)((uint32_t) 9 << 24))
-#define TSC_CTPL_11CYCLES ((uint32_t)((uint32_t)10 << 24))
-#define TSC_CTPL_12CYCLES ((uint32_t)((uint32_t)11 << 24))
-#define TSC_CTPL_13CYCLES ((uint32_t)((uint32_t)12 << 24))
-#define TSC_CTPL_14CYCLES ((uint32_t)((uint32_t)13 << 24))
-#define TSC_CTPL_15CYCLES ((uint32_t)((uint32_t)14 << 24))
-#define TSC_CTPL_16CYCLES ((uint32_t)((uint32_t)15 << 24))
+#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24U))
+#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24U))
+#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24U))
+#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24U))
+#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24U))
+#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24U))
+#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24U))
+#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24U))
+#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24U))
+#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24U))
+#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24U))
+#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24U))
+#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24U))
+#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24U))
+#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24U))
+#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24U))
/**
* @}
*/
@@ -190,7 +190,7 @@
/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
* @{
*/
-#define TSC_SS_PRESC_DIV1 ((uint32_t)0)
+#define TSC_SS_PRESC_DIV1 (0U)
#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
/**
* @}
@@ -199,14 +199,14 @@
/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
* @{
*/
-#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
-#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
-#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
-#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
-#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
-#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
-#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
-#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
+#define TSC_PG_PRESC_DIV1 ((uint32_t)(0U << 12U))
+#define TSC_PG_PRESC_DIV2 ((uint32_t)(1U << 12U))
+#define TSC_PG_PRESC_DIV4 ((uint32_t)(2U << 12U))
+#define TSC_PG_PRESC_DIV8 ((uint32_t)(3U << 12U))
+#define TSC_PG_PRESC_DIV16 ((uint32_t)(4U << 12U))
+#define TSC_PG_PRESC_DIV32 ((uint32_t)(5U << 12U))
+#define TSC_PG_PRESC_DIV64 ((uint32_t)(6U << 12U))
+#define TSC_PG_PRESC_DIV128 ((uint32_t)(7U << 12U))
/**
* @}
*/
@@ -214,13 +214,13 @@
/** @defgroup TSC_MaxCount_Value Max Count Value
* @{
*/
-#define TSC_MCV_255 ((uint32_t)(0 << 5))
-#define TSC_MCV_511 ((uint32_t)(1 << 5))
-#define TSC_MCV_1023 ((uint32_t)(2 << 5))
-#define TSC_MCV_2047 ((uint32_t)(3 << 5))
-#define TSC_MCV_4095 ((uint32_t)(4 << 5))
-#define TSC_MCV_8191 ((uint32_t)(5 << 5))
-#define TSC_MCV_16383 ((uint32_t)(6 << 5))
+#define TSC_MCV_255 ((uint32_t)(0U << 5U))
+#define TSC_MCV_511 ((uint32_t)(1U << 5U))
+#define TSC_MCV_1023 ((uint32_t)(2U << 5U))
+#define TSC_MCV_2047 ((uint32_t)(3U << 5U))
+#define TSC_MCV_4095 ((uint32_t)(4U << 5U))
+#define TSC_MCV_8191 ((uint32_t)(5U << 5U))
+#define TSC_MCV_16383 ((uint32_t)(6U << 5U))
/**
* @}
*/
@@ -228,7 +228,7 @@
/** @defgroup TSC_IO_Default_Mode IO Default Mode
* @{
*/
-#define TSC_IODEF_OUT_PP_LOW ((uint32_t)0)
+#define TSC_IODEF_OUT_PP_LOW (0U)
#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
/**
* @}
@@ -237,7 +237,7 @@
/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
* @{
*/
-#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0)
+#define TSC_SYNC_POLARITY_FALLING (0U)
#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
/**
* @}
@@ -246,7 +246,7 @@
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
-#define TSC_ACQ_MODE_NORMAL ((uint32_t)0)
+#define TSC_ACQ_MODE_NORMAL (0U)
#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
/**
* @}
@@ -255,10 +255,10 @@
/** @defgroup TSC_IO_Mode IO Mode
* @{
*/
-#define TSC_IOMODE_UNUSED ((uint32_t)0)
-#define TSC_IOMODE_CHANNEL ((uint32_t)1)
-#define TSC_IOMODE_SHIELD ((uint32_t)2)
-#define TSC_IOMODE_SAMPLING ((uint32_t)3)
+#define TSC_IOMODE_UNUSED (0U)
+#define TSC_IOMODE_CHANNEL (1U)
+#define TSC_IOMODE_SHIELD (2U)
+#define TSC_IOMODE_SAMPLING (3U)
/**
* @}
*/
@@ -284,76 +284,76 @@
/** @defgroup TSC_Group_definition Group definition
* @{
*/
-#define TSC_NB_OF_GROUPS (8)
+#define TSC_NB_OF_GROUPS (8U)
-#define TSC_GROUP1 ((uint32_t)0x00000001)
-#define TSC_GROUP2 ((uint32_t)0x00000002)
-#define TSC_GROUP3 ((uint32_t)0x00000004)
-#define TSC_GROUP4 ((uint32_t)0x00000008)
-#define TSC_GROUP5 ((uint32_t)0x00000010)
-#define TSC_GROUP6 ((uint32_t)0x00000020)
-#define TSC_GROUP7 ((uint32_t)0x00000040)
-#define TSC_GROUP8 ((uint32_t)0x00000080)
-#define TSC_ALL_GROUPS ((uint32_t)0x000000FF)
+#define TSC_GROUP1 (0x00000001U)
+#define TSC_GROUP2 (0x00000002U)
+#define TSC_GROUP3 (0x00000004U)
+#define TSC_GROUP4 (0x00000008U)
+#define TSC_GROUP5 (0x00000010U)
+#define TSC_GROUP6 (0x00000020U)
+#define TSC_GROUP7 (0x00000040U)
+#define TSC_GROUP8 (0x00000080U)
+#define TSC_ALL_GROUPS (0x000000FFU)
-#define TSC_GROUP1_IDX ((uint32_t)0)
-#define TSC_GROUP2_IDX ((uint32_t)1)
-#define TSC_GROUP3_IDX ((uint32_t)2)
-#define TSC_GROUP4_IDX ((uint32_t)3)
-#define TSC_GROUP5_IDX ((uint32_t)4)
-#define TSC_GROUP6_IDX ((uint32_t)5)
-#define TSC_GROUP7_IDX ((uint32_t)6)
-#define TSC_GROUP8_IDX ((uint32_t)7)
+#define TSC_GROUP1_IDX (0U)
+#define TSC_GROUP2_IDX (1U)
+#define TSC_GROUP3_IDX (2U)
+#define TSC_GROUP4_IDX (3U)
+#define TSC_GROUP5_IDX (4U)
+#define TSC_GROUP6_IDX (5U)
+#define TSC_GROUP7_IDX (6U)
+#define TSC_GROUP8_IDX (7U)
-#define TSC_GROUP1_IO1 ((uint32_t)0x00000001)
-#define TSC_GROUP1_IO2 ((uint32_t)0x00000002)
-#define TSC_GROUP1_IO3 ((uint32_t)0x00000004)
-#define TSC_GROUP1_IO4 ((uint32_t)0x00000008)
-#define TSC_GROUP1_ALL_IOS ((uint32_t)0x0000000F)
+#define TSC_GROUP1_IO1 (0x00000001U)
+#define TSC_GROUP1_IO2 (0x00000002U)
+#define TSC_GROUP1_IO3 (0x00000004U)
+#define TSC_GROUP1_IO4 (0x00000008U)
+#define TSC_GROUP1_ALL_IOS (0x0000000FU)
-#define TSC_GROUP2_IO1 ((uint32_t)0x00000010)
-#define TSC_GROUP2_IO2 ((uint32_t)0x00000020)
-#define TSC_GROUP2_IO3 ((uint32_t)0x00000040)
-#define TSC_GROUP2_IO4 ((uint32_t)0x00000080)
-#define TSC_GROUP2_ALL_IOS ((uint32_t)0x000000F0)
+#define TSC_GROUP2_IO1 (0x00000010U)
+#define TSC_GROUP2_IO2 (0x00000020U)
+#define TSC_GROUP2_IO3 (0x00000040U)
+#define TSC_GROUP2_IO4 (0x00000080U)
+#define TSC_GROUP2_ALL_IOS (0x000000F0U)
-#define TSC_GROUP3_IO1 ((uint32_t)0x00000100)
-#define TSC_GROUP3_IO2 ((uint32_t)0x00000200)
-#define TSC_GROUP3_IO3 ((uint32_t)0x00000400)
-#define TSC_GROUP3_IO4 ((uint32_t)0x00000800)
-#define TSC_GROUP3_ALL_IOS ((uint32_t)0x00000F00)
+#define TSC_GROUP3_IO1 (0x00000100U)
+#define TSC_GROUP3_IO2 (0x00000200U)
+#define TSC_GROUP3_IO3 (0x00000400U)
+#define TSC_GROUP3_IO4 (0x00000800U)
+#define TSC_GROUP3_ALL_IOS (0x00000F00U)
-#define TSC_GROUP4_IO1 ((uint32_t)0x00001000)
-#define TSC_GROUP4_IO2 ((uint32_t)0x00002000)
-#define TSC_GROUP4_IO3 ((uint32_t)0x00004000)
-#define TSC_GROUP4_IO4 ((uint32_t)0x00008000)
-#define TSC_GROUP4_ALL_IOS ((uint32_t)0x0000F000)
+#define TSC_GROUP4_IO1 (0x00001000U)
+#define TSC_GROUP4_IO2 (0x00002000U)
+#define TSC_GROUP4_IO3 (0x00004000U)
+#define TSC_GROUP4_IO4 (0x00008000U)
+#define TSC_GROUP4_ALL_IOS (0x0000F000U)
-#define TSC_GROUP5_IO1 ((uint32_t)0x00010000)
-#define TSC_GROUP5_IO2 ((uint32_t)0x00020000)
-#define TSC_GROUP5_IO3 ((uint32_t)0x00040000)
-#define TSC_GROUP5_IO4 ((uint32_t)0x00080000)
-#define TSC_GROUP5_ALL_IOS ((uint32_t)0x000F0000)
+#define TSC_GROUP5_IO1 (0x00010000U)
+#define TSC_GROUP5_IO2 (0x00020000U)
+#define TSC_GROUP5_IO3 (0x00040000U)
+#define TSC_GROUP5_IO4 (0x00080000U)
+#define TSC_GROUP5_ALL_IOS (0x000F0000U)
-#define TSC_GROUP6_IO1 ((uint32_t)0x00100000)
-#define TSC_GROUP6_IO2 ((uint32_t)0x00200000)
-#define TSC_GROUP6_IO3 ((uint32_t)0x00400000)
-#define TSC_GROUP6_IO4 ((uint32_t)0x00800000)
-#define TSC_GROUP6_ALL_IOS ((uint32_t)0x00F00000)
+#define TSC_GROUP6_IO1 (0x00100000U)
+#define TSC_GROUP6_IO2 (0x00200000U)
+#define TSC_GROUP6_IO3 (0x00400000U)
+#define TSC_GROUP6_IO4 (0x00800000U)
+#define TSC_GROUP6_ALL_IOS (0x00F00000U)
-#define TSC_GROUP7_IO1 ((uint32_t)0x01000000)
-#define TSC_GROUP7_IO2 ((uint32_t)0x02000000)
-#define TSC_GROUP7_IO3 ((uint32_t)0x04000000)
-#define TSC_GROUP7_IO4 ((uint32_t)0x08000000)
-#define TSC_GROUP7_ALL_IOS ((uint32_t)0x0F000000)
+#define TSC_GROUP7_IO1 (0x01000000U)
+#define TSC_GROUP7_IO2 (0x02000000U)
+#define TSC_GROUP7_IO3 (0x04000000U)
+#define TSC_GROUP7_IO4 (0x08000000U)
+#define TSC_GROUP7_ALL_IOS (0x0F000000U)
-#define TSC_GROUP8_IO1 ((uint32_t)0x10000000)
-#define TSC_GROUP8_IO2 ((uint32_t)0x20000000)
-#define TSC_GROUP8_IO3 ((uint32_t)0x40000000)
-#define TSC_GROUP8_IO4 ((uint32_t)0x80000000)
-#define TSC_GROUP8_ALL_IOS ((uint32_t)0xF0000000)
+#define TSC_GROUP8_IO1 (0x10000000U)
+#define TSC_GROUP8_IO2 (0x20000000U)
+#define TSC_GROUP8_IO3 (0x40000000U)
+#define TSC_GROUP8_IO4 (0x80000000U)
+#define TSC_GROUP8_ALL_IOS (0xF0000000U)
-#define TSC_ALL_GROUPS_ALL_IOS ((uint32_t)0xFFFFFFFF)
+#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
/**
* @}
*/
@@ -555,7 +555,7 @@
* @retval SET or RESET
*/
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
-((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) == (uint32_t)((uint32_t)1U << ((__GX_INDEX__) + (uint32_t)16U))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/**
* @}
@@ -603,7 +603,7 @@
#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-#define IS_TSC_SSD(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < 128)))
+#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
@@ -637,7 +637,7 @@
#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0) || (((VAL) > 0) && ((VAL) < TSC_NB_OF_GROUPS)))
+#define IS_TSC_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_uart.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -64,12 +64,13 @@
by calling the HAL_RS485Ex_Init() API.
[..]
- (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
- also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+ (@) These APIs (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
+ also configure the low level Hardware (GPIO, CLOCK, CORTEX...etc) by
calling the customized HAL_UART_MspInit() API.
- Three operation modes are available within this driver :
-
+ [..]
+ [..] Three operation modes are available within this driver :
+
*** Polling mode IO operation ***
=================================
[..]
@@ -176,7 +177,6 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define UART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< UART TX or RX enable acknowledge time-out value */
#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
/**
@@ -186,14 +186,24 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
+/** @addtogroup UART_Private_Functions
* @{
*/
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
/**
* @}
*/
@@ -330,8 +340,8 @@
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
@@ -385,11 +395,11 @@
/* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- huart->Instance->CR3 |= USART_CR3_HDSEL;
+ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
@@ -405,8 +415,8 @@
* @param huart: UART handle.
* @param BreakDetectLength: specifies the LIN break detection length.
* This parameter can be one of the following values:
- * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
- * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
@@ -461,16 +471,16 @@
/* In LIN mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
- huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- huart->Instance->CR2 |= USART_CR2_LINEN;
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
/* Set the USART LIN Break detection length. */
MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
- /* Enable the Peripheral */
+ /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -485,8 +495,8 @@
* @param Address: UART node address (4-, 6-, 7- or 8-bit long).
* @param WakeUpMethod: specifies the UART wakeup method.
* This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHOD_IDLELINE: WakeUp by an idle line detection
- * @arg UART_WAKEUPMETHOD_ADDRESSMARK: WakeUp by an address mark
+ * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+ * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
* @note If the user resorts to idle line detection wake up, the Address parameter
* is useless and ignored by the initialization function.
* @note If the user resorts to address mark wake up, the address length detection
@@ -535,8 +545,8 @@
/* In multiprocessor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
- huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
- huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
{
@@ -576,16 +586,16 @@
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- huart->Instance->CR1 = 0x0;
- huart->Instance->CR2 = 0x0;
- huart->Instance->CR3 = 0x0;
+ huart->Instance->CR1 = 0x0U;
+ huart->Instance->CR2 = 0x0U;
+ huart->Instance->CR3 = 0x0U;
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
@@ -598,7 +608,7 @@
* @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -613,7 +623,7 @@
* @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -638,10 +648,10 @@
and Half duplex data transfers.
(#) There are two mode of transfer:
- (+) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (+) No-Blocking mode: The communication is performed using Interrupts
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: The communication is performed using Interrupts
or DMA, These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
@@ -651,28 +661,51 @@
The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
- (+) HAL_UART_Transmit()
- (+) HAL_UART_Receive()
-
- (#) No-Blocking mode API's with Interrupt are :
- (+) HAL_UART_Transmit_IT()
- (+) HAL_UART_Receive_IT()
- (+) HAL_UART_IRQHandler()
-
- (#) No-Blocking mode API's with DMA are :
- (+) HAL_UART_Transmit_DMA()
- (+) HAL_UART_Receive_DMA()
- (+) HAL_UART_DMAPause()
- (+) HAL_UART_DMAResume()
- (+) HAL_UART_DMAStop()
-
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (+) HAL_UART_TxHalfCpltCallback()
- (+) HAL_UART_TxCpltCallback()
- (+) HAL_UART_RxHalfCpltCallback()
- (+) HAL_UART_RxCpltCallback()
- (+) HAL_UART_ErrorCallback()
-
+ (++) HAL_UART_Transmit()
+ (++) HAL_UART_Receive()
+
+ (#) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_UART_Transmit_IT()
+ (++) HAL_UART_Receive_IT()
+ (++) HAL_UART_IRQHandler()
+
+ (#) Non-Blocking mode API's with DMA are :
+ (++) HAL_UART_Transmit_DMA()
+ (++) HAL_UART_Receive_DMA()
+ (++) HAL_UART_DMAPause()
+ (++) HAL_UART_DMAResume()
+ (++) HAL_UART_DMAStop()
+
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+ (++) HAL_UART_TxHalfCpltCallback()
+ (++) HAL_UART_TxCpltCallback()
+ (++) HAL_UART_RxHalfCpltCallback()
+ (++) HAL_UART_RxCpltCallback()
+ (++) HAL_UART_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_UART_Abort()
+ (++) HAL_UART_AbortTransmit()
+ (++) HAL_UART_AbortReceive()
+ (++) HAL_UART_Abort_IT()
+ (++) HAL_UART_AbortTransmit_IT()
+ (++) HAL_UART_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (++) HAL_UART_AbortCpltCallback()
+ (++) HAL_UART_AbortTransmitCpltCallback()
+ (++) HAL_UART_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-@- In the Half duplex communication, it is forbidden to run the transmit
and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
@@ -691,12 +724,13 @@
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -707,31 +741,34 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0)
+ while(huart->TxXferCount > 0U)
{
huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pData += 2;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pData += 2U;
}
else
{
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
}
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -758,11 +795,12 @@
{
uint16_t* tmp;
uint16_t uhMask;
+ uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -773,6 +811,9 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
huart->RxXferSize = Size;
huart->RxXferCount = Size;
@@ -781,10 +822,10 @@
uhMask = huart->Mask;
/* as long as data have to be received */
- while(huart->RxXferCount > 0)
+ while(huart->RxXferCount > 0U)
{
huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -792,7 +833,7 @@
{
tmp = (uint16_t*) pData ;
*tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2;
+ pData +=2U;
}
else
{
@@ -826,7 +867,7 @@
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -845,7 +886,7 @@
__HAL_UNLOCK(huart);
/* Enable the UART Transmit Data Register Empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+ SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -867,7 +908,7 @@
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -885,17 +926,14 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
- /* Enable the UART Parity Error Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Data Register not empty Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
return HAL_OK;
}
@@ -917,15 +955,13 @@
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check if UART instance supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
/* Check that a Tx process is not already ongoing */
if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -949,19 +985,21 @@
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
/* Enable the UART transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size);
+ HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
- huart->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -985,15 +1023,13 @@
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
/* Check if UART instance supports continuous communication using DMA */
assert_param(IS_UART_DMA_INSTANCE(huart->Instance));
/* Check that a Rx process is not already ongoing */
if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1016,16 +1052,24 @@
/* Set the DMA error callback */
huart->hdmarx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, *(uint32_t*)tmp, Size);
+ HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
- huart->Instance->CR3 |= USART_CR3_DMAR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -1045,15 +1089,21 @@
/* Process Locked */
__HAL_LOCK(huart);
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
{
/* Disable the UART DMA Tx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
{
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Disable the UART DMA Rx request */
- huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
@@ -1075,15 +1125,19 @@
if(huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
- huart->Instance->CR3 |= USART_CR3_DMAT;
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Enable the UART DMA Rx request */
- huart->Instance->CR3 |= USART_CR3_DMAR;
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
@@ -1101,29 +1155,457 @@
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
- HAL_UART_TxHalfCpltCallback() / HAL_UART_RxHalfCpltCallback ():
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
- generated if the DMA transfer interruption occurs at the middle or at the end of the stream
- and the corresponding call back is executed.
- */
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t abortcplt = 1U;
- /* Disable the UART Tx/Rx DMA requests */
- huart->Instance->CR3 &= ~USART_CR3_DMAT;
- huart->Instance->CR3 &= ~USART_CR3_DMAR;
-
- /* Abort the UART DMA tx channel */
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
if(huart->hdmatx != NULL)
{
- HAL_DMA_Abort(huart->hdmatx);
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
}
- /* Abort the UART DMA rx channel */
+ /* DMA Rx Handle is valid */
if(huart->hdmarx != NULL)
{
- HAL_DMA_Abort(huart->hdmarx);
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
}
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable UART Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
return HAL_OK;
}
@@ -1135,75 +1617,149 @@
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- /* UART parity error interrupt occurred -------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET))
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_PE;
- }
-
- /* UART frame error interrupt occurred --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ cr3its = READ_REG(huart->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- /* UART noise error interrupt occurred --------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
-
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- /* UART Over-Run interrupt occurred -----------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET))
- {
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
-
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- /* UART wakeup from Stop mode interrupt occurred -------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET))
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_UART_ErrorCallback(huart);
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+ /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+ if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
{
__HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
/* Set the UART state ready to be able to start again the process */
- huart->gState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
-
HAL_UARTEx_WakeupCallback(huart);
- }
-
- /* UART in mode Receiver ---------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET))
- {
- UART_Receive_IT(huart);
+ return;
}
/* UART in mode Transmitter ------------------------------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET))
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
UART_Transmit_IT(huart);
+ return;
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
- if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET))
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
UART_EndTransmit_IT(huart);
+ return;
}
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* Set the UART state ready to be able to start again the Tx/Rx process */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- HAL_UART_ErrorCallback(huart);
- }
}
/**
@@ -1211,7 +1767,7 @@
* @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1226,7 +1782,7 @@
* @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1271,7 +1827,7 @@
* @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1282,6 +1838,51 @@
}
/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -1318,7 +1919,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Enable USART mute mode by setting the MME bit in the CR1 register */
- huart->Instance->CR1 |= USART_CR1_MME;
+ SET_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -1339,7 +1940,7 @@
huart->gState = HAL_UART_STATE_BUSY;
/* Disable USART mute mode by clearing the MME bit in the CR1 register */
- huart->Instance->CR1 &= ~(USART_CR1_MME);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -1430,6 +2031,8 @@
return HAL_OK;
}
+
+
/**
* @}
*/
@@ -1458,10 +2061,10 @@
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- uint32_t temp1= 0x00, temp2 = 0x00;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
temp1 = huart->gState;
temp2 = huart->RxState;
-
+
return (HAL_UART_StateTypeDef)(temp1 | temp2);
}
@@ -1470,7 +2073,7 @@
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval UART Error Code
-*/
+ */
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
@@ -1494,10 +2097,10 @@
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00000000;
+ uint32_t tmpreg = 0x00000000U;
UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000;
- uint16_t usartdiv = 0x0000;
+ uint16_t brrtemp = 0x0000U;
+ uint16_t usartdiv = 0x0000U;
HAL_StatusTypeDef ret = HAL_OK;
/* Check the parameters */
@@ -1537,7 +2140,7 @@
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
-
+
/* Check UART Over Sampling to set Baud Rate Register */
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
@@ -1564,8 +2167,8 @@
break;
}
- brrtemp = usartdiv & 0xFFF0;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
huart->Instance->BRR = brrtemp;
}
else
@@ -1579,13 +2182,13 @@
huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_UNDEFINED:
default:
@@ -1609,55 +2212,55 @@
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
}
/* if required, configure RX pin active level inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
}
/* if required, configure data inversion */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
/* if required, configure RX/TX pins swap */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure RX overrun detection disabling */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
}
/* if required, configure DMA disabling on reception error */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
}
/* if required, configure auto Baud rate detection scheme */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
/* set auto Baudrate detection parameters if detection is enabled */
- if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
@@ -1665,7 +2268,7 @@
}
/* if required, configure MSB first on communication line */
- if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
@@ -1674,19 +2277,24 @@
/**
* @brief Check the UART Idle State.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
+ uint32_t tickstart = 0U;
+
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Check if the Transmitter is enabled */
if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout Occured */
return HAL_TIMEOUT;
@@ -1696,7 +2304,7 @@
if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, UART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
/* Timeout Occured */
return HAL_TIMEOUT;
@@ -1704,8 +2312,8 @@
}
/* Initialize the UART State */
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1713,95 +2321,93 @@
return HAL_OK;
}
-
/**
* @brief Handle UART Communication Timeout.
- * @param huart: UART handle.
- * @param Flag: specifies the UART flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Timeout: Timeout duration.
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
- while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+ return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
+
+/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+}
+
+
/**
* @brief DMA UART transmit process complete callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- huart->TxXferCount = 0;
-
+ {
+ huart->TxXferCount = 0U;
+
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
@@ -1813,74 +2419,235 @@
/**
* @brief DMA UART transmit process half complete callback.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
HAL_UART_TxHalfCpltCallback(huart);
}
/**
* @brief DMA UART receive process complete callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
/* DMA Normal mode */
if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
{
- huart->RxXferCount = 0;
+ huart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
- huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
}
-
+
HAL_UART_RxCpltCallback(huart);
}
/**
* @brief DMA UART receive process half complete callback.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
HAL_UART_RxHalfCpltCallback(huart);
}
/**
* @brief DMA UART communication error callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0;
- huart->TxXferCount = 0;
- huart->gState= HAL_UART_STATE_READY;
- huart->RxState= HAL_UART_STATE_READY;
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop UART DMA Tx request if ongoing */
+ if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
huart->ErrorCode |= HAL_UART_ERROR_DMA;
HAL_UART_ErrorCallback(huart);
}
/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmarx != NULL)
+ {
+ if(huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmatx != NULL)
+ {
+ if(huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+
+ huart->TxXferCount = 0U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+}
+
+/**
* @brief Send an amount of data in interrupt mode.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
@@ -1890,14 +2657,13 @@
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
-
- if(huart->TxXferCount == 0)
+ if(huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Data Register Empty Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
/* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
return HAL_OK;
}
@@ -1906,14 +2672,13 @@
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- huart->pTxBuffPtr += 2;
+ huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ huart->pTxBuffPtr += 2U;
}
else
{
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF);
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
}
-
huart->TxXferCount--;
return HAL_OK;
@@ -1925,17 +2690,16 @@
}
}
-
/**
* @brief Wrap up transmission in non-blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1945,43 +2709,41 @@
return HAL_OK;
}
-
/**
* @brief Receive an amount of data in interrupt mode.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
/* Check that a Rx process is ongoing */
if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
-
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- huart->pRxBuffPtr +=2;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr +=2U;
}
else
{
- *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
}
- if(--huart->RxXferCount == 0)
+ if(--huart->RxXferCount == 0U)
{
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+ /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -2003,10 +2765,10 @@
}
/**
- * @brief Initializes the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart: UART handle
- * @param WakeUpSelection: UART wake up from stop mode parameters
- * @retval HAL status
+ * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+ * @param huart: UART handle.
+ * @param WakeUpSelection: UART wake up from stop mode parameters.
+ * @retval None
*/
void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
@@ -2019,7 +2781,6 @@
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
}
-
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_uart.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -68,16 +68,16 @@
The baud rate register is computed using the following formula:
- If oversampling is 16 or in LIN mode,
Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
- - If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ - If oversampling is 8U,
+ Baud Rate Register[15:4] = ((2U * PCLKx) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
+ Baud Rate Register[2:0] = (((2U * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UARTEx_Word_Length */
+ This parameter can be a value of @ref UARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits */
+ This parameter can be a value of @ref UART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@@ -87,14 +87,14 @@
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode */
+ This parameter can be a value of @ref UART_Mode. */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control */
+ This parameter can be a value of @ref UART_Hardware_Flow_Control. */
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling */
+ uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8U).
+ This parameter can be a value of @ref UART_Over_Sampling. */
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
@@ -108,36 +108,36 @@
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
- This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type */
+ This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref UART_Tx_Inv */
+ This parameter can be a value of @ref UART_Tx_Inv. */
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref UART_Rx_Inv */
+ This parameter can be a value of @ref UART_Rx_Inv. */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
- This parameter can be a value of @ref UART_Data_Inv */
+ This parameter can be a value of @ref UART_Data_Inv. */
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref UART_Rx_Tx_Swap */
+ This parameter can be a value of @ref UART_Rx_Tx_Swap. */
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref UART_Overrun_Disable */
+ This parameter can be a value of @ref UART_Overrun_Disable. */
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error */
+ This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
This parameter can be a value of @ref UART_AutoBaudRate_Enable */
uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
detection is carried out.
- This parameter can be a value of @ref UART_AutoBaud_Rate_Mode */
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref UART_MSB_First */
+ This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
/**
@@ -151,9 +151,9 @@
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref UART_WakeUp_Address_Length */
+ This parameter can be a value of @ref UART_WakeUp_Address_Length. */
- uint8_t Address; /*!< UART/USART node address (7-bit long max) */
+ uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
@@ -221,12 +221,12 @@
*/
typedef enum
{
- UART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- UART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- UART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- UART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- UART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
}UART_ClockSourceTypeDef;
/**
@@ -244,13 +244,13 @@
uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
uint16_t Mask; /*!< UART Rx RDR register mask */
@@ -258,7 +258,7 @@
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
@@ -283,12 +283,13 @@
/** @defgroup UART_Error UART Error
* @{
*/
-#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_UART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
-#define HAL_UART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
-#define HAL_UART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
-#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */
/**
* @}
*/
@@ -297,7 +298,7 @@
* @{
*/
#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
-#define UART_STOPBITS_1 ((uint32_t)0x00000000) /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
/**
@@ -307,7 +308,7 @@
/** @defgroup UART_Parity UART Parity
* @{
*/
-#define UART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define UART_PARITY_NONE (0x00000000U) /*!< No parity */
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
@@ -317,7 +318,7 @@
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
-#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /*!< No hardware control */
+#define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
@@ -338,7 +339,7 @@
/** @defgroup UART_State UART State
* @{
*/
-#define UART_STATE_DISABLE ((uint32_t)0x00000000) /*!< UART disabled */
+#define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
/**
* @}
@@ -347,7 +348,7 @@
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
-#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16U */
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
/**
* @}
@@ -356,7 +357,7 @@
/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
* @{
*/
-#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */
#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
/**
* @}
@@ -365,7 +366,7 @@
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
@@ -376,7 +377,7 @@
/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
* @{
*/
-#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /*!< UART receiver timeout disable */
+#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
/**
* @}
@@ -385,7 +386,7 @@
/** @defgroup UART_LIN UART Local Interconnection Network mode
* @{
*/
-#define UART_LIN_DISABLE ((uint32_t)0x00000000) /*!< Local Interconnect Network disable */
+#define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */
#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
/**
* @}
@@ -394,7 +395,7 @@
/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
* @{
*/
-#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
/**
* @}
@@ -403,7 +404,7 @@
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
-#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA TX disabled */
+#define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */
#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
/**
* @}
@@ -412,7 +413,7 @@
/** @defgroup UART_DMA_Rx UART DMA Rx
* @{
*/
-#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< UART DMA RX disabled */
+#define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */
#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
/**
* @}
@@ -421,7 +422,7 @@
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
*/
-#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */
#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
/**
* @}
@@ -430,7 +431,7 @@
/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
* @{
*/
-#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
/**
* @}
@@ -439,7 +440,7 @@
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
* @{
*/
-#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
/**
* @}
@@ -450,28 +451,28 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define UART_FLAG_REACK ((uint32_t)0x00400000)
-#define UART_FLAG_TEACK ((uint32_t)0x00200000)
-#define UART_FLAG_WUF ((uint32_t)0x00100000)
-#define UART_FLAG_RWU ((uint32_t)0x00080000)
-#define UART_FLAG_SBKF ((uint32_t)0x00040000)
-#define UART_FLAG_CMF ((uint32_t)0x00020000)
-#define UART_FLAG_BUSY ((uint32_t)0x00010000)
-#define UART_FLAG_ABRF ((uint32_t)0x00008000)
-#define UART_FLAG_ABRE ((uint32_t)0x00004000)
-#define UART_FLAG_EOBF ((uint32_t)0x00001000)
-#define UART_FLAG_RTOF ((uint32_t)0x00000800)
-#define UART_FLAG_CTS ((uint32_t)0x00000400)
-#define UART_FLAG_CTSIF ((uint32_t)0x00000200)
-#define UART_FLAG_LBDF ((uint32_t)0x00000100)
-#define UART_FLAG_TXE ((uint32_t)0x00000080)
-#define UART_FLAG_TC ((uint32_t)0x00000040)
-#define UART_FLAG_RXNE ((uint32_t)0x00000020)
-#define UART_FLAG_IDLE ((uint32_t)0x00000010)
-#define UART_FLAG_ORE ((uint32_t)0x00000008)
-#define UART_FLAG_NE ((uint32_t)0x00000004)
-#define UART_FLAG_FE ((uint32_t)0x00000002)
-#define UART_FLAG_PE ((uint32_t)0x00000001)
+#define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */
+#define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */
+#define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */
+#define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */
+#define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */
+#define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */
+#define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */
+#define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */
+#define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */
+#define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */
+#define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */
+#define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */
+#define UART_FLAG_NE (0x00000004U) /*!< UART noise error */
+#define UART_FLAG_FE (0x00000002U) /*!< UART frame error */
+#define UART_FLAG_PE (0x00000001U) /*!< UART parity error */
/**
* @}
*/
@@ -486,31 +487,19 @@
* - ZZZZZ : Flag position in the ISR register(5bits)
* @{
*/
-#define UART_IT_PE ((uint16_t)0x0028)
-#define UART_IT_TXE ((uint16_t)0x0727)
-#define UART_IT_TC ((uint16_t)0x0626)
-#define UART_IT_RXNE ((uint16_t)0x0525)
-#define UART_IT_IDLE ((uint16_t)0x0424)
-#define UART_IT_LBD ((uint16_t)0x0846)
-#define UART_IT_CTS ((uint16_t)0x096A)
-#define UART_IT_CM ((uint16_t)0x112E)
-#define UART_IT_WUF ((uint16_t)0x1476)
-
-/** Elements values convention: 000000000XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- */
-#define UART_IT_ERR ((uint16_t)0x0060)
-
-/** Elements values convention: 0000ZZZZ00000000b
- * - ZZZZ : Flag position in the ISR register(4bits)
- */
-#define UART_IT_ORE ((uint16_t)0x0300)
-#define UART_IT_NE ((uint16_t)0x0200)
-#define UART_IT_FE ((uint16_t)0x0100)
+#define UART_IT_PE (0x0028U) /*!< UART parity error interruption */
+#define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */
+#define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */
+#define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */
+#define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */
+#define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */
+#define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */
+#define UART_IT_CM (0x112EU) /*!< UART character match interruption */
+#define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */
+#define UART_IT_ERR (0x0060U) /*!< UART error interruption */
+#define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */
+#define UART_IT_NE (0x0200U) /*!< UART noise error interruption */
+#define UART_IT_FE (0x0100U) /*!< UART frame error interruption */
/**
* @}
*/
@@ -518,17 +507,17 @@
/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
* @{
*/
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
-#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
+#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
/**
* @}
@@ -537,11 +526,11 @@
/** @defgroup UART_Request_Parameters UART Request Parameters
* @{
*/
-#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
/**
* @}
*/
@@ -549,15 +538,15 @@
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
* @{
*/
-#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
-#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
-#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
-#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
-#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /*!< Auto Baud rate detection initialization */
-#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
+#define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -565,7 +554,7 @@
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
/**
* @}
@@ -574,7 +563,7 @@
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
/**
* @}
@@ -583,7 +572,7 @@
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
* @{
*/
-#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
/**
* @}
@@ -592,7 +581,7 @@
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
* @{
*/
-#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
/**
* @}
@@ -601,7 +590,7 @@
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
* @{
*/
-#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
/**
* @}
@@ -610,7 +599,7 @@
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */
#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
/**
* @}
@@ -619,7 +608,7 @@
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
/**
* @}
@@ -628,7 +617,7 @@
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
-#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
/**
* @}
@@ -637,7 +626,7 @@
/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
* @{
*/
-#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */
#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
/**
* @}
@@ -646,7 +635,7 @@
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
*/
-#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */
#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
/**
* @}
@@ -655,7 +644,7 @@
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
-#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24)
+#define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
@@ -663,9 +652,9 @@
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
-#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000)
-#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1)
-#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS)
+#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
/**
* @}
*/
@@ -673,7 +662,7 @@
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
*/
-#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */
#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
/**
* @}
@@ -682,7 +671,7 @@
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /*!< UART Driver Enable assertion time LSB position in CR1 register */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -690,7 +679,7 @@
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -698,7 +687,7 @@
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
* @{
*/
-#define UART_IT_MASK ((uint32_t)0x001F) /*!< UART interruptions flags mask */
+#define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */
/**
* @}
*/
@@ -711,7 +700,6 @@
* @}
*/
-
/**
* @}
*/
@@ -728,33 +716,33 @@
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0)
+ } while(0U)
/** @brief Flush the UART Data registers.
- * @param __HANDLE__: UART handle.
+ * @param __HANDLE__: specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__: specifies the UART Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg UART_CLEAR_PEF, Parity Error Clear Flag
- * @arg UART_CLEAR_FEF, Framing Error Clear Flag
- * @arg UART_CLEAR_NEF, Noise detected Clear Flag
- * @arg UART_CLEAR_OREF, OverRun Error Clear Flag
- * @arg UART_CLEAR_IDLEF, IDLE line detected Clear Flag
- * @arg UART_CLEAR_TCF, Transmission Complete Clear Flag
- * @arg UART_CLEAR_LBDF, LIN Break Detection Clear Flag (not available on all devices)
- * @arg UART_CLEAR_CTSF, CTS Interrupt Clear Flag
- * @arg UART_CLEAR_RTOF, Receiver Time Out Clear Flag
- * @arg UART_CLEAR_EOBF, End Of Block Clear Flag (not available on all devices)
- * @arg UART_CLEAR_CMF, Character Match Clear Flag
- * @arg UART_CLEAR_WUF, Wake Up from stop mode Clear Flag (not available on all devices)
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+ * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -791,162 +779,146 @@
/** @brief Check whether the specified UART flag is set or not.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral (datasheet: up to five USART/UARTs)
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg UART_FLAG_REACK: Receive enable acknowledge flag
- * @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg UART_FLAG_WUF: Wake up from stop mode flag
- * @arg UART_FLAG_RWU: Receiver wake up flag
- * @arg UART_FLAG_SBKF: Send Break flag
- * @arg UART_FLAG_CMF: Character match flag
- * @arg UART_FLAG_BUSY: Busy flag
- * @arg UART_FLAG_ABRF: Auto Baud rate detection flag
- * @arg UART_FLAG_ABRE: Auto Baud rate detection error flag
- * @arg UART_FLAG_EOBF: End of block flag
- * @arg UART_FLAG_RTOF: Receiver timeout flag
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TXE: Transmit data register empty flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_RXNE: Receive data register not empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
- * @arg UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
+ * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag
+ * @arg @ref UART_FLAG_SBKF Send Break flag
+ * @arg @ref UART_FLAG_CMF Character match flag
+ * @arg @ref UART_FLAG_BUSY Busy flag
+ * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
+ * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
+ * @arg @ref UART_FLAG_EOBF End of block flag
+ * @arg @ref UART_FLAG_RTOF Receiver timeout flag
+ * @arg @ref UART_FLAG_CTS CTS Change flag (not available for UART4 and UART5)
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
+ * @arg @ref UART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref UART_FLAG_TC Transmission Complete flag
+ * @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref UART_FLAG_ORE Overrun Error flag
+ * @arg @ref UART_FLAG_NE Noise Error flag
+ * @arg @ref UART_FLAG_FE Framing Error flag
+ * @arg @ref UART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __INTERRUPT__: specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __INTERRUPT__: specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
+ ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __IT__: specifies the UART interrupt to check.
* This parameter can be one of the following values:
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_ORE Overrun Error interrupt
+ * @arg @ref UART_IT_NE Noise Error interrupt
+ * @arg @ref UART_IT_FE Framing Error interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __IT__: specifies the UART interrupt source to check.
* This parameter can be one of the following values:
- * @arg UART_IT_WUF: Wakeup from stop mode interrupt
- * @arg UART_IT_CM: Character match interrupt
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ORE: OverRun Error interrupt
- * @arg UART_IT_NE: Noise Error interrupt
- * @arg UART_IT_FE: Framing Error interrupt
- * @arg UART_IT_PE: Parity Error interrupt
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt (not available for UART4 and UART5)
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @arg @ref UART_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg UART_CLEAR_PEF: Parity Error Clear Flag
- * @arg UART_CLEAR_FEF: Framing Error Clear Flag
- * @arg UART_CLEAR_NEF: Noise detected Clear Flag
- * @arg UART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg UART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg UART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg UART_CLEAR_LBDF: LIN Break Detection Clear Flag
- * @arg UART_CLEAR_CTSF: CTS Interrupt Clear Flag
- * @arg UART_CLEAR_RTOF: Receiver Time Out Clear Flag
- * @arg UART_CLEAR_EOBF: End Of Block Clear Flag
- * @arg UART_CLEAR_CMF: Character Match Clear Flag
- * @arg UART_CLEAR_WUF: Wake Up from stop mode Clear Flag
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
+ * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
* @retval None
*/
#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific UART request flag.
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4, 5 to select the USART or
- * UART peripheral. (datasheet: up to five USART/UARTs)
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
- * @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
- * @arg UART_SENDBREAK_REQUEST: Send Break Request
- * @arg UART_MUTE_MODE_REQUEST: Mute Mode Request
- * @arg UART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+ * @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+ * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+ * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
/** @brief Enable the UART one bit sample method.
* @param __HANDLE__: specifies the UART Handle.
@@ -962,14 +934,12 @@
/** @brief Enable UART.
* @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-/** @brief Disable UART
+/** @brief Disable UART.
* @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be UARTx where x: 1, 2, 3, 4 or 5 to select the UART peripheral
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -990,7 +960,7 @@
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable CTS flow control.
* @note This macro allows to disable CTS hardware flow control for a given UART instance,
@@ -1008,7 +978,7 @@
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0)
+ } while(0U)
/** @brief Enable RTS flow control.
* @note This macro allows to enable RTS hardware flow control for a given UART instance,
@@ -1026,7 +996,7 @@
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable RTS flow control.
* @note This macro allows to disable RTS hardware flow control for a given UART instance,
@@ -1044,7 +1014,7 @@
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0)
+ } while(0U)
/**
* @}
@@ -1054,40 +1024,39 @@
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
-
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__: UART clock.
* @param __BAUD__: Baud rate set by the user.
* @retval Division result
*/
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__: UART clock.
* @param __BAUD__: Baud rate set by the user.
* @retval Division result
*/
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
-/** @brief Check UART Baud rate
+/** @brief Check UART Baud rate.
* @param __BAUDRATE__: Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8)
+ * divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
/** @brief Check UART assertion time.
* @param __TIME__: 5-bit value assertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/** @brief Check UART deassertion time.
* @param __TIME__: 5-bit value deassertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/**
* @brief Ensure that UART frame number of stop bits is valid.
@@ -1124,7 +1093,7 @@
* @param __MODE__: UART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that UART state is valid.
@@ -1163,9 +1132,9 @@
* @param __MODE__: UART auto Baud rate detection mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
/**
@@ -1346,11 +1315,12 @@
((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
/**
* @}
*/
-/* Include UART HAL Extension module */
+/* Include UART HAL Extended module */
#include "stm32f3xx_hal_uart_ex.h"
/* Exported functions --------------------------------------------------------*/
@@ -1389,12 +1359,23 @@
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
/**
* @}
@@ -1439,11 +1420,12 @@
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Extended UART HAL module driver.
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
@@ -156,8 +156,8 @@
* @param huart: UART handle.
* @param Polarity: select the driver enable polarity.
* This parameter can be one of the following values:
- * @arg UART_DE_POLARITY_HIGH: DE signal is active high
- * @arg UART_DE_POLARITY_LOW: DE signal is active low
+ * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+ * @arg @ref UART_DE_POLARITY_LOW DE signal is active low
* @param AssertionTime: Driver Enable assertion time:
* 5-bit value defining the time between the activation of the DE (Driver Enable)
* signal and the beginning of the start bit. It is expressed in sample time
@@ -171,7 +171,7 @@
*/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
{
- uint32_t temp = 0x0;
+ uint32_t temp = 0x0U;
/* Check the UART handle allocation */
if(huart == NULL)
@@ -258,18 +258,18 @@
/**
- * @brief UART wakeup from Stop mode callback
- * @param huart: UART handle
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart: UART handle.
* @retval None
*/
- __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_UARTEx_WakeupCallback can be implemented in the user file
- */
+ the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+ */
}
/**
@@ -280,10 +280,10 @@
/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### Peripheral Control function #####
- ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
[..]
This subsection provides extended functions allowing to control the UART.
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
@@ -301,14 +301,15 @@
* @param huart: UART handle.
* @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
* This parameter can be one of the following values:
- * @arg UART_WAKEUP_ON_ADDRESS
- * @arg UART_WAKEUP_ON_STARTBIT
- * @arg UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart = 0U;
/* check the wake-up from stop mode UART instance */
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
@@ -334,8 +335,11 @@
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
status = HAL_TIMEOUT;
}
@@ -414,8 +418,8 @@
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
* @param huart: UART handle.
* @param AddressLength: this parameter can be one of the following values:
- * @arg UART_ADDRESS_DETECT_4B: 4-bit long address
- * @arg UART_ADDRESS_DETECT_7B: 6-, 7- or 8-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f3xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
- * @brief Header file of UART HAL Extension module.
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
@@ -66,12 +66,12 @@
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1)
-#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0)
+#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
#else
-#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
@@ -100,15 +100,7 @@
* @}
*/
-/** @addtogroup UARTEx_Exported_Functions_Group2
- * @{
- */
-
/* IO operation functions *****************************************************/
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-/**
- * @}
- */
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
@@ -119,6 +111,8 @@
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
/**
* @}
*/
@@ -139,7 +133,7 @@
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -250,10 +244,10 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -288,9 +282,9 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#else
-#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -359,7 +353,7 @@
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx */
@@ -382,36 +376,36 @@
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU ; \
} \
} \
-} while(0)
+} while(0U)
#else
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
@@ -419,25 +413,25 @@
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
-} while(0)
+} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_usart.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
@@ -47,7 +47,7 @@
flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_USART_MspInit(&husart) API.
(#) Three operation modes are available within this driver :
@@ -107,6 +107,10 @@
[..]
(@) You can refer to the USART HAL driver header file for more useful macros
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
@endverbatim
******************************************************************************
@@ -158,10 +162,8 @@
/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
-#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
-#define USART_TEACK_REACK_TIMEOUT ((uint32_t) 1000) /*!< USART TX or RX enable acknowledge time-out value */
-#define USART_TXDMA_TIMEOUTVALUE 22000
-#define USART_TIMEOUT_VALUE 22000
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
@@ -173,15 +175,19 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions USART Private Functions
+/** @addtogroup USART_Private_Functions
* @{
*/
+static void USART_EndTransfer(USART_HandleTypeDef *husart);
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
@@ -264,9 +270,9 @@
*/
/**
- * @brief Initializes the USART mode according to the specified
+ * @brief Initialize the USART mode according to the specified
* parameters in the USART_InitTypeDef and initialize the associated handle.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
@@ -315,12 +321,12 @@
/**
* @brief DeInitialize the USART peripheral.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
- /* Check the USART handle allocation */
+ /* Check the USART handle allocation */
if(husart == NULL)
{
return HAL_ERROR;
@@ -331,9 +337,9 @@
husart->State = HAL_USART_STATE_BUSY;
- husart->Instance->CR1 = 0x0;
- husart->Instance->CR2 = 0x0;
- husart->Instance->CR3 = 0x0;
+ husart->Instance->CR1 = 0x0U;
+ husart->Instance->CR2 = 0x0U;
+ husart->Instance->CR3 = 0x0U;
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
@@ -352,7 +358,7 @@
* @param husart: USART handle.
* @retval None
*/
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -367,7 +373,7 @@
* @param husart: USART handle.
* @retval None
*/
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -382,7 +388,7 @@
*/
/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+ * @brief USART Transmit and Receive functions
*
@verbatim
===============================================================================
@@ -408,18 +414,18 @@
The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
- (++) HAL_USART_Transmit()in simplex mode
+ (++) HAL_USART_Transmit() in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
(#) No-Blocking mode APIs with Interrupt are :
- (++) HAL_USART_Transmit_IT()in simplex mode
+ (++) HAL_USART_Transmit_IT() in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
(++) HAL_USART_TransmitReceive_IT()in full duplex mode
(++) HAL_USART_IRQHandler()
(#) No-Blocking mode APIs with DMA are :
- (++) HAL_USART_Transmit_DMA()in simplex mode
+ (++) HAL_USART_Transmit_DMA() in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
@@ -434,25 +440,44 @@
(++) HAL_USART_ErrorCallback()
(++) HAL_USART_TxRxCpltCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (++) HAL_USART_Abort()
+ (++) HAL_USART_Abort_IT()
+
+ (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided:
+ (++) HAL_USART_AbortCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
* @brief Simplex send an amount of data in blocking mode.
- * @param husart: USART handle.
- * @param pTxData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Timeout duration.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -463,34 +488,38 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
husart->TxXferSize = Size;
husart->TxXferCount = Size;
/* Check the remaining data to be sent */
- while(husart->TxXferCount > 0)
+ while(husart->TxXferCount > 0U)
{
husart->TxXferCount--;
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- pTxData += 2;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ pTxData += 2U;
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFF);
+ husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
}
}
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
+ /* At end of Tx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -507,29 +536,34 @@
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart: USART handle.
- * @param pRxData: Pointer to data buffer.
- * @param Size: Amount of data to be received.
- * @param Timeout: Timeout duration.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
uint16_t uhMask;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
husart->RxXferSize = Size;
husart->RxXferCount = Size;
@@ -538,7 +572,7 @@
uhMask = husart->Mask;
/* as long as data have to be received */
- while(husart->RxXferCount > 0)
+ while(husart->RxXferCount > 0U)
{
husart->RxXferCount--;
@@ -546,14 +580,14 @@
* clock for the slave to send data.
* Whatever the frame length (7, 8 or 9-bit long), the same dummy value
* can be written for all the cases. */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -562,7 +596,7 @@
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ pRxData +=2U;
}
else
{
@@ -570,6 +604,7 @@
}
}
+ /* At end of Rx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -585,30 +620,35 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be sent (same amount to be received).
- * @param Timeout: Timeout duration.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
uint16_t uhMask;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
husart->RxXferSize = Size;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
@@ -619,13 +659,13 @@
uhMask = husart->Mask;
/* Check the remain data to be sent */
- while(husart->TxXferCount > 0)
+ while(husart->TxXferCount > 0U)
{
husart->TxXferCount--;
husart->RxXferCount--;
/* Wait until TC flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -633,7 +673,7 @@
{
tmp = (uint16_t*) pTxData;
husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2;
+ pTxData += 2U;
}
else
{
@@ -641,7 +681,7 @@
}
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -650,7 +690,7 @@
{
tmp = (uint16_t*) pRxData ;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ pRxData +=2U;
}
else
{
@@ -658,6 +698,7 @@
}
}
+ /* At end of TxRx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
@@ -673,16 +714,16 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -718,21 +759,22 @@
}
/**
- * @brief Receive an amount of data in blocking mode.
+ * @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart: USART handle.
- * @param pRxData: pointer to data buffer.
- * @param Size: amount of data to be received.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -745,27 +787,23 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Enable the USART Parity Error Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
- /* Enable the USART Data Register not empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Send dummy byte in order to generate the clock for the Slave to send the next data */
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FF);
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
}
else
{
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
}
return HAL_OK;
@@ -778,10 +816,10 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be sent (same amount to be received).
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -789,10 +827,11 @@
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -809,20 +848,17 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
- /* Enable the USART Data Register not empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
-
- /* Enable the USART Parity Error Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
/* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -830,29 +866,29 @@
{
return HAL_BUSY;
}
-
}
/**
* @brief Send an amount of data in DMA mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to data buffer.
- * @param Size: amount of data to be sent.
- * @note This function starts a DMA transfer in interrrupt mode meaning that
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @note This function starts a DMA transfer in interrupt mode meaning that
* DMA half transfer complete, DMA transfer complete and DMA transfer
* error interrupts are enabled
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- uint32_t *tmp=0;
+ uint32_t *tmp=0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -879,12 +915,12 @@
/* Clear the TC flag in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
- husart->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -896,13 +932,13 @@
/**
* @brief Receive an amount of data in DMA mode.
- * @param husart: USART handle.
- * @param pRxData: pointer to data buffer.
- * @param Size: amount of data to be received.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer.
+ * @param Size amount of data to be received.
* @note When the USART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note This function starts a DMA transfer in interrrupt mode meaning that
+ * @note This function starts a DMA transfer in interrupt mode meaning that
* DMA half transfer complete, DMA transfer complete and DMA transfer
* error interrupts are enabled
* @retval HAL status
@@ -911,9 +947,10 @@
{
uint32_t *tmp;
+ /* Check that a Rx process is not already ongoing */
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -945,19 +982,28 @@
/* Enable the USART transmit DMA channel: the transmit channel is used in order
to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive mode */
- tmp = (uint32_t*)&pRxData;
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
- husart->Instance->CR3 |= USART_CR3_DMAR;
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
- husart->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -969,12 +1015,12 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: USART handle.
- * @param pTxData: pointer to TX data buffer.
- * @param pRxData: pointer to RX data buffer.
- * @param Size: amount of data to be received/sent.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer.
+ * @param pRxData pointer to RX data buffer.
+ * @param Size amount of data to be received/sent.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note This function starts a 2 DMA transfers in interrrupt mode meaning that
+ * @note This function starts a 2 DMA transfers in interrupt mode meaning that
* DMA half transfer complete, DMA transfer complete and DMA transfer
* error interrupts are enabled
* @retval HAL status
@@ -985,10 +1031,11 @@
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
+
/* Process Locked */
__HAL_LOCK(husart);
@@ -1026,19 +1073,25 @@
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
/* Clear the TC flag in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
- husart->Instance->CR3 |= USART_CR3_DMAR;
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
- husart->Instance->CR3 |= USART_CR3_DMAT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -1050,7 +1103,7 @@
/**
* @brief Pause the DMA Transfer.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
@@ -1058,22 +1111,29 @@
/* Process Locked */
__HAL_LOCK(husart);
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
{
/* Disable the USART DMA Tx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
- }
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- /* Disable the USART DMA Rx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+ (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
{
- /* Disable the USART DMA Tx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
- /* Disable the USART DMA Rx request */
- husart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the USART DMA Tx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Rx request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
}
/* Process Unlocked */
@@ -1084,7 +1144,7 @@
/**
* @brief Resume the DMA Transfer.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
@@ -1095,26 +1155,23 @@
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Enable the USART DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAT;
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if(husart->State == HAL_USART_STATE_BUSY_RX)
+ else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
+ (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
- /* Enable the USART DMA Rx request */
- husart->Instance->CR3 |= USART_CR3_DMAR;
- }
- else if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
- {
- /* Clear the Overrun flag before resumming the Rx transfer*/
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* Enable the USART DMA Rx request before the DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAR;
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Enable the USART DMA Tx request */
- husart->Instance->CR3 |= USART_CR3_DMAT;
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
/* Process Unlocked */
@@ -1125,7 +1182,7 @@
/**
* @brief Stop the DMA Transfer.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
@@ -1139,8 +1196,8 @@
*/
/* Disable the USART Tx/Rx DMA requests */
- husart->Instance->CR3 &= ~USART_CR3_DMAT;
- husart->Instance->CR3 &= ~USART_CR3_DMAR;
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA tx channel */
if(husart->hdmatx != NULL)
@@ -1153,76 +1210,355 @@
HAL_DMA_Abort(husart->hdmarx);
}
+ USART_EndTransfer(husart);
husart->State = HAL_USART_STATE_READY;
return HAL_OK;
}
/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable USART Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t abortcplt = 1U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Handle USART interrupt request.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
{
-
- /* USART parity error interrupt occurred ------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
- husart->ErrorCode |= HAL_USART_ERROR_PE;
- /* Set the USART state ready to be able to start again the process */
- husart->State = HAL_USART_STATE_READY;
- }
+ uint32_t isrflags = READ_REG(husart->Instance->ISR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
- /* USART frame error interrupt occurred -------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
- husart->ErrorCode |= HAL_USART_ERROR_FE;
- /* Set the USART state ready to be able to start again the process */
- husart->State = HAL_USART_STATE_READY;
- }
-
- /* USART noise error interrupt occurred -------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
{
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
- husart->ErrorCode |= HAL_USART_ERROR_NE;
- /* Set the USART state ready to be able to start again the process */
- husart->State = HAL_USART_STATE_READY;
- }
-
- /* USART Over-Run interrupt occurred ----------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET))
- {
- __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
- husart->ErrorCode |= HAL_USART_ERROR_ORE;
- /* Set the USART state ready to be able to start again the process */
- husart->State = HAL_USART_STATE_READY;
- }
-
- /* Call USART Error Call back function if need be --------------------------*/
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
- {
- HAL_USART_ErrorCallback(husart);
- }
-
- /* USART in mode Receiver --------------------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_RXNE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE) != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
}
}
- /* USART in mode Transmitter -----------------------------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_TXE) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE) != RESET))
+ /* If some errors occur */
+ cr3its = READ_REG(husart->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* USART parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
+
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ /* Call USART Error Call back function if need be --------------------------*/
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the USART state ready to be able to start again the process,
+ Disable Interrupts, and disable DMA requests, if ongoing */
+ USART_EndTransfer(husart);
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
+
+ /* Abort the USART DMA Tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART Tx DMA Abort callback to NULL : no callback
+ executed at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA TX */
+ HAL_DMA_Abort_IT(husart->hdmatx);
+ }
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART Rx DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_USART_ErrorCallback(husart);
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+
+ } /* End if some error occurs */
+
+
+ /* USART in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
@@ -1232,12 +1568,14 @@
{
USART_TransmitReceive_IT(husart);
}
+ return;
}
/* USART in mode Transmitter (transmission end) -----------------------------*/
- if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET))
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
USART_EndTransmit_IT(husart);
+ return;
}
}
@@ -1259,10 +1597,10 @@
/**
* @brief Tx Half Transfer completed callback.
- * @param husart: USART handle
+ * @param husart: USART handle.
* @retval None
*/
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -1304,7 +1642,7 @@
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: USART handle
+ * @param husart: USART handle.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1333,6 +1671,21 @@
}
/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -1395,6 +1748,283 @@
@endverbatim
* @{
*/
+/**
+ * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_EndTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->TxXferCount = 0U;
+
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ }
+ /* DMA Circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ HAL_USART_TxCpltCallback(husart);
+ }
+ }
+}
+
+/**
+ * @brief DMA USART transmit process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_USART_TxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART receive process complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ {
+ husart->RxXferCount = 0U;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
+ in USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* similarly, disable the DMA TX transfer that was started to provide the
+ clock to the slave device */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ husart->State= HAL_USART_STATE_READY;
+ }
+ /* DMA circular mode */
+ else
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ HAL_USART_RxCpltCallback(husart);
+ }
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
+ else
+ {
+ HAL_USART_TxRxCpltCallback(husart);
+ }
+ }
+
+}
+
+/**
+ * @brief DMA USART receive process half complete callback.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ HAL_USART_RxHalfCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication error callback.
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+ USART_EndTransfer(husart);
+
+ husart->ErrorCode |= HAL_USART_ERROR_DMA;
+ husart->State= HAL_USART_STATE_READY;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmarx != NULL)
+ {
+ if(husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmatx != NULL)
+ {
+ if(husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+
+/**
+ * @brief Handle USART Communication Timeout.
+ * @param husart USART handle.
+ * @param Flag Specifies the USART flag to check.
+ * @param Status the Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout timeout duration.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
/**
* @brief Configure the USART peripheral.
@@ -1403,11 +2033,11 @@
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
- uint32_t tmpreg = 0x0;
+ uint32_t tmpreg = 0x0U;
USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
HAL_StatusTypeDef ret = HAL_OK;
- uint16_t brrtemp = 0x0000;
- uint16_t usartdiv = 0x0000;
+ uint16_t brrtemp = 0x0000U;
+ uint16_t usartdiv = 0x0000U;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -1450,19 +2080,19 @@
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetPCLK2Freq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint16_t)(((2U*HSI_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint16_t)(((2U*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint16_t)(((2U*LSE_VALUE) + (husart->Init.BaudRate/2U)) / husart->Init.BaudRate);
break;
case USART_CLOCKSOURCE_UNDEFINED:
default:
@@ -1470,8 +2100,8 @@
break;
}
- brrtemp = usartdiv & 0xFFF0;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U);
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
husart->Instance->BRR = brrtemp;
return ret;
@@ -1484,14 +2114,19 @@
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
+ uint32_t tickstart = 0U;
+
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Check if the Transmitter is enabled */
if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout Occured */
return HAL_TIMEOUT;
@@ -1507,7 +2142,7 @@
if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
@@ -1526,212 +2161,22 @@
/**
- * @brief Handle USART Communication Timeout.
- * @param husart: USART handle.
- * @param Flag: specifies the USART flag to check.
- * @param Status: the Flag status (SET or RESET).
- * @param Timeout: timeout duration.
- * @retval HAL status
- */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-
-/**
- * @brief DMA USART transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- husart->TxXferCount = 0;
-
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- /* Disable the DMA transfer for transmit request by resetting the DMAT bit
- in the USART CR3 register */
- husart->Instance->CR3 &= ~(USART_CR3_DMAT);
-
- /* Enable the USART Transmit Complete Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
- }
- }
- /* DMA Circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_TX)
- {
- HAL_USART_TxCpltCallback(husart);
- }
- }
-}
-
-
-/**
- * @brief DMA USART transmit process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_USART_TxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART receive process complete callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
- {
- husart->RxXferCount = 0;
-
- /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit
- in USART CR3 register */
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
- /* similarly, disable the DMA TX transfer that was started to provide the
- clock to the slave device */
- husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
-
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- husart->State= HAL_USART_STATE_READY;
- }
- /* DMA circular mode */
- else
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
- {
- HAL_USART_RxCpltCallback(husart);
- }
- /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
- else
- {
- HAL_USART_TxRxCpltCallback(husart);
- }
- }
-
-}
-
-/**
- * @brief DMA USART receive process half complete callback.
- * @param hdma : DMA handle.
- * @retval None
- */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- HAL_USART_RxHalfCpltCallback(husart);
-}
-
-/**
- * @brief DMA USART communication error callback.
- * @param hdma: DMA handle.
- * @retval None
- */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
-{
- USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- husart->RxXferCount = 0;
- husart->TxXferCount = 0;
- husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
-
- HAL_USART_ErrorCallback(husart);
-}
-
-/**
* @brief Simplex send an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Transmit_IT().
* @note The USART errors are not managed to avoid the overrun error.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
+ /* Check that a Tx process is ongoing */
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
- if(husart->TxXferCount == 0)
+ if(husart->TxXferCount == 0U)
{
/* Disable the USART Transmit data register empty interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
@@ -1746,12 +2191,12 @@
if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FF);
- husart->pTxBuffPtr += 2;
+ husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ husart->pTxBuffPtr += 2U;
}
else
{
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
}
husart->TxXferCount--;
@@ -1768,7 +2213,7 @@
/**
* @brief Wraps up transmission in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1780,6 +2225,7 @@
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+ /* Tx process is ended, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxCpltCallback(husart);
@@ -1792,12 +2238,12 @@
* @brief Simplex receive an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Receive_IT().
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_RX)
@@ -1807,7 +2253,7 @@
{
tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2;
+ husart->pRxBuffPtr += 2U;
}
else
{
@@ -1815,18 +2261,17 @@
}
/* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
- if(--husart->RxXferCount == 0)
+ if(--husart->RxXferCount == 0U)
{
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-
- /* Disable the USART Parity Error Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Rx process is completed, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
@@ -1851,13 +2296,13 @@
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
+ uint16_t* tmp=0U;
uint16_t uhMask = husart->Mask;
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
- if(husart->TxXferCount != 0x00)
+ if(husart->TxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
@@ -1865,7 +2310,7 @@
{
tmp = (uint16_t*) husart->pTxBuffPtr;
husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
- husart->pTxBuffPtr += 2;
+ husart->pTxBuffPtr += 2U;
}
else
{
@@ -1874,14 +2319,14 @@
husart->TxXferCount--;
/* Check the latest data transmitted */
- if(husart->TxXferCount == 0)
+ if(husart->TxXferCount == 0U)
{
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
}
}
}
- if(husart->RxXferCount != 0x00)
+ if(husart->RxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
@@ -1889,7 +2334,7 @@
{
tmp = (uint16_t*) husart->pRxBuffPtr;
*tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2;
+ husart->pRxBuffPtr += 2U;
}
else
{
@@ -1900,16 +2345,15 @@
}
/* Check the latest data received */
- if(husart->RxXferCount == 0)
+ if(husart->RxXferCount == 0U)
{
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-
- /* Disable the USART Parity Error Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ /* Disable the USART Parity Error Interrupt and RXNE interrupt*/
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Rx process is completed, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
HAL_USART_TxRxCpltCallback(husart);
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_usart.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
@@ -100,14 +100,14 @@
*/
typedef enum
{
- HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
}HAL_USART_StateTypeDef;
/**
@@ -115,12 +115,12 @@
*/
typedef enum
{
- USART_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
- USART_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
- USART_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
- USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
- USART_CLOCKSOURCE_LSE = 0x08, /*!< LSE clock source */
- USART_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
+ USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
+ USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
}USART_ClockSourceTypeDef;
@@ -137,13 +137,13 @@
uint16_t TxXferSize; /*!< USART Tx Transfer size */
- uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
uint16_t RxXferSize; /*!< USART Rx Transfer size */
- uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
uint16_t Mask; /*!< USART Rx RDR register mask */
@@ -151,11 +151,11 @@
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
- __IO uint32_t ErrorCode; /*!< USART Error code */
+ __IO uint32_t ErrorCode; /*!< USART Error code */
}USART_HandleTypeDef;
@@ -171,31 +171,31 @@
/** @defgroup USART_Error USART Error
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
+#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
/**
* @}
- */
+ */
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
-#define USART_STOPBITS_1 ((uint32_t)0x00000000) /*!< USART frame with 1 stop bit */
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
+#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
/**
* @}
- */
+ */
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
+#define USART_PARITY_NONE (0x00000000U) /*!< No parity */
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
@@ -205,7 +205,7 @@
/** @defgroup USART_Mode USART Mode
* @{
*/
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
/**
@@ -215,7 +215,7 @@
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< USART clock disable */
+#define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
/**
* @}
@@ -224,8 +224,8 @@
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< USART Clock signal is steady Low */
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
+#define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
/**
* @}
*/
@@ -233,7 +233,7 @@
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE ((uint32_t)0x00000000) /*!< USART frame phase on first clock transition */
+#define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
/**
* @}
@@ -242,7 +242,7 @@
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
@@ -262,19 +262,20 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define USART_FLAG_REACK ((uint32_t)0x00400000) /*!< USART receive enable acknowledge flag */
-#define USART_FLAG_TEACK ((uint32_t)0x00200000) /*!< USART transmit enable acknowledge flag */
-#define USART_FLAG_BUSY ((uint32_t)0x00010000) /*!< USART busy flag */
-#define USART_FLAG_CTS ((uint32_t)0x00000400) /*!< USART clear to send flag */
-#define USART_FLAG_CTSIF ((uint32_t)0x00000200) /*!< USART clear to send interrupt flag */
-#define USART_FLAG_TXE ((uint32_t)0x00000080) /*!< USART transmit data register empty */
-#define USART_FLAG_TC ((uint32_t)0x00000040) /*!< USART transmission complete */
-#define USART_FLAG_RXNE ((uint32_t)0x00000020) /*!< USART read data register not empty */
-#define USART_FLAG_IDLE ((uint32_t)0x00000010) /*!< USART idle flag */
-#define USART_FLAG_ORE ((uint32_t)0x00000008) /*!< USART overrun error */
-#define USART_FLAG_NE ((uint32_t)0x00000004) /*!< USART noise error */
-#define USART_FLAG_FE ((uint32_t)0x00000002) /*!< USART frame error */
-#define USART_FLAG_PE ((uint32_t)0x00000001) /*!< USART parity error */
+#define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
+#define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
+#define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
+#define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
+#define USART_FLAG_LBDF (0x00000100U) /*!< USART LIN break detection flag */
+#define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
+#define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
+#define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
+#define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
+#define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
+#define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
+#define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
+#define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
/**
* @}
*/
@@ -290,15 +291,15 @@
* @{
*/
-#define USART_IT_PE ((uint16_t)0x0028) /*!< USART parity error interruption */
-#define USART_IT_TXE ((uint16_t)0x0727) /*!< USART transmit data register empty interruption */
-#define USART_IT_TC ((uint16_t)0x0626) /*!< USART transmission complete interruption */
-#define USART_IT_RXNE ((uint16_t)0x0525) /*!< USART read data register not empty interruption */
-#define USART_IT_IDLE ((uint16_t)0x0424) /*!< USART idle interruption */
-#define USART_IT_ERR ((uint16_t)0x0060) /*!< USART error interruption */
-#define USART_IT_ORE ((uint16_t)0x0300) /*!< USART overrun error interruption */
-#define USART_IT_NE ((uint16_t)0x0200) /*!< USART noise error interruption */
-#define USART_IT_FE ((uint16_t)0x0100) /*!< USART frame error interruption */
+#define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
+#define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
+#define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
+#define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
+#define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
+#define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
+#define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
+#define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
/**
* @}
*/
@@ -320,7 +321,7 @@
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
*/
-#define USART_IT_MASK ((uint16_t)0x001F) /*!< USART interruptions flags mask */
+#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
/**
* @}
*/
@@ -348,24 +349,24 @@
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ } while(0U)
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__: specifies the USART Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive enable acknowledge flag
- * @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
- * @arg USART_FLAG_BUSY: Busy flag
- * @arg USART_FLAG_CTS: CTS Change flag
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
+ * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
+ * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
+ * @arg @ref USART_FLAG_BUSY Busy flag
+ * @arg @ref USART_FLAG_CTS CTS Change flag
+ * @arg @ref USART_FLAG_TXE Transmit data register empty flag
+ * @arg @ref USART_FLAG_TC Transmission Complete flag
+ * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref USART_FLAG_IDLE Idle Line detection flag
+ * @arg @ref USART_FLAG_ORE OverRun Error flag
+ * @arg @ref USART_FLAG_NE Noise Error flag
+ * @arg @ref USART_FLAG_FE Framing Error flag
+ * @arg @ref USART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
@@ -374,13 +375,13 @@
* @param __HANDLE__: specifies the USART Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg USART_CLEAR_PEF
- * @arg USART_CLEAR_FEF
- * @arg USART_CLEAR_NEF
- * @arg USART_CLEAR_OREF
- * @arg USART_CLEAR_IDLEF
- * @arg USART_CLEAR_TCF
- * @arg USART_CLEAR_CTSF
+ * @arg @ref USART_CLEAR_PEF
+ * @arg @ref USART_CLEAR_FEF
+ * @arg @ref USART_CLEAR_NEF
+ * @arg @ref USART_CLEAR_OREF
+ * @arg @ref USART_CLEAR_IDLEF
+ * @arg @ref USART_CLEAR_TCF
+ * @arg @ref USART_CLEAR_CTSF
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -419,32 +420,32 @@
* @param __HANDLE__: specifies the USART Handle.
* @param __INTERRUPT__: specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__: specifies the USART Handle.
* @param __INTERRUPT__: specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
@@ -452,34 +453,34 @@
* @param __HANDLE__: specifies the USART Handle.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__: specifies the USART Handle.
* @param __IT__: specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ORE: OverRun Error interrupt
- * @arg USART_IT_NE: Noise Error interrupt
- * @arg USART_IT_FE: Framing Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5) == 2)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
+ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
(((uint16_t)(__IT__)) & USART_IT_MASK)))
@@ -488,13 +489,13 @@
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg USART_CLEAR_PEF: Parity Error Clear Flag
- * @arg USART_CLEAR_FEF: Framing Error Clear Flag
- * @arg USART_CLEAR_NEF: Noise detected Clear Flag
- * @arg USART_CLEAR_OREF: OverRun Error Clear Flag
- * @arg USART_CLEAR_IDLEF: IDLE line detected Clear Flag
- * @arg USART_CLEAR_TCF: Transmission Complete Clear Flag
- * @arg USART_CLEAR_CTSF: CTS Interrupt Clear Flag
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -503,8 +504,8 @@
* @param __HANDLE__: specifies the USART Handle.
* @param __REQ__: specifies the request flag to set.
* This parameter can be one of the following values:
- * @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
- * @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
+ * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+ * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
@@ -513,13 +514,13 @@
/** @brief Enable the USART one bit sample method.
* @param __HANDLE__: specifies the USART Handle.
* @retval None
- */
+ */
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the USART one bit sample method.
* @param __HANDLE__: specifies the USART Handle.
* @retval None
- */
+ */
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable USART.
@@ -546,10 +547,10 @@
/** @brief Check USART Baud rate.
* @param __BAUDRATE__: Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 8)
+ * divided by the smallest oversampling used on the USART (i.e. 8).
* @retval Test result (TRUE or FALSE).
*/
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001)
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
/**
* @brief Ensure that USART frame number of stop bits is valid.
@@ -575,7 +576,7 @@
* @param __MODE__: USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_USART_MODE(__MODE__) ((((__MODE__) & (uint32_t)0xFFFFFFF3U) == 0x00) && ((__MODE__) != (uint32_t)0x00))
+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that USART clock state is valid.
@@ -619,7 +620,7 @@
* @}
*/
-/* Include USART HAL Extension module */
+/* Include USART HAL Extended module */
#include "stm32f3xx_hal_usart_ex.h"
/* Exported functions --------------------------------------------------------*/
@@ -658,6 +659,10 @@
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
@@ -665,6 +670,7 @@
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f3xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
- * @brief Header file of USART HAL Extension module.
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
@@ -50,9 +50,9 @@
* @{
*/
-/** @defgroup USARTEx USARTEx
+/** @addtogroup USARTEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -66,12 +66,12 @@
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
#else
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
@@ -79,7 +79,6 @@
* @}
*/
-
/**
* @}
*/
@@ -89,14 +88,14 @@
* @{
*/
-/** @brief Reports the USART clock source.
- * @param __HANDLE__: specifies the USART Handle
- * @param __CLOCKSOURCE__ : output variable
+/** @brief Report the USART clock source.
+ * @param __HANDLE__: specifies the USART Handle.
+ * @param __CLOCKSOURCE__: output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -131,9 +130,9 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
-#else
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ } while(0U)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
@@ -202,7 +201,7 @@
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
- } while(0)
+ } while(0U)
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
/** @brief Compute the USART mask to apply to retrieve the received data
@@ -223,36 +222,36 @@
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x003F ; \
+ (__HANDLE__)->Mask = 0x003FU ; \
} \
} \
-} while(0)
+} while(0U)
#else
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
@@ -260,25 +259,25 @@
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x01FF ; \
+ (__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
- (__HANDLE__)->Mask = 0x00FF ; \
+ (__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
- (__HANDLE__)->Mask = 0x007F ; \
+ (__HANDLE__)->Mask = 0x007FU ; \
} \
} \
-} while(0)
+} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
@@ -306,11 +305,6 @@
*/
/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions ****************************/
-/* IO operation functions *****************************************************/
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_wwdg.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_wwdg.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
@@ -15,9 +15,9 @@
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (T[6;0] downcounter)
+ time period, unless the program refreshes the counter (T[6U;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
+ value rolls over from 0x40 to 0x3FU).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
@@ -31,20 +31,20 @@
(+) The WWDG downcounter input clock is derived from the APB clock divided
by a programmable prescaler.
- (+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG downcounter clock (Hz) = PCLK1 / (4096U * Prescaler)
- (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
- where T[5;0] are the lowest 6 bits of downcounter.
+ (+) WWDG timeout (ms) = (1000U * (T[5U;0] + 1U)) / (WWDG downcounter clock)
+ where T[5U;0] are the lowest 6 bits of downcounter.
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
- (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
+ (++) min time (ms) = (1000U * (T[5U;0] - Window)) / (WWDG downcounter clock)
+ (++) max time (ms) = (1000U * (T[5U;0] - 0x40U)) / (WWDG downcounter clock)
(+) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
(+) The Early Wakeup Interrupt (EWI) can be used if specific safety
operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
+ generated. When the downcounter reaches the value 0x40U, an EWI interrupt
is generated and the corresponding interrupt service routine (ISR) can
be used to trigger specific actions (such as communications or data
logging), before resetting the device.
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_wwdg.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_wwdg.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.3.0
- * @date 01-July-2016
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
@@ -69,10 +69,10 @@
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7FU */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7FU */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
@@ -119,10 +119,10 @@
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096U)/1U */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096U)/2U */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096U)/4U */
+#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096U)/8U */
/**
* @}
*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_adc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2011 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_adc.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_adc.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. b */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
+/* features (refer to reference manual). */
+/* - STM32F37x: */
+/* ADC IP 1Msamples/sec, 1 ADC instance */
+/* This file contains the drivers of these ADC IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(ADC5_V1_1)
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+ * @{
+ */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values: */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
+/* values definition. */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent */
+/* of device clock setting. */
+/* In user application, ADC timeout values should be defined with */
+/* temporal values, in function of device clock settings. */
+/* Highest ratio CPU clock frequency vs ADC clock frequency: */
+/* - ADC clock from synchronous clock with AHB prescaler 512, */
+/* APB prescaler 16, ADC prescaler 4. */
+/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
+/* with highest ratio CPU clock frequency vs HSI clock frequency: */
+/* CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1. */
+/* Unit: CPU cycles. */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
+ ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
+ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
+ ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
+ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
+ )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
+ ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12) \
+ ) \
+ : \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
+ ) \
+ : \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
+ ) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F334x8)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ )
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ )
+#endif
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
+ ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12) \
+ ) \
+ : \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ ) \
+ : \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ ) \
+ )
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F334x8)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ )
+#endif
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
+ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
+ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
+ )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
+ )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
+ ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
+ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
+ )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
+ ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
+ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
+ )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
+ )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @note This function is performing a hard reset, using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * To de-initialize only 1 ADC instance, use
+ * function @ref LL_ADC_DeInit().
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ if(ADCxy_COMMON == ADC12_COMMON)
+ {
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
+ }
+ else
+ {
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC34);
+ }
+ #elif defined(ADC1) && defined(ADC2)
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
+ #elif defined(ADC1)
+ LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC1);
+ #endif
+
+ /* Release reset of ADC clock (core clock) */
+ #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ if(ADCxy_COMMON == ADC12_COMMON)
+ {
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
+ }
+ else
+ {
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
+ }
+ #elif defined(ADC1) && defined(ADC2)
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
+ #elif defined(ADC1)
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
+ #endif
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+ assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
+ assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
+ }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 serie, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - Set ADC clock (conversion clock) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_DUAL
+ | ADC_CCR_MDMA
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | ADC_CommonInitStruct->Multimode
+ | ADC_CommonInitStruct->MultiDMATransfer
+ | ADC_CommonInitStruct->MultiTwoSamplingDelay
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CCR,
+ ADC_CCR_CKMODE
+ | ADC_CCR_DUAL
+ | ADC_CCR_MDMA
+ | ADC_CCR_DELAY
+ ,
+ ADC_CommonInitStruct->CommonClock
+ | LL_ADC_MULTI_INDEPENDENT
+ );
+ }
+#else
+ LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
+#endif
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+ ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+ ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @note If this functions returns error status, it means that ADC instance
+ * is in an unknown state.
+ * In this case, perform a hard reset using high level
+ * clock source RCC ADC reset.
+ * Caution: On this STM32 serie, if several ADC instances are available
+ * on the selected device, RCC ADC reset will reset
+ * all ADC instances belonging to the common ADC instance.
+ * Refer to function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ __IO uint32_t timeout_cpu_cycles = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group regular. */
+ if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
+ {
+ if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
+ {
+ LL_ADC_REG_StopConversion(ADCx);
+ }
+ }
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Stop potential ADC conversion on going on ADC group injected. */
+ if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
+ {
+ if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
+ {
+ LL_ADC_INJ_StopConversion(ADCx);
+ }
+ }
+
+ /* Wait for ADC conversions are effectively stopped */
+ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+ while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
+ | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
+ {
+ if(timeout_cpu_cycles-- == 0U)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+
+ /* Flush group injected contexts queue (register JSQR): */
+ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
+ /* contexts queue is maintained with the last active context). */
+ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+
+ /* Wait for ADC instance is effectively disabled */
+ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+ while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
+ {
+ if(timeout_cpu_cycles-- == 0U)
+ {
+ /* Time-out error */
+ status = ERROR;
+ }
+ }
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ if(READ_BIT(ADCx->CR,
+ ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN )
+ )
+ == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register IER */
+ CLEAR_BIT(ADCx->IER,
+ ( LL_ADC_IT_ADRDY
+ | LL_ADC_IT_EOC
+ | LL_ADC_IT_EOS
+ | LL_ADC_IT_OVR
+ | LL_ADC_IT_EOSMP
+ | LL_ADC_IT_JEOC
+ | LL_ADC_IT_JEOS
+ | LL_ADC_IT_JQOVF
+ | LL_ADC_IT_AWD1
+ | LL_ADC_IT_AWD2
+ | LL_ADC_IT_AWD3 )
+ );
+
+ /* Reset register ISR */
+ SET_BIT(ADCx->ISR,
+ ( LL_ADC_FLAG_ADRDY
+ | LL_ADC_FLAG_EOC
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_OVR
+ | LL_ADC_FLAG_EOSMP
+ | LL_ADC_FLAG_JEOC
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_JQOVF
+ | LL_ADC_FLAG_AWD1
+ | LL_ADC_FLAG_AWD2
+ | LL_ADC_FLAG_AWD3 )
+ );
+
+ /* Reset register CR */
+ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
+ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
+ /* access mode "read-set": no direct reset applicable. */
+ /* - Reset Calibration mode to default setting (single ended). */
+ /* - Disable ADC internal voltage regulator. */
+ /* Note: ADC internal voltage regulator disable is conditioned to */
+ /* ADC state disabled: already done above. */
+ /* Sequence to disable voltage regulator: */
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to disable state. */
+ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
+ /* 2. Set ADVREGEN bits to 0x10 */
+ SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
+
+ /* Reset register CFGR */
+ CLEAR_BIT(ADCx->CFGR,
+ ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
+ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+ | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+ | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
+ | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
+ | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+ | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+ | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+ | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+ | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+ );
+
+ /* Reset register TR1 */
+ MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+ /* Reset register TR2 */
+ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+ /* Reset register TR3 */
+ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+ | ADC_SQR1_SQ1 | ADC_SQR1_L)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+ | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+ );
+
+ /* Reset register SQR3 */
+ CLEAR_BIT(ADCx->SQR3,
+ ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+ | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+ );
+
+ /* Reset register SQR4 */
+ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Flush ADC group injected contexts queue */
+ SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
+ CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
+ /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
+ SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+
+ /* Reset register DR */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register OFR1 */
+ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+ /* Reset register OFR2 */
+ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+ /* Reset register OFR3 */
+ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+ /* Reset register OFR4 */
+ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* Note: bits in access mode read only, no direct reset applicable */
+
+ /* Reset register AWD2CR */
+ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+ /* Reset register AWD3CR */
+ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+ /* Reset register DIFSEL */
+ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+ /* Reset register CALFACT */
+ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+ }
+ else
+ {
+ /* ADC instance is in an unknown state */
+ /* Need to performing a hard reset of ADC instance, using high level */
+ /* clock source RCC ADC reset. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* on the selected device, RCC ADC reset will reset */
+ /* all ADC instances belonging to the common ADC instance. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC data resolution */
+ /* - Set ADC conversion data alignment */
+ /* - Set ADC low power mode */
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_RES
+ | ADC_CFGR_ALIGN
+ | ADC_CFGR_AUTDLY
+ ,
+ ADC_InitStruct->Resolution
+ | ADC_InitStruct->DataAlignment
+ | ADC_InitStruct->LowPowerMode
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+ ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+ assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* - Set ADC group regular overrun behavior */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMAEN
+ | ADC_CFGR_DMACFG
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->SequencerDiscont
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_EXTSEL
+ | ADC_CFGR_EXTEN
+ | ADC_CFGR_DISCEN
+ | ADC_CFGR_DISCNUM
+ | ADC_CFGR_CONT
+ | ADC_CFGR_DMAEN
+ | ADC_CFGR_DMACFG
+ | ADC_CFGR_OVRMOD
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ | ADC_REG_InitStruct->Overrun
+ );
+ }
+
+ /* Set ADC group regular sequencer length and scan direction */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+ ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* setting of trigger source to SW start. */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CFGR,
+ ADC_CFGR_JDISCEN
+ | ADC_CFGR_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->JSQR,
+ ADC_JSQR_JEXTSEL
+ | ADC_JSQR_JEXTEN
+ | ADC_JSQR_JL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ | ADC_INJ_InitStruct->SequencerLength
+ );
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (ADC1_V2_5)
+
+#if defined (ADC1)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
+
+#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
+ ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
+
+#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
+ ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset (LL_APB2_GRP1_PERIPH_ADC1);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ /* (hardware requirements of bits state to reset registers below) */
+ if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ CLEAR_BIT(ADCx->SR,
+ ( LL_ADC_FLAG_STRT
+ | LL_ADC_FLAG_JSTRT
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_AWD1 )
+ );
+
+ /* Reset register CR1 */
+ CLEAR_BIT(ADCx->CR1,
+ ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN
+ | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
+ | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
+ | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
+ | ADC_CR1_AWDCH )
+ );
+
+ /* Reset register CR2 */
+ CLEAR_BIT(ADCx->CR2,
+ ( ADC_CR2_TSVREFE
+ | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
+ | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
+ | ADC_CR2_ALIGN | ADC_CR2_DMA
+ | ADC_CR2_RSTCAL | ADC_CR2_CAL
+ | ADC_CR2_CONT | ADC_CR2_ADON )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
+ | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
+ | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP9
+ | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
+ | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
+ | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
+ );
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ SET_BIT(ADCx->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_L
+ | ADC_SQR1_SQ16
+ | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
+ | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
+ );
+
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable */
+
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC conversion data alignment */
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_SCAN
+ ,
+ ADC_InitStruct->SequencersScanMode
+ );
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_ALIGN
+ ,
+ ADC_InitStruct->DataAlignment
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+
+ /* Enable scan mode to have a generic behavior with ADC of other */
+ /* STM32 families, without this setting available: */
+ /* ADC group regular sequencer and ADC group injected sequencer depend */
+ /* only of their own configuration. */
+ ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | ADC_REG_InitStruct->SequencerDiscont
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_EXTSEL
+ | ADC_CR2_CONT
+ | ADC_CR2_DMA
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ );
+
+ /* Set ADC group regular sequencer length and scan direction */
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_JEXTSEL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ );
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_adc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,10835 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_adc.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_ADC_H
+#define __STM32F3xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
+/* features (refer to reference manual). */
+/* - STM32F37x: */
+/* ADC IP 1Msamples/sec, 1 ADC instance */
+/* This file contains the drivers of these ADC IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(ADC5_V1_1)
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */
+
+
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+
+
+
+/* Internal mask for ADC group regular trigger: */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
+/* - regular trigger source */
+/* - regular trigger edge */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 1U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 2U)) | \
+ ((ADC_CFGR_EXTSEL) << (4U * 3U)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
+ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
+
+/* Definition of ADC group regular trigger bits information. */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */
+
+
+
+/* Internal definitions for ADC group regular trigger sources: */
+/* To differentiate into literal LL_ADC_REG_TRIG_x the trigger sources */
+/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
+/* available on the selected device). */
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Internal mask offset for ADC group injected trigger sources */
+/* available only on specific ADC instances. */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_REG_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC1, ADC2 */
+#define ADC_REG_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group regular external trigger available only on ADC instance: ADC3, ADC4 */
+#endif
+
+/* Internal mask for ADC group injected trigger: */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
+/* - injected trigger source */
+/* - injected trigger edge */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 1U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 2U)) | \
+ ((ADC_JSQR_JEXTSEL) << (4U * 3U)) )
+
+/* Mask containing trigger edge masks for each of possible */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
+#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \
+ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
+
+/* Definition of ADC group injected trigger bits information. */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */
+
+
+
+/* Internal definitions for ADC group injected trigger sources: */
+/* To differentiate into literal LL_ADC_INJ_TRIG_x the trigger sources */
+/* depending on ADC instances ADC1, ADC2, ADC3, ADC4 (if ADC instance is */
+/* available on the selected device). */
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Internal mask offset for ADC group injected trigger sources */
+/* available only on specific ADC instances. */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_INJ_TRIG_EXT_INST_ADC12 ((uint32_t)0x00000001U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC1, ADC2 */
+#define ADC_INJ_TRIG_EXT_INST_ADC34 ((uint32_t)0x00000002U) /* Marker for differentiation of ADC group injected external trigger available only on ADC instance: ADC3, ADC4 */
+#endif
+
+
+
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel identifier defined by bitfield */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
+
+/* Definition of channels ID bitfield information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
+#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
+
+
+/* Internal mask for ADC mode single or differential ended: */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
+/* the relevant bits for: */
+/* (concatenation of multiple bits used in different registers) */
+/* - ADC calibration: calibration start, calibration factor get or set */
+/* - ADC channels: set each ADC channel ending mode */
+#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
+
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
+/* selection on groups. */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_AWD_CR2_REGOFFSET ((uint32_t)0x00100000U)
+#define ADC_AWD_CR3_REGOFFSET ((uint32_t)0x00200000U)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL ((uint32_t)0x00000024U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+
+
+/* Internal mask for ADC offset: */
+/* Internal register offset for ADC offset number configuration */
+#define ADC_OFR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_OFR2_REGOFFSET ((uint32_t)0x00000001U)
+#define ADC_OFR3_REGOFFSET ((uint32_t)0x00000002U)
+#define ADC_OFR4_REGOFFSET ((uint32_t)0x00000003U)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS ((uint32_t)23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */
+#define ADC_TR1_HT1_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F3, temperature sensor ADC raw data acquired at temperature 25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F3, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 25) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
+ This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+ @note On this STM32 serie, if ADC group injected is used, some
+ clock ratio constraints between ADC clock and AHB clock
+ must be respected. Refer to reference manual.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+
+ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
+
+ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t Resolution; /*!< Set ADC resolution.
+ This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
+
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t LowPowerMode; /*!< Set ADC low power mode.
+ This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
+ data preserved or overwritten.
+ This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
+ In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
+#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
+#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
+#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
+#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
+#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
+#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
+#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
+#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
+#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
+#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI ((uint32_t)0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
+ * @{
+ */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
+#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
+ * @{
+ */
+#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
+ * @{
+ */
+#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+ * @{
+ */
+#define LL_ADC_OFFSET_DISABLE ((uint32_t)0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F3, ADC channel available only on all ADC instances, but only one ADC instance is allowed to be connected to VrefInt at the same time. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On STM32F3, ADC channel available only on ADC instance: ADC1. */
+#endif
+#if defined(OPAMP2_CSR_OPAMP2EN)
+#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On STM32F3, ADC channel available only on ADC instance: ADC2. */
+#endif
+#if defined(OPAMP3_CSR_OPAMP3EN)
+#define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On STM32F3, ADC channel available only on ADC instance: ADC3. */
+#endif
+#if defined(OPAMP4_CSR_OPAMP4EN)
+#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP4 output. On STM32F3, ADC channel available only on ADC instance: ADC4. */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+/* ADC group regular external triggers for ADC instances: ADC3, ADC4 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 CCx. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) /*!< ADC group regular conversion trigger from external IP: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F334x8)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG3. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
+* @{
+*/
+#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/*!< ADC group regular behavior in case of overrun: data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+/* ADC group injected external triggers for ADC instances: ADC3, ADC4 (for */
+/* ADC instances ADCx available on the selected device) */
+/* Note: Literal without suffix "ADCxy" means that external trigger */
+/* is available on all ADC instances. */
+/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CH3 event). */
+/* JEXT2 is the main trigger, JEXT5 is kept as spare trigger for */
+/* future devices. */
+/* Note: For devices STM32F303xE, STM32F398xx: some triggers require to set */
+/* register SYSCFG_CFGR4. Refer to reference manual. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) /*!< ADC group injected conversion trigger from external IP: TIM20 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif /* STM32F303xE || STM32F398xx */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F334x8)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM TRG4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+
+#elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRG02. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRG0. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRG0. Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
+ * @{
+ */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE ((uint32_t)0x00000000U)/* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_4CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 4.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_61CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 61.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_181CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 181.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_601CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 601.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
+ * @{
+ */
+#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#endif
+#if defined(OPAMP2_CSR_OPAMP2EN)
+#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
+#endif
+#if defined(OPAMP3_CSR_OPAMP3EN)
+#define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#endif
+#if defined(OPAMP4_CSR_OPAMP4EN)
+#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+/**
+ * @}
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT ((uint32_t)0x00000000U) /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
+ * @{
+ */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC ((uint32_t)0x00000000U) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
+ * @{
+ */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE ((uint32_t)0x00000000U) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC calibration time: maximum delay is 112/fADC. */
+/* (refer to device datasheet, parameter "tCAL") */
+/* - ADC enable time: maximum delay is 1 conversion cycle. */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC disable time: maximum delay should be a few ADC clock cycles */
+/* - ADC stop conversion time: maximum delay should be a few ADC clock */
+/* cycles */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tADCVREG_STUP"). */
+/* Unit: us */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ((uint32_t) 10U) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time. */
+/* Delay set to maximum value (refer to device datasheet, */
+/* parameter "tstart_vrefint"). */
+/* Unit: us */
+#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 12U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
+
+/* Delay required between ADC end of calibration and ADC enable. */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* are required between ADC end of calibration and ADC enable. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 4U) /*!< Delay required between ADC end of calibration and ADC enable */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
+ ? ( \
+ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+ ) \
+ : \
+ ( \
+ POSITION_VAL((__CHANNEL__)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#if defined (ADC1) && defined (ADC2) && defined (ADC3) && defined (ADC4)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC3) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC4) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) \
+ ) \
+ : \
+ (0U) \
+ )
+#elif defined (ADC1) && defined (ADC2)
+#if defined(OPAMP1_CSR_OPAMP1EN) && defined(OPAMP2_CSR_OPAMP2EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ (0U) \
+ )
+#elif defined(OPAMP2_CSR_OPAMP2EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
+ ) \
+ : \
+ (0U) \
+ )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
+ ) \
+ : \
+ (0U) \
+ )
+#endif
+#elif defined (ADC1)
+#if defined(OPAMP1_CSR_OPAMP1EN)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) \
+ )
+#else
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ )
+#endif
+#endif
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+ * or @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+ * @brief Helper macro to get the ADC analog watchdog threshold high
+ * or low from raw value containing both thresholds concatenated.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, to get analog watchdog threshold high from the register raw value:
+ * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+ * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
+ (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+ * @brief Helper macro to set the ADC calibration value with both single ended
+ * and differential modes calibration factors concatenated.
+ * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
+ * Example, to set calibration factors single ended to 0x55
+ * and differential ended to 0x2A:
+ * LL_ADC_SetCalibrationFactor(
+ * ADC1,
+ * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+ * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
+ (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#if defined(ADC3) && defined(ADC4)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
+ ? ( \
+ (ADC12_COMMON) \
+ ) \
+ : \
+ ( \
+ (ADC34_COMMON) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+#endif
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#if defined(ADC3) && defined(ADC4)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ( \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) ) \
+ ) \
+ : \
+ ( \
+ (LL_ADC_IsEnabled(ADC3) | \
+ LL_ADC_IsEnabled(ADC4) ) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ LL_ADC_IsEnabled(ADC1)
+#endif
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * Otherwise, this macro performs the processing to scale
+ * ADC conversion data to 12 bits.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32F3, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32F3, refer to device datasheet parameter "V25" (corresponding to TS_CAL1).
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
+ * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t)&(ADCx->DR);
+ }
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register CDR */
+ data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: Clock source and prescaler.
+ * @note On this STM32 serie, if ADC group injected is used, some
+ * clock ratio constraints between ADC clock and AHB clock
+ * must be respected.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
+ * CCR PRESC LL_ADC_SetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param CommonClock This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE, CommonClock);
+}
+
+/**
+ * @brief Get parameter common to several ADC: Clock source and prescaler.
+ * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
+ * CCR PRESC LL_ADC_GetCommonClock
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+ * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+ * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE));
+}
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
+ * CCR VBATEN LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note This function is intended to set calibration parameters
+ * without having to perform a new calibration using
+ * @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration factor must be specified for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note In case of setting calibration factors of both modes single ended
+ * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+ * both calibration factors must be concatenated.
+ * To perform this processing, use helper macro
+ * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled, without calibration on going, without conversion
+ * on going on group regular.
+ * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+ * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+ MODIFY_REG(ADCx->CALFACT,
+ SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+ CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+ * @brief Get ADC calibration factor in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note Calibration factors are set by hardware after performing
+ * a calibration run using function @ref LL_ADC_StartCalibration().
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
+ * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Retrieve bits with position in register depending on parameter */
+ /* "SingleDiff". */
+ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));
+}
+
+/**
+ * @brief Set ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR RES LL_ADC_SetResolution
+ * @param ADCx ADC instance
+ * @param Resolution This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+ * @brief Get ADC resolution.
+ * Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR RES LL_ADC_GetResolution
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @arg @ref LL_ADC_RESOLUTION_10B
+ * @arg @ref LL_ADC_RESOLUTION_8B
+ * @arg @ref LL_ADC_RESOLUTION_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+ * @brief Set ADC low power mode.
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
+ * @param ADCx ADC instance
+ * @param LowPowerMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+ * @brief Get ADC low power mode:
+ * @note Description of ADC low power modes:
+ * - ADC low power mode "auto wait": Dynamic low power mode,
+ * ADC conversions occurrences are limited to the minimum necessary
+ * in order to reduce power consumption.
+ * New ADC conversion starts only when the previous
+ * unitary conversion data (for ADC group regular)
+ * or previous sequence conversions data (for ADC group injected)
+ * has been retrieved by user software.
+ * In the meantime, ADC remains idle: does not performs any
+ * other conversion.
+ * This mode allows to automatically adapt the ADC conversions
+ * triggers to the speed of the software that reads the data.
+ * Moreover, this avoids risk of overrun for low frequency
+ * applications.
+ * How to use this low power mode:
+ * - Do not use with interruption or DMA since these modes
+ * have to clear immediately the EOC flag to free the
+ * IRQ vector sequencer.
+ * - Do use with polling: 1. Start conversion,
+ * 2. Later on, when conversion data is needed: poll for end of
+ * conversion to ensure that conversion is completed and
+ * retrieve ADC conversion data. This will trig another
+ * ADC conversion start.
+ * - ADC low power mode "auto power-off" (feature available on
+ * this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
+ * the ADC automatically powers-off after a conversion and
+ * automatically wakes up when a new conversion is triggered
+ * (with startup time between trigger and start of sampling).
+ * This feature can be combined with low power mode "auto wait".
+ * @note With ADC low power mode "auto wait", the ADC conversion data read
+ * is corresponding to previous ADC conversion start, independently
+ * of delay during which ADC was idle.
+ * Therefore, the ADC conversion data may be outdated: does not
+ * correspond to the current voltage level on the selected
+ * ADC channel.
+ * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_LP_MODE_NONE
+ * @arg @ref LL_ADC_LP_AUTOWAIT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+ * @brief Set ADC selected offset number 1, 2, 3 or 4.
+ * @note This function set the 2 items of offset configuration:
+ * - ADC channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note This function enables the offset, by default. It can be forced
+ * to disable state using function LL_ADC_SetOffsetState().
+ * @note If a channel is mapped on several offsets numbers, only the offset
+ * with the lowest value is considered for the subtraction.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
+ * OFR1 OFFSET1 LL_ADC_SetOffset\n
+ * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
+ * OFR2 OFFSET2 LL_ADC_SetOffset\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
+ * OFR3 OFFSET3 LL_ADC_SetOffset\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
+ * OFR4 OFFSET4 LL_ADC_SetOffset\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffset
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+ ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Channel to which the offset programmed will be applied
+ * (independently of channel mapped on ADC group regular
+ * or group injected)
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
+ * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
+ * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
+ * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * Offset level (offset to be subtracted from the raw
+ * converted data).
+ * @note Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
+ * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
+ * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
+ * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+ * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
+ * force offset state disable or enable
+ * without modifying offset channel or offset value.
+ * @note This function should be needed only in case of offset to be
+ * enabled-disabled dynamically, and should not be needed in other cases:
+ * function LL_ADC_SetOffset() automatically enables the offset.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @param OffsetState This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+ register uint32_t *preg = (uint32_t *)((uint32_t)
+ ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));
+
+ MODIFY_REG(*preg,
+ ADC_OFR1_OFFSET1_EN,
+ OffsetState);
+}
+
+/**
+ * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
+ * offset state disabled or enabled.
+ * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
+ * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
+ * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
+ * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
+ * @param ADCx ADC instance
+ * @param Offsety This parameter can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_1
+ * @arg @ref LL_ADC_OFFSET_2
+ * @arg @ref LL_ADC_OFFSET_3
+ * @arg @ref LL_ADC_OFFSET_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_OFFSET_DISABLE
+ * @arg @ref LL_ADC_OFFSET_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+ return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_REG_SetTriggerEdge().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
+
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
+ * CFGR EXTEN LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO (1)(2)(3)(5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (3) (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (5)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12 (1) (7)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC3 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34 (1) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12 (1)(2) (7)
+
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
+ | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));
+}
+
+/**
+ * @brief Set ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger polarity.
+ * @note Applicable only for trigger source set to external trigger.
+ * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note For devices with several ADC instances: ADC multimode DMA
+ * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
+ * CFGR DMACFG LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+/**
+ * @brief Set ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @note Compatibility with devices without feature overrun:
+ * other devices without this feature have a behavior
+ * equivalent to data overwritten.
+ * The default setting of overrun is data preserved.
+ * Therefore, for compatibility with all devices, parameter
+ * overrun should be set to data overwritten.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on group regular.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
+ * @param ADCx ADC instance
+ * @param Overrun This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+ * @brief Get ADC group regular behavior in case of overrun:
+ * data preserved or overwritten.
+ * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+ * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, setting trigger source to external trigger
+ * also set trigger polarity to rising edge
+ * (default setting for compatibility with some ADC on other
+ * STM32 families having this setting set by HW default value).
+ * In case of need to modify trigger edge, use
+ * function @ref LL_ADC_INJ_SetTriggerEdge().
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
+ * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+ /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
+ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
+ register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
+
+ /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
+ /* to match with triggers literals definition. */
+ return ((TriggerSource
+ & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
+ | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
+ * @param ADCx ADC instance
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger polarity.
+ * Applicable only for trigger source set to external trigger.
+ * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * using successively several times this function will appear has
+ * having no effect.
+ * This is due to ADC group injected contexts queue (this feature
+ * cannot be disabled on this STM32 serie).
+ * To set several features of ADC group injected, use
+ * function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.\n
+ * (1, 2, 3, 4, 5) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK)))
+ << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected contexts queue mode.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * If contexts queue is disabled:
+ * - only 1 sequence can be configured
+ * and is active perpetually.
+ * If contexts queue is enabled:
+ * - up to 2 contexts can be queued
+ * and are checked in and out as a FIFO stack (first-in, first-out).
+ * - If a new context is set when queues is full, error is triggered
+ * by interruption "Injected Queue Overflow".
+ * - Two behaviors are possible when all contexts have been processed:
+ * the contexts queue can maintain the last context active perpetually
+ * or can be empty and injected group triggers are disabled.
+ * - Triggers can be only external (not internal SW start)
+ * - Caution: The sequence must be fully configured in one time
+ * (one write of register JSQR makes a check-in of a new context
+ * into the queue).
+ * Therefore functions to set separately injected trigger and
+ * sequencer channels cannot be used, register JSQR must be set
+ * using function @ref LL_ADC_INJ_ConfigQueueContext().
+ * @note This parameter can be modified only when no conversion is on going
+ * on either groups regular or injected.
+ * @note A modification of the context mode (bit JQDIS) causes the contexts
+ * queue to be flushed and the register JSQR is cleared.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode
+ * @param ADCx ADC instance
+ * @param QueueMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+ MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM, QueueMode);
+}
+
+/**
+ * @brief Get ADC group injected context queue mode.
+ * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+ * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM));
+}
+
+/**
+ * @brief Set one context on ADC group injected that will be checked in
+ * contexts queue.
+ * @note A context is a setting of group injected sequencer:
+ * - group injected trigger
+ * - sequencer length
+ * - sequencer ranks
+ * This function is intended to be used when contexts queue is enabled,
+ * because the sequence must be fully configured in one time
+ * (functions to set separately injected trigger and sequencer channels
+ * cannot be used):
+ * Refer to function @ref LL_ADC_INJ_SetQueueMode().
+ * @note In the contexts queue, only the active context can be read.
+ * The parameters of this function can be read using functions:
+ * @arg @ref LL_ADC_INJ_GetTriggerSource()
+ * @arg @ref LL_ADC_INJ_GetTriggerEdge()
+ * @arg @ref LL_ADC_INJ_GetSequencerRanks()
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must not be disabled. Can be enabled with or without conversion
+ * on going on either groups regular or injected.
+ * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
+ * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (1)(2)(3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12 (1)(2)(3)(4)(5) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (3) (5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (3)(4)(5)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (1)(2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12 (1)(2) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34 (1)(2) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12 (1) (7)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2_ADC34 (1) (8)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (3)(4)(5)(6)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12 (1)(2) (7)
+ *
+ * (1) On STM32F3, parameter not available on all devices: among others, on STM32F303xE, STM32F398xx.\n
+ * (2) On STM32F3, parameter not available on all devices: among others, on STM32F303xC, STM32F358xx.\n
+ * (3) On STM32F3, parameter not available on all devices: among others, on STM32F303x8, STM32F328xx.\n
+ * (4) On STM32F3, parameter not available on all devices: among others, on STM32F334x8.\n
+ * (5) On STM32F3, parameter not available on all devices: among others, on STM32F302xC, STM32F302xE.\n
+ * (6) On STM32F3, parameter not available on all devices: among others, on STM32F301x8, STM32F302x8, STM32F318xx.\n
+ * (7) On STM32F3, parameter not available on all ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (8) On STM32F3, parameter not available on all ADC instances: ADC3, ADC4 (for ADC instances ADCx available on the selected device).
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+ *
+ * Note: This parameter is discarded in case of SW start:
+ * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @param Rank1_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank2_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank3_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param Rank4_Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+ uint32_t TriggerSource,
+ uint32_t ExternalTriggerEdge,
+ uint32_t SequencerNbRanks,
+ uint32_t Rank1_Channel,
+ uint32_t Rank2_Channel,
+ uint32_t Rank3_Channel,
+ uint32_t Rank4_Channel)
+{
+ /* Set bits with content of parameter "Rankx_Channel" with bits position */
+ /* in register depending on literal "LL_ADC_INJ_RANK_x". */
+ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
+ /* because containing other bits reserved for other purpose. */
+ /* If parameter "TriggerSource" is set to SW start, then parameter */
+ /* "ExternalTriggerEdge" is discarded. */
+ MODIFY_REG(ADCx->JSQR ,
+ ADC_JSQR_JEXTSEL |
+ ADC_JSQR_JEXTEN |
+ ADC_JSQR_JSQ4 |
+ ADC_JSQR_JSQ3 |
+ ADC_JSQR_JSQ2 |
+ ADC_JSQR_JSQ1 |
+ ADC_JSQR_JL ,
+ TriggerSource |
+ (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |
+ ((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ ((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK))) |
+ SequencerNbRanks
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * On this STM32 serie, ADC processing time is:
+ * - 12.5 ADC clock cycles at ADC resolution 12 bits
+ * - 10.5 ADC clock cycles at ADC resolution 10 bits
+ * - 8.5 ADC clock cycles at ADC resolution 8 bits
+ * - 6.5 ADC clock cycles at ADC resolution 6 bits
+ * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_18
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (5)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ * @arg @ref LL_ADC_CHANNEL_VBAT (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)
+ * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (4)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_61CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_181CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_601CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note Channel ending is on channel scope: independently of channel mapped
+ * on ADC group regular or injected.
+ * In differential mode: Differential measurement is carried out
+ * between the selected channel 'i' (positive input) and
+ * channel 'i+1' (negative input). Only channel 'i' has to be
+ * configured, channel 'i+1' is configured automatically.
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32F3, channels 16, 17, 18 of ADC1,
+ * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
+ * are internally fixed to single-ended inputs configuration.
+ * @note For ADC channels configured in differential mode, both inputs
+ * should be biased at (Vref+)/2 +/-200mV.
+ * (Vref+ is the analog voltage reference)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.
+ * @param SingleDiff This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+ /* Bits of channels in single or differential mode are set only for */
+ /* differential mode (for single mode, mask of bits allowed to be set is */
+ /* shifted out of range of bits of channels in single or differential mode. */
+ MODIFY_REG(ADCx->DIFSEL,
+ Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+ (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+ * @brief Get mode single-ended or differential input of the selected
+ * ADC channel.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * Therefore, to ensure a channel is configured in single-ended mode,
+ * the configuration of channel itself and the channel 'i-1' must be
+ * read back (to ensure that the selected channel channel has not been
+ * configured in differential mode by the previous channel).
+ * @note Refer to Reference Manual to ensure the selected channel is
+ * available in differential mode.
+ * For example, internal channels (VrefInt, TempSensor, ...) are
+ * not available in differential mode.
+ * @note When configuring a channel 'i' in differential mode,
+ * the channel 'i+1' is not usable separately.
+ * @note On STM32F3, channels 16, 17, 18 of ADC1,
+ * channels 17, 18 of ADC2, ADC3, ADC4 (if available)
+ * are internally fixed to single-ended inputs configuration.
+ * @note One or several values can be selected. In this case, the value
+ * returned is null if all channels are in single ended-mode.
+ * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+ * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16 (1)
+ *
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.
+ * @retval 0: channel in single-ended mode, else: channel in differential mode
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel, multiple channels or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(5)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (5)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (0)(3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(4)
+ * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (4)
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.\n
+ * (1) On STM32F3, parameter available only on ADC instance: ADC1.\n
+ * (2) On STM32F3, parameter available only on ADC instance: ADC2.\n
+ * (3) On STM32F3, parameter available only on ADC instance: ADC3.\n
+ * (4) On STM32F3, parameter available only on ADC instances: ADC4.\n
+ * (5) On STM32F3, ADC channel available only on all ADC instances, but
+ * only one ADC instance is allowed to be connected to VrefInt at the same time.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+ /* Set bits with content of parameter "AWDChannelGroup" with bits position */
+ /* in register and register position depending on parameter "AWDy". */
+ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ MODIFY_REG(*preg,
+ (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+ AWDChannelGroup & AWDy);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
+ * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2 (1)
+ * @arg @ref LL_ADC_AWD3 (1)
+ *
+ * (1) On this AWD number, monitored channel can be retrieved
+ * if only 1 channel is programmed (or none or all channels).
+ * This function cannot retrieve monitored channel if
+ * multiple channels are programmed simultaneously
+ * by bitfield.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
+ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+ *
+ * (0) On STM32F3, parameter available only on analog watchdog number: AWD1.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+ /* Variable "AWDy" used to retrieve appropriate bitfield corresponding to */
+ /* ADC_AWD_CR1_CHANNEL_MASK or ADC_AWD_CR23_CHANNEL_MASK. */
+ register uint32_t AWD123ChannelGroup = READ_BIT(*preg, (AWDy | ADC_AWD_CR_ALL_CHANNEL_MASK));
+
+ /* Set variable of AWD1 monitored channel according to AWD1 features */
+ /* and ADC channel definition: */
+ /* - channel ID with number */
+ /* - channel ID with bitfield */
+ /* - AWD1 single or all channels */
+ /* - AWD1 enable or disable (also used to discard AWD1 bitfield in case of */
+ /* AWD2 or AWD3 selected). */
+ register uint32_t AWD1ChannelSingle = ((AWD123ChannelGroup & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS);
+
+ register uint32_t AWD1ChannelGroup = ( ( AWD123ChannelGroup
+ | ((ADC_CHANNEL_0_BITFIELD << ((AWD123ChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)) * AWD1ChannelSingle)
+ | (ADC_CHANNEL_ID_BITFIELD_MASK * (~AWD1ChannelSingle & ((uint32_t)0x00000001U)))
+ )
+ * (((AWD123ChannelGroup & ADC_CFGR_JAWD1EN) >> ADC_CFGR_JAWD1EN_BITOFFSET_POS) | ((AWD123ChannelGroup & ADC_CFGR_AWD1EN) >> ADC_CFGR_AWD1EN_BITOFFSET_POS))
+ );
+
+ /* Set variable of AWD2 and AWD3 monitored channel according to AWD2-3 */
+ /* features and ADC channel definition: */
+ /* - channel ID with number */
+ /* - channel ID with bitfield */
+ /* - AWD2-3 single or all channels (shift value 32 (0x1 shift 5) used to */
+ /* shift AWD1 equivalent single-all channels out of register) */
+ /* - AWD2-3 enable or disable */
+ /* Note: Use modulo 3 to avoid a shift value too long. On AWD2 and AWD3, */
+ /* channel can be read back if only 1 channel monitoring */
+ /* is activated, therefore the channel monitoring value channel "3" */
+ /* is not not supported by this function, there is no risk of */
+ /* conflict. */
+ register uint32_t AWD23Enabled = ((((uint32_t)0x00000001U) >> (AWD123ChannelGroup % 3U)) << 6U); /* Value "0" if AWD2-3 is enabled, value "32" if AWD2-3 is disabled */
+
+ register uint32_t AWD23ChannelGroup = ((( AWD123ChannelGroup
+ | ((uint32_t)POSITION_VAL(AWD123ChannelGroup) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+ | ((ADC_CFGR_AWD1SGL) >> ((((uint32_t)0x00000001U) >> (ADC_AWD_CR23_CHANNEL_MASK - AWD123ChannelGroup)) << 5U))
+ | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)
+ ) >> AWD23Enabled
+ ) >> (((AWDy & ADC_CFGR_AWD1SGL) >> ADC_CFGR_AWD1SGL_BITOFFSET_POS) << 5U));
+
+ return (AWD1ChannelGroup | AWD23ChannelGroup);
+}
+
+/**
+ * @brief Set ADC analog watchdog thresholds value of both thresholds
+ * high and low.
+ * @note If value of only one threshold high or low must be set,
+ * use function @ref LL_ADC_SetAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
+{
+ /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
+ /* position in register and register position depending on parameter */
+ /* "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_TR1_HT1 | ADC_TR1_LT1,
+ (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note If values of both thresholds high or low must be set,
+ * use function @ref LL_ADC_ConfigAnalogWDThresholds().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+ * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * - AWD flexible (instances AWD2, AWD3):
+ * - channels monitored: flexible on channels monitored, selection is
+ * channel wise, from from 1 to all channels.
+ * Specificity of this analog watchdog: Multiple channels can
+ * be selected. For example:
+ * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+ * - groups monitored: not selection possible (monitoring on both
+ * groups regular and injected).
+ * Channels selected are monitored on groups regular and injected:
+ * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+ * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+ * - resolution: resolution is limited to 8 bits: if ADC resolution is
+ * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+ * the 2 LSB are ignored.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be disabled or enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ /* Set bits with content of parameter "AWDThresholdValue" with bits */
+ /* position in register and register position depending on parameters */
+ /* "AWDThresholdsHighLow" and "AWDy". */
+ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
+ /* containing other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ AWDThresholdsHighLow,
+ AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high,
+ * threshold low or raw data with ADC thresholds high and low
+ * concatenated.
+ * @note If raw data with ADC thresholds high and low is retrieved,
+ * the data of each threshold high or low can be isolated
+ * using helper macro:
+ * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
+ * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
+ * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
+ * TR3 LT3 LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDy This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD1
+ * @arg @ref LL_ADC_AWD2
+ * @arg @ref LL_ADC_AWD3
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ (AWDThresholdsHighLow | ADC_TR1_LT1))
+ >> POSITION_VAL(AWDThresholdsHighLow)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+ * @{
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DUAL LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CCR DUAL LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+ * @brief Set ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled
+ * or enabled without conversion on going on group regular.
+ * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_SetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiDMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+}
+
+/**
+ * @brief Get ADC multimode conversion data transfer: no transfer
+ * or transfer by DMA.
+ * @note If ADC multimode transfer by DMA is not selected:
+ * each ADC uses its own DMA channel, with its individual
+ * DMA transfer settings.
+ * If ADC multimode transfer by DMA is selected:
+ * One DMA channel is used for both ADC (DMA of ADC master)
+ * Specifies the DMA requests mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note How to retrieve multimode conversion data:
+ * Whatever multimode transfer by DMA setting: using function
+ * @ref LL_ADC_REG_ReadMultiConversionData32().
+ * If ADC multimode transfer by DMA is selected: conversion data
+ * is a raw data with ADC master and slave concatenated.
+ * A macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
+ * CCR DMACFG LL_ADC_GetMultiDMATransfer
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+ * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+ * @brief Set ADC multimode delay between 2 sampling phases.
+ * @note The sampling delay range depends on ADC resolution:
+ * - ADC resolution 12 bits can have maximum delay of 12 cycles.
+ * - ADC resolution 10 bits can have maximum delay of 10 cycles.
+ * - ADC resolution 8 bits can have maximum delay of 8 cycles.
+ * - ADC resolution 6 bits can have maximum delay of 6 cycles.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * This check can be done with function @ref LL_ADC_IsEnabled() for each
+ * ADC instance or by using helper macro helper macro
+ * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+ * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param MultiTwoSamplingDelay This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+ MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+ * @brief Get ADC multimode delay between 2 sampling phases.
+ * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+ * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+ *
+ * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+ * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+ * (3) Parameter available only if ADC resolution is 12 bits.
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable ADC instance internal voltage regulator.
+ * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * a delay for ADC internal voltage regulator stabilization
+ * is required before performing a ADC calibration or ADC enable.
+ * Refer to device datasheet, parameter tADCVREG_STUP.
+ * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ /* 1. Set the intermediate state before moving the ADC voltage regulator */
+ /* to state enable. */
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
+ /* 2. Set the final state of ADC voltage regulator enable */
+ /* (ADVREGEN bits set to 0x01). */
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADVREGEN_0);
+}
+
+/**
+ * @brief Disable ADC internal voltage regulator.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+ * @brief Get the selected ADC instance internal voltage regulator state.
+ * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
+ * @param ADCx ADC instance
+ * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)) == (ADC_CR_ADVREGEN_0));
+}
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled and ADC internal voltage regulator enabled.
+ * @rmtoll CR ADEN LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADEN);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be not disabled. Must be enabled without conversion on going
+ * on either groups regular or injected.
+ * @rmtoll CR ADDIS LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADDIS);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll CR ADEN LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
+}
+
+/**
+ * @brief Get the selected ADC instance disable state.
+ * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no ADC disable command on going.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * are required between ADC end of calibration and ADC enable.
+ * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+ * @note For devices with differential mode available:
+ * Calibration of offset is specific to each of
+ * single-ended and differential modes
+ * (calibration run must be performed for each of these
+ * differential modes, if used afterwards and if the application
+ * requires their calibration).
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be ADC disabled.
+ * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
+ * CR ADCALDIF LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @param SingleDiff This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SINGLE_ENDED
+ * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group regular,
+ * without conversion stop command on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTART);
+}
+
+/**
+ * @brief Stop ADC group regular conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group regular,
+ * without ADC disable command on going.
+ * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_ADSTP);
+}
+
+/**
+ * @brief Get ADC group regular conversion state.
+ * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
+}
+
+/**
+ * @brief Get ADC group regular command of conversion stop state
+ * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group regular.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+{
+ return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
+ * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+ ConversionData)
+ >> POSITION_VAL(ConversionData)
+ );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled without conversion on going on group injected,
+ * without conversion stop command on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTART);
+}
+
+/**
+ * @brief Stop ADC group injected conversion.
+ * @note On this STM32 serie, setting of this feature is conditioned to
+ * ADC state:
+ * ADC must be enabled with conversion on going on group injected,
+ * without ADC disable command on going.
+ * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Write register with some additional bits forced to state reset */
+ /* instead of modifying only the selected bit for this function, */
+ /* to not interfere with bits with HW property "rs". */
+ MODIFY_REG(ADCx->CR,
+ ADC_CR_BITS_PROPERTY_RS,
+ ADC_CR_JADSTP);
+}
+
+/**
+ * @brief Get ADC group injected conversion state.
+ * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no conversion is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));
+}
+
+/**
+ * @brief Get ADC group injected command of conversion stop state
+ * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
+ * @param ADCx ADC instance
+ * @retval 0: no command of conversion stop is on going on ADC group injected.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 10 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 8 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 6 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint8_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
+}
+
+/**
+ * @brief Get flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
+}
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+/**
+ * @brief Get flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
+}
+
+/**
+ * @brief Get flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
+}
+
+/**
+ * @brief Get flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));
+}
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));
+}
+
+/**
+ * @brief Clear flag ADC ready.
+ * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * is enabled and when conversion clock is active.
+ * (not only core clock: this ADC has a dual clock domain)
+ * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of unitary conversion.
+ * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+ * @brief Clear flag ADC group regular overrun.
+ * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sampling phase.
+ * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of unitary conversion.
+ * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC group injected contexts queue overflow.
+ * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 2.
+ * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 3.
+ * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC ready of the ADC master.
+ * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC ready of the ADC slave.
+ * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+ * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+ * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+ * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+ * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC master.
+ * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular overrun of the ADC slave.
+ * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
+ * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
+ * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+ * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+ * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+ * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+ * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
+ * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
+ * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.
+ * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
+ * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
+ * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
+ * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
+ * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Enable ADC group regular interruption overrun.
+ * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Enable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Disable interruption ADC ready.
+ * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+ * @brief Disable interruption ADC group regular overrun.
+ * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sampling.
+ * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of unitary conversion.
+ * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC group injected context queue overflow.
+ * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 2.
+ * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 3.
+ * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+ * @brief Get state of interruption ADC ready
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular overrun
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sampling
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of unitary conversion
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC group injected context queue overflow interrupt state
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 2
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));
+}
+
+/**
+ * @brief Get state of interruption Get ADC analog watchdog 3
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (ADC1_V2_5)
+
+#if defined (ADC1)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+
+
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - offset register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
+#define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
+#define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
+
+/* Internal register offset for ADC group injected offset configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
+#define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
+#define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition. */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+
+
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 ((uint32_t)0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
+#define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CR1_DUALMOD_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7B8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F37x, temperature sensor ADC raw data acquired at temperature 25 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7C2U)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F37x, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP (( int32_t) 25) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t SequencersScanMode; /*!< Set ADC scan selection.
+ This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
+#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
+ * @{
+ */
+#define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F37x, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal (SW start) */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM2 CC2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger external from TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH2 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM4 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_TRGO ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger external from TIM19 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_CH3 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger external from TIM19 CC3. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM19_CH4 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external from TIM19 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U)/*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversions are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal (SW start) */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external from TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM2 CC1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger external from TIM3 CC4. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM19_CH1 ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger external from TIM19 CC1. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM19_CH2 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger external from TIM19 CC2. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC enable time: maximum delay is 1us */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay required between ADC disable and ADC calibration start. */
+/* Note: On this STM32 serie, before starting a calibration, */
+/* ADC must be disabled. */
+/* A minimum number of ADC clock cycles are required */
+/* between ADC disable state and calibration start. */
+/* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES ((uint32_t) 2U) /*!< Delay required between ADC disable and ADC calibration start */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin)
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
+ ) \
+ : \
+ (0U) \
+ )
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << (0U))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ (__AWD_THRESHOLD_12_BITS__)
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On STM32F37x, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * (equivalence with other STM32 families featuring several
+ * ADC instances).
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @note On STM32F37x, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * (equivalence with other STM32 families featuring several
+ * ADC instances).
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" All ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" At least one ADC instance sharing the same ADC common instance
+ * is enabled
+ */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ LL_ADC_IsEnabled(ADC1)
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ ((uint32_t)0xFFFU)
+
+/**
+ * @brief Helper macro to convert the ADC conversion data from
+ * a resolution to another resolution.
+ * @note On STM32F37x, the only ADC resolution available is 12 bits.
+ * This macro has been kept for compatibility purpose over other
+ * STM32 families.
+ * @param __DATA__ ADC conversion data to be converted
+ * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data to the requested resolution
+ */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+ __ADC_RESOLUTION_CURRENT__,\
+ __ADC_RESOLUTION_TARGET__) \
+ (((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (0U))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (0U)) \
+ )
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+
+/**
+ * @brief Helper macro to calculate analog reference voltage (Vref+)
+ * (unit: mVolt) from ADC conversion data of internal voltage
+ * reference VrefInt.
+ * @note Computation is using VrefInt calibration value
+ * stored in system memory for each device during production.
+ * @note This voltage depends on user board environment: voltage level
+ * connected to pin Vref+.
+ * On devices with small package, the pin Vref+ is not present
+ * and internally bonded to pin Vdda.
+ * @note On this STM32 serie, calibration data of internal voltage reference
+ * VrefInt corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * internal voltage reference VrefInt.
+ * On STM32F37x, the only ADC resolution available is 12 bits.
+ * The parameter of ADC resolution is kept for compatibility purpose
+ * over other STM32 families.
+ * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
+ * of internal voltage reference VrefInt (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Analog reference voltage (unit: mV)
+ */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor calibration values
+ * stored in system memory for each device during production.
+ * @note Calculation formula:
+ * Temperature = ((TS_ADC_DATA - TS_CAL1)
+ * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+ * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * Avg_Slope = (TS_CAL2 - TS_CAL1)
+ * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+ * TS_CAL1 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL1 (calibrated in factory)
+ * TS_CAL2 = equivalent TS_ADC_DATA at temperature
+ * TEMP_DEGC_CAL2 (calibrated in factory)
+ * Caution: Calculation relevancy under reserve that calibration
+ * parameters are correct (address and data).
+ * To calculate temperature using temperature sensor
+ * datasheet typical values (generic values less, therefore
+ * less accurate than calibrated values),
+ * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note On this STM32 serie, calibration data of temperature sensor
+ * corresponds to a resolution of 12 bits,
+ * this is the recommended ADC resolution to convert voltage of
+ * temperature sensor.
+ * On STM32F37x, the only ADC resolution available is 12 bits.
+ * The parameter of ADC resolution is kept for compatibility purpose
+ * over other STM32 families.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+ * temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
+ * sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+ )
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32F37x, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32F37x, refer to device datasheet parameter "V25".
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @retval ADC register address
+ */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
+}
+
+/**
+ * @brief Set ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
+ * @param ADCx ADC instance
+ * @param ScanMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
+}
+
+/**
+ * @brief Get ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_REG_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH2
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_TRGO
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH3
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM19_CH4
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" trigger source external trigger
+ * Value "1" trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or external from timer or external interrupt.
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH1
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM19_CH2
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" trigger source external trigger
+ * Value "1" trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+ >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected offset.
+ * @note It sets:
+ * - ADC group injected rank to which the offset programmed
+ * will be applied
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note Offset cannot be enabled or disabled.
+ * To emulate offset disabled, set an offset value equal to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_JOFR1_JOFFSET1,
+ OffsetLevel);
+}
+
+/**
+ * @brief Get ADC group injected offset.
+ * @note It gives offset level (offset to be subtracted from the raw converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JOFR1_JOFFSET1)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F37x, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+ MODIFY_REG(ADCx->CR1,
+ (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
+ AWDChannelGroup);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
+ * LTR LT LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ MODIFY_REG(*preg,
+ ADC_HTR_HT,
+ AWDThresholdValue);
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high or
+ * threshold low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
+ * LTR LT LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @rmtoll CR2 ADON LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @rmtoll CR2 ADON LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @rmtoll CR2 ADON LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, before starting a calibration,
+ * ADC must be disabled.
+ * A minimum number of ADC clock cycles are required
+ * between ADC disable state and calibration start.
+ * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
+ * @note On this STM32 serie, hardware prerequisite before starting a calibration:
+ the ADC must have been in power-on state for at least
+ two ADC clock cycles.
+ * @rmtoll CR2 CAL LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_CAL);
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @rmtoll CR2 EXTTRIG LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Set bit ADC_CR2_SWSTART for case of trigger source set to */
+ /* SW start. In case of external trigger selected, this bit */
+ /* has no effect. */
+ SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+}
+
+/**
+ * @brief Stop ADC group regular conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant for both
+ * internal trigger (SW start) and external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * will start at next trigger event (on the selected trigger edge)
+ * following the ADC start conversion command.
+ * @rmtoll CR2 JEXTTRIG LL_ADC_REG_StartConversion
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+ /* Note: Set bit ADC_CR2_JSWSTART for case of trigger source set to */
+ /* SW start. In case of external trigger selected, this bit */
+ /* has no effect. */
+ SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+}
+
+/**
+ * @brief Stop ADC group injected conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
+}
+
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+/* Note: On STM32F37x ADC, there is no ADC common initialization */
+/* function. */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_bus.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1081 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_bus.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_BUS_H
+#define __STM32F3xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
+#if defined(DMA2)
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
+#endif /*DMA2*/
+#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
+#if defined(FMC_Bank1)
+#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN
+#endif /*FMC_Bank1*/
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
+#if defined(GPIOH)
+#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
+#endif /*GPIOH*/
+#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
+#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
+#if defined(GPIOE)
+#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
+#endif /*GPIOE*/
+#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
+#if defined(GPIOG)
+#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
+#endif /*GPIOH*/
+#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN
+#if defined(RCC_AHBENR_ADC1EN)
+#define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN
+#endif /*RCC_AHBENR_ADC1EN*/
+#if defined(ADC1_2_COMMON)
+#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN
+#endif /*ADC1_2_COMMON*/
+#if defined(ADC3_4_COMMON)
+#define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN
+#endif /*ADC3_4_COMMON*/
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
+#endif /*TIM3*/
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
+#endif /*TIM4*/
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
+#endif /*TIM5*/
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
+#endif /*TIM7*/
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
+#endif /*TIM12*/
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
+#endif /*TIM13*/
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
+#endif /*TIM14*/
+#if defined(TIM18)
+#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN
+#endif /*TIM18*/
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
+#endif /*SPI2*/
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
+#endif /*SPI3*/
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
+#endif /*UART4*/
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
+#endif /*UART5*/
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
+#endif /*I2C2*/
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
+#endif /*USB*/
+#if defined(CAN)
+#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN
+#endif /*CAN*/
+#if defined(DAC2)
+#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN
+#endif /*DAC2*/
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
+#endif /*CEC*/
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
+#endif /*I2C3*/
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
+#if defined(RCC_APB2ENR_ADC1EN)
+#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
+#endif /*RCC_APB2ENR_ADC1EN*/
+#if defined(TIM1)
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#endif /*TIM1*/
+#if defined(SPI1)
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#endif /*SPI1*/
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /*TIM8*/
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
+#endif /*SPI4*/
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#if defined(TIM19)
+#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN
+#endif /*TIM19*/
+#if defined(TIM20)
+#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
+#endif /*TIM20*/
+#if defined(HRTIM1)
+#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
+#endif /*HRTIM1*/
+#if defined(SDADC1)
+#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN
+#endif /*SDADC1*/
+#if defined(SDADC2)
+#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN
+#endif /*SDADC2*/
+#if defined(SDADC3)
+#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN
+#endif /*SDADC3*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHBENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBENR, Periphs);
+}
+
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
+ * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_comp.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1053 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_comp.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief COMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_comp.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* COMP IP from 3 to 7 instances and other specific features */
+/* (comparator output blanking, ...) (refer to reference manual). */
+/* - STM32F37x: */
+/* COMP IP with 2 instances */
+/* This file contains the drivers of these COMP IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(COMP_V1_3_0_0)
+
+#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
+
+/** @addtogroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of COMP hierarchical scope: */
+/* COMP instance. */
+
+#if defined(COMP_CSR_COMPxMODE)
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
+ )
+#else
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)
+#endif
+
+/* Note: On this STM32 serie, comparator input plus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1) \
+ )
+#elif defined(COMP_CSR_COMPxNONINSEL) && defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
+ )
+#elif defined(COMP_CSR_COMPxNONINSEL)
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
+ )
+#elif defined(LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2)
+/* Note: On devices where bit COMP_CSR_COMPxNONINSEL is available, */
+/* feature LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 is also available. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2) \
+ )
+#else
+/* Note: Device without comparator input plus configurable: corresponds to */
+/* setting "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" */
+/* compared to other STM32F3 devices, depending on comparator instance */
+/* (refer to reference manual). */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)
+#endif
+
+#if defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#else /* STM32F301x8 || STM32F318xx || STM32F302x8 */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ )
+#endif
+
+#if defined(COMP_CSR_COMPxHYST)
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
+ )
+#else
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)
+#endif
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4)\
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xE) || defined(STM32F398xx)
+#define IS_LL_COMP_OUTPUT_SELECTION(__COMP_INSTANCE__, __OUTPUT_SELECTION__) \
+ (( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_BKIN2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2) \
+ ) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC1_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4_COMP1_2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP1_2) \
+ || (((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM20_OCCLR_COMP2) \
+ && ((__COMP_INSTANCE__) == COMP2) ) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC2_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC1_COMP3) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC3_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_IC2_COMP4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM15_OCCLR_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC3_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_IC1_COMP5) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC2_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC4_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_IC1_COMP6) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_OCCLR_COMP6) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM1_IC2_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC3_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_OCCLR_COMP7) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM17_BKIN) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#endif
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
+ ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
+ )
+
+#if defined(COMP_CSR_COMPxBLANKING)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP2) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ ( \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
+ ) \
+ : \
+ ( \
+ (0U) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F302xE) || defined(STM32F302xC)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ ( \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
+ ) \
+ : \
+ ( \
+ (0U) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) \
+ ? ( \
+ (1U) \
+ ) \
+ : \
+ ((((__COMP_INSTANCE__) == COMP1) || ((__COMP_INSTANCE__) == COMP2)) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP3) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP4) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP5) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ ) \
+ : \
+ (((__COMP_INSTANCE__) == COMP6) \
+ ? ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
+ ) \
+ : \
+ ( \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ ) \
+ )
+#endif
+#else
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)
+#endif
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected COMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param COMPx COMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are de-initialized
+ * - ERROR: COMP registers are not de-initialized
+ */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* COMP instance must not be locked. */
+ if(LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ LL_COMP_WriteReg(COMPx, CSR, 0x00000000U);
+ }
+ else
+ {
+ /* Comparator instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the comparator is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of COMP instance.
+ * @note This function configures features of the selected COMP instance.
+ * Some features are also available at scope COMP common instance
+ * (common to several COMP instances).
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param COMPx COMP instance
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are initialized
+ * - ERROR: COMP registers are not initialized
+ */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+ assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+ assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+ assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+ assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+ assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMPx, COMP_InitStruct->OutputSelection));
+ assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+ assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* COMP instance must not be locked. */
+ if(LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Configuration of comparator instance : */
+ /* - PowerMode */
+ /* - InputPlus */
+ /* - InputMinus */
+ /* - InputHysteresis */
+ /* - OutputSelection */
+ /* - OutputPolarity */
+ /* - OutputBlankingSource */
+ MODIFY_REG(COMPx->CSR,
+ ((uint32_t)0x00000000U)
+#if defined(COMP_CSR_COMPxMODE)
+ | COMP_CSR_COMPxMODE
+#endif
+#if defined(COMP_CSR_COMPxNONINSEL)
+ | COMP_CSR_COMPxNONINSEL
+#endif
+ | COMP_CSR_COMPxINSEL
+#if defined(COMP_CSR_COMPxHYST)
+ | COMP_CSR_COMPxHYST
+#endif
+ | COMP_CSR_COMPxOUTSEL
+ | COMP_CSR_COMPxPOL
+ | COMP_CSR_COMPxBLANKING
+ ,
+ ((uint32_t)0x00000000U)
+#if defined(COMP_CSR_COMPxMODE)
+ | COMP_InitStruct->PowerMode
+#endif
+#if defined(COMP_CSR_COMPxNONINSEL)
+ | COMP_InitStruct->InputPlus
+#endif
+ | COMP_InitStruct->InputMinus
+#if defined(COMP_CSR_COMPxHYST)
+ | COMP_InitStruct->InputHysteresis
+#endif
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ | COMP_InitStruct->OutputBlankingSource
+ );
+
+ }
+ else
+ {
+ /* Initialization error: COMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+ * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ /* Set COMP_InitStruct fields to default values */
+ /* Note: Comparator power mode "high speed" is the only mode */
+ /* available on all STMF3 devices. */
+ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_HIGHSPEED;
+ COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
+ COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+ COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+ COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
+ COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+ COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (COMP_V1_1_0_0)
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of COMP hierarchical scope: */
+/* COMP instance. */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \
+ ( ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_LOWPOWER) \
+ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
+ )
+
+/* Note: On this STM32 serie, comparator input plus parameters are */
+/* the different depending on COMP instances. */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
+ (((__COMP_INSTANCE__) == COMP1) \
+ ? ( \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_DAC1_CH1) \
+ ) \
+ : \
+ ( \
+ ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
+ ) \
+ )
+
+/* Note: On this STM32 serie, comparator input minus parameters are */
+/* the same on all COMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
+ ( ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO4) \
+ || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) \
+ )
+
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \
+ ( ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \
+ || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \
+ )
+
+/* Note: Output redirection is specific to COMP instances but is checked */
+/* with literals of instance COMP2 (no differentiation possible since */
+/* literals of COMP1 and COMP2 share the same values range). */
+#define IS_LL_COMP_OUTPUT_SELECTION(__OUTPUT_SELECTION__) \
+ ( ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_NONE) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM16_BKIN) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_IC1) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM4_OCCLR) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_IC4) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM2_OCCLR) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_IC1_COMP2) \
+ || ((__OUTPUT_SELECTION__) == LL_COMP_OUTPUT_TIM3_OCCLR_COMP2) \
+ )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \
+ ( ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \
+ || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup COMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected COMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param COMPx COMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are de-initialized
+ * - ERROR: COMP registers are not de-initialized
+ */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* COMP instance must not be locked. */
+ if(LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ if(COMPx == COMP1)
+ {
+ CLEAR_BIT(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1SW1
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ | COMP_CSR_COMP1EN
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+ else
+ {
+ CLEAR_BIT(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ | COMP_CSR_COMP1EN
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+
+ }
+ else
+ {
+ /* Comparator instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the comparator is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of COMP instance.
+ * @note This function configures features of the selected COMP instance.
+ * Some features are also available at scope COMP common instance
+ * (common to several COMP instances).
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param COMPx COMP instance
+ * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: COMP registers are initialized
+ * - ERROR: COMP registers are not initialized
+ */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+ assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+ assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+ assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+ assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+ assert_param(IS_LL_COMP_OUTPUT_SELECTION(COMP_InitStruct->OutputSelection));
+ assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* COMP instance must not be locked. */
+ if(LL_COMP_IsLocked(COMPx) == 0U)
+ {
+ /* Configuration of comparator instance : */
+ /* - PowerMode */
+ /* - InputPlus */
+ /* - InputMinus */
+ /* - InputHysteresis */
+ /* - OutputSelection */
+ /* - OutputPolarity */
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ if(COMPx == COMP1)
+ {
+ MODIFY_REG(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1SW1
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ ,
+ ( COMP_InitStruct->PowerMode
+ | COMP_InitStruct->InputPlus
+ | COMP_InitStruct->InputMinus
+ | COMP_InitStruct->InputHysteresis
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+ else
+ {
+ MODIFY_REG(COMP->CSR,
+ ( COMP_CSR_COMP1MODE
+ | COMP_CSR_COMP1INSEL
+ | COMP_CSR_COMP1OUTSEL
+ | COMP_CSR_COMP1HYST
+ | COMP_CSR_COMP1POL
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ ,
+ ( COMP_InitStruct->PowerMode
+ | COMP_InitStruct->InputPlus
+ | COMP_InitStruct->InputMinus
+ | COMP_InitStruct->InputHysteresis
+ | COMP_InitStruct->OutputSelection
+ | COMP_InitStruct->OutputPolarity
+ ) << __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+ }
+
+ }
+ else
+ {
+ /* Initialization error: COMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+ * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+ /* Set COMP_InitStruct fields to default values */
+ COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_ULTRALOWPOWER;
+ COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1;
+ COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT;
+ COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
+ COMP_InitStruct->OutputSelection = LL_COMP_OUTPUT_NONE;
+ COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_comp.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2277 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_comp.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of COMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_COMP_H
+#define __STM32F3xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
+/* COMP IP from 3 to 7 instances and other specific features */
+/* (comparator output blanking, ...) (refer to reference manual). */
+/* - STM32F37x: */
+/* COMP IP with 2 instances */
+/* This file contains the drivers of these COMP IP, located in 2 area */
+/* delimited by compilation switches. */
+
+#if defined(COMP_V1_3_0_0)
+
+#if defined (COMP1) || defined (COMP2) || defined (COMP3) || defined (COMP4) || defined (COMP5) || defined (COMP6) || defined (COMP7)
+
+/** @defgroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)30U) /* Value equivalent to POSITION_VAL(COMPxOUT) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of COMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
+ This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+ uint32_t OutputSelection; /*!< Set comparator output selection.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
+
+ uint32_t OutputPolarity; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+ uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+ * @{
+ */
+#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#if defined(COMP2_CSR_COMP2WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP2_CSR_COMP2WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+#endif
+#if defined(COMP4_CSR_COMP4WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (COMP4_CSR_COMP4WNDWEN) /*!< Window mode enable: Comparators instances pair COMP3 and COMP4 have their input plus connected together. The common input is COMP3 input plus (COMP4 input plus is no more accessible). */
+#endif
+#if defined(COMP6_CSR_COMP6WNDWEN)
+#define LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (COMP6_CSR_COMP6WNDWEN) /*!< Window mode enable: Comparators instances pair COMP5 and COMP6 have their input plus connected together. The common input is COMP5 input plus (COMP6 input plus is no more accessible). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+ * @{
+ */
+#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
+#if defined(COMP_CSR_COMPxMODE)
+#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMPxMODE_0) /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMPxMODE_1) /*!< COMP power mode to low power */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMPxMODE_1 | COMP_CSR_COMPxMODE_0) /*!< COMP power mode to ultra-low power */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+ * @{
+ */
+#if !defined(COMP_CSR_COMPxNONINSEL)
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, PA3 for COMP2 (except STM32F334xx: PA7), PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
+#define LL_COMP_INPUT_PLUS_IO2 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO2: Same as IO1 */
+#else
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA7 for COMP2, PB14 for COMP3, PB0 for COMP4, PD12 for COMP5, PD11 for COMP6, PA0 for COMP7) (COMP instance availability depends on the selected device) */
+#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_COMPxNONINSEL) /*!< Comparator input plus connected to IO2 (pin PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5, PB11 for COMP6, PC1 for COMP7) (COMP instance availability depends on the selected device) */
+#endif
+#if defined(STM32F302xC) || defined(STM32F302xE) || defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F358xx) || defined(STM32F398xx)
+#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
+
+/* Note: Comparator input plus specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8)
+#define LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (COMP_CSR_COMPxSW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP2 input plus (highly resistive switch)) (specific to COMP instance: COMP2) */
+
+/* Note: Comparator input plus specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F302x8) || defined(STM32F302xC) || defined(STM32F302xE)
+/* This device has no comparator input minus DAC1_CH2 */
+#else
+#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#endif
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8)
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA2 for COMP2) */
+#else
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2, PD15 for COMP3, PE8 for COMP4, PD13 for COMP5, PD10 for COMP6, PC0 for COMP7 (COMP instance availability depends on the selected device)) */
+#endif
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_1 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO2 ( PB12 for COMP3, PB2 for COMP4, PB10 for COMP5, PB15 for COMP6 (COMP instance availability depends on the selected device)) */
+#if defined(STM32F301x8) || defined(STM32F318xx) || defined(STM32F334x8) || defined(STM32F302x8) || defined(STM32F303x8) || defined(STM32F328xx)
+/* This device has no comparator input minus IO3 */
+#else
+#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMPxINSEL_2 | COMP_CSR_COMPxINSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
+#endif
+#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMPxINSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1/2/3/4/5/6/7 (COMP instance availability depends on the selected device)) */
+#if defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)
+#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMPxINSEL_3 ) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */
+#else
+/* This device has no comparator input minus DAC2_CH1 */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+ * @{
+ */
+#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
+#if defined(COMP_CSR_COMPxHYST)
+#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMPxHYST_0) /*!< Hysteresis level low (available only on devices: STM32F303xB/C, STM32F358xC) */
+#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMPxHYST_1 ) /*!< Hysteresis level medium (available only on devices: STM32F303xB/C, STM32F358xC) */
+#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMPxHYST_1 | COMP_CSR_COMPxHYST_0) /*!< Hysteresis level high (available only on devices: STM32F303xB/C, STM32F358xC) */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
+ * @{
+ */
+#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
+#if defined(COMP_CSR_COMPxOUT)
+/* Note: Output redirection common to all COMP instances, all STM32F3 serie */
+/* devices. */
+#define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM1_BKIN2 (COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2 (BKIN2) */
+
+#if defined(STM32F301x8) || defined(STM32F318xx)
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx) || defined(STM32F334x8)|| defined(STM32F302x8)
+/* Note: Output redirection specific to COMP instance: COMP2, COMP4 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM1 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F302xC) || defined(STM32F302xE)
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2, COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/* Note: Output redirection specific to COMP instances, defined with */
+/* partially generic naming grouping COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 /*!< COMP output connected to TIM2 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303xC) || defined(STM32F358xx) || defined(STM32F303xE) || defined(STM32F398xx)
+/* Note: Output redirection common to all COMP instances */
+#define LL_COMP_OUTPUT_TIM8_BKIN (COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
+#define LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input 2 and TIM8 break input 2 (BKIN2) */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_BKIN (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2) /*!< COMP output connected to TIM8 break input (BKIN) */
+#define LL_COMP_OUTPUT_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 break input 2 (BKIN2) */
+#define LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2| COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2, TIM8 break input 2 and TIM20 break input 2 (BKIN2) */
+#endif
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3, COMP7 */
+#define LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3, COMP7) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP3 */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP3) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2, COMP4, COMP5 */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1, COMP2, COMP4, COMP5) */
+/* Note: Output redirection specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
+#define LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM8 OCREF clear (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
+/* Note: Output redirection specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 input capture 4 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM20 OCREF clear (specific to COMP instance: COMP2) */
+#endif
+/* Note: Output redirection specific to COMP instance: COMP3 */
+#define LL_COMP_OUTPUT_TIM3_IC2_COMP3 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM3 input capture 2 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM4_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM15_IC1_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP3) */
+#define LL_COMP_OUTPUT_TIM15_BKIN_COMP3 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) */
+/* Note: Output redirection specific to COMP instance: COMP4 */
+#define LL_COMP_OUTPUT_TIM3_IC3_COMP4 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM3 input capture 3 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM4_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 2 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_IC2_COMP4 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM15 input capture 1 (specific to COMP instance: COMP4) */
+#define LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM15 OCREF clear (specific to COMP instance: COMP4) */
+/* Note: Output redirection specific to COMP instance: COMP5 */
+#define LL_COMP_OUTPUT_TIM2_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM4_IC3_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM17_IC1_COMP5 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM17 input capture 1 (specific to COMP instance: COMP5) */
+#define LL_COMP_OUTPUT_TIM16_BKIN_COMP5 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 break input (BKIN) */
+/* Note: Output redirection specific to COMP instance: COMP6 */
+#define LL_COMP_OUTPUT_TIM2_IC2_COMP6 (COMP_CSR_COMPxOUTSEL_2 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM2 input capture 2 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM2_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM2 OCREF clear (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM4_IC4_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM4 input capture 4 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_IC1_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM16 input capture 1 (specific to COMP instance: COMP6) */
+#define LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM16 OCREF clear (specific to COMP instance: COMP6) */
+/* Note: Output redirection specific to COMP instance: COMP7 */
+#define LL_COMP_OUTPUT_TIM1_IC2_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM2 input capture 1 (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM2_IC3_COMP7 (COMP_CSR_COMPxOUTSEL_3) /*!< COMP output connected to TIM4 input capture 3 (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM17 OCREF clear (specific to COMP instance: COMP7) */
+#define LL_COMP_OUTPUT_TIM17_BKIN_COMP7 (COMP_CSR_COMPxOUTSEL_3 | COMP_CSR_COMPxOUTSEL_1 | COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM17 break input (BKIN) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */
+/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
+#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_IC2 LL_COMP_OUTPUT_TIM1_IC2_COMP7 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC1 LL_COMP_OUTPUT_TIM2_IC1_COMP5 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC2 LL_COMP_OUTPUT_TIM2_IC2_COMP6 /*!< COMP output connected to TIM2 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC3 LL_COMP_OUTPUT_TIM2_IC3_COMP7 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM2_IC4 LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 /*!< COMP output connected to TIM2 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC1 LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 /*!< COMP output connected to TIM3 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC2 LL_COMP_OUTPUT_TIM3_IC2_COMP3 /*!< COMP output connected to TIM3 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_IC3 LL_COMP_OUTPUT_TIM3_IC3_COMP4 /*!< COMP output connected to TIM3 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM3_OCCLR LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 /*!< COMP output connected to TIM3 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP3 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC2 LL_COMP_OUTPUT_TIM4_IC2_COMP4 /*!< COMP output connected to TIM4 input capture 2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC3 LL_COMP_OUTPUT_TIM4_IC3_COMP5 /*!< COMP output connected to TIM4 input capture 3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC4 LL_COMP_OUTPUT_TIM4_IC4_COMP6 /*!< COMP output connected to TIM4 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM8_OCCLR LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 /*!< COMP output connected to TIM8 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC1 LL_COMP_OUTPUT_TIM15_IC1_COMP3 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_IC2 LL_COMP_OUTPUT_TIM15_IC2_COMP4 /*!< COMP output connected to TIM15 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP3 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM15_OCCLR LL_COMP_OUTPUT_TIM15_OCCLR_COMP4 /*!< COMP output connected to TIM15 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_IC1 LL_COMP_OUTPUT_TIM16_IC1_COMP6 /*!< COMP output connected to TIM16 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP5 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_OCCLR LL_COMP_OUTPUT_TIM16_OCCLR_COMP6 /*!< COMP output connected to TIM16 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_IC1 LL_COMP_OUTPUT_TIM17_IC1_COMP5 /*!< COMP output connected to TIM17 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_BKIN LL_COMP_OUTPUT_TIM17_BKIN_COMP7 /*!< COMP output connected to TIM17 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM17_OCCLR LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 /*!< COMP output connected to TIM17 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#if defined(STM32F303xE) || defined(STM32F398xx)
+#define LL_COMP_OUTPUT_TIM20_OCCLR LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 /*!< COMP output connected to TIM20 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#endif
+
+#endif
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+ * @{
+ */
+#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMPxPOL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+ * @{
+ */
+#define LL_COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000U) /*!<Comparator output without blanking */
+#if defined(COMP_CSR_COMPxBLANKING)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+/* Note: Output blanking source specific to COMP instance: COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+/* Note: Output blanking source specific to COMP instance: COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F302xE) || defined(STM32F302xC)
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+/* Note: Output blanking source specific to COMP instance: COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (COMP_CSR_COMPxBLANKING_0 | COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#elif defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1, COMP2, COMP7) */
+/* Note: Output blanking source specific to COMP instance: COMP1, COMP2 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1, COMP2) */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1, COMP2) */
+/* Note: Output blanking source specific to COMP instance: COMP3, COMP6 */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3, COMP6) */
+/* Note: Output blanking source specific to COMP instance: COMP4, COMP5, COMP6, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (COMP_CSR_COMPxBLANKING_1) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4, COMP5, COMP6, COMP7) */
+/* Note: Output blanling source specific to COMP instance: COMP6, COMP7 */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (COMP_CSR_COMPxBLANKING_2) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6, COMP7) */
+/* Note: Output blanking source specific to COMP instance: COMP4 */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 (COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4) */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (COMP_CSR_COMPxBLANKING_1 | COMP_CSR_COMPxBLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4) */
+
+/* Note: Output blanking source specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5 LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 /*!< Comparator output blanking source TIM1 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3 LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 /*!< Comparator output blanking source TIM2 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4 LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 /*!< Comparator output blanking source TIM2 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3 LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 /*!< Comparator output blanking source TIM3 OC3. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4 LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 /*!< Comparator output blanking source TIM3 OC4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5 LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 /*!< Comparator output blanking source TIM8 OC5. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1 LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 /*!< Comparator output blanking source TIM15 OC1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2 LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 /*!< Comparator output blanking source TIM15 OC2. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+
+#endif
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+ * @{
+ */
+#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
+ * @note Only COMP IP HW delays are defined in COMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for comparator startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
+#else
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 10U) /*!< Delay for COMP startup time */
+#endif
+
+/* Delay for comparator voltage scaler stabilization time. */
+/* Note: Voltage scaler is used when selecting comparator input */
+/* based on VrefInt: VrefInt or subdivision of VrefInt. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tS_SC"). */
+/* Unit: us */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+ * @{
+ */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+
+/**
+ * @brief Write a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to select the COMP common instance
+ * to which is belonging the selected COMP instance.
+ * @note COMP common register instance can be used to
+ * set parameters common to several COMP instances.
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param __COMPx__ COMP instance
+ * @retval COMP common instance or value "0" if there is no COMP common instance.
+ */
+#if defined(COMP1) && defined(COMP2) && defined(COMP3) && defined(COMP4) && defined(COMP5) && defined(COMP6) && defined(COMP7)
+/* Note: On STM32F3 serie devices with 7 comparator instances, */
+/* COMP instance COMP7 has no other comparator instance to work */
+/* in pair with: window mode is not available for COMP7. */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2)) \
+ ? ( \
+ (COMP12_COMMON) \
+ ) \
+ : \
+ ((((__COMPx__) == COMP3) || ((__COMPx__) == COMP4)) \
+ ? ( \
+ (COMP34_COMMON) \
+ ) \
+ : \
+ ((((__COMPx__) == COMP5) || ((__COMPx__) == COMP6)) \
+ ? ( \
+ (COMP56_COMMON) \
+ ) \
+ : \
+ ( \
+ ((uint32_t)0U) \
+ ) \
+ ) \
+ ) \
+ )
+#elif defined(COMP1) && defined(COMP2) && defined(COMP4) && defined(COMP6)
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((((__COMPx__) == COMP1) || ((__COMPx__) == COMP2)) \
+ ? ( \
+ (COMP12_COMMON) \
+ ) \
+ : \
+ ( \
+ ((uint32_t)0U) \
+ ) \
+ )
+#elif defined(COMP2) && defined(COMP4) && defined(COMP6)
+/* Note: On STM32F3 serie devices with 3 comparator instances (COMP2, 4, 6) */
+/* COMP instances have no other comparator instance to work */
+/* in pair with: window mode is not available for all COMP instances. */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ ((uint32_t)0U)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+ * @{
+ */
+
+/**
+ * @brief Set window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR COMPxWNDWEN LL_COMP_SetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
+ *
+ * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+#if defined(COMP_CSR_COMPxWNDWEN)
+ MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN, WindowMode);
+#else
+ /* Device without pair of comparator working in window mode */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_WINDOWMODE_DISABLE"). */
+#endif
+}
+
+/**
+ * @brief Get window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR COMPxWNDWEN LL_COMP_GetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP3_INPUT_PLUS_COMMON (2)
+ * @arg @ref LL_COMP_WINDOWMODE_COMP5_INPUT_PLUS_COMMON (2)
+ *
+ * (1) Parameter available on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * (2) Parameter available on devices: STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+#if defined(COMP_CSR_COMPxWNDWEN)
+ return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_COMPxWNDWEN));
+#else
+ /* Device without pair of comparator working in window mode */
+ return (LL_COMP_WINDOWMODE_DISABLE);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMPxMODE LL_COMP_SetPowerMode
+ * @param COMPx Comparator instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1)
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1)
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+#if defined(COMP_CSR_COMPxMODE)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxMODE, PowerMode);
+#else
+ /* Device without comparator power mode configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_POWERMODE_HIGHSPEED"). */
+#endif
+}
+
+/**
+ * @brief Get comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMPxMODE LL_COMP_GetPowerMode
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED (1)
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER (1)
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxMODE)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxMODE));
+#else
+ /* Device without comparator power mode configurable */
+ return (LL_COMP_POWERMODE_HIGHSPEED);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+ * @{
+ */
+
+/**
+ * @brief Set comparator inputs minus (inverting) and plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 serie, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tS_SC".
+ * @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
+ * CSR NONINSEL LL_COMP_ConfigInputs
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1,
+ InputMinus | InputPlus);
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxNONINSEL,
+ InputMinus | InputPlus);
+#elif defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL | COMP_CSR_COMPxSW1,
+ InputMinus | InputPlus);
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+ MODIFY_REG(COMPx->CSR,
+ COMP_CSR_COMPxINSEL,
+ InputMinus);
+#endif
+}
+
+/**
+ * @brief Set comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR NONINSEL LL_COMP_SetInputPlus
+ * @param COMPx Comparator instance
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1), InputPlus);
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxNONINSEL, InputPlus);
+#elif defined(COMP_CSR_COMPxSW1)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxSW1, InputPlus);
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+#endif
+}
+
+/**
+ * @brief Get comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR NONINSEL LL_COMP_GetInputPlus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_IO2 (1)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP1 (2)
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1_COMP2 (3)
+ *
+ * (1) Parameter available only on devices STM32F302xB/C, STM32F303xB/C, STM32F358xC.\n
+ * (2) Parameter available on devices: STM32F302xB/C, STM32F302xD/E, STM32F303xB/C/D/E, STM32F358xC, STM32F398xE.\n
+ * (3) Parameter available on devices: STM32F301x6/8, STM32F318xx, STM32F302x6/8.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxNONINSEL) && defined(COMP_CSR_COMPxSW1)
+ return (uint32_t)(READ_BIT(COMPx->CSR, (COMP_CSR_COMPxNONINSEL | COMP_CSR_COMPxSW1)));
+#elif defined(COMP_CSR_COMPxNONINSEL)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxNONINSEL));
+#elif defined(COMP_CSR_COMPxSW1)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxSW1));
+#else
+ /* Device without comparator input plus configurable */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_INPUT_PLUS_IO1" or "LL_COMP_INPUT_PLUS_IO2" compared to */
+ /* other STM32F3 devices, depending on comparator instance */
+ /* (refer to reference manual)). */
+ return (LL_COMP_INPUT_PLUS_IO1);
+#endif
+}
+
+/**
+ * @brief Set comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note On this STM32 serie, a voltage scaler is used
+ * when COMP input is based on VrefInt (VrefInt or subdivision
+ * of VrefInt):
+ * Voltage scaler requires a delay for voltage stabilization.
+ * Refer to device datasheet, parameter "tS_SC".
+ * @rmtoll CSR INMSEL LL_COMP_SetInputMinus
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxINSEL, InputMinus);
+}
+
+/**
+ * @brief Get comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR INMSEL LL_COMP_GetInputMinus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (3)
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (2)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3 (1)
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * (1) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302x6/8, STM32F303x6/8, STM32F328xx, STM32F334xx.\n
+ * (2) Parameter available only on devices STM32F303x6/8, STM32F328x8, STM32F334xx.\n
+ * (3) Parameter available on all devices except STM32F301x6/8, STM32F318x8, STM32F302xx.\n
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxINSEL));
+}
+
+/**
+ * @brief Set comparator instance hysteresis mode of the input minus (inverting input).
+ * @rmtoll CSR COMPxHYST LL_COMP_SetInputHysteresis
+ * @param COMPx Comparator instance
+ * @param InputHysteresis This parameter can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW (1)
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1)
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+#if defined(COMP_CSR_COMPxHYST)
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxHYST, InputHysteresis);
+#else
+ /* Device without comparator input hysteresis */
+ /* No update of comparator register (corresponds to setting */
+ /* "LL_COMP_HYSTERESIS_NONE"). */
+#endif
+}
+
+/**
+ * @brief Get comparator instance hysteresis mode of the minus (inverting) input.
+ * @rmtoll CSR COMPxHYST LL_COMP_GetInputHysteresis
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW (1)
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM (1)
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH (1)
+ *
+ * (1) Parameter available only on devices: STM32F302xB/C, STM32F303xB/C, STM32F358xC
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+#if defined(COMP_CSR_COMPxHYST)
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxHYST));
+#else
+ /* Device without comparator input hysteresis */
+ return (LL_COMP_HYSTERESIS_NONE);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+ * @{
+ */
+
+/**
+ * @brief Set comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxOUTSEL LL_COMP_SetOutputSelection
+ * @param COMPx Comparator instance
+ * @param OutputSelection This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4)
+ *
+ * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
+ * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
+ * (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxOUTSEL , OutputSelection);
+}
+
+/**
+ * @brief Get comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxOUTSEL LL_COMP_GetOutputSelection
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM1_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_BKIN2 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_TIM8_TIM20_BKIN2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2_3_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP1_2_4_5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM8_OCCLR_COMP4_5_6_7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR_COMP2_4 (6)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP2 (2)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP2 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1_COMP1_2 (3)
+ * @arg @ref LL_COMP_OUTPUT_TIM20_OCCLR_COMP2 (5)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC2_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC1_COMP3 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM15_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC3_COMP4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_IC2_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM15_OCCLR_COMP4
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC3_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_IC1_COMP5 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC2_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC4_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_IC1_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM16_OCCLR_COMP6
+ * @arg @ref LL_COMP_OUTPUT_TIM1_IC2_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC3_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_OCCLR_COMP7 (4)
+ * @arg @ref LL_COMP_OUTPUT_TIM17_BKIN (4)
+ *
+ * (1) Parameter available on devices: STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8, STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (2) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F328xx, STM32F334x8.\n
+ * (3) Parameter available on devices: STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (4) Parameter available on devices: STM32F303xC, STM32F358xx, STM32F303xE, STM32F398xx.\n
+ * (5) Parameter available on devices: STM32F303xE, STM32F398xx.\n
+ * (6) Parameter available on devices: STM32F303x8, STM32F328xx, STM32F334x8.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUTSEL));
+}
+
+/**
+ * @brief Set comparator instance output polarity.
+ * @rmtoll CSR COMPxPOL LL_COMP_SetOutputPolarity
+ * @param COMPx Comparator instance
+ * @param OutputPolarity This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxPOL, OutputPolarity);
+}
+
+/**
+ * @brief Get comparator instance output polarity.
+ * @rmtoll CSR COMPxPOL LL_COMP_GetOutputPolarity
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxPOL));
+}
+
+/**
+ * @brief Set comparator instance blanking source.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMPxBLANKING LL_COMP_SetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @param BlankingSource This parameter can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (1)(2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3)
+ *
+ * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
+ * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
+ * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+ MODIFY_REG(COMPx->CSR, COMP_CSR_COMPxBLANKING, BlankingSource);
+}
+
+/**
+ * @brief Get comparator instance blanking source.
+ * @note Availability of parameters of blanking source from timer
+ * depends on timers availability on the selected device.
+ * @note Blanking source may be specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMPxBLANKING LL_COMP_GetOutputBlankingSource
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_BLANKINGSRC_NONE
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 (1)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1_2 (2)(3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 (2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (1)(2)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1_2_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3_6 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4_5_6_7 (3)
+ * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6_7 (3)
+ *
+ * (1) Parameter available on devices: STM32F301x8, STM32F302x8, STM32F318xx, STM32F303x8, STM32F334x8, STM32F328xx.\n
+ * (2) Parameter available on devices: STM32F302xE, STM32F302xC.\n
+ * (3) Parameter available on devices: STM32F303xE, STM32F398xx, STM32F303xC, STM32F358xx.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxBLANKING));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+ * @{
+ */
+
+/**
+ * @brief Enable comparator instance.
+ * @note After enable from off state, comparator requires a delay
+ * to reach reach propagation delay specification.
+ * Refer to device datasheet, parameter "tSTART".
+ * @rmtoll CSR COMPxEN LL_COMP_Enable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+ * @brief Disable comparator instance.
+ * @rmtoll CSR COMPxEN LL_COMP_Disable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMPx->CSR, COMP_CSR_COMPxEN);
+}
+
+/**
+ * @brief Get comparator enable state
+ * (0: COMP is disabled, 1: COMP is enabled)
+ * @rmtoll CSR COMPxEN LL_COMP_IsEnabled
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxEN) == (COMP_CSR_COMPxEN));
+}
+
+/**
+ * @brief Lock comparator instance.
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMPxLOCK LL_COMP_Lock
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK);
+}
+
+/**
+ * @brief Get comparator lock state
+ * (0: COMP is unlocked, 1: COMP is locked).
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMPxLOCK LL_COMP_IsLocked
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMPx->CSR, COMP_CSR_COMPxLOCK) == (COMP_CSR_COMPxLOCK));
+}
+
+/**
+ * @brief Read comparator instance output level.
+ * @note The comparator output level depends on the selected polarity
+ * (Refer to function @ref LL_COMP_SetOutputPolarity()).
+ * If the comparator polarity is not inverted:
+ * - Comparator output is low when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is high when the input plus
+ * is at a higher voltage than the input minus
+ * If the comparator polarity is inverted:
+ * - Comparator output is high when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is low when the input plus
+ * is at a higher voltage than the input minus
+ * @rmtoll CSR COMPxOUT LL_COMP_ReadOutputLevel
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_COMPxOUT)
+ >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 || COMP3 || COMP4 || COMP5 || COMP6 || COMP7 */
+
+
+#endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
+
+#if defined (COMP_V1_1_0_0)
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @defgroup COMP_LL COMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Constants COMP Private Constants
+ * @{
+ */
+
+/* Differentiation between COMP instances */
+/* Note: Value not corresponding to a register offset since both */
+/* COMP instances are sharing the same register) . */
+#define COMPX_BASE COMP_BASE
+#define COMPX (COMP1 - COMP2)
+
+/* COMP registers bits positions */
+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(COMP_CSR_COMP1OUT) */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Macros COMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: if COMP instance selected
+ * is odd (COMP1, COMP3, ...), return value '1', else return '0'.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval If COMP instance is odd, value '1'. Else, value '0'.
+*/
+#define __COMP_IS_INSTANCE_ODD(__COMP_INSTANCE__) \
+ ((~(((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)) & 0x00000001)
+
+/**
+ * @brief Driver macro reserved for internal use: if COMP instance selected
+ * is even (COMP2, COMP4, ...), return value '1', else return '0'.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval If COMP instance is even, value '1'. Else, value '0'.
+*/
+#define __COMP_IS_INSTANCE_EVEN(__COMP_INSTANCE__) \
+ (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) >> 1U)
+
+/**
+ * @brief Driver macro reserved for internal use: from COMP instance
+ * selected, set offset of bits into COMP register.
+ * @note Since both COMP instances are sharing the same register
+ * with 2 area of bits with an offset of 16 bits, this function
+ * returns value "0" if COMP1 is selected and "16" if COMP2 is
+ * selected.
+ * @param __COMP_INSTANCE__ COMP instance
+ * @retval Bits offset in register 32 bits
+*/
+#define __COMP_BITOFFSET_INSTANCE(__COMP_INSTANCE__) \
+ (((uint32_t)(__COMP_INSTANCE__) - COMP_BASE) << 3U)
+
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of COMP instance.
+ */
+typedef struct
+{
+ uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
+ This parameter can be a value of @ref COMP_LL_EC_POWERMODE
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */
+
+ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
+
+ uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
+
+ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
+ This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
+
+ uint32_t OutputSelection; /*!< Set comparator output selection.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputSelection(). */
+
+ uint32_t OutputPolarity; /*!< Set comparator output polarity.
+ This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+ * @{
+ */
+
+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
+ * @{
+ */
+#define LL_COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WNDWEN) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
+ * @{
+ */
+#define LL_COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000U) /*!< COMP power mode to high speed */
+#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_COMP1MODE_0) /*!< COMP power mode to medium speed */
+#define LL_COMP_POWERMODE_LOWPOWER (COMP_CSR_COMP1MODE_1) /*!< COMP power mode to low power */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_COMP1MODE_1 | COMP_CSR_COMP1MODE_0) /*!< COMP power mode to ultra-low power */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000U) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA3 for COMP2) */
+#define LL_COMP_INPUT_PLUS_DAC1_CH1 (COMP_CSR_COMP1SW1) /*!< Comparator input plus connected to DAC1 channel 1 (DAC_OUT1), through dedicated switch (Note: this switch is solely intended to redirect signals onto high impedance input, such as COMP1 input plus (highly resistive switch)) (specific to COMP instance: COMP1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+ * @{
+ */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT ((uint32_t)0x00000000U) /*!< Comparator input minus connected to 1/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
+#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA0 for COMP1, pin PA2 for COMP2) */
+#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO2 (pin PA6 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_IO3 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to IO3 (pin PA5 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_COMP1INSEL_2 ) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1 & COMP2) */
+#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_COMP1INSEL_2 | COMP_CSR_COMP1INSEL_1 | COMP_CSR_COMP1INSEL_0) /*!< Comparator input minus connected to DAC2 channel 1 (DAC2_OUT1) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+ * @{
+ */
+#define LL_COMP_HYSTERESIS_NONE ((uint32_t)0x00000000U) /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_COMP1HYST_0) /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_COMP1HYST_1 ) /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_COMP1HYST_1 | COMP_CSR_COMP1HYST_0) /*!< Hysteresis level high */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_SELECTION Comparator output - Output selection
+ * @{
+ */
+/* Note: Output redirection is common for COMP1 and COMP2 */
+#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000U) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) */
+#define LL_COMP_OUTPUT_TIM2_IC4 (COMP_CSR_COMP1OUTSEL_2) /*!< COMP output connected to TIM2 input capture 4 */
+#define LL_COMP_OUTPUT_TIM2_OCCLR (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear */
+
+/* Note: Output redirection specific to COMP instance: COMP1 */
+#define LL_COMP_OUTPUT_TIM15_BKIN_COMP1 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM15 break input (BKIN) (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP1 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM5_IC4_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM5 input capture 4 (specific to COMP instance: COMP1) */
+#define LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM5 OCREF clear (specific to COMP instance: COMP1) */
+
+/* Note: Output redirection specific to COMP instance: COMP2 */
+#define LL_COMP_OUTPUT_TIM16_BKIN_COMP2 (COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM16 break input (BKIN) (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM4_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM4 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM4 OCREF clear (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_IC1_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1) /*!< COMP output connected to TIM3 input capture 1 (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM3_OCCLR_COMP2 (COMP_CSR_COMP1OUTSEL_2 | COMP_CSR_COMP1OUTSEL_1 | COMP_CSR_COMP1OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear (specific to COMP instance: COMP2) */
+
+/* Note: Output redirection specific to COMP instances, defined with */
+/* generic naming not taking into account COMP instance constraints. */
+/* Refer to literal definitions above for COMP instance constraints. */
+/* Note: Some output redirections cannot have a generic naming, */
+/* due to literal value different depending on COMP instance. */
+/* (For exemple: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and */
+/* LL_COMP_OUTPUT_TIM3_IC1_COMP2). */
+#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_IC1 LL_COMP_OUTPUT_TIM4_IC1_COMP2 /*!< COMP output connected to TIM4 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM4_OCCLR LL_COMP_OUTPUT_TIM4_OCCLR_COMP2 /*!< COMP output connected to TIM4 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM5_IC4 LL_COMP_OUTPUT_TIM5_IC1_COMP1 /*!< COMP output connected to TIM5 input capture 4. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+#define LL_COMP_OUTPUT_TIM5_OCCLR LL_COMP_OUTPUT_TIM5_OCCLR_COMP1 /*!< COMP output connected to TIM5 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+ * @{
+ */
+#define LL_COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000U) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_COMP1POL) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+ * @{
+ */
+#define LL_COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
+ * @note Only COMP IP HW delays are defined in COMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for comparator startup time. */
+/* Note: Delay required to reach propagation delay specification. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_COMP_DELAY_STARTUP_US ((uint32_t) 60U) /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time */
+/* (voltage from VrefInt, delay based on VrefInt startup time). */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tS_SC"). */
+/* Unit: us */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ((uint32_t) 200U) /*!< Delay for COMP voltage scaler stabilization time */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+ * @{
+ */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+
+/**
+ * @brief Write a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in COMP register
+ * @param __INSTANCE__ comparator instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to select the COMP common instance
+ * to which is belonging the selected COMP instance.
+ * @note COMP common register instance can be used to
+ * set parameters common to several COMP instances.
+ * Refer to functions having argument "COMPxy_COMMON" as parameter.
+ * @param __COMPx__ COMP instance
+ * @retval COMP common instance or value "0" if there is no COMP common instance.
+ */
+#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
+ (COMP12_COMMON)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+ * @{
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances
+ * @{
+ */
+
+/**
+ * @brief Set window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR WNDWEN LL_COMP_SetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @param WindowMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
+{
+ MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN, WindowMode);
+}
+
+/**
+ * @brief Get window mode of a pair of comparators instances
+ * (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).
+ * @rmtoll CSR WNDWEN LL_COMP_GetCommonWindowMode
+ * @param COMPxy_COMMON Comparator common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_WINDOWMODE_DISABLE
+ * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WNDWEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
+ * @{
+ */
+
+/**
+ * @brief Set comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMP1MODE LL_COMP_SetPowerMode\n
+ * COMP2MODE LL_COMP_SetPowerMode
+ * @param COMPx Comparator instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx),
+ PowerMode << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator instance operating mode to adjust power and speed.
+ * @rmtoll CSR COMP1MODE LL_COMP_GetPowerMode\n
+ * COMP2MODE LL_COMP_GetPowerMode
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_POWERMODE_HIGHSPEED
+ * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
+ * @arg @ref LL_COMP_POWERMODE_LOWPOWER
+ * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1MODE << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+ * @{
+ */
+
+/**
+ * @brief Set comparator inputs minus (inverting) and plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_ConfigInputs\n
+ * CSR COMP2INSEL LL_COMP_ConfigInputs\n
+ * CSR COMP1SW1 LL_COMP_ConfigInputs
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore if COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ MODIFY_REG(COMP->CSR,
+ (COMP_CSR_COMP1INSEL | (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx))) << __COMP_BITOFFSET_INSTANCE(COMPx),
+ (InputMinus | InputPlus) << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Set comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_SetInputPlus\n
+ * CSR COMP2INSEL LL_COMP_SetInputPlus
+ * @param COMPx Comparator instance
+ * @param InputPlus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore if COMP2 is selected the equivalent bit is */
+ /* kept unmodified. */
+ MODIFY_REG(COMP->CSR,
+ (COMP_CSR_COMP1SW1 * __COMP_IS_INSTANCE_ODD(COMPx)) << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputPlus << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator input plus (non-inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1INSEL LL_COMP_GetInputPlus\n
+ * CSR COMP2INSEL LL_COMP_GetInputPlus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_PLUS_IO1
+ * @arg @ref LL_COMP_INPUT_PLUS_DAC1_CH1 (1)
+ *
+ * (1) Parameter available only on COMP instance: COMP1.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+{
+ /* Note: Connection switch is applicable only to COMP instance COMP1, */
+ /* therefore is COMP2 is selected the returned value will be null. */
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1SW1 << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1SW1 LL_COMP_SetInputMinus
+ * @param COMPx Comparator instance
+ * @param InputMinus This parameter can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputMinus << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator input minus (inverting).
+ * @note In case of comparator input selected to be connected to IO:
+ * GPIO pins are specific to each comparator instance.
+ * Refer to description of parameters or to reference manual.
+ * @rmtoll CSR COMP1SW1 LL_COMP_GetInputMinus
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO1
+ * @arg @ref LL_COMP_INPUT_MINUS_IO2
+ * @arg @ref LL_COMP_INPUT_MINUS_IO3
+ * @arg @ref LL_COMP_INPUT_MINUS_IO4
+ * @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1INSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator instance hysteresis mode of the input minus (inverting input).
+ * @rmtoll CSR COMP1HYST LL_COMP_SetInputHysteresis\n
+ * COMP2HYST LL_COMP_SetInputHysteresis
+ * @param COMPx Comparator instance
+ * @param InputHysteresis This parameter can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx),
+ InputHysteresis << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator instance hysteresis mode of the minus (inverting) input.
+ * @rmtoll CSR COMP1HYST LL_COMP_GetInputHysteresis\n
+ * COMP2HYST LL_COMP_GetInputHysteresis
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_HYSTERESIS_NONE
+ * @arg @ref LL_COMP_HYSTERESIS_LOW
+ * @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+ * @arg @ref LL_COMP_HYSTERESIS_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1HYST << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+ * @{
+ */
+
+/**
+ * @brief Set comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMP1OUTSEL LL_COMP_SetOutputSelection\n
+ * COMP2OUTSEL LL_COMP_SetOutputSelection
+ * @param COMPx Comparator instance
+ * @param OutputSelection This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
+ *
+ * (1) Parameter availability depending on timer availability
+ * on the selected device.
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputSelection(COMP_TypeDef *COMPx, uint32_t OutputSelection)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ OutputSelection << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator output selection.
+ * @note Availability of parameters of output selection to timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CSR COMP1OUTSEL LL_COMP_GetOutputSelection\n
+ * COMP2OUTSEL LL_COMP_GetOutputSelection
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_NONE
+ * @arg @ref LL_COMP_OUTPUT_TIM16_BKIN (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM4_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_IC4 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM2_OCCLR (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_IC1 (1)
+ * @arg @ref LL_COMP_OUTPUT_TIM3_OCCLR (1)
+ *
+ * (1) Parameter availability depending on timer availability
+ * on the selected device.
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputSelection(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1OUTSEL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @brief Set comparator instance output polarity.
+ * @rmtoll CSR COMP1POL LL_COMP_SetOutputPolarity\n
+ * COMP2POL LL_COMP_SetOutputPolarity
+ * @param COMPx Comparator instance
+ * @param OutputPolarity This parameter can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+ MODIFY_REG(COMP->CSR,
+ COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx),
+ OutputPolarity << __COMP_BITOFFSET_INSTANCE(COMPx) );
+}
+
+/**
+ * @brief Get comparator instance output polarity.
+ * @rmtoll CSR COMP1POL LL_COMP_GetOutputPolarity\n
+ * COMP2POL LL_COMP_GetOutputPolarity
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+ * @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1POL << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> __COMP_BITOFFSET_INSTANCE(COMPx)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+ * @{
+ */
+
+/**
+ * @brief Enable comparator instance.
+ * @note After enable from off state, comparator requires a delay
+ * to reach reach propagation delay specification.
+ * Refer to device datasheet, parameter "tSTART".
+ * @rmtoll CSR COMP1EN LL_COMP_Enable\n
+ * COMP2EN LL_COMP_Enable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Disable comparator instance.
+ * @rmtoll CSR COMP1EN LL_COMP_Disable\n
+ * COMP2EN LL_COMP_Disable
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator enable state
+ * (0: COMP is disabled, 1: COMP is enabled)
+ * @rmtoll CSR COMP1EN LL_COMP_IsEnabled\n
+ * COMP2EN LL_COMP_IsEnabled
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMP->CSR, COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1EN << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Lock comparator instance.
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMP1LOCK LL_COMP_Lock\n
+ * COMP2LOCK LL_COMP_Lock
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Get comparator lock state
+ * (0: COMP is unlocked, 1: COMP is locked).
+ * @note Once locked, comparator configuration can be accessed in read-only.
+ * @note The only way to unlock the comparator is a device hardware reset.
+ * @rmtoll CSR COMP1LOCK LL_COMP_IsLocked\n
+ * COMP2LOCK LL_COMP_IsLocked
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+{
+ return (READ_BIT(COMP->CSR, COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx)) == COMP_CSR_COMP1LOCK << __COMP_BITOFFSET_INSTANCE(COMPx));
+}
+
+/**
+ * @brief Read comparator instance output level.
+ * @note The comparator output level depends on the selected polarity
+ * (Refer to function @ref LL_COMP_SetOutputPolarity()).
+ * If the comparator polarity is not inverted:
+ * - Comparator output is low when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is high when the input plus
+ * is at a higher voltage than the input minus
+ * If the comparator polarity is inverted:
+ * - Comparator output is high when the input plus
+ * is at a lower voltage than the input minus
+ * - Comparator output is low when the input plus
+ * is at a higher voltage than the input minus
+ * @rmtoll CSR COMP1OUT LL_COMP_ReadOutputLevel\n
+ * COMP2OUT LL_COMP_ReadOutputLevel
+ * @param COMPx Comparator instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+ * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+{
+ return (uint32_t)(READ_BIT(COMP->CSR,
+ COMP_CSR_COMP1OUT << __COMP_BITOFFSET_INSTANCE(COMPx))
+ >> (__COMP_BITOFFSET_INSTANCE(COMPx) + LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS)
+ );
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* COMP1 || COMP2 */
+
+
+#endif /* STM32F373xC || STM32F378xx */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_COMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_cortex.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,658 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_cortex.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (MPU services provided only on some devices)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_CORTEX_H
+#define __STM32F3xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x0: revision 0)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M4 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC24 for Cortex-M4
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_crc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,137 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_crc.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_crc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+ /* Set programmable polynomial size in CR register to reset value (32 bits)*/
+ LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
+
+ /* Set programmable polynomial in POL register to reset value */
+ LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
+
+ /* Set INIT register to reset value */
+ LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
+
+ /* Set Reversibility options on I/O data values in CR register to reset value */
+ LL_CRC_SetInputDataReverseMode(CRCx, LL_CRC_INDATA_REVERSE_NONE);
+ LL_CRC_SetOutputDataReverseMode(CRCx, LL_CRC_OUTDATA_REVERSE_NONE);
+
+ /* Reset the CRC calculation unit */
+ LL_CRC_ResetCRCCalculationUnit(CRCx);
+
+ /* Reset IDR register */
+ LL_CRC_Write_IDR(CRCx, 0x00U);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_crc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,479 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_crc.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of CRC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_CRC_H
+#define __STM32F3xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
+ * @{
+ */
+
+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
+ * @{
+ */
+#define LL_CRC_POLYLENGTH_32B (uint32_t)0x00000000U /*!< 32 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
+#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
+ * @{
+ */
+#define LL_CRC_INDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Input Data bit order not affected */
+#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
+#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
+#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
+ * @{
+ */
+#define LL_CRC_OUTDATA_REVERSE_NONE (uint32_t)0x00000000U /*!< Output Data bit order not affected */
+#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
+ * @brief Normal representation of this polynomial value is
+ * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC32_POLY (uint32_t)0x04C11DB7U /*!< Default CRC generating polynomial value */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define LL_CRC_DEFAULT_CRC_INITVALUE (uint32_t)0xFFFFFFFFU /*!< Default CRC computation initialization value */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Reset the CRC calculation unit.
+ * @note If Programmable Initial CRC value feature
+ * is available, also set the Data Register to the value stored in the
+ * CRC_INIT register, otherwise, reset Data Register to its default value.
+ * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
+ * @param CRCx CRC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+ SET_BIT(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+ * @brief Configure size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
+ * @param CRCx CRC Instance
+ * @param PolySize This parameter can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
+}
+
+/**
+ * @brief Return size of the polynomial.
+ * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_POLYLENGTH_32B
+ * @arg @ref LL_CRC_POLYLENGTH_16B
+ * @arg @ref LL_CRC_POLYLENGTH_8B
+ * @arg @ref LL_CRC_POLYLENGTH_7B
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the input data
+ * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
+}
+
+/**
+ * @brief Return type of reversal for input data bit order
+ * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_INDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_INDATA_REVERSE_BYTE
+ * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
+ * @arg @ref LL_CRC_INDATA_REVERSE_WORD
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @param ReverseMode This parameter can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
+{
+ MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
+}
+
+/**
+ * @brief Configure the reversal of the bit order of the Output data
+ * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
+ * @param CRCx CRC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
+ * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
+}
+
+/**
+ * @brief Initialize the Programmable initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to write the correct value
+ * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
+ * @rmtoll INIT INIT LL_CRC_SetInitialData
+ * @param CRCx CRC Instance
+ * @param InitCrc Value to be programmed in Programmable initial CRC value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
+{
+ WRITE_REG(CRCx->INIT, InitCrc);
+}
+
+/**
+ * @brief Return current Initial CRC value.
+ * @note If the CRC size is less than 32 bits, the least significant bits
+ * are used to read the correct value
+ * @rmtoll INIT INIT LL_CRC_GetInitialData
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable initial CRC value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->INIT));
+}
+
+/**
+ * @brief Initialize the Programmable polynomial value
+ * (coefficients of the polynomial to be used for CRC calculation).
+ * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_SetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @param PolynomCoef Value to be programmed in Programmable Polynomial value register
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
+{
+ WRITE_REG(CRCx->POL, PolynomCoef);
+}
+
+/**
+ * @brief Return current Programmable polynomial value
+ * @note Please check Reference Manual and existing Errata Sheets,
+ * regarding possible limitations for Polynomial values usage.
+ * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @rmtoll POL POL LL_CRC_GetPolynomialCoef
+ * @param CRCx CRC Instance
+ * @retval Value programmed in Programmable Polynomial value register
+ */
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->POL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write given 32-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData32
+ * @param CRCx CRC Instance
+ * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+ * @brief Write given 16-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData16
+ * @param CRCx CRC Instance
+ * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
+{
+ *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+}
+
+/**
+ * @brief Write given 8-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData8
+ * @param CRCx CRC Instance
+ * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
+{
+ *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
+}
+
+/**
+ * @brief Return current CRC calculation result. 32 bits value is returned.
+ * @rmtoll DR DR LL_CRC_ReadData32
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+ */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+ * @brief Return current CRC calculation result. 16 bits value is returned.
+ * @note This function is expected to be used in a 16 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData16
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
+ */
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+{
+ return (uint16_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 8 bits value is returned.
+ * @note This function is expected to be used in a 8 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData8
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)READ_REG(CRCx->DR);
+}
+
+/**
+ * @brief Return current CRC calculation result. 7 bits value is returned.
+ * @note This function is expected to be used in a 7 bits CRC polynomial size context.
+ * @rmtoll DR DR LL_CRC_ReadData7
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
+ */
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+{
+ return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
+}
+
+/**
+ * @brief Return data stored in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Read_IDR
+ * @param CRCx CRC Instance
+ * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+ */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+ * @brief Store data in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Write_IDR
+ * @param CRCx CRC Instance
+ * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dac.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,354 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dac.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief DAC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_dac.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC1) || defined (DAC2)
+
+/** @addtogroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+ * @{
+ */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ )
+#else
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F301x8) || defined(STM32F318xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+
+#elif defined(STM32F334x8)
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG2) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG3) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+#endif
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
+ ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
+ )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
+ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected DAC instance
+ * to their default reset values.
+ * @param DACx DAC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+ if(DACx == DAC1)
+ {
+ /* Force reset of DAC clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+ /* Release reset of DAC clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+ }
+#if defined(DAC2)
+ else
+ {
+ /* Force reset of DAC clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2);
+
+ /* Release reset of DAC clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2);
+ }
+#endif
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of DAC instance.
+ * @note The setting of these parameters by function @ref LL_DAC_Init()
+ * is conditioned to DAC state:
+ * DAC instance must be disabled.
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are initialized
+ * - ERROR: DAC registers are not initialized
+ */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+ assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+ assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+ assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* DAC instance must be disabled. */
+ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+ {
+ /* Configuration of DAC channel: */
+ /* - TriggerSource */
+ /* - WaveAutoGeneration */
+ /* - OutputBuffer */
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_MAMP1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | DAC_InitStruct->WaveAutoGeneration
+ | DAC_InitStruct->WaveAutoGenerationConfig
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | LL_DAC_WAVE_AUTO_GENERATION_NONE
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: DAC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+ * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ /* Set DAC_InitStruct fields to default values */
+ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
+ DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+ /* Note: Parameter discarded if wave auto generation is disabled, */
+ /* set anyway to its default value. */
+ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+ DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 || DAC2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dac.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1528 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dac.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of DAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_DAC_H
+#define __STM32F3xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC1) || defined (DAC2)
+
+/** @defgroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
+/* - channel bits position into register CR */
+/* - channel bits position into register SWTRIG */
+/* - channel register offset of data holding register DHRx */
+/* - channel register offset of data output register DORx */
+#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+#else
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+#else
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* DAC registers bits positions */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+*/
+#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of DAC instance.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled, this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+ * @brief Flags defines which can be used with LL_DAC_ReadReg function
+ * @{
+ */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+ * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
+ * @{
+ */
+#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+ * @{
+ */
+#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+ * @{
+ */
+#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F303x8) || defined(STM32F328xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F301x8) || defined(STM32F318xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F373xC) || defined(STM32F378xx)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#elif defined(STM32F334x8)
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */
+#define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+ * @{
+ */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+ * @{
+ */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+ * @{
+ */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+ * @{
+ */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+
+#if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2)
+#define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */
+#define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */
+#endif
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
+ * @{
+ */
+#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
+ * @{
+ */
+/* List of DAC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
+ * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time. */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm min, 50pF max */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSETTLING"). */
+/* Unit: us */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get DAC channel number in decimal format
+ * from literals LL_DAC_CHANNEL_x.
+ * Example:
+ * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+ * will return decimal number "1".
+ * @note The input can be a value from functions where a channel
+ * number is returned.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval 1...2 (value "2" depending on DAC channel 2 availability)
+ */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+ * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+ * from number in decimal format.
+ * Example:
+ * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+ * will return a data equivalent to "LL_DAC_CHANNEL_1".
+ * @note If the input parameter does not correspond to a DAC channel,
+ * this macro returns value '0'.
+ * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ */
+#if defined(DAC_CHANNEL2_SUPPORT)
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ (((__DECIMAL_NB__) == 2U) \
+ ? ( \
+ LL_DAC_CHANNEL_2 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ ) \
+ )
+#else
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ )
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Helper macro to define the DAC conversion data full-scale digital
+ * value corresponding to the selected DAC resolution.
+ * @note DAC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+ * @brief Helper macro to calculate the DAC conversion data (unit: digital
+ * value) corresponding to a voltage (unit: mVolt).
+ * @note This helper macro is intended to provide input data in voltage
+ * rather than digital value,
+ * to be used with LL DAC functions such as
+ * @ref LL_DAC_ConvertData12RightAligned().
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+ * (unit: mVolt).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval DAC conversion data (unit: digital value)
+ */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+ __DAC_VOLTAGE__,\
+ __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+ * @{
+ */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+ * @{
+ */
+
+/**
+ * @brief Set the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note To set conversion trigger source, DAC channel must be disabled.
+ * Otherwise, the setting is discarded.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
+ * CR TSEL2 LL_DAC_SetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ *
+ * (1) On STM32F3, parameter not available on all devices
+ * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
+ * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
+ * CR TSEL2 LL_DAC_GetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2)
+ * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3)
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ *
+ * (1) On STM32F3, parameter not available on all devices
+ * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n
+ * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device).
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_SetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param WaveAutoGeneration This parameter can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_GetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param NoiseLFSRMask This parameter can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param TriangleAmplitude This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output buffer for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
+ * CR BOFF2 LL_DAC_SetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
+ *
+ * (1) Feature specific to STM32F303x6/8 and STM32F328:
+ * On DAC1 channel 2, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA5.
+ * On DAC2 channel 1, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA6.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output buffer state for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
+ * CR BOFF2 LL_DAC_GetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1)
+ * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1)
+ *
+ * (1) Feature specific to STM32F303x6/8 and STM32F328:
+ * On DAC1 channel 2, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA5.
+ * On DAC2 channel 1, output buffer is replaced by a switch
+ * to connect DAC channel output to pin PA6.
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
+ * CR DMAEN2 LL_DAC_EnableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
+ * CR DMAEN2 LL_DAC_DisableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA transfer request state of the selected channel.
+ * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+ * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
+ * CR DMAEN2 LL_DAC_IsDMAReqEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Function to help to configure DMA transfer to DAC: retrieve the
+ * DAC register address from DAC instance and a list of DAC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These DAC registers are data holding registers:
+ * when DAC conversion is requested, DAC generates a DMA transfer
+ * request to have data available in DAC data holding registers.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * (uint32_t)&< array or variable >,
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+ * @retval DAC register address
+ */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+ /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
+ /* DAC channel selected. */
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+ * @{
+ */
+
+/**
+ * @brief Enable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Enable\n
+ * CR EN2 LL_DAC_Enable
+ * @note After enable from off state, DAC channel requires a delay
+ * for output voltage to reach accuracy +/- 1 LSB.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Disable\n
+ * CR EN2 LL_DAC_Disable
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC enable state of the selected channel.
+ * (0: DAC channel is disabled, 1: DAC channel is enabled)
+ * @rmtoll CR EN1 LL_DAC_IsEnabled\n
+ * CR EN2 LL_DAC_IsEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Enable DAC trigger of the selected channel.
+ * @note - If DAC trigger is disabled, DAC conversion is performed
+ * automatically once the data holding register is updated,
+ * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...
+ * - If DAC trigger is enabled, DAC conversion is performed
+ * only when a hardware of software trigger event is occurring.
+ * Select trigger source using
+ * function @ref LL_DAC_SetTriggerSource().
+ * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
+ * CR TEN2 LL_DAC_EnableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC trigger of the selected channel.
+ * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
+ * CR TEN2 LL_DAC_DisableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC trigger state of the selected channel.
+ * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+ * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
+ * CR TEN2 LL_DAC_IsTriggerEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Trig DAC conversion by software for the selected DAC channel.
+ * @note Preliminarily, DAC trigger must be set to software trigger
+ * using function @ref LL_DAC_SetTriggerSource()
+ * with parameter "LL_DAC_TRIGGER_SOFTWARE".
+ * and DAC trigger must be enabled using
+ * function @ref LL_DAC_EnableTrigger().
+ * @note For devices featuring DAC with 2 channels: this function
+ * can perform a SW start of both DAC channels simultaneously.
+ * Two channels can be selected as parameter.
+ * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+ * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
+ * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can a combination of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->SWTRIGR,
+ (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
+ * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12R1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for the selected DAC channel.
+ * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
+ * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12L1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
+ * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR8R1_DACC1DHR,
+ Data);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
+ * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR12RD,
+ (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for both DAC channels.
+ * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
+ * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
+ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
+ /* the 4 LSB must be taken into account for the shift value. */
+ MODIFY_REG(DACx->DHR12LD,
+ (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+ ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
+ * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR8RD,
+ (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+#endif /* DAC_CHANNEL2_SUPPORT */
+/**
+ * @brief Retrieve output data currently generated for the selected DAC channel.
+ * @note Whatever alignment and resolution settings
+ * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...),
+ * output data format is 12 bits right aligned (LSB aligned on bit 0).
+ * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
+ * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2 (1)
+ *
+ * (1) On this STM32 serie, parameter not available on all devices.
+ * Refer to device datasheet for channels availability.
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+
+ return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+/**
+ * @brief Get DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Clear DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Clear DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+
+#if defined(DAC_CHANNEL2_SUPPORT)
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CHANNEL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC1 || DAC2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,354 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dma.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_dma.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
+
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#endif
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+ /* Reset DMAx_Channely memory address register */
+ LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = (uint32_t)0x00000000U;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_dma.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2033 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_dma.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_DMA_H
+#define __STM32F3xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+ * @{
+ */
+/* Define used to get CSELR register offset */
+#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7 ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
+#endif
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined (DMA2)
+#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
+ DMA2_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t Direction)
+{
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+ SrcAddress);
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+ DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+ SrcAddress);
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+ DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+ MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+ PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
+ DMA_CMAR_MA));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
+ DMA_CPAR_PA));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
+ MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
+ MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
+ DMA_CPAR_PA));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
+ DMA_CMAR_MA));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_exti.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,319 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_exti.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+#if defined(EXTI_32_63_SUPPORT)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#endif
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR, 0x1F800000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER, 0x00000000U);
+ /* Pending register set to default reset values */
+ LL_EXTI_WriteReg(PR, 0x007FFFFFU);
+
+#if defined(EXTI_32_63_SUPPORT)
+ /* Interrupt mask register 2 set to default reset values */
+#if defined(STM32F334x8)
+ LL_EXTI_WriteReg(IMR2, 0xFFFFFFFEU);
+#else
+ LL_EXTI_WriteReg(IMR2, 0xFFFFFFFCU);
+#endif
+ /* Event mask register 2 set to default reset values */
+ LL_EXTI_WriteReg(EMR2, 0x00000000U);
+ /* Rising Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(RTSR2, 0x00000000U);
+ /* Falling Trigger selection register 2 set to default reset values */
+ LL_EXTI_WriteReg(FTSR2, 0x00000000U);
+ /* Software interrupt event register 2 set to default reset values */
+ LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+ /* Pending register 2 set to default reset values */
+ LL_EXTI_WriteReg(PR2, 0x00000003U);
+
+#endif
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+#if defined(EXTI_32_63_SUPPORT)
+ assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+#endif
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+#if defined(EXTI_32_63_SUPPORT)
+ /* Configure EXTI Lines in range from 32 to 63 */
+ if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+#endif
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+#if defined(EXTI_32_63_SUPPORT)
+ /* De-configure EXTI Lines in range from 32 to 63 */
+ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+#endif
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+#if defined(EXTI_32_63_SUPPORT)
+ EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
+#endif
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_exti.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1398 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_exti.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_EXTI_H
+#define __STM32F3xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+#if defined(EXTI_32_63_SUPPORT)
+
+ uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+#endif
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
+#endif
+#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
+
+#if defined(EXTI_32_63_SUPPORT)
+#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
+#if defined(EXTI_IMR2_IM33)
+#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
+#endif
+#if defined(EXTI_IMR2_IM34)
+#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
+#endif
+#if defined(EXTI_IMR2_IM35)
+#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
+#endif
+#if defined(EXTI_IMR2_IM36)
+#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
+#endif
+#if defined(EXTI_IMR2_IM37)
+#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
+#endif
+#if defined(EXTI_IMR2_IM38)
+#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
+#endif
+#if defined(EXTI_IMR2_IM39)
+#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
+#endif
+#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
+
+#endif
+
+#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR, ExtiLine);
+}
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
+ * @note The reset value for the direct lines (lines from 32 to 34, line
+ * 39) is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_23
+ * @arg @ref LL_EXTI_LINE_24
+ * @arg @ref LL_EXTI_LINE_25
+ * @arg @ref LL_EXTI_LINE_26
+ * @arg @ref LL_EXTI_LINE_27
+ * @arg @ref LL_EXTI_LINE_28
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
+ * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_32
+ * @arg @ref LL_EXTI_LINE_33
+ * @arg @ref LL_EXTI_LINE_34
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @arg @ref LL_EXTI_LINE_39
+ * @arg @ref LL_EXTI_LINE_ALL_32_63
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR2, ExtiLine);
+}
+#endif
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
+ * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 32 to 63
+ * @note If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER2, ExtiLine);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));
+}
+#endif
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
+}
+#endif
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_20
+ * @arg @ref LL_EXTI_LINE_21
+ * @arg @ref LL_EXTI_LINE_22
+ * @arg @ref LL_EXTI_LINE_29
+ * @arg @ref LL_EXTI_LINE_30
+ * @arg @ref LL_EXTI_LINE_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+#if defined(EXTI_32_63_SUPPORT)
+/**
+ * @brief Clear ExtLine Flags for Lines in range 32 to 63
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_35
+ * @arg @ref LL_EXTI_LINE_36
+ * @arg @ref LL_EXTI_LINE_37
+ * @arg @ref LL_EXTI_LINE_38
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR2, ExtiLine);
+}
+#endif
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,49 +2,49 @@
******************************************************************************
* @file stm32f3xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 12-Sept-2014
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief FMC Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the Flexible Memory Controller (FMC) peripheral memories:
* + Initialization/de-initialization functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
- ==============================================================================
+ =============================================================================
##### FMC peripheral features #####
- ==============================================================================
- [..] The Flexible memory controller (FMC) includes three memory controllers:
- (+) The NOR/PSRAM memory controller
- (+) The NAND/PC Card memory controller
-
- [..] The FMC functional block makes the interface with synchronous and asynchronous static
- memories, and 16-bit PC memory cards. Its main purposes are:
- (+) to translate AHB transactions into the appropriate external device protocol
- (+) to meet the access time requirements of the external memory devices
-
- [..] All external memories share the addresses, data and control signals with the controller.
- Each external device is accessed by means of a unique Chip Select. The FMC performs
- only one access at a time to an external device.
- The main features of the FMC controller are the following:
- (+) Interface with static-memory mapped devices including:
- (++) Static random access memory (SRAM)
- (++) Read-only memory (ROM)
- (++) NOR Flash memory/OneNAND Flash memory
- (++) PSRAM (4 memory banks)
- (++) 16-bit PC Card compatible devices
- (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
+ =============================================================================
+ [..] The Flexible memory controller (FMC) includes following memory controllers:
+ (+) The NOR/PSRAM memory controller
+ (+) The PC Card memory controller
+ (+) The NAND memory controller
+
+ [..] The FMC functional block makes the interface with synchronous and asynchronous static
+ memories and 16-bit PC memory cards. Its main purposes are:
+ (+) to translate AHB transactions into the appropriate external device protocol.
+ (+) to meet the access time requirements of the external memory devices.
+
+ [..] All external memories share the addresses, data and control signals with the controller.
+ Each external device is accessed by means of a unique Chip Select. The FMC performs
+ only one access at a time to an external device.
+ The main features of the FMC controller are the following:
+ (+) Interface with static-memory mapped devices including:
+ (++) Static random access memory (SRAM).
+ (++) NOR Flash memory.
+ (++) PSRAM (4 memory banks).
+ (++) 16-bit PC Card compatible devices
+ (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
data
- (+) Independent Chip Select control for each memory bank
- (+) Independent configuration for each memory bank
-
+ (+) Independent Chip Select control for each memory bank
+ (+) Independent configuration for each memory bank
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -69,7 +69,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -78,79 +78,138 @@
* @{
*/
-/** @defgroup FMC
+#if defined(FMC_BANK1)
+
+#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+
+/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
* @{
*/
-#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
-
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FMC_Private_Functions
+/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
* @{
*/
-/** @defgroup FMC_NORSRAM Controller functions
- * @brief NORSRAM Controller functions
+/* ----------------------- FMC registers bit mask --------------------------- */
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN | \
+ FMC_PCRx_PTYP | FMC_PCRx_PWID | \
+ FMC_PCRx_ECCEN | FMC_PCRx_TCLR | \
+ FMC_PCRx_TAR | FMC_PCRx_ECCPS))
+
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEMx_MEMSETx | FMC_PMEMx_MEMWAITx |\
+ FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATTx_ATTSETx | FMC_PATTx_ATTWAITx |\
+ FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
+
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+#define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
+ FMC_BCRx_MTYP | FMC_BCRx_MWID |\
+ FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
+ FMC_BCRx_WAITPOL | FMC_BCRx_WRAPMOD |\
+ FMC_BCRx_WAITCFG | FMC_BCRx_WREN |\
+ FMC_BCRx_WAITEN | FMC_BCRx_EXTMOD |\
+ FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW |\
+ FMC_BCR1_CCLKEN))
+
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
+ FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
+ FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
+ FMC_BTRx_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
+ FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
+ FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
+ * @brief NORSRAM Controller functions
*
- @verbatim
- ==============================================================================
+ @verbatim
+ ==============================================================================
##### How to use NORSRAM device driver #####
==============================================================================
-
- [..]
+
+ [..]
This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
to run the NORSRAM external devices.
-
- (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
+
+ (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
(+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
(+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
- (+) FMC NORSRAM bank extended timing configuration using the function
+ (+) FMC NORSRAM bank extended timing configuration using the function
FMC_NORSRAM_Extended_Timing_Init()
(+) FMC NORSRAM bank enable/disable write operation using the functions
FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
-
+
@endverbatim
* @{
*/
-
-/** @defgroup FMC_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+
+/** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
*
- @verbatim
+ @verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
(+) Initialize and configure the FMC NORSRAM interface
- (+) De-initialize the FMC NORSRAM interface
- (+) Configure the FMC clock and associated GPIOs
-
+ (+) De-initialize the FMC NORSRAM interface
+ (+) Configure the FMC clock and associated GPIOs
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initialize the FMC_NORSRAM device according to the specified
* control parameters in the FMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
-{
- uint32_t tmpr = 0;
-
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
@@ -166,48 +225,66 @@
assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
-
+ assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
+
+ /* Disable NORSRAM Device */
+ __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
+
/* Set NORSRAM device control parameters */
- tmpr = (uint32_t)(Init->DataAddressMux |\
- Init->MemoryType |\
- Init->MemoryDataWidth |\
- Init->BurstAccessMode |\
- Init->WaitSignalPolarity |\
- Init->WrapMode |\
- Init->WaitSignalActive |\
- Init->WriteOperation |\
- Init->WaitSignal |\
- Init->ExtendedMode |\
- Init->AsynchronousWait |\
- Init->WriteBurst |\
- Init->ContinuousClock
- );
-
- if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
+ if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
{
- tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
+ | Init->DataAddressMux
+ | Init->MemoryType
+ | Init->MemoryDataWidth
+ | Init->BurstAccessMode
+ | Init->WaitSignalPolarity
+ | Init->WrapMode
+ | Init->WaitSignalActive
+ | Init->WriteOperation
+ | Init->WaitSignal
+ | Init->ExtendedMode
+ | Init->AsynchronousWait
+ | Init->WriteBurst
+ | Init->ContinuousClock
+ )
+ );
}
-
- Device->BTCR[Init->NSBank] = tmpr;
+ else
+ {
+ MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
+ | Init->DataAddressMux
+ | Init->MemoryType
+ | Init->MemoryDataWidth
+ | Init->BurstAccessMode
+ | Init->WaitSignalPolarity
+ | Init->WrapMode
+ | Init->WaitSignalActive
+ | Init->WriteOperation
+ | Init->WaitSignal
+ | Init->ExtendedMode
+ | Init->AsynchronousWait
+ | Init->WriteBurst
+ | Init->ContinuousClock
+ )
+ );
+ }
/* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
- if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
- {
- Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
- Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
- Init->ContinuousClock);
- }
-
+ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
+ {
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
+ }
+
return HAL_OK;
}
/**
- * @brief DeInitialize the FMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
+ * @brief DeInitialize the FMC_NORSRAM peripheral
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -216,25 +293,25 @@
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
+
/* Disable the FMC_NORSRAM device */
__FMC_NORSRAM_DISABLE(Device, Bank);
-
+
/* De-initialize the FMC_NORSRAM device */
/* FMC_NORSRAM_BANK1 */
- if(Bank == FMC_NORSRAM_BANK1)
+ if (Bank == FMC_NORSRAM_BANK1)
{
- Device->BTCR[Bank] = 0x000030DB;
+ Device->BTCR[Bank] = 0x000030DB;
}
/* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
else
- {
- Device->BTCR[Bank] = 0x000030D2;
+ {
+ Device->BTCR[Bank] = 0x000030D2;
}
-
+
Device->BTCR[Bank + 1] = 0x0FFFFFFF;
ExDevice->BWTR[Bank] = 0x0FFFFFFF;
-
+
return HAL_OK;
}
@@ -242,15 +319,15 @@
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr = 0;
-
+
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
@@ -261,86 +338,86 @@
assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- /* Set FMC_NORSRAM device timing parameters */
- tmpr = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode)
- );
-
- Device->BTCR[Bank + 1] = tmpr;
-
+
+ /* Set FMC_NORSRAM device timing parameters */
+ MODIFY_REG(Device->BTCR[Bank + 1], \
+ BTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BTRx_ADDHLD)) | \
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BTRx_DATAST)) | \
+ ((Timing->BusTurnAroundDuration) << POSITION_VAL(FMC_BTRx_BUSTURN)) | \
+ (((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV)) | \
+ (((Timing->DataLatency) - 2) << POSITION_VAL(FMC_BTRx_DATLAT)) | \
+ (Timing->AccessMode)));
+
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
- if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
+ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
{
- tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
- tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
- Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
- }
-
- return HAL_OK;
+ tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
+ tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
+ MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
+ }
+
+ return HAL_OK;
}
/**
* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
+ * @param ExtendedMode FMC Extended Mode
+ * This parameter can be one of the following values:
+ * @arg FMC_EXTENDED_MODE_DISABLE
+ * @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{
+{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
-
+
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
- if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
+ if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
{
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
- assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
- Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
- ((Timing->AddressHoldTime) << 4) |\
- ((Timing->DataSetupTime) << 8) |\
- ((Timing->BusTurnAroundDuration) << 16) |\
- (((Timing->CLKDivision)-1) << 20) |\
- (((Timing->DataLatency)-2) << 24) |\
- (Timing->AccessMode));
+ assert_param(IS_FMC_NORSRAM_BANK(Bank));
+
+ /* Set NORSRAM device timing register for write configuration, if extended mode is used */
+ MODIFY_REG(Device->BWTR[Bank], \
+ BWTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
+ ((Timing->DataSetupTime) << POSITION_VAL(FMC_BWTRx_DATAST)) | \
+ (Timing->AccessMode)));
}
- else
+ else
{
Device->BWTR[Bank] = 0x0FFFFFFF;
- }
-
- return HAL_OK;
+ }
+
+ return HAL_OK;
}
/**
* @}
*/
-
-
-/** @defgroup FMC_NORSRAM_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
+
+
+/** @defgroup FMC_NORSRAM_Group2 Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FMC NORSRAM interface.
@@ -348,11 +425,11 @@
@endverbatim
* @{
*/
-
+
/**
* @brief Enables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -360,29 +437,29 @@
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
+
/* Enable write operation */
- Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
+ SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
-{
+{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
assert_param(IS_FMC_NORSRAM_BANK(Bank));
-
+
/* Disable write operation */
- Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
+ CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -392,60 +469,57 @@
/**
* @}
*/
-
-/** @defgroup FMC_NAND Controller functions
- * @brief NAND Controller functions
+/** @defgroup FMC_NAND FMC NAND Controller functions
+ * @brief NAND Controller functions
*
- @verbatim
+ @verbatim
==============================================================================
##### How to use NAND device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FMC NAND banks in order
to run the NAND external devices.
-
- (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
+
+ (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
(+) FMC NAND bank control configuration using the function FMC_NAND_Init()
- (+) FMC NAND bank common space timing configuration using the function
+ (+) FMC NAND bank common space timing configuration using the function
FMC_NAND_CommonSpace_Timing_Init()
- (+) FMC NAND bank attribute space timing configuration using the function
+ (+) FMC NAND bank attribute space timing configuration using the function
FMC_NAND_AttributeSpace_Timing_Init()
(+) FMC NAND bank enable/disable ECC correction feature using the functions
FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
- (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
+ (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
@endverbatim
* @{
*/
-
+
/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
(+) Initialize and configure the FMC NAND interface
- (+) De-initialize the FMC NAND interface
+ (+) De-initialize the FMC NAND interface
(+) Configure the FMC clock and associated GPIOs
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
{
- uint32_t tmppcr = 0;
-
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Init->NandBank));
@@ -454,29 +528,32 @@
assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
/* Set NAND device control parameters */
- tmppcr = (uint32_t)(Init->Waitfeature |\
- FMC_PCR_MEMORY_TYPE_NAND |\
- Init->MemoryDataWidth |\
- Init->EccComputation |\
- Init->ECCPageSize |\
- ((Init->TCLRSetupTime) << 9) |\
- ((Init->TARSetupTime) << 13)
- );
-
- if(Init->NandBank == FMC_NAND_BANK2)
+ if (Init->NandBank == FMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PCR2 = tmppcr;
+ MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
}
else
{
/* NAND bank 3 registers configuration */
- Device->PCR3 = tmppcr;
+ MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
+ ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
}
-
+
return HAL_OK;
}
@@ -484,15 +561,52 @@
/**
* @brief Initializes the FMC_NAND Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
- uint32_t tmppmem = 0;
-
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
+ assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
+ assert_param(IS_FMC_NAND_BANK(Bank));
+
+ /* Set FMC_NAND device timing parameters */
+ if (Bank == FMC_NAND_BANK2)
+ {
+ /* NAND bank 2 registers configuration */
+ MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+ else
+ {
+ /* NAND bank 3 registers configuration */
+ MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
+ * parameters in the FMC_NAND_PCC_TimingTypeDef
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
@@ -500,295 +614,259 @@
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FMC_NAND_BANK(Bank));
-
+
/* Set FMC_NAND device timing parameters */
- tmppmem = (uint32_t)(Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- ((Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
- if(Bank == FMC_NAND_BANK2)
+ if (Bank == FMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- Device->PMEM2 = tmppmem;
+ MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
}
else
{
/* NAND bank 3 registers configuration */
- Device->PMEM3 = tmppmem;
- }
-
- return HAL_OK;
-}
+ MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+ }
-/**
- * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
- * parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
- * @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
-{
- uint32_t tmppatt = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
- assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
- assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
- assert_param(IS_FMC_NAND_BANK(Bank));
-
- /* Set FMC_NAND device timing parameters */
- tmppatt = (uint32_t)(Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- ((Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
- if(Bank == FMC_NAND_BANK2)
- {
- /* NAND bank 2 registers configuration */
- Device->PATT2 = tmppatt;
- }
- else
- {
- /* NAND bank 3 registers configuration */
- Device->PATT3 = tmppatt;
- }
-
return HAL_OK;
}
/**
- * @brief DeInitializes the FMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @brief DeInitialize the FMC_NAND device
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Bank));
-
+
/* Disable the NAND Bank */
__FMC_NAND_DISABLE(Device, Bank);
-
+
/* De-initialize the NAND Bank */
- if(Bank == FMC_NAND_BANK2)
+ if (Bank == FMC_NAND_BANK2)
{
/* Set the FMC_NAND_BANK2 registers to their reset values */
- Device->PCR2 = 0x00000018;
- Device->SR2 = 0x00000040;
- Device->PMEM2 = 0xFCFCFCFC;
- Device->PATT2 = 0xFCFCFCFC;
+ WRITE_REG(Device->PCR2, 0x00000018);
+ WRITE_REG(Device->SR2, 0x00000040);
+ WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT2, 0xFCFCFCFC);
}
- /* FMC_Bank3_NAND */
+ /* FMC_Bank3_NAND */
else
{
/* Set the FMC_NAND_BANK3 registers to their reset values */
- Device->PCR3 = 0x00000018;
- Device->SR3 = 0x00000040;
- Device->PMEM3 = 0xFCFCFCFC;
- Device->PATT3 = 0xFCFCFCFC;
+ WRITE_REG(Device->PCR3, 0x00000018);
+ WRITE_REG(Device->SR3, 0x00000040);
+ WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT3, 0xFCFCFCFC);
}
-
+
return HAL_OK;
}
/**
* @}
*/
-
-
-/** @defgroup FMC_NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
+
+
+/** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
==============================================================================
##### FMC_NAND Control functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FMC NAND interface.
@endverbatim
* @{
- */
+ */
-
+
/**
* @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
- */
+ */
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Bank));
-
+
/* Enable ECC feature */
- if(Bank == FMC_NAND_BANK2)
+ if (Bank == FMC_NAND_BANK2)
{
- Device->PCR2 |= FMC_PCR2_ECCEN;
+ SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
}
else
{
- Device->PCR3 |= FMC_PCR3_ECCEN;
- }
-
- return HAL_OK;
+ SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
+
+ return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
- */
-HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
-{
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
+ */
+HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Bank));
-
+
/* Disable ECC feature */
- if(Bank == FMC_NAND_BANK2)
+ if (Bank == FMC_NAND_BANK2)
{
- Device->PCR2 &= ~FMC_PCR2_ECCEN;
+ CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
}
else
{
- Device->PCR3 &= ~FMC_PCR3_ECCEN;
- }
+ CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
+ }
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
{
- uint32_t timeout = 0;
+ uint32_t tickstart = 0;
- /* Check the parameters */
- assert_param(IS_FMC_NAND_DEVICE(Device));
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_DEVICE(Device));
assert_param(IS_FMC_NAND_BANK(Bank));
-
- timeout = HAL_GetTick() + Timeout;
-
- /* Wait untill FIFO is empty */
- while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until FIFO is empty */
+ while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
- }
+ }
}
-
- if(Bank == FMC_NAND_BANK2)
- {
+
+ if (Bank == FMC_NAND_BANK2)
+ {
/* Get the ECCR2 register value */
*ECCval = (uint32_t)Device->ECCR2;
}
else
- {
+ {
/* Get the ECCR3 register value */
*ECCval = (uint32_t)Device->ECCR3;
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @}
*/
-
+
/**
* @}
*/
-
-/** @defgroup FMC_PCCARD Controller functions
- * @brief PCCARD Controller functions
+
+/** @defgroup FMC_PCCARD FMC PCCARD Controller functions
+ * @brief PCCARD Controller functions
*
- @verbatim
- ==============================================================================
+ @verbatim
+ ==============================================================================
##### How to use PCCARD device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FMC PCCARD bank in order
to run the PCCARD/compact flash external devices.
-
- (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
+
+ (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
(+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
- (+) FMC PCCARD bank common space timing configuration using the function
+ (+) FMC PCCARD bank common space timing configuration using the function
FMC_PCCARD_CommonSpace_Timing_Init()
- (+) FMC PCCARD bank attribute space timing configuration using the function
+ (+) FMC PCCARD bank attribute space timing configuration using the function
FMC_PCCARD_AttributeSpace_Timing_Init()
- (+) FMC PCCARD bank IO space timing configuration using the function
+ (+) FMC PCCARD bank IO space timing configuration using the function
FMC_PCCARD_IOSpace_Timing_Init()
-
+
@endverbatim
* @{
*/
-
+
/** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
(+) Initialize and configure the FMC PCCARD interface
- (+) De-initialize the FMC PCCARD interface
+ (+) De-initialize the FMC PCCARD interface
(+) Configure the FMC clock and associated GPIOs
-
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the FMC_PCCARD device according to the specified
* control parameters in the FMC_PCCARD_HandleTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Init: Pointer to PCCARD Initialization structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
-
+ assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
+
/* Set FMC_PCCARD device control parameters */
- Device->PCR4 = (uint32_t)(Init->Waitfeature |\
- FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
- (Init->TCLRSetupTime << 9) |\
- (Init->TARSetupTime << 13));
-
+ MODIFY_REG(Device->PCR4,
+ (FMC_PCRx_PTYP | FMC_PCRx_PWAITEN | FMC_PCRx_PWID |
+ FMC_PCRx_TCLR | FMC_PCRx_TAR),
+ (FMC_PCR_MEMORY_TYPE_PCCARD |
+ Init->Waitfeature |
+ FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
+ (Init->TCLRSetupTime << POSITION_VAL(FMC_PCRx_TCLR)) |
+ (Init->TARSetupTime << POSITION_VAL(FMC_PCRx_TAR))));
+
return HAL_OK;
}
@@ -796,8 +874,8 @@
/**
* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
@@ -810,51 +888,51 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
- Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
+ MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
+ (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx)) |
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx)) |
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
{
- /* Check the parameters */
- assert_param(IS_FMC_PCCARD_DEVICE(Device));
+ /* Check the parameters */
+ assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
- Device->PATT4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
+ MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx)) | \
+ ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx)) | \
+ ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
+
return HAL_OK;
}
/**
* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
@@ -862,35 +940,35 @@
assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FMC_PCCARD device timing parameters */
- Device->PIO4 = (uint32_t)((Timing->SetupTime |\
- ((Timing->WaitSetupTime) << 8) |\
- (Timing->HoldSetupTime) << 16) |\
- ((Timing->HiZSetupTime) << 24)
- );
-
+ MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ (Timing->WaitSetupTime << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
+ (Timing->HoldSetupTime << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
+ (Timing->HiZSetupTime << POSITION_VAL(FMC_PIO4_IOHIZ4))));
+
return HAL_OK;
}
-
+
/**
- * @brief DeInitializes the FMC_PCCARD device
- * @param Device: Pointer to PCCARD device instance
+ * @brief DeInitialize the FMC_PCCARD device
+ * @param Device Pointer to PCCARD device instance
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
{
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_FMC_PCCARD_DEVICE(Device));
-
+
/* Disable the FMC_PCCARD device */
__FMC_PCCARD_DISABLE(Device);
-
+
/* De-initialize the FMC_PCCARD device */
- Device->PCR4 = 0x00000018;
- Device->SR4 = 0x00000000;
- Device->PMEM4 = 0xFCFCFCFC;
- Device->PATT4 = 0xFCFCFCFC;
- Device->PIO4 = 0xFCFCFCFC;
-
+ WRITE_REG(Device->PCR4, 0x00000018);
+ WRITE_REG(Device->SR4, 0x00000040);
+ WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
+ WRITE_REG(Device->PATT4, 0xFCFCFCFC);
+ WRITE_REG(Device->PIO4, 0xFCFCFCFC);
+
return HAL_OK;
}
@@ -905,14 +983,15 @@
/**
* @}
*/
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
-
-#endif /* HAL_FMC_MODULE_ENABLED */
/**
* @}
*/
+#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
+
+#endif /* FMC_BANK1 */
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_fmc.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f3xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 12-Sept-2014
+ * @version V1.4.0
+ * @date 16-December-2016
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,18 +33,16 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_FMC_H
#define __STM32F3xx_LL_FMC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
@@ -52,112 +50,323 @@
* @{
*/
-/** @addtogroup FMC
+#if defined(FMC_BANK1)
+
+/** @addtogroup FMC_LL
+ * @{
+ */
+
+/** @addtogroup FMC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
+
+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+
+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+
+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+
+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
+
+#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
+ ((__BANK__) == FMC_NAND_BANK3))
+
+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
+
+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Setup_Time FMC_Setup_Time
+ * @{
+ */
+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
* @{
- */
+ */
+
+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
+ * @{
+ */
+
+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
+ * @{
+ */
+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance
+ * @{
+ */
+#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FMC_WRAP_MODE_ENABLE))
+
+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
-/* Exported typedef ----------------------------------------------------------*/
+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
+
+/** @defgroup FMC_Data_Latency FMC Data Latency
+ * @{
+ */
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
+ * @{
+ */
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
+ * @{
+ */
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
+ * @{
+ */
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+
+/** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
+ * @{
+ */
+
#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
-#define FMC_NORSRAM_DEVICE FMC_Bank1
-#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
-#define FMC_NAND_DEVICE FMC_Bank2_3
-#define FMC_PCCARD_DEVICE FMC_Bank4
+#define FMC_NORSRAM_DEVICE FMC_Bank1
+#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
+#define FMC_NAND_DEVICE FMC_Bank2_3
+#define FMC_PCCARD_DEVICE FMC_Bank4
-/**
- * @brief FMC_NORSRAM Configuration Structure definition
- */
+/**
+ * @brief FMC_NORSRAM Configuration Structure definition
+ */
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
+ This parameter can be a value of @ref FMC_NORSRAM_Bank */
+
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
+ multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
+
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FMC_Memory_Type */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
+
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
+
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
+
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FMC_Wrap_Mode */
-
+
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
+ valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
+
+ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
-
+
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
+ signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
-
+
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
-
+
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
-
+
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
+ This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
+ This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
}FMC_NORSRAM_InitTypeDef;
-/**
- * @brief FMC_NORSRAM Timing parameters structure definition
+/**
+ * @brief FMC_NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
+ the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
+ This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
-
+
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
+ @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
-
+
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
+
+ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
+ @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
-
+
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
@@ -165,44 +374,44 @@
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
+
+ uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
}FMC_NORSRAM_TimingTypeDef;
-/**
- * @brief FMC_NAND Configuration Structure definition
- */
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
+ This parameter can be a value of @ref FMC_NAND_Bank */
+
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
-
+
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
-
+
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
-
+
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_NAND_InitTypeDef;
+
+}FMC_NAND_InitTypeDef;
-/**
- * @brief FMC_NAND_PCCARD Timing parameters structure definition
+/**
+ * @brief FMC_NAND_PCC Timing parameters structure definition
*/
typedef struct
{
@@ -211,53 +420,61 @@
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
+ memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
+
}FMC_NAND_PCC_TimingTypeDef;
-/**
- * @brief FMC_NAND Configuration Structure definition
- */
+/**
+ * @brief FMC_NAND Configuration Structure definition
+ */
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
-
+
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
+
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FMC_PCCARD_InitTypeDef;
+
+}FMC_PCCARD_InitTypeDef;
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup FMC_NOR_SRAM_Controller
+/** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
* @{
- */
-
-/** @defgroup FMC_NORSRAM_Bank
+ */
+
+/** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
+ * @{
+ */
+
+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
@@ -265,688 +482,598 @@
#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
- ((BANK) == FMC_NORSRAM_BANK2) || \
- ((BANK) == FMC_NORSRAM_BANK3) || \
- ((BANK) == FMC_NORSRAM_BANK4))
/**
* @}
*/
-/** @defgroup FMC_Data_Address_Bus_Multiplexing
+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
-#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FMC_BCRx_MUXEN)
+
/**
* @}
*/
-/** @defgroup FMC_Memory_Type
+/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
-#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \
- ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((MEMORY) == FMC_MEMORY_TYPE_NOR))
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)FMC_BCRx_MTYP_0)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)FMC_BCRx_MTYP_1)
+
/**
* @}
*/
-/** @defgroup FMC_NORSRAM_Data_Width
+/** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FMC_BCRx_MWID_0)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FMC_BCRx_MWID_1)
+
/**
* @}
*/
-/** @defgroup FMC_NORSRAM_Flash_Access
+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
+
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FMC_BCRx_FACCEN)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
-/** @defgroup FMC_Burst_Access_Mode
+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
-#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
-/**
- * @}
- */
-
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FMC_BCRx_BURSTEN)
-/** @defgroup FMC_Wait_Signal_Polarity
- * @{
- */
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
-
-#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
/**
* @}
*/
-/** @defgroup FMC_Wrap_Mode
+
+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
-#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \
- ((MODE) == FMC_WRAP_MODE_ENABLE))
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FMC_BCRx_WAITPOL)
+
/**
* @}
*/
-/** @defgroup FMC_Wait_Timing
+/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)FMC_BCRx_WRAPMOD)
+
/**
* @}
*/
-/** @defgroup FMC_Write_Operation
+/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
-
-#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) || \
- ((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
-/**
- * @}
- */
-/** @defgroup FMC_Wait_Signal
- * @{
- */
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)FMC_BCRx_WAITCFG)
-#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
/**
* @}
*/
-/** @defgroup FMC_Extended_Mode
+/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)FMC_BCRx_WREN)
+
+/**
+ * @}
+ */
-#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \
- ((MODE) == FMC_EXTENDED_MODE_ENABLE))
+/** @defgroup FMC_Wait_Signal FMC Wait Signal
+ * @{
+ */
+
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)FMC_BCRx_WAITEN)
+
/**
* @}
*/
-/** @defgroup FMC_AsynchronousWait
- * @{
- */
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
-
-#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Burst
+/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
-#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) || \
- ((BURST) == FMC_WRITE_BURST_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock
- * @{
- */
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)FMC_BCRx_EXTMOD)
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Setup_Time
- * @{
- */
-#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
/**
* @}
*/
-/** @defgroup FMC_Address_Hold_Time
+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
+
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FMC_BCRx_ASYNCWAIT)
+
/**
* @}
*/
-/** @defgroup FMC_Data_Setup_Time
+/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
+
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)FMC_BCRx_CBURSTRW)
+
/**
* @}
*/
-/** @defgroup FMC_Bus_Turn_around_Duration
+/** @defgroup FMC_Continous_Clock FMC Continous Clock
* @{
*/
-#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_CLK_Division
- * @{
- */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)FMC_BCR1_CCLKEN)
/**
* @}
*/
-/** @defgroup FMC_Data_Latency
+/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
-#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
-/**
- * @}
- */
-/** @defgroup FMC_Access_Mode
- * @{
- */
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+#define FMC_ACCESS_MODE_B ((uint32_t)FMC_BTRx_ACCMOD_0)
+#define FMC_ACCESS_MODE_C ((uint32_t)FMC_BTRx_ACCMOD_1)
+#define FMC_ACCESS_MODE_D ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
-#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \
- ((MODE) == FMC_ACCESS_MODE_B) || \
- ((MODE) == FMC_ACCESS_MODE_C) || \
- ((MODE) == FMC_ACCESS_MODE_D))
/**
* @}
*/
-
-/**
- * @}
- */
-/** @defgroup FMC_NAND_Controller
- * @{
- */
-
-/** @defgroup FMC_NAND_Bank
- * @{
- */
-#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
-
-#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
- ((BANK) == FMC_NAND_BANK3))
/**
* @}
*/
-/** @defgroup FMC_Wait_feature
+/** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
* @{
*/
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_PCR_Memory_Type
+/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+
/**
* @}
*/
-/** @defgroup FMC_NAND_Data_Width
+/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FMC_PCRx_PWAITEN)
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
/**
* @}
*/
-/** @defgroup FMC_ECC
+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
- ((STATE) == FMC_NAND_ECC_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC_Page_Size
- * @{
- */
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FMC_PCRx_PTYP)
/**
* @}
*/
-/** @defgroup FMC_TCLR_Setup_Time
+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FMC_PCRx_PWID_0)
-/** @defgroup FMC_TAR_Setup_Time
- * @{
- */
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time
- * @{
- */
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
/**
* @}
*/
-/** @defgroup FMC_Wait_Setup_Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time
+/** @defgroup FMC_ECC FMC NAND ECC
* @{
*/
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)FMC_PCRx_ECCEN)
-/** @defgroup FMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Device_Instance
- * @{
- */
-#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
/**
* @}
*/
-/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Device_Instance
- * @{
- */
-#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Device_Instance
- * @{
- */
-#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FMC_PCRx_ECCPS_0)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FMC_PCRx_ECCPS_2)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
/**
* @}
- */
+ */
-/** @defgroup FMC_Interrupt_definition
+/** @defgroup FMC_Interrupt_definition FMC Interrupt definition
* @brief FMC Interrupt definition
* @{
- */
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
-#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+ */
+#define FMC_IT_RISING_EDGE ((uint32_t)FMC_SRx_IREN)
+#define FMC_IT_LEVEL ((uint32_t)FMC_SRx_ILEN)
+#define FMC_IT_FALLING_EDGE ((uint32_t)FMC_SRx_IFEN)
-#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-
-#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) || \
- ((IT) == FMC_IT_LEVEL) || \
- ((IT) == FMC_IT_FALLING_EDGE) || \
- ((IT) == FMC_IT_REFRESH_ERROR))
/**
* @}
*/
-
-/** @defgroup FMC_Flag_definition
+
+/** @defgroup FMC_Flag_definition FMC Flag definition
* @brief FMC Flag definition
* @{
- */
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+ */
+#define FMC_FLAG_RISING_EDGE ((uint32_t)FMC_SRx_IRS)
+#define FMC_FLAG_LEVEL ((uint32_t)FMC_SRx_ILS)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)FMC_SRx_IFS)
+#define FMC_FLAG_FEMPT ((uint32_t)FMC_SRx_FEMPT)
-#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) || \
- ((FLAG) == FMC_FLAG_LEVEL) || \
- ((FLAG) == FMC_FLAG_FALLING_EDGE) || \
- ((FLAG) == FMC_FLAG_FEMPT))
+/**
+ * @}
+ */
-#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FMC_NOR_Macros
+/** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
+ * @{
+ */
+
+/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
-
+
/**
* @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
- * @retval None
- */
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
- * @retval None
- */
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
+ * @retval none
+ */
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
/**
* @}
- */
+ */
-/** @defgroup FMC_NAND_Macros
+/** @defgroup FMC_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
-
+
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
- */
-#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
+ */
+#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
- */
-#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+ */
+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
+ CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
+
/**
* @}
- */
-
-/** @defgroup FMC_PCCARD_Macros
- * @brief macros to handle SRAM read/write operations
+ */
+
+/** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
+ * @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
- * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
- */
-#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
+ */
+#define __FMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
/**
* @brief Disable the PCCARD device access.
- * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
- */
-#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
+ */
+#define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
/**
* @}
*/
-
-/** @defgroup FMC_Interrupt
+
+/** @defgroup FMC_Interrupt FMC Interrupt
* @brief macros to handle FMC interrupts
* @{
- */
+ */
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
-#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+ */
+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
*/
-#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
-
+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
+
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
* @retval None
*/
-#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
+ CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
+
/**
* @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__: FMC_PCCARD Instance
- * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
-#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
+ */
+#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__: FMC_PCCARD Instance
- * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FMC_IT_LEVEL: Interrupt level.
- * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
+ * @arg FMC_IT_RISING_EDGE Interrupt rising edge.
+ * @arg FMC_IT_LEVEL Interrupt level.
+ * @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
* @retval None
- */
-#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
+ */
+#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FMC_PCCARD Instance
- * @param __FLAG__: FMC_PCCARD flag
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FMC_PCCARD Instance
- * @param __FLAG__: FMC_PCCARD flag
+ * @param __INSTANCE__ FMC_PCCARD Instance
+ * @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FMC_FLAG_FEMPT: FIFO empty flag.
+ * @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
+ * @arg FMC_FLAG_LEVEL Interrupt level edge flag.
+ * @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
+ * @arg FMC_FLAG_FEMPT FIFO empty flag.
* @retval None
*/
-#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
-
+#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
+
/**
* @}
- */
+ */
+
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-/* FMC_NORSRAM Controller functions *******************************************/
+/** @addtogroup FMC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup FMC_NORSRAM
+ * @{
+ */
+
+/** @addtogroup FMC_NORSRAM_Group1
+ * @{
+ */
+
+/* FMC_NORSRAM Controller functions ******************************************/
/* Initialization/de-initialization functions */
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_NORSRAM_Group2
+ * @{
+ */
+
/* FMC_NORSRAM Control functions */
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_NAND
+ * @{
+ */
+
/* FMC_NAND Controller functions **********************************************/
/* Initialization/de-initialization functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group1
+ * @{
+ */
+
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
+/**
+ * @}
+ */
+
/* FMC_NAND Control functions */
+/** @addtogroup FMC_NAND_Exported_Functions_Group2
+ * @{
+ */
+
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup FMC_PCCARD
+ * @{
+ */
+
/* FMC_PCCARD Controller functions ********************************************/
/* Initialization/de-initialization functions */
+/** @addtogroup FMC_PCCARD_Exported_Functions_Group1
+ * @{
+ */
+
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
+#endif /* FMC_BANK1 */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
@@ -954,3 +1081,4 @@
#endif /* __STM32F3xx_LL_FMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_gpio.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,304 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_gpio.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_gpio.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP) ||\
+ ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_1 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_2 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_3 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_4 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_5 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_6 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_7 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_8 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_9 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_10 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_11 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_12 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_13 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_14 ) ||\
+ ((__VALUE__) == LL_GPIO_AF_15 ))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
+ }
+#if defined(GPIOD)
+ else if (GPIOx == GPIOD)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
+ }
+#endif /* GPIOD */
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
+ }
+#endif /* GPIOE */
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
+ }
+#endif /* GPIOF */
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
+ }
+#endif /* GPIOG */
+#if defined(GPIOH)
+ else if (GPIOx == GPIOH)
+ {
+ LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
+ }
+#endif /* GPIOH */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00000000U;
+ uint32_t currentpin = 0x00000000U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ {
+ /* Get current io position */
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+
+ if (currentpin)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ {
+ /* Check Alternate parameter */
+ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+ /* Speed mode configuration */
+ if (POSITION_VAL(currentpin) < 0x00000008U)
+ {
+ LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ else
+ {
+ LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+ }
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
+ GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_gpio.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,997 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_gpio.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_GPIO_H
+#define __STM32F3xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
+ GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
+ GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
+ GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+ GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+ GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_NO ((uint32_t)0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+ * @{
+ */
+#define LL_GPIO_AF_0 ((uint32_t)0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1 ((uint32_t)0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2 ((uint32_t)0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3 ((uint32_t)0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4 ((uint32_t)0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5 ((uint32_t)0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6 ((uint32_t)0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7 ((uint32_t)0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8 ((uint32_t)0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9 ((uint32_t)0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10 ((uint32_t)0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11 ((uint32_t)0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12 ((uint32_t)0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13 ((uint32_t)0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14 ((uint32_t)0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15 ((uint32_t)0x000000FU) /*!< Select alternate function 15 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll MODER MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->MODER,
+ (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+ (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+ (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_NO
+ * @arg @ref LL_GPIO_PULL_UP
+ * @arg @ref LL_GPIO_PULL_DOWN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+ (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
+ (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+ * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+ (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Alternate This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+ MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
+ (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+ * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+ * @note Possible values are from AF0 to AF15 depending on target.
+ * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_0
+ * @arg @ref LL_GPIO_AF_1
+ * @arg @ref LL_GPIO_AF_2
+ * @arg @ref LL_GPIO_AF_3
+ * @arg @ref LL_GPIO_AF_4
+ * @arg @ref LL_GPIO_AF_5
+ * @arg @ref LL_GPIO_AF_6
+ * @arg @ref LL_GPIO_AF_7
+ * @arg @ref LL_GPIO_AF_8
+ * @arg @ref LL_GPIO_AF_9
+ * @arg @ref LL_GPIO_AF_10
+ * @arg @ref LL_GPIO_AF_11
+ * @arg @ref LL_GPIO_AF_12
+ * @arg @ref LL_GPIO_AF_13
+ * @arg @ref LL_GPIO_AF_14
+ * @arg @ref LL_GPIO_AF_15
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+ (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ WRITE_REG(GPIOx->LCKR, PinMask);
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, PinMask);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_hrtim.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_hrtim.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief HRTIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_hrtim.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (HRTIM1)
+
+/** @addtogroup HRTIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRTIM_LL_Exported_Functions
+ * @{
+ */
+/**
+ * @brief Set HRTIM instance registers to their reset values.
+ * @param HRTIMx High Resolution Timer instance
+ * @retval ErrorStatus enumeration value:
+ * - SUCCESS: HRTIMx registers are de-initialized
+ * - ERROR: invalid HRTIMx instance
+ */
+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_ALL_INSTANCE(HRTIMx));
+
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_HRTIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_HRTIM1);
+
+ return result;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_hrtim.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,10544 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_hrtim.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of HRTIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_HRTIM_H
+#define __STM32F3xx_LL_HRTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (HRTIM1)
+
+/** @defgroup HRTIM_LL HRTIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
+ * @{
+ */
+static const uint16_t REG_OFFSET_TAB_TIMER[] =
+{
+ 0x00U, /* 0: MASTER */
+ 0x80U, /* 1: TIMER A */
+ 0x100U, /* 2: TIMER B */
+ 0x180U, /* 3: TIMER C */
+ 0x200U, /* 4: TIMER D */
+ 0x280U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_OFFSET_TAB_ADCxR[] =
+{
+ 0x00U, /* 0: HRTIM_ADC1R */
+ 0x04U, /* 1: HRTIM_ADC2R */
+ 0x08U, /* 2: HRTIM_ADC3R */
+ 0x0CU, /* 3: HRTIM_ADC4R */
+};
+
+static const uint16_t REG_OFFSET_TAB_SETxR[] =
+{
+ 0x00U, /* 0: TA1 */
+ 0x08U, /* 1: TA2 */
+ 0x80U, /* 2: TB1 */
+ 0x88U, /* 3: TB2 */
+ 0x100U, /* 4: TC1 */
+ 0x108U, /* 5: TC2 */
+ 0x180U, /* 6: TD1 */
+ 0x188U, /* 7: TD2 */
+ 0x200U, /* 8: TE1 */
+ 0x208U /* 9: TE2 */
+};
+
+static const uint16_t REG_OFFSET_TAB_OUTxR[] =
+{
+ 0x00U, /* 0: TA1 */
+ 0x00U, /* 1: TA2 */
+ 0x80U, /* 2: TB1 */
+ 0x80U, /* 3: TB2 */
+ 0x100U, /* 4: TC1 */
+ 0x100U, /* 5: TC2 */
+ 0x180U, /* 6: TD1 */
+ 0x180U, /* 7: TD2 */
+ 0x200U, /* 8: TE1 */
+ 0x200U /* 9: TE2 */
+};
+
+
+static const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
+{
+ 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
+ 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
+};
+
+static const uint8_t REG_OFFSET_TAB_EECR[] =
+{
+ 0x00U, /* LL_HRTIM_EVENT_1 */
+ 0x00U, /* LL_HRTIM_EVENT_2 */
+ 0x00U, /* LL_HRTIM_EVENT_3 */
+ 0x00U, /* LL_HRTIM_EVENT_4 */
+ 0x00U, /* LL_HRTIM_EVENT_5 */
+ 0x04U, /* LL_HRTIM_EVENT_6 */
+ 0x04U, /* LL_HRTIM_EVENT_7 */
+ 0x04U, /* LL_HRTIM_EVENT_8 */
+ 0x04U, /* LL_HRTIM_EVENT_9 */
+ 0x04U /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint8_t REG_OFFSET_TAB_FLTINR[] =
+{
+ 0x00U, /* LL_HRTIM_FAULT_1 */
+ 0x00U, /* LL_HRTIM_FAULT_2 */
+ 0x00U, /* LL_HRTIM_FAULT_3 */
+ 0x00U, /* LL_HRTIM_FAULT_4 */
+ 0x04U /* LL_HRTIM_FAULT_5 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
+{
+ 0x20000000U, /* 0: MASTER */
+ 0x01FE0000U, /* 1: TIMER A */
+ 0x01FE0000U, /* 2: TIMER B */
+ 0x01FE0000U, /* 3: TIMER C */
+ 0x01FE0000U, /* 4: TIMER D */
+ 0x01FE0000U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
+{
+ 12U, /* 0: MASTER */
+ 0U, /* 1: TIMER A */
+ 0U, /* 2: TIMER B */
+ 0U, /* 3: TIMER C */
+ 0U, /* 4: TIMER D */
+ 0U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_EExSRC[] =
+{
+ 0U, /* LL_HRTIM_EVENT_1 */
+ 6U, /* LL_HRTIM_EVENT_2 */
+ 12U, /* LL_HRTIM_EVENT_3 */
+ 18U, /* LL_HRTIM_EVENT_4 */
+ 24U, /* LL_HRTIM_EVENT_5 */
+ 0U, /* LL_HRTIM_EVENT_6 */
+ 6U, /* LL_HRTIM_EVENT_7 */
+ 12U, /* LL_HRTIM_EVENT_8 */
+ 18U, /* LL_HRTIM_EVENT_9 */
+ 24U /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
+{
+ HRTIM_MCR_BRSTDMA, /* 0: MASTER */
+ HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
+ HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
+ HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
+ HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
+ HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
+{
+ 2U, /* 0: MASTER */
+ 0U, /* 1: TIMER A */
+ 0U, /* 2: TIMER B */
+ 0U, /* 3: TIMER C */
+ 0U, /* 4: TIMER D */
+ 0U, /* 5: TIMER E */
+};
+
+static const uint8_t REG_SHIFT_TAB_OUTxR[] =
+{
+ 0U, /* 0: TA1 */
+ 16U, /* 1: TA2 */
+ 0U, /* 2: TB1 */
+ 16U, /* 3: TB2 */
+ 0U, /* 4: TC1 */
+ 16U, /* 5: TC2 */
+ 0U, /* 6: TD1 */
+ 16U, /* 7: TD2 */
+ 0U, /* 8: TE1 */
+ 16U /* 9: TE2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
+{
+ 0U, /* 0: TA1 */
+ 1U, /* 1: TA2 */
+ 0U, /* 2: TB1 */
+ 1U, /* 3: TB2 */
+ 0U, /* 4: TC1 */
+ 1U, /* 5: TC2 */
+ 0U, /* 6: TD1 */
+ 1U, /* 7: TD2 */
+ 0U, /* 8: TE1 */
+ 1U /* 9: TE2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTxE[] =
+{
+ 0U, /* LL_HRTIM_FAULT_1 */
+ 8U, /* LL_HRTIM_FAULT_2 */
+ 16U, /* LL_HRTIM_FAULT_3 */
+ 24U, /* LL_HRTIM_FAULT_4 */
+ 0U /* LL_HRTIM_FAULT_5 */
+};
+
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
+ * @{
+ */
+#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
+ HRTIM_CR1_TAUDIS |\
+ HRTIM_CR1_TBUDIS |\
+ HRTIM_CR1_TCUDIS |\
+ HRTIM_CR1_TDUDIS |\
+ HRTIM_CR1_TEUDIS))
+
+#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
+ HRTIM_CR2_TASWU |\
+ HRTIM_CR2_TBSWU |\
+ HRTIM_CR2_TCSWU |\
+ HRTIM_CR2_TDSWU |\
+ HRTIM_CR2_TESWU))
+
+#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
+ HRTIM_CR2_TARST |\
+ HRTIM_CR2_TBRST |\
+ HRTIM_CR2_TCRST |\
+ HRTIM_CR2_TDRST |\
+ HRTIM_CR2_TERST))
+
+#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
+ HRTIM_OENR_TA2OEN |\
+ HRTIM_OENR_TB1OEN |\
+ HRTIM_OENR_TB2OEN |\
+ HRTIM_OENR_TC1OEN |\
+ HRTIM_OENR_TC2OEN |\
+ HRTIM_OENR_TD1OEN |\
+ HRTIM_OENR_TD2OEN |\
+ HRTIM_OENR_TE1OEN |\
+ HRTIM_OENR_TE2OEN))
+
+#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
+ HRTIM_ODISR_TA2ODIS |\
+ HRTIM_ODISR_TB1ODIS |\
+ HRTIM_ODISR_TB2ODIS |\
+ HRTIM_ODISR_TC1ODIS |\
+ HRTIM_ODISR_TC2ODIS |\
+ HRTIM_ODISR_TD1ODIS |\
+ HRTIM_ODISR_TD2ODIS |\
+ HRTIM_ODISR_TE1ODIS |\
+ HRTIM_ODISR_TE2ODIS))
+
+#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
+ HRTIM_OUTR_IDLM1 |\
+ HRTIM_OUTR_IDLES1 |\
+ HRTIM_OUTR_FAULT1 |\
+ HRTIM_OUTR_CHP1 |\
+ HRTIM_OUTR_DIDL1))
+
+#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
+ HRTIM_EECR1_EE1POL |\
+ HRTIM_EECR1_EE1SNS |\
+ HRTIM_EECR1_EE1FAST))
+
+#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
+ HRTIM_FLTINR1_FLT1SRC))
+
+#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
+ HRTIM_BMCR_BMCLK |\
+ HRTIM_BMCR_BMOM))
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
+ * @{
+ */
+/* TO BE COMPLETED */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
+ * @{
+ */
+
+/** @defgroup HRTIM_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
+ * @{
+ */
+#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
+#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
+#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
+#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
+#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
+#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
+#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
+#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
+
+#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
+#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
+#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
+#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
+#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
+#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
+#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
+
+#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
+#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
+#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
+#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
+#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
+#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
+#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
+#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
+#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
+#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
+#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
+#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
+#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
+#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
+ * @{
+ */
+#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
+#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
+#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
+#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
+#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
+#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
+#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
+#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
+
+#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
+#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
+#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
+#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
+#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
+#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
+#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
+
+
+#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
+#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
+#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
+#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
+#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
+#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
+#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
+#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
+#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
+#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
+#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
+#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
+#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
+#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
+ * @{
+ * @brief Constants defining defining the synchronization input source.
+ */
+#define LL_HRTIM_SYNCIN_SRC_NONE ((uint32_t)0x00000000U) /*!< HRTIM is not synchronized and runs in standalone mode */
+#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
+#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
+ * @{
+ * @brief Constants defining the source and event to be sent on the synchronization output.
+ */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START ((uint32_t)0x00000000U) /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
+ * @{
+ * @brief Constants defining the routing and conditioning of the synchronization output event.
+ */
+#define LL_HRTIM_SYNCOUT_DISABLED ((uint32_t)0x00000000U) /*!< Synchronization output event is disabled */
+#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIMER TIMER ID
+ * @{
+ * @brief Constants identifying a timing unit.
+ */
+#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
+#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
+#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
+#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
+#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
+#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUTPUT OUTPUT ID
+ * @{
+ * @brief Constants identifying an HRTIM output.
+ */
+#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_COMPAREUNIT COMPARE UNIT ID
+ * @{
+ * @brief Constants identifying a compare unit.
+ */
+#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
+#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CAPTUREUNIT CAPTURE UNIT ID
+ * @{
+ * @brief Constants identifying a capture unit.
+ */
+#define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
+#define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FAULT FAULT ID
+ * @{
+ * @brief Constants identifying a fault channel.
+ */
+#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
+#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
+#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
+#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
+#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EVENT EXTERNAL EVENT ID
+ * @{
+ * @brief Constants identifying an external event channel.
+ */
+#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
+#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
+#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
+#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
+#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
+#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
+#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
+#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
+#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
+#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUTPUTSTATE OUTPUT STATE
+ * @{
+ * @brief Constants defining the state of an HRTIM output.
+ */
+#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
+#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
+#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG ADC TRIGGER
+ * @{
+ * @brief Constants identifying an ADC trigger.
+ */
+#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
+#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
+#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
+#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
+ * @{
+ * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
+ */
+#define LL_HRTIM_ADCTRIG_UPDATE_MASTER ((uint32_t)0x00000000U) /*!< HRTIM_ADCxR register update is triggered by the Master timer */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
+ * @{
+ * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
+ */
+#define LL_HRTIM_ADCTRIG_SRC13_NONE ((uint32_t)0x00000000U) /*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
+ * @{
+ * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
+ */
+#define LL_HRTIM_ADCTRIG_SRC24_NONE ((uint32_t)0x00000000U)/*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
+ * @{
+ * @brief Constants defining the DLL calibration mode.
+ */
+#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT ((uint32_t)0x00000000U)/*!<Calibration is perfomed only once */
+#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CALIBRATIONRATE DLL CALIBRATION RATE
+ * @{
+ * @brief Constants defining the DLL calibration periods (in micro seconds).
+ */
+#define LL_HRTIM_DLLCALIBRATION_RATE_7300 ((uint32_t)0x00000000U) /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 ms) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_PRESCALERRATIO PRESCALER RATIO
+ * @{
+ * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define LL_HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000U) /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
+#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_MODE COUNTER MODE
+ * @{
+ * @brief Constants defining timer counter operating mode.
+ */
+#define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
+#define LL_HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
+#define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DACTRIG DAC TRIGGER
+ * @{
+ * @brief Constants defining on which output the DAC synchronization event is sent.
+ */
+#define LL_HRTIM_DACTRIG_NONE ((uint32_t)0x00000000U) /*!< No DAC synchronization event generated */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_UPDATETRIG UPDATE TRIGGER
+ * @{
+ * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
+ */
+#define LL_HRTIM_UPDATETRIG_NONE ((uint32_t)0x00000000U)/*!< Register update is disabled */
+#define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
+#define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
+#define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
+#define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
+#define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
+#define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
+#define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
+#define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_UPDATEGATING UPDATE GATING
+ * @{
+ * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
+ */
+#define LL_HRTIM_UPDATEGATING_INDEPENDENT ((uint32_t)0x00000000U) /*!< Update done independently from the DMA burst transfer completion */
+#define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
+#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
+#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_COMPAREMODE COMPARE MODE
+ * @{
+ * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
+ */
+#define LL_HRTIM_COMPAREMODE_REGULAR ((uint32_t)0x00000000U) /*!< standard compare mode */
+#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_RESETTRIG RESET TRIGGER
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
+ */
+#define LL_HRTIM_RESETTRIG_NONE ((uint32_t)0x00000000U)/*!< No counter reset trigger */
+#define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
+#define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
+#define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
+#define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
+#define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
+#define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
+#define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
+#define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
+#define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
+#define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
+#define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CAPTURETRIG CAPTURE TRIGGER
+ * @{
+ * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
+ */
+#define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */
+#define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
+ * @{
+ * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
+ */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 ((uint32_t)0x00000000U) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
+
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 ((uint32_t)0x00000000U) /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BURSTMODE BURST MODE
+ * @{
+ * @brief Constants defining how the timer behaves during a burst mode operation.
+ */
+#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BURSTDMA BURST DMA
+ * @{
+ * @brief Constants defining the registers that can be written during a burst DMA operation.
+ */
+#define LL_HRTIM_BURSTDMA_NONE ((uint32_t)0x00000000U) /*!< No register is updated by Burst DMA accesses */
+
+#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
+
+#define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CPPSTAT CURRENT PUSH-PULL STATUS
+ * @{
+ * @brief Constants defining on which output the signal is currently applied in push-pull mode.
+ */
+#define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
+#define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_IPPSTAT IDLE PUSH-PULL STATUS
+ * @{
+ * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
+ */
+#define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
+ * @{
+ * @brief Constants defining the event filtering applied to external events by a timer.
+ */
+#define LL_HRTIM_EEFLTR_NONE ((uint32_t)0x00000000U)
+#define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
+#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
+ * @{
+ * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
+ */
+#define LL_HRTIM_EELATCH_DISABLED ((uint32_t)0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_PRESCALER DEADTIME PRESCALER
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
+ */
+#define LL_HRTIM_DT_PRESCALER_MUL8 ((uint32_t)0x00000000U) /*!< fDTG = fHRTIM * 8 */
+#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
+#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
+#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
+#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
+#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_RISING_SIGN DEADTIME RISING SIGN
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
+ */
+#define LL_HRTIM_DT_RISING_POSITIVE ((uint32_t)0x00000000U) /*!< Positive deadtime on rising edge */
+#define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
+ * @{
+ * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
+ */
+#define LL_HRTIM_DT_FALLING_POSITIVE ((uint32_t)0x00000000U) /*!< Positive deadtime on falling edge */
+#define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
+ * @{
+ * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
+ */
+#define LL_HRTIM_CHP_PRESCALER_DIV16 ((uint32_t)0x00000000U) /*!< fCHPFRQ = fHRTIM / 16 */
+#define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
+#define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
+#define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
+#define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
+#define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
+#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
+#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
+#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
+#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
+#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
+#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
+#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
+#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
+#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
+#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
+ * @{
+ * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
+ */
+#define LL_HRTIM_CHP_DUTYCYCLE_0 ((uint32_t)0x00000000U) /*!< Only 1st pulse is present */
+#define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
+ * @{
+ * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
+ */
+#define LL_HRTIM_CHP_PULSEWIDTH_16 ((uint32_t)0x00000000U) /*!< tSTPW = tHRTIM x 16 */
+#define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
+#define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
+#define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
+#define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
+#define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
+#define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
+#define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
+#define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
+#define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
+#define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
+#define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
+#define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
+#define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
+#define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
+#define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_CROSSBAR_INPUT CROSSBAR INPUT
+ * @{
+ * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
+ */
+#define LL_HRTIM_CROSSBAR_NONE ((uint32_t)0x00000000U) /*!< Reset the output set crossbar */
+#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
+#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_POLARITY OUPUT_POLARITY
+ * @{
+ * @brief Constants defining the polarity of a timer output.
+ */
+#define LL_HRTIM_OUT_POSITIVE_POLARITY ((uint32_t)0x00000000U) /*!< Output is acitve HIGH */
+#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_IDLEMODE OUTPUT IDLE MODE
+ * @{
+ * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
+ */
+#define LL_HRTIM_OUT_NO_IDLE ((uint32_t)0x00000000U)/*!< The output is not affected by the burst mode operation */
+#define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
+ * @{
+ * @brief Constants defining the output level when output is in IDLE state
+ */
+#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE ((uint32_t)0x00000000U)/*!< Output at inactive level when in IDLE state */
+#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
+ * @{
+ * @brief Constants defining the output level when output is in FAULT state.
+ */
+#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION ((uint32_t)0x00000000U) /*!< The output is not affected by the fault input */
+#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
+ * @{
+ * @brief Constants defining whether or not chopper mode is enabled for a timer output.
+ */
+#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED ((uint32_t)0x00000000U) /*!< Output signal is not altered */
+#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
+ * @{
+ * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
+during a programmable period before the output takes its idle state.
+ */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR ((uint32_t)0x00000000U)/*!< The programmed Idle state is applied immediately to the Output */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
+/**
+ * @}
+ */
+/** @defgroup HRTIM_EC_OUT_LEVEL OUTPUT LEVEL
+ * @{
+ * @brief Constants defining the level of a timer output.
+ */
+#define LL_HRTIM_OUT_LEVEL_INACTIVE ((uint32_t)0x00000000U)/*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
+#define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_SRC EXTERNAL EVENT SOURCE
+ * @{
+ * @brief Constants defining available sources associated to external events.
+ */
+#define LL_HRTIM_EE_SRC_1 ((uint32_t)0x00000000U) /*!< External event source 1 (EExSrc1)*/
+#define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */
+#define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */
+#define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */
+/**
+ * @}
+ */
+/** @defgroup HRTIM_EC_EE_POLARITY EXTERNAL EVENT POLARITY
+ * @{
+ * @brief Constants defining the polarity of an external event.
+ */
+#define LL_HRTIM_EE_POLARITY_HIGH ((uint32_t)0x00000000U) /*!< External event is active high */
+#define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
+ * @{
+ * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
+ */
+#define LL_HRTIM_EE_SENSITIVITY_LEVEL ((uint32_t)0x00000000U) /*!< External event is active on level */
+#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
+#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
+#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
+ * @{
+ * @brief Constants defining whether or not an external event is programmed in fast mode.
+ */
+#define LL_HRTIM_EE_FASTMODE_DISABLE ((uint32_t)0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
+ * @{
+ * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
+ */
+#define LL_HRTIM_EE_FILTER_NONE ((uint32_t)0x00000000U) /*!< Filter disabled */
+#define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
+#define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
+#define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
+#define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
+#define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
+#define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
+#define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
+#define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
+#define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
+#define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
+#define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
+#define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
+#define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
+#define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
+#define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
+ * @{
+ * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
+ */
+#define LL_HRTIM_EE_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fEEVS = fHRTIM */
+#define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
+#define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
+#define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_SRC FAULT SOURCE
+ * @{
+ * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
+ */
+#define LL_HRTIM_FLT_SRC_DIGITALINPUT ((uint32_t)0x00000000U) /*!< Fault input is FLT input pin */
+#define LL_HRTIM_FLT_SRC_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_POLARITY FAULT POLARITY
+ * @{
+ * @brief Constants defining the polarity of a fault event.
+ */
+#define LL_HRTIM_FLT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< Fault input is active low */
+#define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_FILTER FAULT DIGITAL FILTER
+ * @{
+ * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
+ */
+#define LL_HRTIM_FLT_FILTER_NONE ((uint32_t)0x00000000U) /*!< Filter disabled */
+#define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
+#define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
+#define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
+#define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
+#define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
+#define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
+#define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
+#define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
+#define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
+#define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
+#define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
+#define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
+#define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
+#define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
+#define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_FLT_PRESCALER BURST FAULT PRESCALER
+ * @{
+ * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
+ */
+#define LL_HRTIM_FLT_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fFLTS = fHRTIM */
+#define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
+#define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
+#define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_MODE BURST MODE OPERATING MODE
+ * @{
+ * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
+ */
+#define LL_HRTIM_BM_MODE_SINGLESHOT ((uint32_t)0x00000000U) /*!< Burst mode operates in single shot mode */
+#define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
+ * @{
+ * @brief Constants defining the clock source for the burst mode counter.
+ */
+#define LL_HRTIM_BM_CLKSRC_MASTER ((uint32_t)0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_PRESCALER BURST MODE PRESCALER
+ * @{
+ * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
+ */
+#define LL_HRTIM_BM_PRESCALER_DIV1 ((uint32_t)0x00000000U) /*!< fBRST = fHRTIM */
+#define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
+#define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
+#define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
+#define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
+#define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
+#define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
+#define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
+#define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
+#define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
+#define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
+#define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
+#define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
+#define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
+#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
+#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_TRIG HRTIM BURST MODE TRIGGER
+ * @{
+ * @brief Constants defining the events that can be used to trig the burst mode operation.
+ */
+#define LL_HRTIM_BM_TRIG_NONE (uint32_t)0x00000000 /*!< No trigger */
+#define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst
+mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst
+mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode
+operation */
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EC_BM_STATUS HRTIM BURST MODE STATUS
+ * @{
+ * @brief Constants defining the operating state of the burst mode controller.
+ */
+#define LL_HRTIM_BM_STATUS_NORMAL ((uint32_t) 0x00000000U) /*!< Normal operation */
+#define LL_HRTIM_BM_STATUS_BURST_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
+ * @{
+ */
+
+/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in HRTIM register
+ * @param __INSTANCE__ HRTIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in HRTIM register
+ * @param __INSTANCE__ HRTIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+/**
+ * @brief HELPER macro returning the output state from output enable/disable status
+ * @param __OUTPUT_STATUS_EN__ output enable status
+ * @param __OUTPUT_STATUS_DIS__ output Disable status
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
+ * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
+*/
+#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
+ (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
+ ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
+ * @{
+ */
+/** @defgroup HRTIM_EF_HRTIM_Control HRTIM_Control
+ * @{
+ */
+
+/**
+ * @brief Select the HRTIM synchronization input source.
+ * @note This function must not be called when the concerned timer(s) is (are) enabled .
+ * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncInSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
+}
+
+/**
+ * @brief Get actual HRTIM synchronization input source.
+ * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncInSrc Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+ * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
+}
+
+/**
+ * @brief Configure the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
+ * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
+ * @param HRTIMx High Resolution Timer instance
+ * @param Config This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
+}
+
+/**
+ * @brief Set the routing and conditioning of the synchronization output event.
+ * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
+ * @note This function can be called only when the master timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncOutConfig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
+}
+
+/**
+ * @brief Get actual routing and conditioning of the synchronization output event.
+ * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncOutConfig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+ * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+ * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
+}
+
+/**
+ * @brief Set the source and event to be sent on the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param SyncOutSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
+{
+ MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
+}
+
+/**
+ * @brief Get actual source and event sent on the HRTIM synchronization output.
+ * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval SyncOutSrc Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+ * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
+}
+
+/**
+ * @brief Disable (temporarily) update event generation.
+ * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
+ * CR1 TEUDIS LL_HRTIM_SuspendUpdate
+ * @note Allow to temporarily disable the transfer from preload to active
+ * registers, whatever the selected update event. This allows to modify
+ * several registers in multiple timers.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
+ * CR1 TEUDIS LL_HRTIM_ResumeUpdate
+ * @note The regular update event takes place.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+ * @brief Force an immediate transfer from the preload to the active register .
+ * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TASWU LL_HRTIM_ForceUpdate\n
+ * CR2 TBSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TCSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TDSWU LL_HRTIM_ForceUpdate\n
+ * CR2 TESWU LL_HRTIM_ForceUpdate
+ * @note Any pending update request is cancelled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
+}
+
+/**
+ * @brief Reset the HRTIM timer(s) counter.
+ * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
+ * CR2 TARST LL_HRTIM_CounterReset\n
+ * CR2 TBRST LL_HRTIM_CounterReset\n
+ * CR2 TCRST LL_HRTIM_CounterReset\n
+ * CR2 TDRST LL_HRTIM_CounterReset\n
+ * CR2 TERST LL_HRTIM_CounterReset
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
+}
+
+/**
+ * @brief Enable the HRTIM timer(s) output(s) .
+ * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
+ * OENR TA2OEN LL_HRTIM_EnableOutput\n
+ * OENR TB1OEN LL_HRTIM_EnableOutput\n
+ * OENR TB2OEN LL_HRTIM_EnableOutput\n
+ * OENR TC1OEN LL_HRTIM_EnableOutput\n
+ * OENR TC2OEN LL_HRTIM_EnableOutput\n
+ * OENR TD1OEN LL_HRTIM_EnableOutput\n
+ * OENR TD2OEN LL_HRTIM_EnableOutput\n
+ * OENR TE1OEN LL_HRTIM_EnableOutput\n
+ * OENR TE2OEN LL_HRTIM_EnableOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Outputs This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+ SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
+}
+
+/**
+ * @brief Disable the HRTIM timer(s) output(s) .
+ * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
+ * OENR TA2OEN LL_HRTIM_DisableOutput\n
+ * OENR TB1OEN LL_HRTIM_DisableOutput\n
+ * OENR TB2OEN LL_HRTIM_DisableOutput\n
+ * OENR TC1OEN LL_HRTIM_DisableOutput\n
+ * OENR TC2OEN LL_HRTIM_DisableOutput\n
+ * OENR TD1OEN LL_HRTIM_DisableOutput\n
+ * OENR TD2OEN LL_HRTIM_DisableOutput\n
+ * OENR TE1OEN LL_HRTIM_DisableOutput\n
+ * OENR TE2OEN LL_HRTIM_DisableOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Outputs This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
+}
+
+/**
+ * @brief Indicates whether the HRTIM timer output is enabled.
+ * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
+ * OENR TE2OEN LL_HRTIM_IsEnabledOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output);
+}
+
+/**
+ * @brief Indicates whether the HRTIM timer output is disabled.
+ * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
+ * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval State of TxyODS bit in HRTIM_ODSR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ODISR, Output) == Output);
+}
+
+/**
+ * @brief Configure an ADC trigger.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
+ * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
+ * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Update This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ * @param Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
+ WRITE_REG(*pReg, Src);
+}
+
+/**
+ * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
+ * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate
+ * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
+ * registers are not preloaded either: a write access will result in an
+ * immediate update of the trigger source.
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Update This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));
+}
+
+/**
+ * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
+ * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
+ * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @retval Update Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+ * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+ register uint32_t shift = 3 * ADCTrig;
+ return (READ_BIT(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift)) >> shift);
+}
+
+/**
+ * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
+ * @rmtoll ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
+ * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @param Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+* @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ WRITE_REG(*pReg, Src);
+}
+
+/**
+ * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
+ * @rmtoll ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
+ * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ADCTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_1
+ * @arg @ref LL_HRTIM_ADCTRIG_2
+ * @arg @ref LL_HRTIM_ADCTRIG_3
+ * @arg @ref LL_HRTIM_ADCTRIG_4
+ * @retval Src This parameter can be a combination of the following values:
+ *
+ * For ADC trigger 1 and ADC trigger 3:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ *
+ * For ADC trigger 2 and ADC trigger 4:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+ REG_OFFSET_TAB_ADCxR[ADCTrig]));
+ return (*pReg);
+}
+
+/**
+ * @brief Configure the DLL calibration mode.
+ * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
+ * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
+ * @param HRTIMx High Resolution Timer instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_7300
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_910
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_114
+ * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_14
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
+}
+
+/**
+ * @brief Launch DLL calibration
+ * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_HRTIM_Timer_Control HRTIM_Timer_Control
+ * @{
+ */
+
+/**
+ * @brief Enable timer(s) counter.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
+ * MDIER MCEN LL_HRTIM_TIM_CounterEnable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+ * @brief Disable timer(s) counter.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
+ * MDIER MCEN LL_HRTIM_TIM_CounterDisable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timers This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+ * @brief Indicate whether the timer counter is enabled.
+ * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
+ * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer));
+}
+
+/**
+ * @brief Set the timer clock prescaler ratio.
+ * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
+ * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
+ * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
+ * @note The prescaling ratio cannot be modified once the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
+}
+
+/**
+ * @brief Get the timer clock prescaler ratio
+ * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
+ * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+ * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
+}
+
+/**
+ * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
+ * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
+ * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
+ * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
+ * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_MODE_CONTINUOUS
+ * @arg @ref LL_HRTIM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
+}
+
+/**
+ * @brief Get the counter operating mode mode
+ * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
+ * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
+ * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
+ * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Mode Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_MODE_CONTINUOUS
+ * @arg @ref LL_HRTIM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
+}
+
+/**
+ * @brief Enable the half duty-cycle mode.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
+ * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
+ * active register is automatically updated with HRTIM_MPER/2
+ * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Disable the half duty-cycle mode.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
+ * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
+ * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_HALF) == HRTIM_MCR_HALF);
+}
+
+/**
+ * @brief Enable the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Disable the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Indicate whether the timer start when receiving a synchronization input event.
+ * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
+ * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+ * @brief Enable the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Disable the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Indicate whether the timer reset when receiving a synchronization input event.
+ * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
+ * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+ * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+ * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
+ * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DACTrig This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DACTRIG_NONE
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
+}
+
+/**
+ * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+ * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
+ * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DACTrig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_DACTRIG_NONE
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+ * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
+}
+
+/**
+ * @brief Enable the timer registers preload mechanism.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
+ * @note When the preload mode is enabled, accessed registers are shadow registers.
+ * Their content is transferred into the active register after an update request,
+ * either software or synchronized with an event.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Disable the timer registers preload mechanism.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Indicate whether the timer registers preload mechanism is enabled.
+ * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
+ * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCR_PREEN) == HRTIM_MCR_PREEN);
+}
+
+/**
+ * @brief Set the timer register update trigger.
+ * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
+ * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param UpdateTrig This parameter can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ *
+ * For timer A..E this parameter can be:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * or a combination of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ * @arg @ref LL_HRTIM_UPDATETRIG_RESET
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+ * @brief Set the timer register update trigger.
+ * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
+ * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval UpdateTrig Returned value can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ *
+ * For timer A..E this parameter can be:
+ * @arg @ref LL_HRTIM_UPDATETRIG_NONE
+ * or a combination of the following values:
+ * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+ * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+ * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+ * @arg @ref LL_HRTIM_UPDATETRIG_RESET
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+ * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
+ * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
+ * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param UpdateGating This parameter can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ *
+ * For the timer A..E this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
+}
+
+/**
+ * @brief Get the timer registers update condition.
+ * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
+ * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval UpdateGating Returned value can be one of the following values:
+ *
+ * For the master timer this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ *
+ * For the timer A..E this parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+ * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
+}
+
+/**
+ * @brief Enable the push-pull mode.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Disable the push-pull mode.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Indicate whether the push-pull mode is enabled.
+ * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+ * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
+ * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
+ * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
+ * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREUNIT_2
+ * @arg @ref LL_HRTIM_COMPAREUNIT_4
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
+ uint32_t Mode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
+ MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
+}
+
+/**
+ * @brief Get the functioning mode of the compare unit.
+ * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
+ * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREUNIT_2
+ * @arg @ref LL_HRTIM_COMPAREUNIT_4
+ * @retval Mode Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+ * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ register uint32_t shift = POSITION_VAL(CompareUnit) - POSITION_VAL(LL_HRTIM_COMPAREUNIT_2);
+ return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
+}
+
+/**
+ * @brief Set the timer counter value.
+ * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
+ * CNTxR CNTx LL_HRTIM_TIM_SetCounter
+ * @note This function can only be called when the timer is stopped.
+ * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
+ * significant bits of the counter are not significant. They cannot be
+ * written and return 0 when read.
+ * @note The timer behavior is not guaranteed if the counter value is set above
+ * the period.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Counter Value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
+}
+
+/**
+ * @brief Get actual timer counter value.
+ * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
+ * CNTxR CNTx LL_HRTIM_TIM_GetCounter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Counter Value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
+}
+
+/**
+ * @brief Set the timer period value.
+ * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
+ * PERxR PERx LL_HRTIM_TIM_SetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Period Value between 0 and 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
+}
+
+/**
+ * @brief Get actual timer period value.
+ * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
+ * PERxR PERx LL_HRTIM_TIM_GetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Period Value between 0 and 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MPER_MPER));
+}
+
+/**
+ * @brief Set the timer repetition period value.
+ * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
+ * REPxR REPx LL_HRTIM_TIM_SetRepetition
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Repetition Value between 0 and 0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
+}
+
+/**
+ * @brief Get actual timer repetition period value.
+ * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
+ * REPxR REPx LL_HRTIM_TIM_GetRepetition
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Repetition Value between 0 and 0xFF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MREP_MREP));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 1.
+ * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
+ * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 1.
+ * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
+ * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 2.
+ * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
+ * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 2.
+ * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
+ * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 3.
+ * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
+ * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 3.
+ * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
+ * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
+}
+
+/**
+ * @brief Set the compare value of the compare unit 4.
+ * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
+ * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
+}
+
+/**
+ * @brief Get actual compare value of the compare unit 4.
+ * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
+ * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
+}
+
+/**
+ * @brief Set the reset trigger of a timer counter.
+ * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
+ * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig
+ * @note The reset of the timer counter can be triggered by up to 30 events
+ * that can be selected among the following sources:
+ * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
+ * @arg The master timer: Reset and Compare 1..4 (5 events).
+ * @arg The external events EXTEVNT1..10 (10 events).
+ * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param ResetTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ WRITE_REG(*pReg, ResetTrig);
+}
+
+/**
+ * @brief Get actual reset trigger of a timer counter.
+ * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
+ * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval ResetTrig Returned value can be one of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Get captured value for capture unit 1.
+ * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Captured value
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Get captured value for capture unit 2.
+ * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Captured value
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Set the trigger of a capture unit for a given timer.
+ * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
+ * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CaptureUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_1
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_2
+ * @param CaptureTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
+ uint32_t CaptureTrig)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
+ REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
+ WRITE_REG(*pReg, CaptureTrig);
+}
+
+/**
+ * @brief Get actual trigger of a capture unit for a given timer.
+ * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
+ * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param CaptureUnit This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_1
+ * @arg @ref LL_HRTIM_CAPTUREUNIT_2
+ * @retval CaptureTrig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+ * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xCR) +
+ REG_OFFSET_TAB_TIMER[iTimer] + CaptureUnit * 4));
+ return (READ_REG(*pReg));
+}
+
+/**
+ * @brief Enable deadtime insertion for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Disable deadtime insertion for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Indicate whether deadtime insertion is enabled for a given timer.
+ * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DTEN) == HRTIM_OUTR_DTEN);
+}
+
+/**
+ * @brief Set the delayed protection (DLYPRT) mode.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
+ * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
+ * @note This function must be called prior enabling the delayed protection
+ * @note Balanced Idle mode is only available in push-pull mode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DLYPRTMode Delayed protection (DLYPRT) mode
+ *
+ * For timers A, B and C this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+ *
+ * For timers D and E this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
+}
+
+/**
+ * @brief Get the delayed protection (DLYPRT) mode.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
+ * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DLYPRTMode Delayed protection (DLYPRT) mode
+ *
+ * For timers A, B and C this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+ *
+ * For timers D and E this parameter can be one of the following vallues:
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+ * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
+}
+
+/**
+ * @brief Enable delayed protection (DLYPRT) for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
+ * @note This function must not be called once the concerned timer is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Disable delayed protection (DLYPRT) for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
+ * @note This function must not be called once the concerned timer is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
+ * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+ * @brief Enable the fault channel(s) for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Faults This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, Faults);
+}
+
+/**
+ * @brief Disable the fault channel(s) for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Faults This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, Faults);
+}
+
+/**
+ * @brief Indicate whether the fault channel is enabled for a given timer.
+ * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
+ * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, Fault) == (Fault));
+}
+
+/**
+ * @brief Lock the fault conditioning set-up for a given timer.
+ * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
+ * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
+}
+
+/**
+ * @brief Define how the timer behaves during a burst mode operation.
+ * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
+ * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption
+ * @note This function must not be called when the burst mode is enabled
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param BurtsModeOption This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+ * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
+}
+
+/**
+ * @brief Retrieve how the timer behaves during a burst mode operation.
+ * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
+ * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval BurtsMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+ * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
+}
+
+/**
+ * @brief Program which registers are to be written by Burst DMA transfers.
+ * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIAEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
+ * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Registers Registers to be updated by the DMA request
+ *
+ * For Master timer this parameter can be can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BURSTDMA_NONE
+ * @arg @ref LL_HRTIM_BURSTDMA_MCR
+ * @arg @ref LL_HRTIM_BURSTDMA_MICR
+ * @arg @ref LL_HRTIM_BURSTDMA_MDIER
+ * @arg @ref LL_HRTIM_BURSTDMA_MCNT
+ * @arg @ref LL_HRTIM_BURSTDMA_MPER
+ * @arg @ref LL_HRTIM_BURSTDMA_MREP
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
+ * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
+ *
+ * For Timers A..E this parameter can be can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BURSTDMA_NONE
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
+ * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + 4 * iTimer));
+ WRITE_REG(*pReg, Registers);
+}
+
+/**
+ * @brief Indicate on which output the signal is currently applied.
+ * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
+ * @note Only significant when the timer operates in push-pull mode.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval CPPSTAT This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
+ * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
+}
+
+/**
+ * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
+ * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval IPPSTAT This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
+ * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
+}
+
+/**
+ * @brief Set the event filter for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EEFLTR_NONE
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual event filter settings for a given timer.
+ * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
+ * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EEFLTR_NONE
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7
+ * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+ * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Enable or disable event latch mechanism for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param LatchStatus This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EELATCH_DISABLED
+ * @arg @ref LL_HRTIM_EELATCH_ENABLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
+ uint32_t LatchStatus)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual event latch status for a given timer.
+ * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
+ * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval LatchStatus This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EELATCH_DISABLED
+ * @arg @ref LL_HRTIM_EELATCH_ENABLED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+ REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Dead_Time_Configuration Dead_Time_Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure the dead time insertion feature for a given timer.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
+ * DTxR SDTF LL_HRTIM_DT_Config\n
+ * DTxR SDRT LL_HRTIM_DT_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
+}
+
+/**
+ * @brief Set the deadtime prescaler value.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
+}
+
+/**
+ * @brief Get actual deadtime prescaler value.
+ * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
+}
+
+/**
+ * @brief Set the deadtime rising value.
+ * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param RisingValue Value between 0 and 0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
+}
+
+/**
+ * @brief Get actual deadtime rising value.
+ * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval RisingValue Value between 0 and 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_DTR));
+}
+
+/**
+ * @brief Set the deadtime sign on rising edge.
+ * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param RisingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
+}
+
+/**
+ * @brief Get actual deadtime sign on rising edge.
+ * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval RisingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
+}
+
+/**
+ * @brief Set the deadime falling value.
+ * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param FallingValue Value between 0 and 0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
+}
+
+/**
+ * @brief Get actual deadtime falling value
+ * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval FallingValue Value between 0 and 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
+}
+
+/**
+ * @brief Set the deadtime sign on falling edge.
+ * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param FallingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
+}
+
+/**
+ * @brief Get actual deadtime sign on falling edge.
+ * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval FallingSign This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+ * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
+}
+
+/**
+ * @brief Lock the deadtime value and sign on rising edge.
+ * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTRLK);
+}
+
+/**
+ * @brief Lock the deadtime sign on rising edge.
+ * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
+}
+
+/**
+ * @brief Lock the deadtime value and sign on falling edge.
+ * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTFLK);
+}
+
+/**
+ * @brief Lock the deadtime sign on falling edge.
+ * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure the chopper stage for a given timer.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
+ * CHPxR CARDTY LL_HRTIM_CHP_Config\n
+ * CHPxR STRTPW LL_HRTIM_CHP_Config
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
+}
+
+/**
+ * @brief Set prescaler determining the carrier frequency to be added on top
+ * of the timer output signals when chopper mode is enabled.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
+}
+
+/**
+ * @brief Get actual chopper stage prescaler value.
+ * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+ * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
+}
+
+/**
+ * @brief Set the chopper duty cycle.
+ * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
+ * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
+}
+
+/**
+ * @brief Get actual chopper duty cycle.
+ * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+ * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
+}
+
+/**
+ * @brief Set the start pulse width.
+ * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
+ * @note This function must not be called if the chopper mode is already
+ * enabled for one of the timer outputs.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @param PulseWidth This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
+}
+
+/**
+ * @brief Get actual start pulse width.
+ * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval PulseWidth This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+ * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Output_Management Output_Management
+ * @{
+ */
+
+/**
+ * @brief Set the timer output set source.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param SetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ WRITE_REG(*pReg, SetSrc);
+}
+
+/**
+ * @brief Get the timer output set source.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
+ * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval SetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+ * @brief Set the timer output reset source.
+ * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param ResetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ WRITE_REG(*pReg, ResetSrc);
+}
+
+/**
+ * @brief Get the timer output set source.
+ * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
+ * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval ResetSrc This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_CROSSBAR_NONE
+ * @arg @ref LL_HRTIM_CROSSBAR_RESYNC
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMPER
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3
+ * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_1
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_2
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_3
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_4
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_5
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_6
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_7
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_8
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_9
+ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10
+ * @arg @ref LL_HRTIM_CROSSBAR_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput]));
+ return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+ * @brief Configure a timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
+ * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
+ * OUTxR CHP1 LL_HRTIM_OUT_Config\n
+ * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
+ * OUTxR POL2 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
+ * OUTxR CHP2 LL_HRTIM_OUT_Config\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
+ (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Set the polarity of a timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
+ * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual polarity of the timer output.
+ * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
+ * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+ * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output IDLE mode.
+ * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
+ * @note This function must not be called when the burst mode is active
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param IdleMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE
+ * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output IDLE mode.
+ * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
+ * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval IdleMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_NO_IDLE
+ * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_IDLM1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output IDLE level.
+ * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
+ * @note This function must be called prior enabling the timer.
+ * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param IdleLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output IDLE level.
+ * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
+ * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval IdleLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output FAULT state.
+ * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
+ * @note This function must not called when the timer is enabled and a fault
+ * channel is enabled at timer level.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param FaultState This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual FAULT state.
+ * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
+ * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval FaultState This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output chopper mode.
+ * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
+ * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
+ * @note This function must not called when the timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param ChopperMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output chopper mode
+ * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
+ * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval ChopperMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+ * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Set the output burst mode entry mode.
+ * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
+ * @note This function must not called when the timer is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param BMEntryMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+ * @brief Get actual output burst mode entry mode.
+ * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
+ * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval BMEntryMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+ * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return (READ_BIT(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput])) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+ * @brief Get the level (active or inactive) of the designated output when the
+ * delayed protection was triggered.
+ * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
+ * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1STAT << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+ HRTIM_TIMISR_O1STAT_Pos);
+}
+
+/**
+ * @brief Force the timer output to its active or inactive level.
+ * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
+ * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
+ * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
+ * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @param OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+ REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
+ SET_BIT(*pReg, HRTIM_SET1R_SST);
+}
+
+/**
+ * @brief Get actual output level, before the output stage (chopper, polarity).
+ * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
+ * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
+ * @param HRTIMx High Resolution Timer instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @retval OutputLevel This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+ * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+ register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+ REG_OFFSET_TAB_OUTxR[iOutput]));
+ return ((READ_BIT(*pReg, (HRTIM_TIMISR_O1CPY << REG_SHIFT_TAB_OxSTAT[iOutput])) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+ HRTIM_TIMISR_O1CPY_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_External_Event_management External_Event_management
+ * @{
+ */
+
+/**
+ * @brief Configure external event conditioning.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE1POL LL_HRTIM_EE_Config\n
+ * EECR1 EE1SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE1FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE2SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE2POL LL_HRTIM_EE_Config\n
+ * EECR1 EE2SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE2FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE3SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE3POL LL_HRTIM_EE_Config\n
+ * EECR1 EE3SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE3FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE4SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE4POL LL_HRTIM_EE_Config\n
+ * EECR1 EE4SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE4FAST LL_HRTIM_EE_Config\n
+ * EECR1 EE5SRC LL_HRTIM_EE_Config\n
+ * EECR1 EE5POL LL_HRTIM_EE_Config\n
+ * EECR1 EE5SNS LL_HRTIM_EE_Config\n
+ * EECR1 EE5FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE6SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE6POL LL_HRTIM_EE_Config\n
+ * EECR2 EE6SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE6FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE7SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE7POL LL_HRTIM_EE_Config\n
+ * EECR2 EE7SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE7FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE8SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE8POL LL_HRTIM_EE_Config\n
+ * EECR2 EE8SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE8FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE9SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE9POL LL_HRTIM_EE_Config\n
+ * EECR2 EE9SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE9FAST LL_HRTIM_EE_Config\n
+ * EECR2 EE10SRC LL_HRTIM_EE_Config\n
+ * EECR2 EE10POL LL_HRTIM_EE_Config\n
+ * EECR2 EE10SNS LL_HRTIM_EE_Config\n
+ * EECR2 EE10FAST LL_HRTIM_EE_Config
+ * @note This function must not be called when the timer counter is enabled.
+ * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
+ * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
+ (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Set the external event source.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
+ * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
+ * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1
+ * @arg @ref LL_HRTIM_EE_SRC_2
+ * @arg @ref LL_HRTIM_EE_SRC_3
+ * @arg @ref LL_HRTIM_EE_SRC_4
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual external event source.
+ * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
+ * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
+ * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval EventSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SRC_1
+ * @arg @ref LL_HRTIM_EE_SRC_2
+ * @arg @ref LL_HRTIM_EE_SRC_3
+ * @arg @ref LL_HRTIM_EE_SRC_4
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the polarity of an external event.
+ * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
+ * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
+ * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
+ * @note This function must not be called when the timer counter is enabled.
+ * @note Event polarity is only significant when event detection is level-sensitive.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+ * @arg @ref LL_HRTIM_EE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual polarity setting of an external event.
+ * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
+ * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
+ * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+ * @arg @ref LL_HRTIM_EE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the sensitivity of an external event.
+ * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
+ * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Sensitivity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual sensitivity setting of an external event.
+ * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
+ * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+ * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the fast mode of an external event.
+ * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
+ * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
+ * @note This function must not be called when the timer counter is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @param FastMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+ * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual fast mode setting of an external event.
+ * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
+ * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_1
+ * @arg @ref LL_HRTIM_EVENT_2
+ * @arg @ref LL_HRTIM_EVENT_3
+ * @arg @ref LL_HRTIM_EVENT_4
+ * @arg @ref LL_HRTIM_EVENT_5
+ * @retval FastMode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+ * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+ REG_OFFSET_TAB_EECR[iEvent]));
+ return (READ_BIT(*pReg, HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the digital noise filter of a external event.
+ * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
+ * EECR3 EE10F LL_HRTIM_EE_SetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FILTER_NONE
+ * @arg @ref LL_HRTIM_EE_FILTER_1
+ * @arg @ref LL_HRTIM_EE_FILTER_2
+ * @arg @ref LL_HRTIM_EE_FILTER_3
+ * @arg @ref LL_HRTIM_EE_FILTER_4
+ * @arg @ref LL_HRTIM_EE_FILTER_5
+ * @arg @ref LL_HRTIM_EE_FILTER_6
+ * @arg @ref LL_HRTIM_EE_FILTER_7
+ * @arg @ref LL_HRTIM_EE_FILTER_8
+ * @arg @ref LL_HRTIM_EE_FILTER_9
+ * @arg @ref LL_HRTIM_EE_FILTER_10
+ * @arg @ref LL_HRTIM_EE_FILTER_11
+ * @arg @ref LL_HRTIM_EE_FILTER_12
+ * @arg @ref LL_HRTIM_EE_FILTER_13
+ * @arg @ref LL_HRTIM_EE_FILTER_14
+ * @arg @ref LL_HRTIM_EE_FILTER_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+ MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
+ (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+ * @brief Get actual digital noise filter setting of a external event.
+ * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
+ * EECR3 EE10F LL_HRTIM_EE_GetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Event This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EVENT_6
+ * @arg @ref LL_HRTIM_EVENT_7
+ * @arg @ref LL_HRTIM_EVENT_8
+ * @arg @ref LL_HRTIM_EVENT_9
+ * @arg @ref LL_HRTIM_EVENT_10
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_FILTER_NONE
+ * @arg @ref LL_HRTIM_EE_FILTER_1
+ * @arg @ref LL_HRTIM_EE_FILTER_2
+ * @arg @ref LL_HRTIM_EE_FILTER_3
+ * @arg @ref LL_HRTIM_EE_FILTER_4
+ * @arg @ref LL_HRTIM_EE_FILTER_5
+ * @arg @ref LL_HRTIM_EE_FILTER_6
+ * @arg @ref LL_HRTIM_EE_FILTER_7
+ * @arg @ref LL_HRTIM_EE_FILTER_8
+ * @arg @ref LL_HRTIM_EE_FILTER_9
+ * @arg @ref LL_HRTIM_EE_FILTER_10
+ * @arg @ref LL_HRTIM_EE_FILTER_11
+ * @arg @ref LL_HRTIM_EE_FILTER_12
+ * @arg @ref LL_HRTIM_EE_FILTER_13
+ * @arg @ref LL_HRTIM_EE_FILTER_14
+ * @arg @ref LL_HRTIM_EE_FILTER_15
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+ register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
+ return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
+ (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent])) >> REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+ * @brief Set the external event prescaler.
+ * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+ * @retval None
+ */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
+}
+
+/**
+ * @brief Get actual external event prescaler setting.
+ * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+ */
+
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Fault_management Fault_management
+ * @{
+ */
+
+/**
+ * @brief Configure fault signal conditioning.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT or @ref LL_HRTIM_FLT_SRC_INTERNAL
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW or @ref LL_HRTIM_FLT_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),
+ (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Set the source of a fault signal.
+ * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+ * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual source of a fault signal.
+ * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
+ * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Src This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+ * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the polarity of a fault signal.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+ * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual polarity of a fault signal.
+ * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
+ * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Polarity This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+ * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the digital noise filter of a fault signal.
+ * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
+ * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter
+ * @note This function must not be called when the fault channel is enabled.
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @param Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_FILTER_NONE
+ * @arg @ref LL_HRTIM_FLT_FILTER_1
+ * @arg @ref LL_HRTIM_FLT_FILTER_2
+ * @arg @ref LL_HRTIM_FLT_FILTER_3
+ * @arg @ref LL_HRTIM_FLT_FILTER_4
+ * @arg @ref LL_HRTIM_FLT_FILTER_5
+ * @arg @ref LL_HRTIM_FLT_FILTER_6
+ * @arg @ref LL_HRTIM_FLT_FILTER_7
+ * @arg @ref LL_HRTIM_FLT_FILTER_8
+ * @arg @ref LL_HRTIM_FLT_FILTER_9
+ * @arg @ref LL_HRTIM_FLT_FILTER_10
+ * @arg @ref LL_HRTIM_FLT_FILTER_11
+ * @arg @ref LL_HRTIM_FLT_FILTER_12
+ * @arg @ref LL_HRTIM_FLT_FILTER_13
+ * @arg @ref LL_HRTIM_FLT_FILTER_14
+ * @arg @ref LL_HRTIM_FLT_FILTER_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Get actual digital noise filter setting of a fault signal.
+ * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
+ * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval Filter This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_FILTER_NONE
+ * @arg @ref LL_HRTIM_FLT_FILTER_1
+ * @arg @ref LL_HRTIM_FLT_FILTER_2
+ * @arg @ref LL_HRTIM_FLT_FILTER_3
+ * @arg @ref LL_HRTIM_FLT_FILTER_4
+ * @arg @ref LL_HRTIM_FLT_FILTER_5
+ * @arg @ref LL_HRTIM_FLT_FILTER_6
+ * @arg @ref LL_HRTIM_FLT_FILTER_7
+ * @arg @ref LL_HRTIM_FLT_FILTER_8
+ * @arg @ref LL_HRTIM_FLT_FILTER_9
+ * @arg @ref LL_HRTIM_FLT_FILTER_10
+ * @arg @ref LL_HRTIM_FLT_FILTER_11
+ * @arg @ref LL_HRTIM_FLT_FILTER_12
+ * @arg @ref LL_HRTIM_FLT_FILTER_13
+ * @arg @ref LL_HRTIM_FLT_FILTER_14
+ * @arg @ref LL_HRTIM_FLT_FILTER_15
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+ * @brief Set the fault circuitry prescaler.
+ * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
+}
+
+/**
+ * @brief Get actual fault circuitry prescaler setting.
+ * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
+
+}
+
+/**
+ * @brief Lock the fault signal conditioning settings.
+ * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
+ * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Enable the fault circuitry for the designated fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_Enable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Disable the fault circuitry for for the designated fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_Disable
+ * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+ * @brief Indicate whether the fault circuitry is enabled for a given fault input.
+ * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
+ * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled
+ * @param HRTIMx High Resolution Timer instance * @param HRTIMx High Resolution Timer instance
+ * @param Fault This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_FAULT_1
+ * @arg @ref LL_HRTIM_FAULT_2
+ * @arg @ref LL_HRTIM_FAULT_3
+ * @arg @ref LL_HRTIM_FAULT_4
+ * @arg @ref LL_HRTIM_FAULT_5
+ * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+ register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+ REG_OFFSET_TAB_FLTINR[iFault]));
+ return ((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
+ (HRTIM_IER_FLT1));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_Burst_Mode_management Burst_Mode_management
+ * @{
+ */
+
+/**
+ * @brief Configure the burst mode controller.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
+ * BMCR BMCLK LL_HRTIM_BM_Config\n
+ * BMCR BMPRSC LL_HRTIM_BM_Config
+ * @param HRTIMx High Resolution Timer instance
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
+}
+
+/**
+ * @brief Set the burst mode controller operating mode.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
+ * @param HRTIMx High Resolution Timer instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
+}
+
+/**
+ * @brief Get actual burst mode controller operating mode.
+ * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Mode This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+ * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
+}
+
+/**
+ * @brief Set the burst mode controller clock source.
+ * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @param ClockSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+ * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
+}
+
+/**
+ * @brief Get actual burst mode controller clock source.
+ * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
+ * @param HRTIMx High Resolution Timer instance
+ * @retval ClockSrc This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+ * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+ * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
+}
+
+/**
+ * @brief Set the burst mode controller prescaler.
+ * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+ MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
+}
+
+/**
+ * @brief Get actual burst mode controller prescaler setting.
+ * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+ * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
+}
+
+/**
+ * @brief Enable burst mode compare and period registers preload.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Disable burst mode compare and period registers preload.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Indicate whether burst mode compare and period registers are preloaded.
+ * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN) == HRTIM_BMCR_BMPREN);
+}
+
+/**
+ * @brief Set the burst mode controller trigger
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TERST LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
+ * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @param Trig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BM_TRIG_NONE
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
+}
+
+/**
+ * @brief Get actual burst mode controller trigger.
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TERST LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
+ * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Trig This parameter can be a combination of the following values:
+ * @arg @ref LL_HRTIM_BM_TRIG_NONE
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+ * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+ * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+ * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
+}
+
+/**
+ * @brief Set the burst mode controller compare value.
+ * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
+ * @param HRTIMx High Resolution Timer instance
+ * @param CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
+}
+
+/**
+ * @brief Get actual burst mode controller compare value.
+ * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
+ * @param HRTIMx High Resolution Timer instance
+ * @retval CompareValue Compare value must be above or equal to 3
+ * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+ * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
+}
+
+/**
+ * @brief Set the burst mode controller period.
+ * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
+ * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * The maximum value is 0x0000 FFDF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
+{
+ WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
+}
+
+/**
+ * @brief Get actual burst mode controller period.
+ * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
+ * @param HRTIMx High Resolution Timer instance
+ * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
+ * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+ * The maximum value is 0x0000 FFDF.
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
+{
+ return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
+}
+
+/**
+ * @brief Enable the burst mode controller
+ * @rmtoll BMCR BME LL_HRTIM_BM_Enable
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Disable the burst mode controller
+ * @rmtoll BMCR BME LL_HRTIM_BM_Disable
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Indicate whether the burst mode controller is enabled.
+ * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == HRTIM_BMCR_BME);
+}
+
+/**
+ * @brief Trigger the burst operation (software trigger)
+ * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
+}
+
+/**
+ * @brief Stop the burst mode operation.
+ * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
+ * @note Causes a burst mode early termination.
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
+}
+
+/**
+ * @brief Get actual burst mode status
+ * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
+ * @param HRTIMx High Resolution Timer instance
+ * @retval Status This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
+ * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Clear the Fault 1 interrupt flag.
+ * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
+}
+
+/**
+ * @brief Indicate whether Fault 1 interrupt occurred.
+ * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1));
+}
+
+/**
+ * @brief Clear the Fault 2 interrupt flag.
+ * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
+}
+
+/**
+ * @brief Indicate whether Fault 2 interrupt occurred.
+ * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2));
+}
+
+/**
+ * @brief Clear the Fault 3 interrupt flag.
+ * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
+}
+
+/**
+ * @brief Indicate whether Fault 3 interrupt occurred.
+ * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3));
+}
+
+/**
+ * @brief Clear the Fault 4 interrupt flag.
+ * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
+}
+
+/**
+ * @brief Indicate whether Fault 4 interrupt occurred.
+ * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4));
+}
+
+/**
+ * @brief Clear the Fault 5 interrupt flag.
+ * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
+}
+
+/**
+ * @brief Indicate whether Fault 5 interrupt occurred.
+ * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5));
+}
+
+/**
+ * @brief Clear the System Fault interrupt flag.
+ * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
+}
+
+/**
+ * @brief Indicate whether System Fault interrupt occurred.
+ * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT));
+}
+
+/**
+ * @brief Clear the DLL ready interrupt flag.
+ * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
+}
+
+/**
+ * @brief Indicate whether DLL ready interrupt occurred.
+ * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY));
+}
+
+/**
+ * @brief Clear the Burst Mode period interrupt flag.
+ * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
+}
+
+/**
+ * @brief Indicate whether Burst Mode period interrupt occurred.
+ * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER));
+}
+
+/**
+ * @brief Clear the Synchronization Input interrupt flag.
+ * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
+}
+
+/**
+ * @brief Indicate whether the Synchronization Input interrupt occurred.
+ * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC));
+}
+
+/**
+ * @brief Clear the update interrupt flag for a given timer (including the master timer) .
+ * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
+ * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MUPD);
+}
+
+/**
+ * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
+ * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD));
+}
+
+/**
+ * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
+ * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
+ * TIMxICR REPC LL_HRTIM_ClearFlag_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MREP);
+
+}
+
+/**
+ * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
+ * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP));
+}
+
+/**
+ * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
+ * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP1);
+}
+
+/**
+ * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
+ * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1));
+}
+
+/**
+ * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
+ * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP2);
+}
+
+/**
+ * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
+ * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2));
+}
+
+/**
+ * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
+ * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP3);
+}
+
+/**
+ * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
+ * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3));
+}
+
+/**
+ * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
+ * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
+ * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MICR_MCMP4);
+}
+
+/**
+ * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
+ * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
+ * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4));
+}
+
+/**
+ * @brief Clear the capture 1 interrupt flag for a given timer.
+ * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
+}
+
+/**
+ * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
+ * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1));
+}
+
+/**
+ * @brief Clear the capture 2 interrupt flag for a given timer.
+ * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
+}
+
+/**
+ * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
+ * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2));
+}
+
+/**
+ * @brief Clear the output 1 set interrupt flag for a given timer.
+ * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
+}
+
+/**
+ * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
+ * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1));
+}
+
+/**
+ * @brief Clear the output 1 reset interrupt flag for a given timer.
+ * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1));
+}
+
+/**
+ * @brief Clear the output 2 set interrupt flag for a given timer.
+ * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
+}
+
+/**
+ * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
+ * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2));
+}
+
+/**
+ * @brief Clear the output 2reset interrupt flag for a given timer.
+ * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2));
+}
+
+/**
+ * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
+ * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
+}
+
+/**
+ * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
+ * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST));
+}
+
+/**
+ * @brief Clear the delayed protection interrupt flag for a given timer.
+ * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMICR_DLYPRT1C);
+}
+
+/**
+ * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
+ * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the fault 1 interrupt.
+ * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+ * @brief Disable the fault 1 interrupt.
+ * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+ * @brief Indicate whether the fault 1 interrupt is enabled.
+ * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1));
+}
+
+/**
+ * @brief Enable the fault 2 interrupt.
+ * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+ * @brief Disable the fault 2 interrupt.
+ * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+ * @brief Indicate whether the fault 2 interrupt is enabled.
+ * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2));
+}
+
+/**
+ * @brief Enable the fault 3 interrupt.
+ * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+ * @brief Disable the fault 3 interrupt.
+ * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+ * @brief Indicate whether the fault 3 interrupt is enabled.
+ * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3));
+}
+
+/**
+ * @brief Enable the fault 4 interrupt.
+ * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+ * @brief Disable the fault 4 interrupt.
+ * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+ * @brief Indicate whether the fault 4 interrupt is enabled.
+ * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4));
+}
+
+/**
+ * @brief Enable the fault 5 interrupt.
+ * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+ * @brief Disable the fault 5 interrupt.
+ * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+ * @brief Indicate whether the fault 5 interrupt is enabled.
+ * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5));
+}
+
+/**
+ * @brief Enable the system fault interrupt.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+ * @brief Disable the system fault interrupt.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+ * @brief Indicate whether the system fault interrupt is enabled.
+ * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT));
+}
+
+/**
+ * @brief Enable the DLL ready interrupt.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+ * @brief Disable the DLL ready interrupt.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+ * @brief Indicate whether the DLL ready interrupt is enabled.
+ * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY));
+}
+
+/**
+ * @brief Enable the burst mode period interrupt.
+ * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+ * @brief Disable the burst mode period interrupt.
+ * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+ * @brief Indicate whether the burst mode period interrupt is enabled.
+ * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER));
+}
+
+/**
+ * @brief Enable the synchronization input interrupt.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+ * @brief Disable the synchronization input interrupt.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+ * @brief Indicate whether the synchronization input interrupt is enabled.
+ * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE));
+}
+
+/**
+ * @brief Enable the update interrupt for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+ * @brief Disable the update interrupt for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+ * @brief Indicate whether the update interrupt is enabled for a given timer.
+ * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
+ * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE));
+}
+
+/**
+ * @brief Enable the repetition interrupt for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+ * @brief Disable the repetition interrupt for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+ * @brief Indicate whether the repetition interrupt is enabled for a given timer.
+ * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
+ * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE));
+}
+
+/**
+ * @brief Enable the compare 1 interrupt for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+ * @brief Disable the compare 1 interrupt for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+ * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
+ * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE));
+}
+
+/**
+ * @brief Enable the compare 2 interrupt for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+ * @brief Disable the compare 2 interrupt for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+ * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
+ * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE));
+}
+
+/**
+ * @brief Enable the compare 3 interrupt for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+ * @brief Disable the compare 3 interrupt for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+ * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
+ * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE));
+}
+
+/**
+ * @brief Enable the compare 4 interrupt for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+ * @brief Disable the compare 4 interrupt for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+ * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
+ * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
+ * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE));
+}
+
+/**
+ * @brief Enable the capture 1 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+ * @brief Enable the capture 1 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+ * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE));
+}
+
+/**
+ * @brief Enable the capture 2 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+ * @brief Enable the capture 2 interrupt for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+ * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE));
+}
+
+/**
+ * @brief Enable the output 1 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+ * @brief Disable the output 1 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+ * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE));
+}
+
+/**
+ * @brief Enable the output 1 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+ * @brief Disable the output 1 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE));
+}
+
+/**
+ * @brief Enable the output 2 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+ * @brief Disable the output 2 set interrupt for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+ * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE));
+}
+
+/**
+ * @brief Enable the output 2 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+ * @brief Disable the output 2 reset interrupt for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
+ * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE));
+}
+
+/**
+ * @brief Enable the reset/roll-over interrupt for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+ * @brief Disable the reset/roll-over interrupt for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+ * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE));
+}
+
+/**
+ * @brief Enable the delayed protection interrupt for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+ * @brief Disable the delayed protection interrupt for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+ * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable the synchronization input DMA request.
+ * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+ * @brief Disable the synchronization input DMA request
+ * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+ * @brief Indicate whether the synchronization input DMA request is enabled.
+ * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
+ * @param HRTIMx High Resolution Timer instance
+ * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+ return (READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE));
+}
+
+/**
+ * @brief Enable the update DMA request for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+ * @brief Disable the update DMA request for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+ * @brief Indicate whether the update DMA request is enabled for a given timer.
+ * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
+ * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE));
+}
+
+/**
+ * @brief Enable the repetition DMA request for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+ * @brief Disable the repetition DMA request for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+ * @brief Indicate whether the repetition DMA request is enabled for a given timer.
+ * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
+ * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE));
+}
+
+/**
+ * @brief Enable the compare 1 DMA request for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+ * @brief Disable the compare 1 DMA request for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+ * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
+ * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE));
+}
+
+/**
+ * @brief Enable the compare 2 DMA request for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+ * @brief Disable the compare 2 DMA request for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+ * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
+ * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE));
+}
+
+/**
+ * @brief Enable the compare 3 DMA request for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+ * @brief Disable the compare 3 DMA request for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+ * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
+ * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE));
+}
+
+/**
+ * @brief Enable the compare 4 DMA request for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+ * @brief Disable the compare 4 DMA request for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+ * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
+ * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
+ * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_MASTER
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE));
+}
+
+/**
+ * @brief Enable the capture 1 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+ * @brief Disable the capture 1 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+ * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE));
+}
+
+/**
+ * @brief Enable the capture 2 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+ * @brief Disable the capture 2 DMA request for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+ * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE));
+}
+
+/**
+ * @brief Enable the output 1 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+ * @brief Disable the output 1 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+ * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE));
+}
+
+/**
+ * @brief Enable the output 1 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+ * @brief Disable the output 1 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+ * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
+ * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE));
+}
+
+/**
+ * @brief Enable the output 2 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+ * @brief Disable the output 2 set DMA request for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+ * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE));
+}
+
+/**
+ * @brief Enable the output 2 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+ * @brief Disable the output 2 reset DMA request for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+ * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE));
+}
+
+/**
+ * @brief Enable the reset/roll-over DMA request for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+ * @brief Disable the reset/roll-over DMA request for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+ * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE));
+}
+
+/**
+ * @brief Enable the delayed protection DMA request for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+ * @brief Disable the delayed protection DMA request for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval None
+ */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+ * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
+ * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
+ * @param HRTIMx High Resolution Timer instance
+ * @param Timer This parameter can be one of the following values:
+ * @arg @ref LL_HRTIM_TIMER_A
+ * @arg @ref LL_HRTIM_TIMER_B
+ * @arg @ref LL_HRTIM_TIMER_C
+ * @arg @ref LL_HRTIM_TIMER_D
+ * @arg @ref LL_HRTIM_TIMER_E
+ * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+ register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+ REG_OFFSET_TAB_TIMER[iTimer]));
+ return (READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup HRTIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_i2c.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,252 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_i2c.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_i2c.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+ ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+#if defined(I2C2)
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+#endif
+#if defined(I2C3)
+ else if (I2Cx == I2C3)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+ assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /*---------------------------- I2Cx CR1 Configuration ------------------------
+ * Configure the analog and digital noise filters with parameters :
+ * - AnalogFilter: I2C_CR1_ANFOFF bit
+ * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+ */
+ LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+ /*---------------------------- I2Cx TIMINGR Configuration --------------------
+ * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+ * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+ * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+ */
+ LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+ LL_I2C_EnableOwnAddress1(I2Cx);
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->Timing = 0U;
+ I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ I2C_InitStruct->DigitalFilter = 0U;
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_i2c.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2246 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_i2c.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of I2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_I2C_H
+#define __STM32F3xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
+ This parameter must be set by referring to the STM32CubeMX Tool and
+ the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+
+ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+
+ uint32_t DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_WriteReg function
+ * @{
+ */
+#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
+#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
+#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
+#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
+#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
+#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
+#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
+#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
+#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_ReadReg function
+ * @{
+ */
+#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
+#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
+#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
+#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
+#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
+#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
+#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
+#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
+#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
+#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
+#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
+#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
+#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
+ * @{
+ */
+#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
+#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
+#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
+#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
+#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
+#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
+#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
+ * @{
+ */
+#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /*!< Analog filter is enabled. */
+#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
+ * @{
+ */
+#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */
+#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
+ * @{
+ */
+#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
+#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_I2C_ACK ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
+ * @{
+ */
+#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /*!< Slave Address in 7-bit. */
+#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
+ * @{
+ */
+#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /*!< Master request a write transfer. */
+#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_MODE Transfer End Mode
+ * @{
+ */
+#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
+#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /*!< Enable I2C Software end mode with no HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
+ * @{
+ */
+#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /*!< Write transfer request by master, slave enters receiver mode. */
+#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /*!< Get address of data register used for transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout. */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
+ * @{
+ */
+#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
+#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
+#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
+ * @{
+ */
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+ * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
+ * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
+ * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
+ * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+ * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
+ */
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable I2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_I2C_Enable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Disable I2C peripheral (PE = 0).
+ * @note When PE = 0, the I2C SCL and SDA lines are released.
+ * Internal state machines and status bits are put back to their reset value.
+ * When cleared, PE must be kept low for at least 3 APB clock cycles.
+ * @rmtoll CR1 PE LL_I2C_Disable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the I2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_I2C_IsEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+/**
+ * @brief Configure Noise Filters (Analog and Digital).
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * The filters can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
+ * CR1 DNF LL_I2C_ConfigFilters
+ * @param I2Cx I2C Instance.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
+ * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+}
+
+/**
+ * @brief Configure Digital Noise Filter.
+ * @note If the analog filter is also enabled, the digital filter is added to analog filter.
+ * This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+ * This parameter is used to configure the digital noise filter on SDA and SCL input.
+ * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Get the current Digital Noise Filter configuration.
+ * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
+}
+
+/**
+ * @brief Enable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Disable Analog Noise Filter.
+ * @note This filter can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
+}
+
+/**
+ * @brief Check if Analog Noise Filter is enabled or disabled.
+ * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+}
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
+ * RXDR RXDATA LL_I2C_DMA_GetRegAddr
+ * @param I2Cx I2C Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TXDR register */
+ data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+ }
+ else
+ {
+ /* return address of RXDR register */
+ data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+ * @brief Enable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Disable hardware byte control in slave mode.
+ * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
+}
+
+/**
+ * @brief Check if hardware byte control in slave mode is enabled or disabled.
+ * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+}
+
+/**
+ * @brief Enable Wakeup from STOP.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when Digital Filter is disabled.
+ * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Disable Wakeup from STOP.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
+}
+
+/**
+ * @brief Check if Wakeup from STOP is enabled or disabled.
+ * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * WakeUpFromStop feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
+}
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+}
+
+/**
+ * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
+ * @note Changing this bit is not allowed, when the START bit is set.
+ * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @param AddressingMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
+}
+
+/**
+ * @brief Get the Master addressing mode.
+ * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
+ * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
+ * OAR1 OA1MODE LL_I2C_SetOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_I2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address1 match address.
+ * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
+ * OAR2 OA2MSK LL_I2C_SetOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
+ * @param OwnAddrMask This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK01
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK02
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK03
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK04
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK05
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK06
+ * @arg @ref LL_I2C_OWNADDRESS2_MASK07
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
+{
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+}
+
+/**
+ * @brief Configure the SDA setup, hold time and the SCL high, low period.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
+ * @param I2Cx I2C Instance.
+ * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
+ * @note This parameter is computed with the STM32CubeMX Tool.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
+{
+ WRITE_REG(I2Cx->TIMINGR, Timing);
+}
+
+/**
+ * @brief Get the Timing Prescaler setting.
+ * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
+}
+
+/**
+ * @brief Get the SCL low period setting.
+ * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
+}
+
+/**
+ * @brief Get the SCL high period setting.
+ * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
+}
+
+/**
+ * @brief Get the SDA hold time.
+ * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
+}
+
+/**
+ * @brief Get the SDA setup time.
+ * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
+ * CR1 SMBDEN LL_I2C_SetMode
+ * @param I2Cx I2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
+ * CR1 SMBDEN LL_I2C_GetMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+}
+
+/**
+ * @brief Configure the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
+ * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @param TimeoutB
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
+ uint32_t TimeoutB)
+{
+ MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
+ TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
+}
+
+/**
+ * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA setting.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
+}
+
+/**
+ * @brief Set the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This bit can only be programmed when TimeoutA is disabled.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @param TimeoutAMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
+}
+
+/**
+ * @brief Get the SMBus Clock TimeoutA mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
+}
+
+/**
+ * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note These bits can only be programmed when TimeoutB is disabled.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
+{
+ WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
+}
+
+/**
+ * @brief Enable the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Disable the SMBus Clock Timeout.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
+}
+
+/**
+ * @brief Check if the SMBus Clock Timeout is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
+ * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
+ * @param I2Cx I2C Instance.
+ * @param ClockTimeout This parameter can be one of the following values:
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTA
+ * @arg @ref LL_I2C_SMBUS_TIMEOUTB
+ * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+{
+ return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Disable TXIS interrupt.
+ * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
+}
+
+/**
+ * @brief Check if the TXIS Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+}
+
+/**
+ * @brief Enable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Disable Address match interrupt (slave mode only).
+ * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
+}
+
+/**
+ * @brief Check if Address match interrupt is enabled or disabled.
+ * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+}
+
+/**
+ * @brief Enable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Disable Not acknowledge received interrupt.
+ * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
+}
+
+/**
+ * @brief Check if Not acknowledge received interrupt is enabled or disabled.
+ * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+}
+
+/**
+ * @brief Enable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Disable STOP detection interrupt.
+ * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
+}
+
+/**
+ * @brief Check if STOP detection interrupt is enabled or disabled.
+ * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+}
+
+/**
+ * @brief Enable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Disable Transfer Complete interrupt.
+ * @note Any of these events will generate interrupt :
+ * Transfer Complete (TC)
+ * Transfer Complete Reload (TCR)
+ * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
+}
+
+/**
+ * @brief Check if Transfer Complete interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Arbitration Loss (ARLO)
+ * Bus Error detection (BERR)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (ALERT)
+ * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+}
+
+/**
+ * @brief Indicate the status of Transmit interrupt flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+}
+
+/**
+ * @brief Indicate the status of Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the received slave address matched with one of the enabled slave address.
+ * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+}
+
+/**
+ * @brief Indicate the status of Not Acknowledge received flag.
+ * @note RESET: Clear default value.
+ * SET: When a NACK is received after a byte transmission.
+ * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag.
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
+ * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+}
+
+/**
+ * @brief Indicate the status of Transfer complete flag (master mode).
+ * @note RESET: Clear default value.
+ * SET: When RELOAD=1 and NBYTES date have been transferred.
+ * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When the received PEC does not match with the PEC register content.
+ * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When a timeout or extended clock timeout occurs.
+ * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: Clear default value.
+ * SET: When SMBus host configuration, SMBus alert enabled and
+ * a falling edge event occurs on SMBA pin.
+ * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
+}
+
+/**
+ * @brief Clear Not Acknowledge flag.
+ * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+}
+
+/**
+ * @brief Clear Transmit data register empty flag (TXE).
+ * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
+ * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable automatic STOP condition generation (master mode).
+ * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
+ * This bit has no effect in slave mode or when RELOAD bit is set.
+ * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Disable automatic STOP condition generation (master mode).
+ * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
+ * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+}
+
+/**
+ * @brief Check if automatic STOP condition is enabled or disabled.
+ * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+}
+
+/**
+ * @brief Enable reload mode (master mode).
+ * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
+ * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Disable reload mode (master mode).
+ * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
+ * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
+}
+
+/**
+ * @brief Check if reload mode is enabled or disabled.
+ * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+}
+
+/**
+ * @brief Configure the number of bytes for transfer.
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
+ * @param I2Cx I2C Instance.
+ * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Get the number of bytes configured for transfer.
+ * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave mode only.
+ * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
+ * @param I2Cx I2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ACK
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR2 START LL_I2C_GenerateStartCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
+}
+
+/**
+ * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master sends the complete 10bit slave address read sequence :
+ * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
+ * @note The master only sends the first 7 bits of 10bit address in Read direction.
+ * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
+}
+
+/**
+ * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
+ * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+}
+
+/**
+ * @brief Configure the transfer direction (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @param TransferRequest This parameter can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
+}
+
+/**
+ * @brief Get the transfer direction requested (master mode).
+ * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_REQUEST_WRITE
+ * @arg @ref LL_I2C_REQUEST_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
+}
+
+/**
+ * @brief Configure the slave address for transfer (master mode).
+ * @note Changing these bits when START bit is set is not allowed.
+ * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
+}
+
+/**
+ * @brief Get the slave address programmed for transfer.
+ * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
+ * CR2 ADD10 LL_I2C_HandleTransfer\n
+ * CR2 RD_WRN LL_I2C_HandleTransfer\n
+ * CR2 START LL_I2C_HandleTransfer\n
+ * CR2 STOP LL_I2C_HandleTransfer\n
+ * CR2 RELOAD LL_I2C_HandleTransfer\n
+ * CR2 NBYTES LL_I2C_HandleTransfer\n
+ * CR2 AUTOEND LL_I2C_HandleTransfer\n
+ * CR2 HEAD10R LL_I2C_HandleTransfer
+ * @param I2Cx I2C Instance.
+ * @param SlaveAddr Specifies the slave address to be programmed.
+ * @param SlaveAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ADDRSLAVE_7BIT
+ * @arg @ref LL_I2C_ADDRSLAVE_10BIT
+ * @param TransferSize Specifies the number of bytes to be programmed.
+ * This parameter must be a value between Min_Data=0 and Max_Data=255.
+ * @param EndMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_RELOAD
+ * @arg @ref LL_I2C_MODE_AUTOEND
+ * @arg @ref LL_I2C_MODE_SOFTEND
+ * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
+ * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
+ * @param Request This parameter can be one of the following values:
+ * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
+ * @arg @ref LL_I2C_GENERATE_STOP
+ * @arg @ref LL_I2C_GENERATE_START_READ
+ * @arg @ref LL_I2C_GENERATE_START_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
+ * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+}
+
+/**
+ * @brief Indicate the value of transfer direction (slave mode).
+ * @note RESET: Write transfer, Slave enters in receiver mode.
+ * SET: Read transfer, Slave enters in transmitter mode.
+ * @rmtoll ISR DIR LL_I2C_GetTransferDirection
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DIRECTION_WRITE
+ * @arg @ref LL_I2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
+}
+
+/**
+ * @brief Return the slave matched address.
+ * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
+}
+
+/**
+ * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+ * This bit has no effect when RELOAD bit is set.
+ * This bit has no effect in device mode when SBC bit is not set.
+ * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+*/
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+ return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
+ * @param I2Cx I2C Instance.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ WRITE_REG(I2Cx->TXDR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_iwdg.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,363 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_IWDG_H
+#define __STM32F3xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+#define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU) /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU) /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U) /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U) /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
+#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U) /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+/**
+ * @brief Specify high limit of the window value to be compared to the down-counter.
+ * @rmtoll WINR WIN LL_IWDG_SetWindow
+ * @param IWDGx IWDG Instance
+ * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
+{
+ WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
+}
+
+/**
+ * @brief Get the high limit of the window value specified.
+ * @rmtoll WINR WIN LL_IWDG_GetWindow
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->WINR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+/**
+ * @brief Check if flag Window Value Update is set or not
+ * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+}
+
+/**
+ * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR WVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_opamp.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,256 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_opamp.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief OPAMP LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_opamp.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
+
+/** @addtogroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup OPAMP_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of OPAMP hierarchical scope: */
+/* OPAMP instance. */
+
+#define IS_LL_OPAMP_FUNCTIONAL_MODE(__FUNCTIONAL_MODE__) \
+ ( ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_STANDALONE) \
+ || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_FOLLOWER) \
+ || ((__FUNCTIONAL_MODE__) == LL_OPAMP_MODE_PGA) \
+ )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \
+ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO1) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO2) \
+ || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO3) \
+ )
+
+/* Note: Comparator non-inverting inputs parameters are the same on all */
+/* OPAMP instances. */
+/* However, comparator instance kept as macro parameter for */
+/* compatibility with other STM32 families. */
+#define IS_LL_OPAMP_INPUT_INVERTING(__OPAMPX__, __INPUT_INVERTING__) \
+ ( ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO0) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_IO1) \
+ || ((__INPUT_INVERTING__) == LL_OPAMP_INPUT_INVERT_CONNECT_NO) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup OPAMP_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup OPAMP_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected OPAMP instance
+ * to their default reset values.
+ * @note If comparator is locked, de-initialization by software is
+ * not possible.
+ * The only way to unlock the comparator is a device hardware reset.
+ * @param OPAMPx OPAMP instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are de-initialized
+ * - ERROR: OPAMP registers are not de-initialized
+ */
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* OPAMP instance must not be locked. */
+ if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
+ {
+ LL_OPAMP_WriteReg(OPAMPx, CSR, 0x00000000U);
+ }
+ else
+ {
+ /* OPAMP instance is locked: de-initialization by software is */
+ /* not possible. */
+ /* The only way to unlock the OPAMP is a device hardware reset. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of OPAMP instance.
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @param OPAMPx OPAMP instance
+ * @param OPAMP_InitStruct Pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: OPAMP registers are initialized
+ * - ERROR: OPAMP registers are not initialized
+ */
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx));
+ assert_param(IS_LL_OPAMP_FUNCTIONAL_MODE(OPAMP_InitStruct->FunctionalMode));
+ assert_param(IS_LL_OPAMP_INPUT_NONINVERTING(OPAMPx, OPAMP_InitStruct->InputNonInverting));
+
+ /* Note: OPAMP inverting input can be used with OPAMP in mode standalone */
+ /* or PGA with external capacitors for filtering circuit. */
+ /* Otherwise (OPAMP in mode follower), OPAMP inverting input is */
+ /* not used (not connected to GPIO pin). */
+ if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ assert_param(IS_LL_OPAMP_INPUT_INVERTING(OPAMPx, OPAMP_InitStruct->InputInverting));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* OPAMP instance must not be locked. */
+ if(LL_OPAMP_IsLocked(OPAMPx) == 0U)
+ {
+ /* Configuration of OPAMP instance : */
+ /* - Functional mode */
+ /* - Input non-inverting */
+ /* - Input inverting */
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode. */
+ if(OPAMP_InitStruct->FunctionalMode != LL_OPAMP_MODE_FOLLOWER)
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_CALON
+ | OPAMP_CSR_VMSEL
+ | OPAMP_CSR_VPSEL
+ ,
+ OPAMP_InitStruct->FunctionalMode
+ | OPAMP_InitStruct->InputNonInverting
+ | OPAMP_InitStruct->InputInverting
+ );
+ }
+ else
+ {
+ MODIFY_REG(OPAMPx->CSR,
+ OPAMP_CSR_CALON
+ | OPAMP_CSR_VMSEL
+ | OPAMP_CSR_VPSEL
+ ,
+ LL_OPAMP_MODE_FOLLOWER
+ | OPAMP_InitStruct->InputNonInverting
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: OPAMP instance is locked. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_OPAMP_InitTypeDef field to default value.
+ * @param OPAMP_InitStruct pointer to a @ref LL_OPAMP_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
+{
+ /* Set OPAMP_InitStruct fields to default values */
+ OPAMP_InitStruct->FunctionalMode = LL_OPAMP_MODE_FOLLOWER;
+ OPAMP_InitStruct->InputNonInverting = LL_OPAMP_INPUT_NONINVERT_IO0;
+ /* Note: Parameter discarded if OPAMP in functional mode follower, */
+ /* set anyway to its default value. */
+ OPAMP_InitStruct->InputInverting = LL_OPAMP_INPUT_INVERT_CONNECT_NO;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_opamp.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,905 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_opamp.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of OPAMP LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_OPAMP_H
+#define __STM32F3xx_LL_OPAMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
+
+/** @defgroup OPAMP_LL OPAMP
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
+ * @{
+ */
+
+/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
+/* or PMOS. */
+/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
+/* - OPAMP trimming selection of transistors differential pair */
+/* - OPAMP trimming values of transistors differential pair */
+#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
+#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Register address
+*/
+#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
+
+
+
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of OPAMP instance.
+ */
+typedef struct
+{
+ uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
+ This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
+ @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
+
+ uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
+
+ uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
+ This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
+ @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
+
+} LL_OPAMP_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
+ * @{
+ */
+#define LL_OPAMP_MODE_FUNCTIONAL ((uint32_t)0x00000000U) /*!< OPAMP functional mode */
+#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
+ * @{
+ */
+#define LL_OPAMP_MODE_STANDALONE ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */
+#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< OPAMP functional mode, OPAMP operation in follower */
+#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
+#define LL_OPAMP_MODE_PGA_EXT_FILT_IO0 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO0. */
+#define LL_OPAMP_MODE_PGA_EXT_FILT_IO1 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO1. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
+ * @{
+ */
+#define LL_OPAMP_PGA_GAIN_2 ((uint32_t)0x00000000U) /*!< OPAMP PGA gain 2 */
+#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */
+#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */
+#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO1 ((uint32_t)0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
+ * @{
+ */
+#define LL_OPAMP_INPUT_INVERT_IO0 ((uint32_t)0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
+ * @{
+ */
+#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (LL_OPAMP_INPUT_NONINVERT_IO0 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC (LL_OPAMP_INPUT_NONINVERT_IO1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC (LL_OPAMP_INPUT_NONINVERT_IO2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC (LL_OPAMP_INPUT_NONINVERT_IO3 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA5 for OPAMP1, pin PD14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
+#define LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
+ * @{
+ */
+#define LL_OPAMP_INPUT_INVERT_IO0_SEC (LL_OPAMP_INPUT_INVERT_IO0 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+#define LL_OPAMP_INPUT_INVERT_IO1_SEC (LL_OPAMP_INPUT_INVERT_IO1 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
+ * @{
+ */
+#define LL_OPAMP_INPUT_MUX_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP inputs multiplexer mode dosabled. */
+#define LL_OPAMP_INPUT_MUX_TIM1_CH6 (OPAMP_CSR_TCMEN) /*!< OPAMP inputs multiplexer mode enabled, controlled by TIM1 CC6. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_VREF_OUTPUT OPAMP internal reference voltage path state to output
+ * @{
+ */
+#define LL_OPAMP_VREF_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< OPAMP internal reference voltage path to output is disabled. */
+#define LL_OPAMP_VREF_OUTPUT_ENABLE (OPAMP_CSR_TSTREF) /*!< OPAMP internal reference voltage path to output is enabled. */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
+#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
+ * @{
+ */
+#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
+#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
+#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
+ * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for OPAMP startup time (transition from state disable to enable). */
+/* Note: OPAMP startup time depends on board application environment: */
+/* impedance connected to OPAMP output. */
+/* The delay below is specified under conditions: */
+/* - OPAMP in functional mode follower */
+/* - load impedance of 4kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 5U) /*!< Delay for OPAMP startup time */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
+ * @{
+ */
+/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
+ * @{
+ */
+/**
+ * @brief Write a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in OPAMP register
+ * @param __INSTANCE__ OPAMP Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @rmtoll CSR CALON LL_OPAMP_SetMode
+ * @param OPAMPx OPAMP instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
+}
+
+/**
+ * @brief Get OPAMP mode calibration or functional.
+ * @note OPAMP mode corresponds to functional or calibration mode:
+ * - functional mode: OPAMP operation in standalone, follower, ...
+ * Set functional mode using function
+ * @ref LL_OPAMP_SetFunctionalMode().
+ * - calibration mode: offset calibration of the selected
+ * transistors differential pair NMOS or PMOS.
+ * @rmtoll CSR CALON LL_OPAMP_GetMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_FUNCTIONAL
+ * @arg @ref LL_OPAMP_MODE_CALIBRATION
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
+}
+
+/**
+ * @brief Set OPAMP functional mode by setting internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @note This function reset bit of calibration mode to ensure
+ * to be in functional mode, in order to have OPAMP parameters
+ * (inputs selection, ...) set with the corresponding OPAMP mode
+ * to be effective.
+ * @rmtoll CSR VMSEL LL_OPAMP_SetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @param FunctionalMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
+{
+ /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
+}
+
+/**
+ * @brief Get OPAMP functional mode from setting of internal connections.
+ * OPAMP operation in standalone, follower, ...
+ * @rmtoll CSR VMSEL LL_OPAMP_GetFunctionalMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_MODE_STANDALONE
+ * @arg @ref LL_OPAMP_MODE_FOLLOWER
+ * @arg @ref LL_OPAMP_MODE_PGA
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
+ * @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
+}
+
+/**
+ * @brief Set OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @param PGAGain This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
+}
+
+/**
+ * @brief Get OPAMP PGA gain.
+ * @note Preliminarily, OPAMP must be set in mode PGA
+ * using function @ref LL_OPAMP_SetFunctionalMode().
+ * @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_PGA_GAIN_2
+ * @arg @ref LL_OPAMP_PGA_GAIN_4
+ * @arg @ref LL_OPAMP_PGA_GAIN_8
+ * @arg @ref LL_OPAMP_PGA_GAIN_16
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputNonInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
+}
+
+/**
+ * @brief Get OPAMP non-inverting input connection.
+ * @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
+}
+
+/**
+ * @brief Set OPAMP inverting input connection.
+ * @note OPAMP inverting input is used with OPAMP in mode standalone
+ * or PGA with external capacitors for filtering circuit.
+ * Otherwise (OPAMP in mode follower), OPAMP inverting input
+ * is not used (not connected to GPIO pin).
+ * @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @param InputInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+ /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11) */
+ /* to not modify OPAMP mode follower or PGA. */
+ /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
+ MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
+}
+
+/**
+ * @brief Get OPAMP inverting input connection.
+ * @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1
+ * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
+{
+ register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
+
+ /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
+ /* input not connected. */
+ return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
+}
+
+/**
+ * @brief Set OPAMP non-inverting input secondary connection.
+ * @rmtoll CSR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @param InputNonInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSSEL, InputNonInverting);
+}
+
+/**
+ * @brief Get OPAMP non-inverting input secondary connection.
+ * @rmtoll CSR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
+ * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
+ *
+ * (1) Parameter specific to OPAMP instances: OPAMP4.\n
+ * (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSSEL));
+}
+
+/**
+ * @brief Set OPAMP inverting input secondary connection.
+ * @note OPAMP inverting input is used with OPAMP in mode standalone
+ * or PGA with external capacitors for filtering circuit.
+ * Otherwise (OPAMP in mode follower), OPAMP inverting input
+ * is not used (not connected to GPIO pin).
+ * @rmtoll CSR VMSSEL LL_OPAMP_SetInputInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @param InputInverting This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary (OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSSEL, InputInverting);
+}
+
+/**
+ * @brief Get OPAMP inverting input secondary connection.
+ * @rmtoll CSR VMSSEL LL_OPAMP_GetInputInvertingSecondary
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
+ * @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSSEL));
+}
+
+/**
+ * @brief Set OPAMP inputs multiplexer mode.
+ * @rmtoll CSR TCMEN LL_OPAMP_SetInputsMuxMode
+ * @param OPAMPx OPAMP instance
+ * @param InputsMuxMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
+ * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TCMEN, InputsMuxMode);
+}
+
+/**
+ * @brief Get OPAMP inputs multiplexer mode.
+ * @rmtoll CSR TCMEN LL_OPAMP_GetInputsMuxMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
+ * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TCMEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
+ * @{
+ */
+
+/**
+ * @brief Set OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @param TrimmingMode This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
+}
+
+/**
+ * @brief Get OPAMP trimming mode.
+ * @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_FACTORY
+ * @arg @ref LL_OPAMP_TRIMMING_USER
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
+}
+
+/**
+ * @brief Set OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
+ *
+ * (1) Default parameters to be used for calibration
+ * using two trimming steps (one with each transistors differential
+ * pair NMOS and PMOS)
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
+{
+ /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
+ /* containing other bits reserved for other purpose. */
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
+}
+
+/**
+ * @brief Get OPAMP offset to calibrate the selected transistors
+ * differential pair NMOS or PMOS.
+ * @note Preliminarily, OPAMP must be set in mode calibration
+ * using function @ref LL_OPAMP_SetMode().
+ * @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
+ *
+ * (1) Default parameters to be used for calibration
+ * using two trimming steps (one with each transistors differential
+ * pair NMOS and PMOS)
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
+{
+ register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+
+ return (CalibrationSelection |
+ ((OPAMP_CSR_TRIMOFFSETN) << (POSITION_VAL(OPAMP_CSR_TRIMOFFSETP) * (CalibrationSelection && OPAMP_CSR_CALSEL))));
+}
+
+/**
+ * @brief Set OPAMP calibration internal reference voltage to output.
+ * @rmtoll CSR TSTREF LL_OPAMP_SetCalibrationVrefOutput
+ * @param OPAMPx OPAMP instance
+ * @param CalibrationVrefOutput This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx, uint32_t CalibrationVrefOutput)
+{
+ MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TSTREF, CalibrationVrefOutput);
+}
+
+/**
+ * @brief Get OPAMP calibration internal reference voltage to output.
+ * @rmtoll CSR TSTREF LL_OPAMP_GetCalibrationVrefOutput
+ * @param OPAMPx OPAMP instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
+ * @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TSTREF));
+}
+
+/**
+ * @brief Get OPAMP calibration result of toggling output.
+ * @note This functions returns:
+ * 0 if OPAMP calibration output is reset
+ * 1 if OPAMP calibration output is set
+ * @rmtoll CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL);
+}
+
+/**
+ * @brief Set OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue\n
+ * CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @param TrimmingValue 0x00...0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
+{
+ MODIFY_REG(OPAMPx->CSR,
+ (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
+ TrimmingValue << (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)));
+}
+
+/**
+ * @brief Get OPAMP trimming factor for the selected transistors
+ * differential pair NMOS or PMOS, corresponding to the selected
+ * power mode.
+ * @rmtoll CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue\n
+ * CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
+ * @param OPAMPx OPAMP instance
+ * @param TransistorsDiffPair This parameter can be one of the following values:
+ * @arg @ref LL_OPAMP_TRIMMING_NMOS
+ * @arg @ref LL_OPAMP_TRIMMING_PMOS
+ * @retval 0x0...0x1F
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair)
+{
+ return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+ >> (POSITION_VAL(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
+ * @{
+ */
+/**
+ * @brief Enable OPAMP instance.
+ * @note After enable from off state, OPAMP requires a delay
+ * to fullfill wake up time specification.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
+{
+ SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+ * @brief Disable OPAMP instance.
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
+{
+ CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
+}
+
+/**
+ * @brief Get OPAMP instance enable state
+ * (0: OPAMP is disabled, 1: OPAMP is enabled)
+ * @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN));
+}
+
+/**
+ * @brief Lock OPAMP instance.
+ * @note Once locked, OPAMP configuration can be accessed in read-only.
+ * @note The only way to unlock the OPAMP is a device hardware reset.
+ * @rmtoll CSR LOCK LL_OPAMP_Lock
+ * @param OPAMPx OPAMP instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
+{
+ SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
+}
+
+/**
+ * @brief Get OPAMP lock state
+ * (0: OPAMP is unlocked, 1: OPAMP is locked).
+ * @note Once locked, OPAMP configuration can be accessed in read-only.
+ * @note The only way to unlock the OPAMP is a device hardware reset.
+ * @rmtoll CSR LOCK LL_OPAMP_IsLocked
+ * @param OPAMPx OPAMP instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
+{
+ return (READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_OPAMP_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_pwr.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_pwr.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_pwr.h"
+#include "stm32f3xx_ll_bus.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_pwr.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,571 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_pwr.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_PWR_H
+#define __STM32F3xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
+#if defined(PWR_PVD_SUPPORT)
+#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
+#endif /* PWR_PVD_SUPPORT */
+#if defined(PWR_CSR_VREFINTRDYF)
+#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
+#endif /* PWR_CSR_VREFINTRDYF */
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
+#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+ * @{
+ */
+#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+ * @}
+ */
+
+#if defined(PWR_CR_LPDS)
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
+/**
+ * @}
+ */
+#endif /* PWR_CR_LPDS */
+
+#if defined(PWR_PVD_SUPPORT)
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+ * @}
+ */
+#endif /* PWR_PVD_SUPPORT */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
+#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
+#endif /* PWR_CSR_EWUP3 */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
+ * @{
+ */
+#if defined(SDADC1)
+#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */
+#endif /* SDADC1 */
+#if defined(SDADC2)
+#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */
+#endif /* SDADC2 */
+#if defined(SDADC3)
+#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */
+#endif /* SDADC3 */
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enables the SDADC peripheral functionality
+ * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
+ * CR ENSD2 LL_PWR_EnableSDADC\n
+ * CR ENSD3 LL_PWR_EnableSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
+{
+ SET_BIT(PWR->CR, Analogx);
+}
+
+/**
+ * @brief Disables the SDADC peripheral functionality
+ * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
+ * CR ENSD2 LL_PWR_EnableSDADC\n
+ * CR ENSD3 LL_PWR_EnableSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
+{
+ CLEAR_BIT(PWR->CR, Analogx);
+}
+
+/**
+ * @brief Check if SDADCx has been enabled or not
+ * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n
+ * CR ENSD2 LL_PWR_IsEnabledSDADC\n
+ * CR ENSD3 LL_PWR_IsEnabledSDADC
+ * @param Analogx This parameter can be a combination of the following values:
+ * @arg @ref LL_PWR_SDADC_ANALOG1
+ * @arg @ref LL_PWR_SDADC_ANALOG2
+ * @arg @ref LL_PWR_SDADC_ANALOG3
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
+{
+ return (READ_BIT(PWR->CR, Analogx) == (Analogx));
+}
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+
+#if defined(PWR_CR_LPDS)
+/**
+ * @brief Set voltage regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
+ * @param RegulMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+ * @brief Get voltage regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+#endif /* PWR_CR_LPDS */
+
+/**
+ * @brief Set power down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_SetPowerMode
+ * @param PDMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+}
+
+/**
+ * @brief Get power down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
+ * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @arg @ref LL_PWR_WAKEUP_PIN2
+ * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+ *
+ * (*) not available on all devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Wake-up Flag
+ * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+ * @brief Get Standby Flag
+ * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+#if defined(PWR_PVD_SUPPORT)
+/**
+ * @brief Indicate whether VDD voltage is below the selected PVD threshold
+ * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+#endif /* PWR_PVD_SUPPORT */
+
+#if defined(PWR_CSR_VREFINTRDYF)
+/**
+ * @brief Get Internal Reference VrefInt Flag
+ * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
+}
+#endif /* PWR_CSR_VREFINTRDYF */
+/**
+ * @brief Clear Standby Flag
+ * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1121 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rcc.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Variables
+ * @{
+ */
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+const uint16_t aADCPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDPRE)
+const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
+#endif /* RCC_CFGR_SDPRE */
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
+#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
+
+#if defined(UART4) && defined(UART5)
+#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
+#elif defined(UART4)
+#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
+#elif defined(UART5)
+#define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
+#endif /* UART4 && UART5*/
+
+#if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW)
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
+#endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */
+
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
+
+#if defined(USB)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+#else
+#if defined(RCC_CFGR2_ADC1PRES)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE))
+#elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE))
+#else /* RCC_CFGR2_ADCPRE12 */
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
+#endif /* RCC_CFGR2_ADC1PRES */
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+#define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE))
+#endif /* RCC_CFGR_SDPRE */
+
+#if defined(CEC)
+#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
+#endif /* CEC */
+
+#if defined(RCC_CFGR3_TIMSW)
+#if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
+ && defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \
+ && defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE))
+
+#elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
+ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \
+ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE))
+
+#elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \
+ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \
+ && !defined(RCC_CFGR3_TIM34SW)
+
+#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE))
+
+#else
+#error "Miss macro"
+#endif /* RCC_CFGR3_TIMxSW */
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+#define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE))
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE and PLL OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ uint32_t vl_mask = 0U;
+
+ /* Set HSION bit */
+ LL_RCC_HSI_Enable();
+
+ /* Set HSITRIM bits to the reset value*/
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+ /* Reset SW, HPRE, PPRE and MCOSEL bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
+ LL_RCC_WriteReg(CFGR, vl_mask);
+
+ /* Reset HSEON, CSSON, PLLON bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
+ LL_RCC_WriteReg(CR, vl_mask);
+
+ /* Reset HSEBYP bit */
+ LL_RCC_HSE_DisableBypass();
+
+ /* Reset CFGR register */
+ LL_RCC_WriteReg(CFGR, 0x00000000U);
+
+ /* Reset CFGR2 register */
+ LL_RCC_WriteReg(CFGR2, 0x00000000U);
+
+ /* Reset CFGR3 register */
+ LL_RCC_WriteReg(CFGR3, 0x00000000U);
+
+ /* Clear pending flags */
+ vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
+ SET_BIT(RCC->CIR, vl_mask);
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIR, 0x00000000U);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ * @note (**) HSI_VALUE is a defined constant but the real value may vary
+ * depending on the variations in voltage and temperature.
+ * @note (***) HSE_VALUE is a defined constant, user has to ensure that
+ * HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+/**
+ * @brief Return USARTx clock frequency
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval USART clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
+{
+ uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
+#if defined(RCC_CFGR3_USART1SW)
+ if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
+ {
+ /* USART1CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+#if defined(RCC_CFGR3_USART1SW_PCLK1)
+ case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+#else
+ case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
+ default:
+ usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+#endif /* RCC_CFGR3_USART1SW_PCLK1 */
+ break;
+ }
+ }
+#endif /* RCC_CFGR3_USART1SW */
+
+#if defined(RCC_CFGR3_USART2SW)
+ if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
+ {
+ /* USART2CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* RCC_CFGR3_USART2SW */
+
+#if defined(RCC_CFGR3_USART3SW)
+ if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
+ {
+ /* USART3CLK clock frequency */
+ switch (LL_RCC_GetUSARTClockSource(USARTxSource))
+ {
+ case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
+ usart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ usart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ usart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
+ default:
+ usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+
+#endif /* RCC_CFGR3_USART3SW */
+ return usart_frequency;
+}
+
+#if defined(UART4) || defined(UART5)
+/**
+ * @brief Return UARTx clock frequency
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval UART clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
+ */
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
+{
+ uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
+
+#if defined(UART4)
+ if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
+ {
+ /* UART4CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
+ default:
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* UART4 */
+
+#if defined(UART5)
+ if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
+ {
+ /* UART5CLK clock frequency */
+ switch (LL_RCC_GetUARTClockSource(UARTxSource))
+ {
+ case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
+ uart_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
+ if (LL_RCC_HSI_IsReady())
+ {
+ uart_frequency = HSI_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
+ if (LL_RCC_LSE_IsReady())
+ {
+ uart_frequency = LSE_VALUE;
+ }
+ break;
+
+ case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
+ default:
+ uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ break;
+ }
+ }
+#endif /* UART5 */
+
+ return uart_frequency;
+}
+#endif /* UART4 || UART5 */
+
+/**
+ * @brief Return I2Cx clock frequency
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval I2C clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
+ */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
+{
+ uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
+
+ /* I2C1 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+
+#if defined(RCC_CFGR3_I2C2SW)
+ /* I2C2 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+#endif /*RCC_CFGR3_I2C2SW*/
+
+#if defined(RCC_CFGR3_I2C3SW)
+ /* I2C3 CLK clock frequency */
+ if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
+ {
+ switch (LL_RCC_GetI2CClockSource(I2CxSource))
+ {
+ case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
+ i2c_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
+ default:
+ if (LL_RCC_HSI_IsReady())
+ {
+ i2c_frequency = HSI_VALUE;
+ }
+ break;
+ }
+ }
+#endif /*RCC_CFGR3_I2C3SW*/
+
+ return i2c_frequency;
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ /* I2S1CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
+ i2s_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */
+ default:
+ i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
+ break;
+ }
+
+ return i2s_frequency;
+}
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(USB)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3) / 2;
+ }
+ break;
+ }
+
+ return usb_frequency;
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC1_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE (*)
+ * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval ADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_prescaler = 0U;
+ uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* Get ADC prescaler */
+ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
+
+#if defined(RCC_CFGR_ADCPRE)
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
+#else
+ if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U))
+ {
+ /* ADC frequency = HCLK frequency */
+ adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq());
+ }
+ else
+ {
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]);
+ }
+#endif /* RCC_CFGR_ADCPRE */
+
+ return adc_frequency;
+}
+#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Return SDADCx clock frequency
+ * @param SDADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSOURCE
+ * @retval SDADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource)
+{
+ uint32_t sdadc_prescaler = 0U;
+ uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource));
+
+ /* Get SDADC prescaler */
+ sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource);
+
+ /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */
+ sdadc_frequency = RCC_GetSystemClockFreq()
+ / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]);
+
+ return sdadc_frequency;
+}
+#endif /*RCC_CFGR_SDPRE */
+
+#if defined(CEC)
+/**
+ * @brief Return CECx clock frequency
+ * @param CECxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval CEC clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
+ */
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
+{
+ uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
+
+ /* CECCLK clock frequency */
+ switch (LL_RCC_GetCECClockSource(CECxSource))
+ {
+ case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
+ if (LL_RCC_HSI_IsReady())
+ {
+ cec_frequency = HSI_VALUE / 244U;
+ }
+ break;
+
+ case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
+ default:
+ if (LL_RCC_LSE_IsReady())
+ {
+ cec_frequency = LSE_VALUE;
+ }
+ break;
+ }
+
+ return cec_frequency;
+}
+#endif /* CEC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Return TIMx clock frequency
+ * @param TIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices
+ * @retval TIM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource)
+{
+ uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource));
+
+ if (TIMxSource == LL_RCC_TIM1_CLKSOURCE)
+ {
+ /* TIM1CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM1 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM1_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM1 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+
+#if defined(RCC_CFGR3_TIM8SW)
+ if (TIMxSource == LL_RCC_TIM8_CLKSOURCE)
+ {
+ /* TIM8CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM8 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM8_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM8 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM8SW*/
+
+#if defined(RCC_CFGR3_TIM15SW)
+ if (TIMxSource == LL_RCC_TIM15_CLKSOURCE)
+ {
+ /* TIM15CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM15 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM15_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM15 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM15SW*/
+
+#if defined(RCC_CFGR3_TIM16SW)
+ if (TIMxSource == LL_RCC_TIM16_CLKSOURCE)
+ {
+ /* TIM16CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM16 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM16_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM16 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM16SW*/
+
+#if defined(RCC_CFGR3_TIM17SW)
+ if (TIMxSource == LL_RCC_TIM17_CLKSOURCE)
+ {
+ /* TIM17CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM17 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM17_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM17 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM17SW*/
+
+#if defined(RCC_CFGR3_TIM20SW)
+ if (TIMxSource == LL_RCC_TIM20_CLKSOURCE)
+ {
+ /* TIM20CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as TIM20 clock source */
+ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM20_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM20 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM20SW*/
+
+#if defined(RCC_CFGR3_TIM2SW)
+ if (TIMxSource == LL_RCC_TIM2_CLKSOURCE)
+ {
+ /* TIM2CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1)
+ {
+ /* PCLK1 used as TIM2 clock source */
+ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM2_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM2 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM2SW*/
+
+#if defined(RCC_CFGR3_TIM34SW)
+ if (TIMxSource == LL_RCC_TIM34_CLKSOURCE)
+ {
+ /* TIM3/4 CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1)
+ {
+ /* PCLK1 used as TIM3/4 clock source */
+ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_TIM34_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as TIM3/4 clock source */
+ tim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ }
+#endif /*RCC_CFGR3_TIM34SW*/
+
+ return tim_frequency;
+}
+#endif /*RCC_CFGR3_TIMSW*/
+
+#if defined(HRTIM1)
+/**
+ * @brief Return HRTIMx clock frequency
+ * @param HRTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
+ * @retval HRTIM clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
+{
+ uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
+
+ /* HRTIM1CLK clock frequency */
+ if (LL_RCC_GetTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
+ {
+ /* PCLK2 used as HRTIM1 clock source */
+ hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ }
+ else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */
+ {
+ /* PLL clock used as HRTIM1 clock source */
+ hrtim_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+
+ return hrtim_frequency;
+}
+#endif /* HRTIM1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = HSI_VALUE;
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE;
+#else
+ case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE / 2;
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+
+ default:
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ pllinputfreq = HSI_VALUE;
+#else
+ pllinputfreq = HSI_VALUE / 2;
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+ break;
+ }
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
+#else
+ return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2844 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rcc.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_RCC_H
+#define __STM32F3xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Constants RCC Private Constants
+ * @{
+ */
+/* Defines used for the bit position in the register and perform offsets*/
+#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
+#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
+#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
+#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
+#define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
+#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+#if defined(RCC_CSR_V18PWRRSTF)
+#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
+#endif /* RCC_CSR_V18PWRRSTF */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
+ * @{
+ */
+#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
+#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
+#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
+#if defined(RCC_CFGR_PLLNODIV)
+#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
+#endif /* RCC_CFGR_PLLNODIV */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
+ * @{
+ */
+#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
+#if defined(RCC_CFGR_MCOPRE)
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
+#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
+#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
+#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
+#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
+#endif /* RCC_CFGR_MCOPRE */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
+ * @{
+ */
+#if defined(RCC_CFGR3_USART1SW_PCLK1)
+#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
+#else
+#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
+#endif /*RCC_CFGR3_USART1SW_PCLK1*/
+#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
+#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
+#if defined(RCC_CFGR3_USART2SW)
+#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
+#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
+#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
+#endif /* RCC_CFGR3_USART3SW */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
+#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
+#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
+#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
+#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
+#if defined(RCC_CFGR3_I2C2SW)
+#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
+#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
+#endif /*RCC_CFGR3_I2C2SW*/
+#if defined(RCC_CFGR3_I2C3SW)
+#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
+#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
+#endif /*RCC_CFGR3_I2C3SW*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_I2SSRC)
+/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
+#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
+ * @{
+ */
+#define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
+#define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
+#if defined(RCC_CFGR3_TIM8SW)
+#define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
+#define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
+#endif /*RCC_CFGR3_TIM8SW*/
+#if defined(RCC_CFGR3_TIM15SW)
+#define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
+#define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
+#endif /*RCC_CFGR3_TIM15SW*/
+#if defined(RCC_CFGR3_TIM16SW)
+#define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
+#define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
+#endif /*RCC_CFGR3_TIM16SW*/
+#if defined(RCC_CFGR3_TIM17SW)
+#define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
+#define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
+#endif /*RCC_CFGR3_TIM17SW*/
+#if defined(RCC_CFGR3_TIM20SW)
+#define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
+#define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
+#endif /*RCC_CFGR3_TIM20SW*/
+#if defined(RCC_CFGR3_TIM2SW)
+#define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
+#define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
+#endif /*RCC_CFGR3_TIM2SW*/
+#if defined(RCC_CFGR3_TIM34SW)
+#define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
+#define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
+#endif /*RCC_CFGR3_TIM34SW*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
+ * @{
+ */
+#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
+#define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
+#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
+/**
+ * @}
+ */
+
+#endif /* CEC */
+
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
+/**
+ * @}
+ */
+
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
+/**
+ * @}
+ */
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
+#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
+/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
+ * @{
+ */
+#define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
+#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#else
+/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
+#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
+
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
+ * @{
+ */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
+#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_SDPRE */
+
+/** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
+ * @{
+ */
+#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
+#if defined(RCC_CFGR3_USART2SW)
+#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
+#endif /* RCC_CFGR3_USART2SW */
+#if defined(RCC_CFGR3_USART3SW)
+#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
+#endif /* RCC_CFGR3_USART3SW */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
+ * @{
+ */
+#define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
+#define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
+ * @{
+ */
+#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
+#if defined(RCC_CFGR3_I2C2SW)
+#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
+#endif /*RCC_CFGR3_I2C2SW*/
+#if defined(RCC_CFGR3_I2C3SW)
+#define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
+#endif /*RCC_CFGR3_I2C3SW*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR_I2SSRC)
+/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
+ * @{
+ */
+#define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
+ * @{
+ */
+#define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
+#if defined(RCC_CFGR3_TIM2SW)
+#define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
+#endif /*RCC_CFGR3_TIM2SW*/
+#if defined(RCC_CFGR3_TIM8SW)
+#define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
+#endif /*RCC_CFGR3_TIM8SW*/
+#if defined(RCC_CFGR3_TIM15SW)
+#define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
+#endif /*RCC_CFGR3_TIM15SW*/
+#if defined(RCC_CFGR3_TIM16SW)
+#define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
+#endif /*RCC_CFGR3_TIM16SW*/
+#if defined(RCC_CFGR3_TIM17SW)
+#define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
+#endif /*RCC_CFGR3_TIM17SW*/
+#if defined(RCC_CFGR3_TIM20SW)
+#define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
+#endif /*RCC_CFGR3_TIM20SW*/
+#if defined(RCC_CFGR3_TIM34SW)
+#define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
+#endif /*RCC_CFGR3_TIM34SW*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
+ * @{
+ */
+#define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
+ * @{
+ */
+#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* CEC */
+
+#if defined(USB)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
+ * @{
+ */
+#if defined(RCC_CFGR2_ADC1PRES)
+#define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
+#else
+#define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
+#if defined(RCC_CFGR2_ADCPRE34)
+#define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
+#endif /*RCC_CFGR2_ADCPRE34*/
+#endif /*RCC_CFGR2_ADC1PRES*/
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+
+#if defined(RCC_CFGR_SDPRE)
+/** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
+ * @{
+ */
+#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR_SDPRE */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
+ * @{
+ */
+#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
+#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
+#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
+#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
+#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
+#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
+#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
+#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
+#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
+#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
+#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
+#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
+#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
+#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
+#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
+#else
+#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
+ * @{
+ */
+#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
+#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
+#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
+#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
+#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
+#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
+#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
+#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
+#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
+#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
+#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
+#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
+#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
+#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
+#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
+ * , @ref LL_RCC_PLL_GetPrediv());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @param __PLLPREDIV__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
+ (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
+ ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
+ * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
+ * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
+ * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Disable the Clock Security System.
+ * @note Cannot be disabled in HSE is ready (only by hardware)
+ * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Set LSE oscillator drive capability
+ * @note The oscillator is in Xtal mode when it is not in bypass mode.
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
+ * @param LSEDrive This parameter can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
+}
+
+/**
+ * @brief Get LSE oscillator drive capability
+ * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_LSEDRIVE_LOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
+ * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
+ * @arg @ref LL_RCC_LSEDRIVE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
+ * CFGR MCOPRE LL_RCC_ConfigMCO\n
+ * CFGR PLLNODIV LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_LSI
+ * @arg @ref LL_RCC_MCO1SOURCE_LSE
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
+ *
+ * (*) value not defined in all devices
+ * @param MCOxPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1_DIV_1
+ * @arg @ref LL_RCC_MCO1_DIV_2 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_4 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_8 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_16 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_32 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_64 (*)
+ * @arg @ref LL_RCC_MCO1_DIV_128 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+#if defined(RCC_CFGR_MCOPRE)
+#if defined(RCC_CFGR_PLLNODIV)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
+#else
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
+#endif /* RCC_CFGR_PLLNODIV */
+#else
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
+#endif /* RCC_CFGR_MCOPRE */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+/**
+ * @brief Configure USARTx clock source
+ * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
+ * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
+ * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
+ * @param USARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
+{
+ MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
+}
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/**
+ * @brief Configure UARTx clock source
+ * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
+ * CFGR3 UART5SW LL_RCC_SetUARTClockSource
+ * @param UARTxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
+{
+ MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
+}
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/**
+ * @brief Configure I2Cx clock source
+ * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
+ * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
+ * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
+ * @param I2CxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Configure I2Sx clock source
+ * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
+}
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Configure TIMx clock source
+ * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
+ * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
+ * @param TIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
+{
+ MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
+}
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/**
+ * @brief Configure HRTIMx clock source
+ * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
+ * @param HRTIMxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
+{
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
+}
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/**
+ * @brief Configure CEC clock source
+ * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
+ * @param CECxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
+{
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
+}
+#endif /* CEC */
+
+#if defined(USB)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
+}
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
+}
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
+ * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
+ * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+#if defined(RCC_CFGR2_ADCPRE34)
+ MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
+#else
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
+#endif /* RCC_CFGR2_ADCPRE34 */
+}
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Configure SDADCx clock source
+ * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
+ * @param SDADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
+}
+#endif /* RCC_CFGR_SDPRE */
+
+/**
+ * @brief Get USARTx clock source
+ * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
+ * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
+ * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
+ * @param USARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE
+ * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
+ * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
+}
+
+#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
+/**
+ * @brief Get UARTx clock source
+ * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
+ * CFGR3 UART5SW LL_RCC_GetUARTClockSource
+ * @param UARTx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
+}
+#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
+
+/**
+ * @brief Get I2Cx clock source
+ * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
+ * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
+ * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
+ * @param I2Cx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
+ * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
+}
+
+#if defined(RCC_CFGR_I2SSRC)
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+}
+#endif /* RCC_CFGR_I2SSRC */
+
+#if defined(RCC_CFGR3_TIMSW)
+/**
+ * @brief Get TIMx clock source
+ * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
+ * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
+ * @param TIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
+ * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
+ * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
+}
+#endif /* RCC_CFGR3_TIMSW */
+
+#if defined(HRTIM1)
+/**
+ * @brief Get HRTIMx clock source
+ * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
+ * @param HRTIMx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
+ * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
+}
+#endif /* HRTIM1 */
+
+#if defined(CEC)
+/**
+ * @brief Get CEC clock source
+ * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
+ * @param CECx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
+ * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
+}
+#endif /* CEC */
+
+#if defined(USB)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
+}
+#endif /* USB */
+
+#if defined(RCC_CFGR_ADCPRE)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
+}
+
+#elif defined(RCC_CFGR2_ADC1PRES)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
+}
+
+#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
+ * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSOURCE
+ * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
+ * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
+ * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
+ * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+#if defined(RCC_CFGR2_ADCPRE34)
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
+#endif /*RCC_CFGR2_ADCPRE34*/
+}
+#endif /* RCC_CFGR_ADCPRE */
+
+#if defined(RCC_CFGR_SDPRE)
+/**
+ * @brief Get SDADCx clock source
+ * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
+ * @param SDADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
+ * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
+}
+#endif /* RCC_CFGR_SDPRE */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed any more unless
+ * the Backup domain is reset. The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @param PLLDiv This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
+}
+
+#else
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
+}
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+}
+
+/**
+ * @brief Get PLL multiplication Factor
+ * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
+}
+
+/**
+ * @brief Get PREDIV division factor for the main PLL
+ * @note They can be written only when the PLL is disabled
+ * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3
+ * @arg @ref LL_RCC_PREDIV_DIV_4
+ * @arg @ref LL_RCC_PREDIV_DIV_5
+ * @arg @ref LL_RCC_PREDIV_DIV_6
+ * @arg @ref LL_RCC_PREDIV_DIV_7
+ * @arg @ref LL_RCC_PREDIV_DIV_8
+ * @arg @ref LL_RCC_PREDIV_DIV_9
+ * @arg @ref LL_RCC_PREDIV_DIV_10
+ * @arg @ref LL_RCC_PREDIV_DIV_11
+ * @arg @ref LL_RCC_PREDIV_DIV_12
+ * @arg @ref LL_RCC_PREDIV_DIV_13
+ * @arg @ref LL_RCC_PREDIV_DIV_14
+ * @arg @ref LL_RCC_PREDIV_DIV_15
+ * @arg @ref LL_RCC_PREDIV_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+#if defined(RCC_CFGR_MCOF)
+/**
+ * @brief Check if switch to new MCO source is effective or not
+ * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
+{
+ return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
+}
+#endif /* RCC_CFGR_MCOF */
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+ * @brief Check if RCC flag is set or not.
+ * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+ * @brief Check if RCC flag POR/PDR reset is set or not.
+ * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+#if defined(RCC_CSR_V18PWRRSTF)
+/**
+ * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
+ * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
+}
+#endif /* RCC_CSR_V18PWRRSTF */
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
+#if defined(UART4) || defined(UART5)
+uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
+#endif /* UART4 || UART5 */
+uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
+#if defined(RCC_CFGR_I2SSRC)
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
+#if defined(RCC_CFGR_SDPRE)
+uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
+#endif /*RCC_CFGR_SDPRE */
+#if defined(CEC)
+uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(RCC_CFGR3_TIMSW)
+uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
+#endif /*RCC_CFGR3_TIMSW*/
+uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RCC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rtc.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,894 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rtc.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rtc.h"
+#include "stm32f3xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
+#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+ || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+ || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+
+#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
+ || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
+ || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
+ || ((__VALUE__) == LL_RTC_MONTH_MAY) \
+ || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
+ || ((__VALUE__) == LL_RTC_MONTH_JULY) \
+ || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
+ || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
+ || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Reset TR, DR and CR registers */
+ LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+ LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
+#else
+ LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
+
+ /* Reset ISR register and exit initialization mode */
+ LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
+
+ /* Reset Tamper and alternate functions configuration register */
+ LL_RTC_WriteReg(RTCx, TAFCR, 0x00000000U);
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Set Hour Format */
+ LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+ }
+ else
+ {
+ RTC_TimeStruct->TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ }
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+ RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+ }
+ else
+ {
+ LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC current date.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+ * the date configuration information for the RTC.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Day register is configured
+ * - ERROR: RTC Day register is not configured
+ */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+ {
+ RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ }
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+ assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+ assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+ assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+ }
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ }
+ else
+ {
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ }
+
+ /* Exit Initialization mode */
+ LL_RTC_DisableInitMode(RTC);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+ {
+ status = LL_RTC_WaitForSynchro(RTCx);
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+ * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+ /* Monday, January 01 xx00 */
+ RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+ RTC_DateStruct->Day = 1U;
+ RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
+ RTC_DateStruct->Year = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm A.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use @ref LL_RTC_ALMA_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMA registers are configured
+ * - ERROR: ALARMA registers are not configured
+ */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMA_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMA_EnableWeekday(RTCx);
+ LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the RTC Alarm B.
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (@ref LL_RTC_ALMB_Disable function).
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARMB registers are configured
+ * - ERROR: ALARMB registers are not configured
+ */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+ assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+ assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ }
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+ {
+ assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Select weekday selection */
+ if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+ {
+ /* Set the date for ALARM */
+ LL_RTC_ALMB_DisableWeekday(RTCx);
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+ else
+ {
+ LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+ }
+ }
+ else
+ {
+ /* Set the week day for ALARM */
+ LL_RTC_ALMB_EnableWeekday(RTCx);
+ LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+ }
+
+ /* Configure the Alarm register */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+ RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+ }
+ else
+ {
+ LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ /* Set ALARM mask */
+ LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+
+ /* Alarm Day Settings : Day = 1st day of the month */
+ RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+ RTC_AlarmStruct->AlarmDateWeekDay = 1U;
+
+ /* Alarm Masks Settings : Mask = all fields are not masked */
+ RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Check if the Initialization mode is set */
+ if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+ {
+ /* Set the Initialization mode */
+ LL_RTC_EnableInitMode(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @note The RTC Initialization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_DisableInitMode(RTCx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ if (status != ERROR)
+ {
+ timeout = RTC_SYNCHRO_TIMEOUT;
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rtc.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,3823 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_rtc.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of RTC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_RTC_H
+#define __STM32F3xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_LL_Private_Constants RTC Private Constants
+ * @{
+ */
+/* Masks Definition */
+#define RTC_INIT_MASK (0xFFFFFFFFU)
+#define RTC_RSF_MASK (0xFFFFFF5FU)
+
+/* Write protection defines */
+#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
+#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
+#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
+
+/* Defines used for the bit position in the register and perform offsets */
+#define RTC_POSITION_TR_HT (uint32_t)POSITION_VAL(RTC_TR_HT)
+#define RTC_POSITION_TR_HU (uint32_t)POSITION_VAL(RTC_TR_HU)
+#define RTC_POSITION_TR_MT (uint32_t)POSITION_VAL(RTC_TR_MNT)
+#define RTC_POSITION_TR_MU (uint32_t)POSITION_VAL(RTC_TR_MNU)
+#define RTC_POSITION_TR_ST (uint32_t)POSITION_VAL(RTC_TR_ST)
+#define RTC_POSITION_TR_SU (uint32_t)POSITION_VAL(RTC_TR_SU)
+#define RTC_POSITION_DR_YT (uint32_t)POSITION_VAL(RTC_DR_YT)
+#define RTC_POSITION_DR_YU (uint32_t)POSITION_VAL(RTC_DR_YU)
+#define RTC_POSITION_DR_MT (uint32_t)POSITION_VAL(RTC_DR_MT)
+#define RTC_POSITION_DR_MU (uint32_t)POSITION_VAL(RTC_DR_MU)
+#define RTC_POSITION_DR_DT (uint32_t)POSITION_VAL(RTC_DR_DT)
+#define RTC_POSITION_DR_DU (uint32_t)POSITION_VAL(RTC_DR_DU)
+#define RTC_POSITION_DR_WDU (uint32_t)POSITION_VAL(RTC_DR_WDU)
+#define RTC_POSITION_ALMA_DT (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)
+#define RTC_POSITION_ALMA_DU (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)
+#define RTC_POSITION_ALMA_HT (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)
+#define RTC_POSITION_ALMA_HU (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)
+#define RTC_POSITION_ALMA_MT (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)
+#define RTC_POSITION_ALMA_MU (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)
+#define RTC_POSITION_ALMA_SU (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)
+#define RTC_POSITION_ALMA_ST (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)
+#define RTC_POSITION_ALMB_DT (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)
+#define RTC_POSITION_ALMB_DU (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)
+#define RTC_POSITION_ALMB_HT (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)
+#define RTC_POSITION_ALMB_HU (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)
+#define RTC_POSITION_ALMB_MT (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)
+#define RTC_POSITION_ALMB_MU (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)
+#define RTC_POSITION_ALMB_SU (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)
+#define RTC_POSITION_ALMB_ST (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)
+#define RTC_POSITION_PRER_PREDIV_A (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)
+#define RTC_POSITION_ALMA_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)
+#define RTC_POSITION_ALMB_MASKSS (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)
+#define RTC_POSITION_TS_HU (uint32_t)POSITION_VAL(RTC_TSTR_HU)
+#define RTC_POSITION_TS_MNU (uint32_t)POSITION_VAL(RTC_TSTR_MNU)
+#define RTC_POSITION_TS_WDU (uint32_t)POSITION_VAL(RTC_TSDR_WDU)
+#define RTC_POSITION_TS_MU (uint32_t)POSITION_VAL(RTC_TSDR_MU)
+
+/* Defines used to combine date & time */
+#define RTC_OFFSET_WEEKDAY (uint32_t)24U
+#define RTC_OFFSET_DAY (uint32_t)16U
+#define RTC_OFFSET_MONTH (uint32_t)8U
+#define RTC_OFFSET_HOUR (uint32_t)16U
+#define RTC_OFFSET_MINUTE (uint32_t)8U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
+ This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetHourFormat(). */
+
+ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetAsynchPrescaler(). */
+
+ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetSynchPrescaler(). */
+} LL_RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
+ This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
+
+ uint8_t Hours; /*!< Specifies the RTC Time Hours.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
+} LL_RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct
+{
+ uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
+
+ uint8_t Month; /*!< Specifies the RTC Date Month.
+ This parameter can be a value of @ref RTC_LL_EC_MONTH
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
+
+ uint8_t Day; /*!< Specifies the RTC Date Day.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 31
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
+
+ uint8_t Year; /*!< Specifies the RTC Date Year.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 99
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
+} LL_RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+ uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
+ or @ref LL_RTC_ALMB_SetMask() for ALARM B
+ */
+
+ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
+ This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
+ for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
+ */
+
+ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
+ If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
+
+ If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
+
+ This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
+ for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
+ */
+} LL_RTC_AlarmTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+ * @{
+ */
+#define LL_RTC_FORMAT_BIN ((uint32_t)0x000000000U) /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD ((uint32_t)0x000000001U) /*!< BCD data format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
+ * @{
+ */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U) /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RTC_ReadReg function
+ * @{
+ */
+#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
+#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
+#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
+#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
+#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
+#define LL_RTC_ISR_TSF RTC_ISR_TSF
+#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
+#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF
+#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF
+#define LL_RTC_ISR_INITF RTC_ISR_INITF
+#define LL_RTC_ISR_RSF RTC_ISR_RSF
+#define LL_RTC_ISR_INITS RTC_ISR_INITS
+#define LL_RTC_ISR_SHPF RTC_ISR_SHPF
+#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF
+#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF
+#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
+ * @{
+ */
+#define LL_RTC_CR_TSIE RTC_CR_TSIE
+#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
+#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
+#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
+#define LL_RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
+ * @{
+ */
+#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */
+#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
+#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */
+#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */
+#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */
+#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
+#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_MONTH MONTH
+ * @{
+ */
+#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */
+#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */
+#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */
+#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */
+#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */
+#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */
+#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */
+#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */
+#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */
+#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */
+#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */
+#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
+ * @{
+ */
+#define LL_RTC_HOURFORMAT_24HOUR (uint32_t)0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
+ * @{
+ */
+#define LL_RTC_ALARMOUT_DISABLE ((uint32_t)0x00000000U) /*!< Output disabled */
+#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
+#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
+#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
+ * @{
+ */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN (uint32_t)0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */
+#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */
+#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
+ * @{
+ */
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TIME_FORMAT_AM_OR_24 (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
+ * @{
+ */
+#define LL_RTC_SHIFT_SECOND_DELAY (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
+ * @{
+ */
+#define LL_RTC_ALMA_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
+#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMA_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
+ * @{
+ */
+#define LL_RTC_ALMB_MASK_NONE ((uint32_t)0x00000000U) /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
+ * @{
+ */
+#define LL_RTC_ALMB_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
+ * @{
+ */
+#define LL_RTC_TIMESTAMP_EDGE_RISING (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
+ * @{
+ */
+#define LL_RTC_TS_TIME_FORMAT_AM (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER TAMPER
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
+ * @{
+ */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
+#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
+ * @{
+ */
+#define LL_RTC_TAMPER_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
+#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
+ * @{
+ */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAFCR_TAMPFREQ_2 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
+/**
+ * @}
+ */
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
+ * @{
+ */
+#if defined(RTC_TAMPER1_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER1_SUPPORT */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER2_SUPPORT */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
+ * @{
+ */
+#define LL_RTC_WAKEUPCLOCK_DIV_16 ((uint32_t)0x00000000U) /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */
+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
+/**
+ * @}
+ */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EC_BKP BACKUP
+ * @{
+ */
+#define LL_RTC_BKP_DR0 ((uint32_t)0x00000000U)
+#define LL_RTC_BKP_DR1 ((uint32_t)0x00000001U)
+#define LL_RTC_BKP_DR2 ((uint32_t)0x00000002U)
+#define LL_RTC_BKP_DR3 ((uint32_t)0x00000003U)
+#define LL_RTC_BKP_DR4 ((uint32_t)0x00000004U)
+#if RTC_BKP_NUMBER > 5
+#define LL_RTC_BKP_DR5 ((uint32_t)0x00000005U)
+#define LL_RTC_BKP_DR6 ((uint32_t)0x00000006U)
+#define LL_RTC_BKP_DR7 ((uint32_t)0x00000007U)
+#define LL_RTC_BKP_DR8 ((uint32_t)0x00000008U)
+#define LL_RTC_BKP_DR9 ((uint32_t)0x00000009U)
+#define LL_RTC_BKP_DR10 ((uint32_t)0x0000000AU)
+#define LL_RTC_BKP_DR11 ((uint32_t)0x0000000BU)
+#define LL_RTC_BKP_DR12 ((uint32_t)0x0000000CU)
+#define LL_RTC_BKP_DR13 ((uint32_t)0x0000000DU)
+#define LL_RTC_BKP_DR14 ((uint32_t)0x0000000EU)
+#define LL_RTC_BKP_DR15 ((uint32_t)0x0000000FU)
+#endif /* RTC_BKP_NUMBER > 5 */
+
+#if RTC_BKP_NUMBER > 16
+#define LL_RTC_BKP_DR16 ((uint32_t)0x00000010U)
+#define LL_RTC_BKP_DR17 ((uint32_t)0x00000011U)
+#define LL_RTC_BKP_DR18 ((uint32_t)0x00000012U)
+#define LL_RTC_BKP_DR19 ((uint32_t)0x00000013U)
+#endif /* RTC_BKP_NUMBER > 16 */
+
+#if RTC_BKP_NUMBER > 20
+#define LL_RTC_BKP_DR20 ((uint32_t)0x00000014U)
+#define LL_RTC_BKP_DR21 ((uint32_t)0x00000015U)
+#define LL_RTC_BKP_DR22 ((uint32_t)0x00000016U)
+#define LL_RTC_BKP_DR23 ((uint32_t)0x00000017U)
+#define LL_RTC_BKP_DR24 ((uint32_t)0x00000018U)
+#define LL_RTC_BKP_DR25 ((uint32_t)0x00000019U)
+#define LL_RTC_BKP_DR26 ((uint32_t)0x0000001AU)
+#define LL_RTC_BKP_DR27 ((uint32_t)0x0000001BU)
+#define LL_RTC_BKP_DR28 ((uint32_t)0x0000001CU)
+#define LL_RTC_BKP_DR29 ((uint32_t)0x0000001DU)
+#define LL_RTC_BKP_DR30 ((uint32_t)0x0000001EU)
+#define LL_RTC_BKP_DR31 ((uint32_t)0x0000001FU)
+#endif /* RTC_BKP_NUMBER > 20 */
+/**
+ * @}
+ */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
+ * @{
+ */
+#define LL_RTC_CALIB_OUTPUT_NONE (uint32_t)0x00000000U /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
+ * @{
+ */
+#define LL_RTC_CALIB_INSERTPULSE_NONE (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
+ * @{
+ */
+#define LL_RTC_CALIB_PERIOD_32SEC (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
+ * @param __VALUE__ Byte to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+ * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
+ * @param __VALUE__ BCD value to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Date Date helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve weekday.
+ * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Year in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Year in BCD format (0x00 . . . 0x99)
+ */
+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Month in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve Day in BCD format
+ * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
+ * @retval Day in BCD format (0x01 . . . 0x31)
+ */
+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Time Time helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to retrieve hour in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
+ */
+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve minute in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Minutes in BCD format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
+
+/**
+ * @brief Helper macro to retrieve second in BCD format
+ * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
+ * @retval Seconds in format (0x00. . .0x59)
+ */
+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Set Hours format (24 hour/day or AM/PM hour format)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR FMT LL_RTC_SetHourFormat
+ * @param RTCx RTC Instance
+ * @param HourFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
+}
+
+/**
+ * @brief Get Hours format (24 hour/day or AM/PM hour format)
+ * @rmtoll CR FMT LL_RTC_GetHourFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_HOURFORMAT_24HOUR
+ * @arg @ref LL_RTC_HOURFORMAT_AMPM
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
+}
+
+/**
+ * @brief Select the flag to be routed to RTC_ALARM output
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @param AlarmOutput This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
+}
+
+/**
+ * @brief Get the flag to be routed to RTC_ALARM output
+ * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARMOUT_DISABLE
+ * @arg @ref LL_RTC_ALARMOUT_ALMA
+ * @arg @ref LL_RTC_ALARMOUT_ALMB
+ * @arg @ref LL_RTC_ALARMOUT_WAKEUP
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
+}
+
+/**
+ * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note Used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @param Output This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE, Output);
+}
+
+/**
+ * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
+ * @note used only when RTC_ALARM is mapped on PC13
+ * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the
+ * PC13 output data
+ * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
+ * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE));
+}
+
+/**
+ * @brief Enable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13 forced to push-pull output if all RTC alternate functions are disabled
+ * @note PC14 and PC15 forced to push-pull output if LSE is disabled
+ * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
+ * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Disable push-pull output on PC13, PC14 and/or PC15
+ * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers.
+ * Consequently PC13, PC14 and/or PC15 are floating in Standby mode.
+ * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n
+ * TAFCR PC15MODE LL_RTC_DisablePushPullMode
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC13
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, PinMask);
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to high level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_SetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ SET_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Set PC14 and/or PC15 to low level.
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n
+ * TAFCR PC15VALUE LL_RTC_ResetOutputPin
+ * @param RTCx RTC Instance
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_PIN_PC14
+ * @arg @ref LL_RTC_PIN_PC15
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+{
+ CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
+}
+
+/**
+ * @brief Enable initialization mode
+ * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+ * and prescaler register (RTC_PRER).
+ * Counters are stopped and start counting from the new value when INIT is reset.
+ * @rmtoll ISR INIT LL_RTC_EnableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Set the Initialization mode */
+ WRITE_REG(RTCx->ISR, RTC_INIT_MASK);
+}
+
+/**
+ * @brief Disable initialization mode (Free running mode)
+ * @rmtoll ISR INIT LL_RTC_DisableInitMode
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+ /* Exit Initialization mode */
+ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
+}
+
+/**
+ * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR POL LL_RTC_SetOutputPolarity
+ * @param RTCx RTC Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
+}
+
+/**
+ * @brief Get Output polarity
+ * @rmtoll CR POL LL_RTC_GetOutputPolarity
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
+ * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
+}
+
+/**
+ * @brief Enable Bypass the shadow registers
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Disable Bypass the shadow registers
+ * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
+}
+
+/**
+ * @brief Check if Shadow registers bypass is enabled or not.
+ * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+}
+
+/**
+ * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_EnableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll CR REFCKON LL_RTC_DisableRefClock
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
+}
+
+/**
+ * @brief Set Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A);
+}
+
+/**
+ * @brief Set Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
+}
+
+/**
+ * @brief Get Asynchronous prescaler factor
+ * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7F
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A);
+}
+
+/**
+ * @brief Get Synchronous prescaler factor
+ * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
+}
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_EnableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
+}
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @rmtoll WPR KEY LL_RTC_DisableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
+ WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Time Time
+ * @{
+ */
+
+/**
+ * @brief Set time format (AM/24-hour or PM notation)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @rmtoll TR PM LL_RTC_TIME_SetFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get time format (AM or PM notation)
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @rmtoll TR PM LL_RTC_TIME_GetFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
+}
+
+/**
+ * @brief Set Hours in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
+ * @rmtoll TR HT LL_RTC_TIME_SetHour\n
+ * TR HU LL_RTC_TIME_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
+ (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)));
+}
+
+/**
+ * @brief Get Hours in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
+ * Binary format
+ * @rmtoll TR HT LL_RTC_TIME_GetHour\n
+ * TR HU LL_RTC_TIME_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
+ return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU));
+}
+
+/**
+ * @brief Set Minutes in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n
+ * TR MNU LL_RTC_TIME_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
+ (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)));
+}
+
+/**
+ * @brief Get Minutes in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
+ * to Binary format
+ * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n
+ * TR MNU LL_RTC_TIME_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
+ return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU));
+}
+
+/**
+ * @brief Set Seconds in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll TR ST LL_RTC_TIME_SetSecond\n
+ * TR SU LL_RTC_TIME_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
+ (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)));
+}
+
+/**
+ * @brief Get Seconds in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
+ * to Binary format
+ * @rmtoll TR ST LL_RTC_TIME_GetSecond\n
+ * TR SU LL_RTC_TIME_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU));
+}
+
+/**
+ * @brief Set time (hour, minute and second) in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
+ * @note TimeFormat and Hours should follow the same format
+ * @rmtoll TR PM LL_RTC_TIME_Config\n
+ * TR HT LL_RTC_TIME_Config\n
+ * TR HU LL_RTC_TIME_Config\n
+ * TR MNT LL_RTC_TIME_Config\n
+ * TR MNU LL_RTC_TIME_Config\n
+ * TR ST LL_RTC_TIME_Config\n
+ * TR SU LL_RTC_TIME_Config
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
+ * @arg @ref LL_RTC_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)) | \
+ (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \
+ (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU));
+ MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
+}
+
+/**
+ * @brief Get time (hour, minute and second) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
+ * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TR HT LL_RTC_TIME_Get\n
+ * TR HU LL_RTC_TIME_Get\n
+ * TR MNT LL_RTC_TIME_Get\n
+ * TR MNU LL_RTC_TIME_Get\n
+ * TR ST LL_RTC_TIME_Get\n
+ * TR SU LL_RTC_TIME_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
+}
+
+/**
+ * @brief Memorize whether the daylight saving time change has been performed
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BCK LL_RTC_TIME_EnableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_BCK);
+}
+
+/**
+ * @brief Disable memorization whether the daylight saving time change has been performed.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR BCK LL_RTC_TIME_DisableDayLightStore
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_BCK);
+}
+
+/**
+ * @brief Check if RTC Day Light Saving stored operation has been enabled or not
+ * @rmtoll CR BCK LL_RTC_TIME_IsDayLightStoreEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK));
+}
+
+/**
+ * @brief Subtract 1 hour (winter time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR SUB1H LL_RTC_TIME_DecHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_SUB1H);
+}
+
+/**
+ * @brief Add 1 hour (summer time change)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ADD1H LL_RTC_TIME_IncHour
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ADD1H);
+}
+
+/**
+ * @brief Get Sub second value in the synchronous prescaler counter.
+ * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
+ * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
+ * SubSeconds value in second fraction ratio with time unit following
+ * generic formula:
+ * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS.
+ * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Sub second value (number between 0 and 65535)
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
+}
+
+/**
+ * @brief Synchronize to a remote clock with a high degree of precision.
+ * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
+ * SHIFTR SUBFS LL_RTC_TIME_Synchronize
+ * @param RTCx RTC Instance
+ * @param ShiftSecond This parameter can be one of the following values:
+ * @arg @ref LL_RTC_SHIFT_SECOND_DELAY
+ * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
+ * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
+{
+ WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Date Date
+ * @{
+ */
+
+/**
+ * @brief Set Year in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
+ * @rmtoll DR YT LL_RTC_DATE_SetYear\n
+ * DR YU LL_RTC_DATE_SetYear
+ * @param RTCx RTC Instance
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
+ (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)));
+}
+
+/**
+ * @brief Get Year in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
+ * @rmtoll DR YT LL_RTC_DATE_GetYear\n
+ * DR YU LL_RTC_DATE_GetYear
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x99
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU));
+}
+
+/**
+ * @brief Set Week day
+ * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU);
+}
+
+/**
+ * @brief Get Week day
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU);
+}
+
+/**
+ * @brief Set Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
+ * @rmtoll DR MT LL_RTC_DATE_SetMonth\n
+ * DR MU LL_RTC_DATE_SetMonth
+ * @param RTCx RTC Instance
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
+ (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)));
+}
+
+/**
+ * @brief Get Month in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll DR MT LL_RTC_DATE_GetMonth\n
+ * DR MU LL_RTC_DATE_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
+ return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU));
+}
+
+/**
+ * @brief Set Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll DR DT LL_RTC_DATE_SetDay\n
+ * DR DU LL_RTC_DATE_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
+ (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)));
+}
+
+/**
+ * @brief Get Day in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll DR DT LL_RTC_DATE_GetDay\n
+ * DR DU LL_RTC_DATE_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
+ return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU));
+}
+
+/**
+ * @brief Set date (WeekDay, Day, Month and Year) in BCD format
+ * @rmtoll DR WDU LL_RTC_DATE_Config\n
+ * DR MT LL_RTC_DATE_Config\n
+ * DR MU LL_RTC_DATE_Config\n
+ * DR DT LL_RTC_DATE_Config\n
+ * DR DU LL_RTC_DATE_Config\n
+ * DR YT LL_RTC_DATE_Config\n
+ * DR YU LL_RTC_DATE_Config
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @param Month This parameter can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ * @param Year Value between Min_Data=0x00 and Max_Data=0x99
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
+{
+ register uint32_t temp = 0U;
+
+ temp = (WeekDay << RTC_POSITION_DR_WDU) | \
+ (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)) | \
+ (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \
+ (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU));
+
+ MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
+}
+
+/**
+ * @brief Get date (WeekDay, Day, Month and Year) in BCD format
+ * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * before reading this bit
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll DR WDU LL_RTC_DATE_Get\n
+ * DR MT LL_RTC_DATE_Get\n
+ * DR MU LL_RTC_DATE_Get\n
+ * DR DT LL_RTC_DATE_Get\n
+ * DR DU LL_RTC_DATE_Get\n
+ * DR YT LL_RTC_DATE_Get\n
+ * DR YU LL_RTC_DATE_Get
+ * @param RTCx RTC Instance
+ * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
+ */
+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMA ALARMA
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Disable Alarm A
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAE LL_RTC_ALMA_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
+}
+
+/**
+ * @brief Specify the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm A masks.
+ * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
+ * ALRMAR MSK1 LL_RTC_ALMA_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMA_MASK_NONE
+ * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMA_MASK_HOURS
+ * @arg @ref LL_RTC_ALMA_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMA_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMA_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n
+ * ALRMAR DU LL_RTC_ALMA_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
+ (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU)));
+}
+
+/**
+ * @brief Get ALARM A Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n
+ * ALRMAR DU LL_RTC_ALMA_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
+ return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU));
+}
+
+/**
+ * @brief Set ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU);
+}
+
+/**
+ * @brief Get ALARM A Weekday
+ * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU);
+}
+
+/**
+ * @brief Set Alarm A time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get Alarm A time format (AM or PM notation)
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
+}
+
+/**
+ * @brief Set ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n
+ * ALRMAR HU LL_RTC_ALMA_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
+ (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)));
+}
+
+/**
+ * @brief Get ALARM A Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n
+ * ALRMAR HU LL_RTC_ALMA_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
+ return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU));
+}
+
+/**
+ * @brief Set ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
+ (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)));
+}
+
+/**
+ * @brief Get ALARM A Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n
+ * ALRMAR MNU LL_RTC_ALMA_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
+ return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU));
+}
+
+/**
+ * @brief Set ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
+ (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)));
+}
+
+/**
+ * @brief Get ALARM A Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n
+ * ALRMAR SU LL_RTC_ALMA_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU));
+}
+
+/**
+ * @brief Set Alarm A Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR HU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR ST LL_RTC_ALMA_ConfigTime\n
+ * ALRMAR SU LL_RTC_ALMA_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)) | \
+ (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \
+ (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU));
+
+ MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n
+ * ALRMAR HU LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNT LL_RTC_ALMA_GetTime\n
+ * ALRMAR MNU LL_RTC_ALMA_GetTime\n
+ * ALRMAR ST LL_RTC_ALMA_GetTime\n
+ * ALRMAR SU LL_RTC_ALMA_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRAE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS);
+}
+
+/**
+ * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS);
+}
+
+/**
+ * @brief Set Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm A Sub seconds value
+ * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARMB ALARMB
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Disable Alarm B
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBE LL_RTC_ALMB_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
+}
+
+/**
+ * @brief Specify the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_SetMask
+ * @param RTCx RTC Instance
+ * @param Mask This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
+}
+
+/**
+ * @brief Get the Alarm B masks.
+ * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
+ * ALRMBR MSK1 LL_RTC_ALMB_GetMask
+ * @param RTCx RTC Instance
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_RTC_ALMB_MASK_NONE
+ * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
+ * @arg @ref LL_RTC_ALMB_MASK_HOURS
+ * @arg @ref LL_RTC_ALMB_MASK_MINUTES
+ * @arg @ref LL_RTC_ALMB_MASK_SECONDS
+ * @arg @ref LL_RTC_ALMB_MASK_ALL
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
+}
+
+/**
+ * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
+ * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
+}
+
+/**
+ * @brief Set ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n
+ * ALRMBR DU LL_RTC_ALMB_SetDay
+ * @param RTCx RTC Instance
+ * @param Day Value between Min_Data=0x01 and Max_Data=0x31
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
+{
+ MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
+ (((Day & 0xF0U) << (RTC_POSITION_ALMB_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMB_DU)));
+}
+
+/**
+ * @brief Get ALARM B Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n
+ * ALRMBR DU LL_RTC_ALMB_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
+ return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_POSITION_ALMB_DT) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU));
+}
+
+/**
+ * @brief Set ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay
+ * @param RTCx RTC Instance
+ * @param WeekDay This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_POSITION_ALMB_DU);
+}
+
+/**
+ * @brief Get ALARM B Weekday
+ * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU);
+}
+
+/**
+ * @brief Set ALARM B time format (AM/24-hour or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat
+ * @param RTCx RTC Instance
+ * @param TimeFormat This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
+{
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
+}
+
+/**
+ * @brief Get ALARM B time format (AM or PM notation)
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
+}
+
+/**
+ * @brief Set ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n
+ * ALRMBR HU LL_RTC_ALMB_SetHour
+ * @param RTCx RTC Instance
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
+ (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU)));
+}
+
+/**
+ * @brief Get ALARM B Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n
+ * ALRMBR HU LL_RTC_ALMB_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
+ return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_POSITION_ALMB_HT) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_POSITION_ALMB_HU));
+}
+
+/**
+ * @brief Set ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_SetMinute
+ * @param RTCx RTC Instance
+ * @param Minutes between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
+ (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)));
+}
+
+/**
+ * @brief Get ALARM B Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n
+ * ALRMBR MNU LL_RTC_ALMB_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
+ return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_POSITION_ALMB_MT) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_POSITION_ALMB_MU));
+}
+
+/**
+ * @brief Set ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_SetSecond
+ * @param RTCx RTC Instance
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
+{
+ MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
+ (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU)));
+}
+
+/**
+ * @brief Get ALARM B Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n
+ * ALRMBR SU LL_RTC_ALMB_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
+{
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
+ return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_POSITION_ALMB_ST) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_POSITION_ALMB_SU));
+}
+
+/**
+ * @brief Set Alarm B Time (hour, minute and second) in BCD format
+ * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR HU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR ST LL_RTC_ALMB_ConfigTime\n
+ * ALRMBR SU LL_RTC_ALMB_ConfigTime
+ * @param RTCx RTC Instance
+ * @param Format12_24 This parameter can be one of the following values:
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
+ * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
+ * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
+{
+ register uint32_t temp = 0U;
+
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU)) | \
+ (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)) | \
+ (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU));
+
+ MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
+}
+
+/**
+ * @brief Get Alarm B Time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n
+ * ALRMBR HU LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNT LL_RTC_ALMB_GetTime\n
+ * ALRMBR MNU LL_RTC_ALMB_GetTime\n
+ * ALRMBR ST LL_RTC_ALMB_GetTime\n
+ * ALRMBR SU LL_RTC_ALMB_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
+}
+
+/**
+ * @brief Set Alarm B Mask the most-significant bits starting at this bit
+ * @note This register can be written only when ALRBE is reset in RTC_CR register,
+ * or in initialization mode.
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
+ * @param RTCx RTC Instance
+ * @param Mask Value between Min_Data=0x00 and Max_Data=0xF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_POSITION_ALMB_MASKSS);
+}
+
+/**
+ * @brief Get Alarm B Mask the most-significant bits starting at this bit
+ * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_POSITION_ALMB_MASKSS);
+}
+
+/**
+ * @brief Set Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
+ * @param RTCx RTC Instance
+ * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
+{
+ MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
+}
+
+/**
+ * @brief Get Alarm B Sub seconds value
+ * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Timestamp Timestamp
+ * @{
+ */
+
+/**
+ * @brief Enable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Disable Timestamp
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSE LL_RTC_TS_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
+}
+
+/**
+ * @brief Set Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
+ * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge
+ * @param RTCx RTC Instance
+ * @param Edge This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
+}
+
+/**
+ * @brief Get Time-stamp event active edge
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
+ * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
+}
+
+/**
+ * @brief Get Timestamp AM/PM notation (AM or 24-hour format)
+ * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_AM
+ * @arg @ref LL_RTC_TS_TIME_FORMAT_PM
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
+}
+
+/**
+ * @brief Get Timestamp Hours in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
+ * @rmtoll TSTR HT LL_RTC_TS_GetHour\n
+ * TSTR HU LL_RTC_TS_GetHour
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU);
+}
+
+/**
+ * @brief Get Timestamp Minutes in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
+ * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n
+ * TSTR MNU LL_RTC_TS_GetMinute
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU);
+}
+
+/**
+ * @brief Get Timestamp Seconds in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
+ * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n
+ * TSTR SU LL_RTC_TS_GetSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x59
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp time (hour, minute and second) in BCD format
+ * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
+ * are available to get independently each parameter.
+ * @rmtoll TSTR HT LL_RTC_TS_GetTime\n
+ * TSTR HU LL_RTC_TS_GetTime\n
+ * TSTR MNT LL_RTC_TS_GetTime\n
+ * TSTR MNU LL_RTC_TS_GetTime\n
+ * TSTR ST LL_RTC_TS_GetTime\n
+ * TSTR SU LL_RTC_TS_GetTime
+ * @param RTCx RTC Instance
+ * @retval Combination of hours, minutes and seconds.
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSTR,
+ RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
+}
+
+/**
+ * @brief Get Timestamp Week day
+ * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WEEKDAY_MONDAY
+ * @arg @ref LL_RTC_WEEKDAY_TUESDAY
+ * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
+ * @arg @ref LL_RTC_WEEKDAY_THURSDAY
+ * @arg @ref LL_RTC_WEEKDAY_FRIDAY
+ * @arg @ref LL_RTC_WEEKDAY_SATURDAY
+ * @arg @ref LL_RTC_WEEKDAY_SUNDAY
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU);
+}
+
+/**
+ * @brief Get Timestamp Month in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
+ * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n
+ * TSDR MU LL_RTC_TS_GetMonth
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_MONTH_JANUARY
+ * @arg @ref LL_RTC_MONTH_FEBRUARY
+ * @arg @ref LL_RTC_MONTH_MARCH
+ * @arg @ref LL_RTC_MONTH_APRIL
+ * @arg @ref LL_RTC_MONTH_MAY
+ * @arg @ref LL_RTC_MONTH_JUNE
+ * @arg @ref LL_RTC_MONTH_JULY
+ * @arg @ref LL_RTC_MONTH_AUGUST
+ * @arg @ref LL_RTC_MONTH_SEPTEMBER
+ * @arg @ref LL_RTC_MONTH_OCTOBER
+ * @arg @ref LL_RTC_MONTH_NOVEMBER
+ * @arg @ref LL_RTC_MONTH_DECEMBER
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU);
+}
+
+/**
+ * @brief Get Timestamp Day in BCD format
+ * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
+ * @rmtoll TSDR DT LL_RTC_TS_GetDay\n
+ * TSDR DU LL_RTC_TS_GetDay
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x01 and Max_Data=0x31
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
+ * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
+ * and __LL_RTC_GET_DAY are available to get independently each parameter.
+ * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n
+ * TSDR MT LL_RTC_TS_GetDate\n
+ * TSDR MU LL_RTC_TS_GetDate\n
+ * TSDR DT LL_RTC_TS_GetDate\n
+ * TSDR DU LL_RTC_TS_GetDate
+ * @param RTCx RTC Instance
+ * @retval Combination of Weekday, Day and Month
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
+}
+
+/**
+ * @brief Get time-stamp sub second value
+ * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
+}
+
+#if defined(RTC_TAFCR_TAMPTS)
+/**
+ * @brief Activate timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_EnableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+
+/**
+ * @brief Disable timestamp on tamper detection event
+ * @rmtoll TAFCR TAMPTS LL_RTC_TS_DisableOnTamper
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPTS);
+}
+#endif /* RTC_TAFCR_TAMPTS */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Enable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Enable\n
+ * TAFCR TAMP3E LL_RTC_TAMPER_Enable
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Clear RTC_TAMPx input detection
+ * @rmtoll TAFCR TAMP1E LL_RTC_TAMPER_Disable\n
+ * TAFCR TAMP2E LL_RTC_TAMPER_Disable\n
+ * TAFCR TAMP3E LL_RTC_TAMPER_Disable
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+#if defined(RTC_TAFCR_TAMPPUDIS)
+/**
+ * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+
+/**
+ * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
+ * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
+}
+#endif /* RTC_TAFCR_TAMPPUDIS */
+
+#if defined(RTC_TAFCR_TAMPPRCH)
+/**
+ * @brief Set RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
+ * @param RTCx RTC Instance
+ * @param Duration This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH, Duration);
+}
+
+/**
+ * @brief Get RTC_TAMPx precharge duration
+ * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
+ * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
+}
+#endif /* RTC_TAFCR_TAMPPRCH */
+
+#if defined(RTC_TAFCR_TAMPFLT)
+/**
+ * @brief Set RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
+ * @param RTCx RTC Instance
+ * @param FilterCount This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFLT, FilterCount);
+}
+
+/**
+ * @brief Get RTC_TAMPx filter count
+ * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
+ * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
+}
+#endif /* RTC_TAFCR_TAMPFLT */
+
+#if defined(RTC_TAFCR_TAMPFREQ)
+/**
+ * @brief Set Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
+ * @param RTCx RTC Instance
+ * @param SamplingFreq This parameter can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
+{
+ MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ, SamplingFreq);
+}
+
+/**
+ * @brief Get Tamper sampling frequency
+ * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
+ * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
+}
+#endif /* RTC_TAFCR_TAMPFREQ */
+
+/**
+ * @brief Enable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n
+ * TAFCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ SET_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @brief Disable Active level for Tamper input
+ * @rmtoll TAFCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n
+ * TAFCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
+ * @param RTCx RTC Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
+{
+ CLEAR_BIT(RTCx->TAFCR, Tamper);
+}
+
+/**
+ * @}
+ */
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Wakeup Wakeup
+ * @{
+ */
+
+/**
+ * @brief Enable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Disable Wakeup timer
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
+}
+
+/**
+ * @brief Check if Wakeup timer is enabled or not
+ * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+}
+
+/**
+ * @brief Select Wakeup clock
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
+ * @param RTCx RTC Instance
+ * @param WakeupClock This parameter can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
+}
+
+/**
+ * @brief Get Wakeup clock
+ * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
+ * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
+ * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
+}
+
+/**
+ * @brief Set Wakeup auto-reload value
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
+ * @param RTCx RTC Instance
+ * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
+{
+ MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
+}
+
+/**
+ * @brief Get Wakeup auto-reload value
+ * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
+}
+
+/**
+ * @}
+ */
+#endif /* RTC_WAKEUP_SUPPORT */
+
+#if defined(RTC_BACKUP_SUPPORT)
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5 (*)
+ * @arg @ref LL_RTC_BKP_DR6 (*)
+ * @arg @ref LL_RTC_BKP_DR7 (*)
+ * @arg @ref LL_RTC_BKP_DR8 (*)
+ * @arg @ref LL_RTC_BKP_DR9 (*)
+ * @arg @ref LL_RTC_BKP_DR10 (*)
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister
+ * @param RTCx RTC Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR0
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5 (*)
+ * @arg @ref LL_RTC_BKP_DR6 (*)
+ * @arg @ref LL_RTC_BKP_DR7 (*)
+ * @arg @ref LL_RTC_BKP_DR8 (*)
+ * @arg @ref LL_RTC_BKP_DR9 (*)
+ * @arg @ref LL_RTC_BKP_DR10 (*)
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)(&(RTCx->BKP0R));
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return (*(__IO uint32_t *)tmp);
+}
+
+/**
+ * @}
+ */
+#endif /* RTC_BACKUP_SUPPORT */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+ * @{
+ */
+
+/**
+ * @brief Set Calibration output frequency (1 Hz or 512 Hz)
+ * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_SetOutputFreq
+ * @param RTCx RTC Instance
+ * @param Frequency This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
+{
+ MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
+}
+
+/**
+ * @brief Get Calibration output frequency (1 Hz or 512 Hz)
+ * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n
+ * CR COSEL LL_RTC_CAL_GetOutputFreq
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
+ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
+}
+
+/**
+ * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALP LL_RTC_CAL_SetPulse
+ * @param RTCx RTC Instance
+ * @param Pulse This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
+ * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
+}
+
+/**
+ * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
+ * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+}
+
+/**
+ * @brief Set the calibration cycle period
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_SetPeriod
+ * @param RTCx RTC Instance
+ * @param Period This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
+}
+
+/**
+ * @brief Get the calibration cycle period
+ * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
+ * CALR CALW16 LL_RTC_CAL_GetPeriod
+ * @param RTCx RTC Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_PERIOD_32SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_16SEC
+ * @arg @ref LL_RTC_CALIB_PERIOD_8SEC
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
+}
+
+/**
+ * @brief Set Calibration minus
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @rmtoll CALR CALM LL_RTC_CAL_SetMinus
+ * @param RTCx RTC Instance
+ * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
+{
+ MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
+}
+
+/**
+ * @brief Get Calibration minus
+ * @rmtoll CALR CALM LL_RTC_CAL_GetMinus
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
+{
+ return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Recalibration pending Flag
+ * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Get RTC_TAMP3 detection flag
+ * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Get RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+ * @brief Get RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+ * @brief Get Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+}
+
+/**
+ * @brief Get Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Get Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Get Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+}
+
+/**
+ * @brief Get Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+}
+
+#if defined(RTC_TAMPER3_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP3 detection flag
+ * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER3_SUPPORT */
+
+#if defined(RTC_TAMPER2_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP2 detection flag
+ * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER2_SUPPORT */
+
+#if defined(RTC_TAMPER1_SUPPORT)
+/**
+ * @brief Clear RTC_TAMP1 detection flag
+ * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_TAMPER1_SUPPORT */
+
+/**
+ * @brief Clear Time-stamp overflow flag
+ * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Time-stamp flag
+ * @rmtoll ISR TSF LL_RTC_ClearFlag_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Clear Wakeup timer flag
+ * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Clear Alarm B flag
+ * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Clear Alarm A flag
+ * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization flag
+ * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll ISR RSF LL_RTC_ClearFlag_RS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+ WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
+}
+
+/**
+ * @brief Get Initialization status flag
+ * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+}
+
+/**
+ * @brief Get Shift operation pending flag
+ * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Get Wakeup timer write flag
+ * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Get Alarm B write flag
+ * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+}
+
+/**
+ * @brief Get Alarm A write flag
+ * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_EnableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+/**
+ * @brief Disable Time-stamp interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR TSIE LL_RTC_DisableIT_TS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Enable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+
+/**
+ * @brief Disable Wakeup timer interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Enable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Disable Alarm B interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
+}
+
+/**
+ * @brief Enable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Disable Alarm A interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
+}
+
+/**
+ * @brief Enable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_EnableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Disable all Tamper Interrupt
+ * @rmtoll TAFCR TAMPIE LL_RTC_DisableIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPIE);
+}
+
+/**
+ * @brief Check if Time-stamp interrupt is enabled or not
+ * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+}
+
+#if defined(RTC_WAKEUP_SUPPORT)
+/**
+ * @brief Check if Wakeup timer interrupt is enabled or not
+ * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+}
+#endif /* RTC_WAKEUP_SUPPORT */
+
+/**
+ * @brief Check if Alarm B interrupt is enabled or not
+ * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+}
+
+/**
+ * @brief Check if Alarm A interrupt is enabled or not
+ * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+}
+
+/**
+ * @brief Check if all the TAMPER interrupts are enabled or not
+ * @rmtoll TAFCR TAMPIE LL_RTC_IsEnabledIT_TAMP
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->TAFCR,
+ RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_spi.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,637 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_spi.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_spi.h"
+#include "stm32f3xx_ll_bus.h"
+#include "stm32f3xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+#if defined(SPI4)
+ if (SPIx == SPI4)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
+
+ status = SUCCESS;
+ }
+#endif /* SPI4 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - DataWidth: DS[3:0] bits
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2,
+ SPI_CR2_DS | SPI_CR2_SSOE,
+ SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+ uint32_t sourceclock = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+/**
+ * @brief Configures the full duplex mode for the I2Sx peripheral using its extension
+ * I2Sxext according to the specified parameters in the I2S_InitStruct.
+ * @note The structure pointed by I2S_InitStruct parameter should be the same
+ * used for the master I2S peripheral. In this case, if the master is
+ * configured as transmitter, the slave will be receiver and vice versa.
+ * Or you can force a different mode by modifying the field I2S_Mode to the
+ * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
+ * @param I2Sxext SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2Sxext registers are Initialized
+ * - ERROR: I2Sxext registers are not Initialized
+ */
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t mode = 0U;
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Reset I2SPR registers */
+ WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
+
+ /* Get the mode to be configured for the extended I2S */
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
+ {
+ mode = LL_I2S_MODE_SLAVE_RX;
+ }
+ else
+ {
+ if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
+ {
+ mode = LL_I2S_MODE_SLAVE_TX;
+ }
+ }
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(I2Sxext->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD | mode);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_spi.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,2264 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_spi.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_SPI_H
+#define __STM32F3xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
+ * @{
+ */
+#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
+#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
+#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
+#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
+#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
+#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
+#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
+#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
+#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
+#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
+#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
+ * @{
+ */
+#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
+#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
+ * @{
+ */
+#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
+ * @{
+ */
+#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
+#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
+#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
+#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
+ * @{
+ */
+#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
+#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
+#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
+#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
+ * @{
+ */
+#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
+#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+/**
+ * @brief Set serial protocol used
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR2 FRF LL_SPI_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
+}
+
+/**
+ * @brief Get serial protocol used
+ * @rmtoll CR2 FRF LL_SPI_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
+ * @arg @ref LL_SPI_PROTOCOL_TI
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
+}
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR2 DS LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR2 DS LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_4BIT
+ * @arg @ref LL_SPI_DATAWIDTH_5BIT
+ * @arg @ref LL_SPI_DATAWIDTH_6BIT
+ * @arg @ref LL_SPI_DATAWIDTH_7BIT
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_9BIT
+ * @arg @ref LL_SPI_DATAWIDTH_10BIT
+ * @arg @ref LL_SPI_DATAWIDTH_11BIT
+ * @arg @ref LL_SPI_DATAWIDTH_12BIT
+ * @arg @ref LL_SPI_DATAWIDTH_13BIT
+ * @arg @ref LL_SPI_DATAWIDTH_14BIT
+ * @arg @ref LL_SPI_DATAWIDTH_15BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
+}
+
+/**
+ * @brief Set threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @param Threshold This parameter can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
+}
+
+/**
+ * @brief Get threshold of RXFIFO that triggers an RXNE event
+ * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_TH_HALF
+ * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+ * @brief Set CRC Length
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
+ * @param SPIx SPI Instance
+ * @param CRCLength This parameter can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
+}
+
+/**
+ * @brief Get CRC Length
+ * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_CRC_8BIT
+ * @arg @ref LL_SPI_CRC_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @brief Enable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Disable NSS pulse management
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
+}
+
+/**
+ * @brief Check if NSS pulse is enabled
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+}
+
+/**
+ * @brief Get FIFO reception Level
+ * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_RX_FIFO_EMPTY
+ * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_RX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
+}
+
+/**
+ * @brief Get FIFO Transmission Level
+ * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_TX_FIFO_EMPTY
+ * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
+ * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
+ * @arg @ref LL_SPI_TX_FIFO_FULL
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
+}
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+ tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @note Clearing this flag is done by reading SPIx_SR register
+ * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+ * @brief Set parity of Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX)));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA reception
+ * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX));
+}
+
+/**
+ * @brief Set parity of Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
+{
+ MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX)));
+}
+
+/**
+ * @brief Get parity configuration for Last DMA transmission
+ * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DMA_PARITY_ODD
+ * @arg @ref LL_SPI_DMA_PARITY_EVEN
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) & (SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+ *((__IO uint8_t *)&SPIx->DR) = TxData;
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ *((__IO uint16_t *)&SPIx->DR) = TxData;
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR LL_SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+}
+
+/**
+ * @brief Get frame format error flag
+ * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_FRE(SPIx);
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @brief Clear frame format error flag
+ * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_FRE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
+ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
+#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_system.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1745 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_system.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of SYSTEM LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_SYSTEM_H
+#define __STM32F3xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/* Defines used for position in the register */
+#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
+
+/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
+#define SYSCFG_OFFSET_CFGR1 (uint32_t)0x00000000U
+#define SYSCFG_OFFSET_CFGR3 (uint32_t)0x00000050U
+
+/* Mask used for TIM breaks functions */
+#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
+#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
+#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#else
+#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
+#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+ * @{
+ */
+#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
+#if defined(FMC_BANK1)
+#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
+#endif /* FMC_BANK1 */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
+#define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
+#define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
+/**
+ * @}
+ */
+#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
+#define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
+#define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
+/** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
+ * @{
+ */
+#if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
+#define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
+#define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
+#endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
+#if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
+#define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
+#define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
+#define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
+#define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
+#endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
+
+/** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
+ * @{
+ */
+#define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
+#define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
+#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
+#define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
+#define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
+#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
+#define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
+#define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
+ * @{
+ */
+#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
+#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
+#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
+#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
+#define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
+#define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
+#if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
+#define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
+#define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
+#endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
+#if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
+#define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
+#define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
+#endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
+/** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
+#define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
+#define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE)
+#define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
+#if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
+#define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
+#endif /* SYSCFG_CFGR1_ENCODER_MODE */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
+/** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
+ * @{
+ */
+#define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
+#define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
+#define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
+#define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
+#define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
+#define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
+#define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
+#define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
+#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
+#define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
+#define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
+#define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
+#define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
+#define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
+#define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
+#define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
+#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
+#define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
+#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
+#define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
+#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
+#define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
+
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
+ * @{
+ */
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
+#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
+#define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
+#if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
+#define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
+#define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
+#endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
+#if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
+#define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
+#define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
+#endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
+
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+ * @{
+ */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
+#if defined(SYSCFG_CFGR1_I2C2_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
+#endif /*SYSCFG_CFGR1_I2C2_FMP*/
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
+#endif /*SYSCFG_CFGR1_I2C3_FMP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+ * @{
+ */
+#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
+#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
+#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
+#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
+#if defined(GPIOE)
+#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
+#endif /* GPIOE */
+#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
+#endif /* GPIOG */
+#if defined(GPIOH)
+#define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
+#endif /* GPIOH */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+ * @{
+ */
+#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+ * @{
+ */
+#if defined(SYSCFG_CFGR2_PVD_LOCK)
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
+#endif /*SYSCFG_CFGR2_PVD_LOCK*/
+#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
+#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
+/**
+ * @}
+ */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
+ * @{
+ */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
+#if defined(SYSCFG_RCR_PAGE4)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
+#endif
+#if defined(SYSCFG_RCR_PAGE8)
+#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
+#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
+#endif
+/**
+ * @}
+ */
+
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
+#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
+#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
+#endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
+#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
+#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
+#endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+ * @{
+ */
+
+/**
+ * @brief Set memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
+ * @param Memory This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+ MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
+}
+
+/**
+ * @brief Get memory mapping at address 0x00000000
+ * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_REMAP_FLASH
+ * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+ * @arg @ref LL_SYSCFG_REMAP_SRAM
+ * @arg @ref LL_SYSCFG_REMAP_FMC (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
+}
+
+#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for SPI
+ * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
+ * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
+ * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
+ * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
+}
+#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for I2C
+ * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
+ * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
+ * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
+}
+#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
+
+#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
+/**
+ * @brief Set DMA request remapping bits for ADC
+ * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
+ * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
+ * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
+ * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
+ MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
+}
+#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
+
+/**
+ * @brief Set DMA request remapping bits for DAC
+ * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
+ * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
+ * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
+ * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
+ * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
+ * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
+ * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
+}
+
+/**
+ * @brief Set DMA request remapping bits for TIM
+ * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
+ * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
+ * @param Remap This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
+ * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
+ * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
+ * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
+ * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
+}
+
+#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
+/**
+ * @brief Set Timer input remap
+ * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
+ * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
+ * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
+ * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
+}
+#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
+
+#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
+/**
+ * @brief Set ADC Trigger remap
+ * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
+ * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
+ * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
+ * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
+ * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
+ * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
+ * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
+ * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
+ * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
+ * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
+ * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
+ * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
+ * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
+ * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
+ * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
+ * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
+ * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
+ * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
+ * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
+ * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
+ * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
+{
+ MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
+}
+#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
+
+#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
+/**
+ * @brief Set DAC Trigger remap
+ * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
+ * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
+ * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
+ * @param Remap This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
+ * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
+{
+ __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
+ MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
+}
+#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
+
+#if defined(SYSCFG_CFGR1_USB_IT_RMP)
+/**
+ * @brief Enable USB interrupt remap
+ * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
+ * respectively
+ * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
+}
+
+/**
+ * @brief Disable USB interrupt remap
+ * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
+}
+#endif /* SYSCFG_CFGR1_USB_IT_RMP */
+
+#if defined(SYSCFG_CFGR1_VBAT)
+/**
+ * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
+ * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+}
+
+/**
+ * @brief Disable VBAT monitoring
+ * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
+}
+#endif /* SYSCFG_CFGR1_VBAT */
+
+/**
+ * @brief Enable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
+ * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Disable the I2C fast mode plus driving capability.
+ * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
+ * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
+ * @param ConfigFastModePlus This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
+ * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
+}
+
+/**
+ * @brief Enable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Enable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Enable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Enable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Enable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Enable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
+{
+ SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Disable Floating Point Unit Invalid operation Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
+}
+
+/**
+ * @brief Disable Floating Point Unit Divide-by-zero Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
+}
+
+/**
+ * @brief Disable Floating Point Unit Underflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
+}
+
+/**
+ * @brief Disable Floating Point Unit Overflow Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
+}
+
+/**
+ * @brief Disable Floating Point Unit Input denormal Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
+}
+
+/**
+ * @brief Disable Floating Point Unit Inexact Interrupt
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
+{
+ CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
+}
+
+/**
+ * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
+}
+
+/**
+ * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
+}
+
+/**
+ * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
+}
+
+/**
+ * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
+}
+
+/**
+ * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
+}
+
+/**
+ * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
+ * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
+{
+ return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
+}
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+ *
+ * (*) value not defined in all devices.
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
+ * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_LINE0
+ * @arg @ref LL_SYSCFG_EXTI_LINE1
+ * @arg @ref LL_SYSCFG_EXTI_LINE2
+ * @arg @ref LL_SYSCFG_EXTI_LINE3
+ * @arg @ref LL_SYSCFG_EXTI_LINE4
+ * @arg @ref LL_SYSCFG_EXTI_LINE5
+ * @arg @ref LL_SYSCFG_EXTI_LINE6
+ * @arg @ref LL_SYSCFG_EXTI_LINE7
+ * @arg @ref LL_SYSCFG_EXTI_LINE8
+ * @arg @ref LL_SYSCFG_EXTI_LINE9
+ * @arg @ref LL_SYSCFG_EXTI_LINE10
+ * @arg @ref LL_SYSCFG_EXTI_LINE11
+ * @arg @ref LL_SYSCFG_EXTI_LINE12
+ * @arg @ref LL_SYSCFG_EXTI_LINE13
+ * @arg @ref LL_SYSCFG_EXTI_LINE14
+ * @arg @ref LL_SYSCFG_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSCFG_EXTI_PORTA
+ * @arg @ref LL_SYSCFG_EXTI_PORTB
+ * @arg @ref LL_SYSCFG_EXTI_PORTC
+ * @arg @ref LL_SYSCFG_EXTI_PORTD
+ * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTF
+ * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+ * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+}
+
+/**
+ * @brief Set connections to TIMx Break inputs
+ * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
+ * @param Break This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+ MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
+}
+
+/**
+ * @brief Get connections to TIMx Break inputs
+ * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
+ * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
+ * @retval Returned value can be can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
+ * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+ *
+ * (*) value not defined in all devices.
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{
+ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
+}
+
+#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
+/**
+ * @brief Disable RAM Parity Check Disable
+ * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
+{
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
+}
+#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
+
+#if defined(SYSCFG_CFGR2_SRAM_PE)
+/**
+ * @brief Check if SRAM parity error detected
+ * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
+{
+ return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
+}
+
+/**
+ * @brief Clear SRAM parity error flag
+ * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
+{
+ SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
+}
+#endif /* SYSCFG_CFGR2_SRAM_PE */
+
+#if defined(SYSCFG_RCR_PAGE0)
+/**
+ * @brief Enable CCM SRAM page write protection
+ * @note Write protection is cleared only by a system reset
+ * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
+ * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
+ * @param PageWRP This parameter can be a combination of the following values:
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
+ * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
+{
+ SET_BIT(SYSCFG->RCR, PageWRP);
+}
+#endif /* SYSCFG_RCR_PAGE0 */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
+ * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
+ * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
+ * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
+ * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+ * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
+}
+
+#if defined(FLASH_ACR_HLFCYA)
+/**
+ * @brief Enable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Disable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Check if Flash Half Cycle Access is enabled or not
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
+}
+#endif /* FLASH_ACR_HLFCYA */
+
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,1467 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_tim.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_tim.h"
+#include "stm32f3xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#if defined(TIM_CCMR1_OC1M_3)
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+#else
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+#endif
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+#if defined(TIM_BDTR_BKF)
+
+#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+
+#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
+
+#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+
+#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+#endif /* TIM_BDTR_BK2E */
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#if defined(TIM_CCER_CC5E)
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#endif /* TIM_CCER_CC5E */
+#if defined(TIM_CCER_CC6E)
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+#endif /* TIM_CCER_CC6E */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+
+ if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+
+#if defined(TIM1)
+ else if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+#endif
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif
+#if defined(TIM4)
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+#endif
+#if defined(TIM5)
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+#endif
+#if defined(TIM6)
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+#endif
+#if defined(TIM7)
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+#endif
+#if defined(TIM8)
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+#endif
+#if defined(TIM12)
+ else if (TIMx == TIM12)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ }
+#endif
+#if defined(TIM13)
+ else if (TIMx == TIM13)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ }
+#endif
+#if defined(TIM14)
+ else if (TIMx == TIM14)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ }
+#endif
+#if defined(TIM15)
+ else if (TIMx == TIM15)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+ }
+#endif
+#if defined(TIM16)
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+#endif
+#if defined(TIM17)
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+#endif
+#if defined(TIM18)
+ else if (TIMx == TIM18)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
+ }
+#endif
+#if defined(TIM19)
+ else if (TIMx == TIM19)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
+ }
+#endif
+#if defined(TIM20)
+ else if (TIMx == TIM20)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
+ }
+#endif
+ else
+ {
+ result = ERROR;
+ }
+
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @note OC5 and OC6 are not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+#if defined(TIM_CCER_CC5E)
+ case LL_TIM_CHANNEL_CH5:
+ result = OC5Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH6:
+ result = OC6Config(TIMx, TIM_OC_InitStruct);
+ break;
+#endif /* TIM_CCER_CC5E */
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+#if defined TIM_CR2_MMS2
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
+ * when TIMx operates in Hall sensor interface mode.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+#endif /* TIM_CR2_MMS2 */
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+#if defined(TIM_BDTR_BKF)
+ TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
+ TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
+ TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+#endif /* TIM_BDTR_BK2E */
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * can be necessary to configure all of them during the first write access to
+ * the TIMx_BDTR register.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+#if defined(TIM_BDTR_BKF)
+ if (IS_TIM_ADVANCED_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ }
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+
+ if (IS_TIM_BKIN2_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
+ assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
+ assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+
+ /* Set the BREAK2 input related BDTR bit-fields */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+ }
+#endif /* TIM_BDTR_BK2E */
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#else
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+#endif
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+#if defined(TIM_CCER_CC5E)
+/**
+ * @brief Configure the TIMx output channel 5.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
+ * @note OC5 is not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC5_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC5E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
+
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 6.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
+ * @note OC6 is not available for all F3 devices
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr3 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC6_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 5: Reset the CC6E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CCMR3 register value */
+ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
+ }
+
+ /* Write to TIMx CCMR3 */
+ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+#endif /* TIM_CCER_CC5E */
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC4P | TIM_CCER_CC4NP),
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_tim.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,4946 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_tim.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_TIM_H
+#define __STM32F3xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U, /* 6: TIMx_CH4 */
+ 0x3CU, /* 7: TIMx_CH5 */
+ 0x3CU /* 8: TIMx_CH6 */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U, /* 6: OC4M, OC4FE, OC4PE */
+ 0U, /* 7: OC5M, OC5FE, OC5PE */
+ 8U /* 8: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U, /* 6: CC4S, IC4PSC, IC4F */
+ 0U, /* 7: - NA */
+ 0U /* 8: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U, /* 6: CC4P */
+ 16U, /* 7: CC5P */
+ 20U /* 8: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U, /* 6: OIS4 */
+ 8U, /* 7: OIS5 */
+ 10U /* 8: OIS6 */
+};
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+
+#define TIMx_OR_RMP_SHIFT (16U)
+#define TIMx_OR_RMP_MASK (0x0000FFFFU)
+#if defined(TIM1)
+#define TIM1_OR_RMP_MASK ((uint32_t)(TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
+#endif /* TIM1 */
+#if defined (TIM8)
+#define TIM8_OR_RMP_MASK ((uint32_t)(TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
+#endif /* TIM8 */
+#if defined(TIM14)
+#define TIM14_OR_RMP_MASK ((uint32_t)(TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
+#endif /* TIM14 */
+#if defined(TIM16)
+#define TIM16_OR_RMP_MASK ((uint32_t)(TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT))
+#endif /* TIM16 */
+#if defined(TIM20)
+#define TIM20_OR_RMP_MASK ((uint32_t)(TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT))
+#endif /* TIM20 */
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7FU)
+#define DT_DELAY_2 ((uint8_t)0x3FU)
+#define DT_DELAY_3 ((uint8_t)0x1FU)
+#define DT_DELAY_4 ((uint8_t)0x1FU)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00U)
+#define DT_RANGE_2 ((uint8_t)0x80U)
+#define DT_RANGE_3 ((uint8_t)0xC0U)
+#define DT_RANGE_4 ((uint8_t)0xE0U)
+
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval none
+ */
+#if defined(TIM_CCR5_CCR5)
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
+#else
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+#endif
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+
+ uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+ has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#if defined(TIM_BDTR_BKF)
+ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+#endif /* TIM_BDTR_BK2E */
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
+#endif /* TIM_CCMR1_OC1M_3 */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE ((uint32_t)0x00000000U) /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+#if defined(TIM_BDTR_BK2E)
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+ * @{
+ */
+#define LL_TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2E */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ * @{
+ */
+#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ * @{
+ */
+#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
+ * @{
+ */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ * @{
+ */
+#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ * @{
+ */
+#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+ * @{
+ */
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
+#else
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+#endif
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ * @{
+ */
+#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ * @{
+ */
+#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
+#endif
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#endif
+#if defined(TIM_CCMR1_OC1M_3)
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ * @{
+ */
+#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ * @{
+ */
+#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+ * @}
+ */
+
+#if defined(TIM_CCR5_CCR5)
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+ * @{
+ */
+#define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+ * @}
+ */
+#endif /* TIM_CCR5_CCR5 */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+ * @{
+ */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI TIM_CCMR1_CC1S_0 << 16U /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI TIM_CCMR1_CC1S_1 << 16U /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC TIM_CCMR1_CC1S << 16U /*!< ICx is mapped on TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+ * @{
+ */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 << 16U /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 << 16U /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC << 16U /*!< Capture is done once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+ * @{
+ */
+#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2 TIM_CCMR1_IC1F_0 << 16U /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4 TIM_CCMR1_IC1F_1 << 16U /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8 (TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6 TIM_CCMR1_IC1F_2 << 16U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8 (TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6 TIM_CCMR1_IC1F_3 << 16U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6 (TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8 TIM_CCMR1_IC1F << 16U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+ * @{
+ */
+#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+ * @{
+ */
+#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+ * @{
+ */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+ * @{
+ */
+#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+ * @}
+ */
+
+#if defined(TIM_CR2_MMS2)
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+ * @{
+ */
+#define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+ * @}
+ */
+#endif /* TIM_CR2_MMS2 */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+ * @{
+ */
+#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#if defined (TIM_SMCR_SMS_3)
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
+#endif /* TIM_SMCR_SMS_3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+ * @{
+ */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+ * @{
+ */
+#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+ * @{
+ */
+#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+ * @{
+ */
+#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 ) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 ) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+ * @{
+ */
+#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+#if defined(TIM_BDTR_BKF)
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+ * @{
+ */
+#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BKF */
+
+#if defined(TIM_BDTR_BK2P)
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+ * @{
+ */
+#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2P */
+
+#if defined(TIM_BDTR_BK2F)
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+ * @{
+ */
+#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+#endif /* TIM_BDTR_BK2F */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+ * @{
+ */
+#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+ * @{
+ */
+#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+ * @{
+ */
+#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#if defined(TIM_CCR6_CCR6)
+#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#endif /* TIM_CCR6_CCR6 */
+#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+ * @{
+ */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+ * @}
+ */
+
+#if defined(TIM1)
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
+* @{
+*/
+#define LL_TIM_TIM1_ETR_ADC1_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_RMP_0 | TIM1_OR_ETR_RMP_1| TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
+/**
+ * @}
+ */
+#if defined(ADC4)
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC4 Remap
+* @{
+*/
+#define LL_TIM_TIM1_ETR_ADC4_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC4 analog watchdog x*/
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC4_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC4 analog watchdog 3 */
+/**
+ * @}
+ */
+#else
+/** @defgroup TIM_LL_EC_TIM1_ETR_ADC2_RMP TIM1 External Trigger ADC3 Remap
+* @{
+*/
+#define LL_TIM_TIM1_ETR_ADC2_RMP_NC (0x00000000U | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is not connected to ADC2 analog watchdog x*/
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 1 */
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (TIM1_OR_ETR_RMP_3 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 2 */
+#define LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (TIM1_OR_ETR_RMP_3 | TIM1_OR_ETR_RMP_2 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC2 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* ADC4 */
+#endif /* TIM1 */
+#if defined(TIM8)
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
+* @{
+*/
+#define LL_TIM_TIM8_ETR_ADC2_RMP_NC (0x00000000U | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR_ETR_RMP_0 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR_ETR_RMP_0 | TIM8_OR_ETR_RMP_1 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
+* @{
+*/
+#define LL_TIM_TIM8_ETR_ADC3_RMP_NC (0x00000000U | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR_ETR_RMP_2 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR_ETR_RMP_2 | TIM8_OR_ETR_RMP_3 | TIM8_OR_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* TIM8 */
+#if defined(TIM16)
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
+* @{
+*/
+#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input capture 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
+#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 clock */
+#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* TIM16 */
+#if defined(TIM20)
+/** @defgroup TIM_LL_EC_TIM20_ETR_ADC3_RMP TIM20 External Trigger ADC3 Remap
+* @{
+*/
+#define LL_TIM_TIM20_ETR_ADC3_RMP_NC (0x00000000U | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is not connected to ADC3 analog watchdog x */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (TIM20_OR_ETR_RMP_0 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 2 */
+#define LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (TIM20_OR_ETR_RMP_0 | TIM20_OR_ETR_RMP_1 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC3 analog watchdog 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TIM20_ETR_ADC4_RMP TIM20 External Trigger ADC4 Remap
+* @{
+*/
+#define LL_TIM_TIM20_ETR_ADC4_RMP_NC (0x00000000U | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is not connected to ADC4 analog watchdog x */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (TIM20_OR_ETR_RMP_2 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 1 */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 2 */
+#define LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (TIM20_OR_ETR_RMP_2 | TIM20_OR_ETR_RMP_3 | TIM20_OR_RMP_MASK) /*!< TIM20_ETR is connected to ADC4 analog watchdog 3 */
+/**
+ * @}
+ */
+#endif /* TIM20 */
+#if defined(TIM14)
+/** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input1 Remap
+* @{
+*/
+#define LL_TIM_TIM14_TI1_RMP_GPIO (0x00000000U | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to GPIO */
+#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC Clock */
+#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 */
+#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
+/**
+ * @}
+ */
+#endif /* TIM14 */
+
+#if defined(TIM_SMCR_OCCS)
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+ * @{
+ */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
+/**
+ * @}
+ */
+#endif /* TIM_SMCR_OCCS*/
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+/**
+ * @brief Write a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+/**
+ * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
+ * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+ * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
+ * to TIMx_CNT register bit 31)
+ * @param __CNT__ Counter value
+ * @retval UIF status bit
+ */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
+ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+#if defined(TIM_CR1_UIFREMAP)
+/**
+ * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+ * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+ * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+ * @brief Disable update interrupt flag (UIF) remapping.
+ * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+#endif /* TIM_CR1_UIFREMAP */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel\n
+ * CCER CC5E LL_TIM_CC_EnableChannel\n
+ * CCER CC6E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel\n
+ * CCER CC5E LL_TIM_CC_DisableChannel\n
+ * CCER CC6E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC6E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * @if STM32F334x8
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @elseif STM32F303xC
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @elseif STM32F302x8
+ * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
+ * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
+ * @endif
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CCER CC5P LL_TIM_OC_ConfigOutput\n
+ * CCER CC6P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS6 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode\n
+ * @if STM32F334x8
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @elseif STM32F303xC
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @elseif STM32F302x8
+ * CCMR3 OC5M LL_TIM_OC_SetMode\n
+ * CCMR3 OC6M LL_TIM_OC_SetMode
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note The following OC modes are not available on all F3 devices :
+ * - LL_TIM_OCMODE_RETRIG_OPM1
+ * - LL_TIM_OCMODE_RETRIG_OPM2
+ * - LL_TIM_OCMODE_COMBINED_PWM1
+ * - LL_TIM_OCMODE_COMBINED_PWM2
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode\n
+ * @if STM32F334x8
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @elseif STM32F303xC
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @elseif STM32F302x8
+ * CCMR3 OC5M LL_TIM_OC_GetMode\n
+ * CCMR3 OC6M LL_TIM_OC_GetMode
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note The following OC modes are not available on all F3 devices :
+ * - LL_TIM_OCMODE_RETRIG_OPM1
+ * - LL_TIM_OCMODE_RETRIG_OPM2
+ * - LL_TIM_OCMODE_COMBINED_PWM1
+ * - LL_TIM_OCMODE_COMBINED_PWM2
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * - LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+ * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+ * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity\n
+ * CCER CC5P LL_TIM_OC_SetPolarity\n
+ * CCER CC6P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity\n
+ * CCER CC5P LL_TIM_OC_GetPolarity\n
+ * CCER CC6P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS5 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS6 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_EnableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * @if STM32F334x8
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @elseif STM32F303xC
+ * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
+ * @elseif STM32F302x8
+ * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
+ * CCMR3 OC6FE LL_TIM_OC_DisableFast
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5FE and OC6FE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_EnablePreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
+ * CCMR3 OC6PE LL_TIM_OC_DisablePreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * @if STM32F334x8
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @elseif STM32F303xC
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @elseif STM32F302x8
+ * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5PE and OC6PE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_EnableClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
+ * CCMR3 OC6CE LL_TIM_OC_DisableClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * @if STM32F334x8
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @elseif STM32F303xC
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @elseif STM32F302x8
+ * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
+ * @endif
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @arg @ref LL_TIM_CHANNEL_CH5
+ * @arg @ref LL_TIM_CHANNEL_CH6
+ * @note OC5CE and OC6CE are not available for all F3 devices
+ * @note CH5 and CH6 channels are not available for all F3 devices
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Set compare value for output channel 5 (TIMx_CCR5).
+ * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @elseif STM32F303xC
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @elseif STM32F302x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
+ * @endif
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @note CH5 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR5, CompareValue);
+}
+
+#endif /* TIM_CCR5_CCR5 */
+#if defined(TIM_CCR6_CCR6)
+/**
+ * @brief Set compare value for output channel 6 (TIMx_CCR6).
+ * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @if STM32F344x8
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @elseif STM32F303xC
+ * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @elseif STM32F302x8
+ * CCR6 CCR6 LL_TIM_OC_SetCompareCH6
+ * @endif
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @note CH6 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+#endif /* TIM_CCR6_CCR6 */
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Get compare value (TIMx_CCR5) set for output channel 5.
+ * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 5 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @elseif STM32F303xC
+ * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @elseif STM32F302x8
+ * CCR5 CCR5 LL_TIM_OC_GetCompareCH5
+ * @endif
+ * @param TIMx Timer instance
+ * @note CH5 channel is not available for all F3 devices
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR5));
+}
+
+#endif /* TIM_CCR5_CCR5 */
+#if defined(TIM_CCR6_CCR6)
+/**
+ * @brief Get compare value (TIMx_CCR6) set for output channel 6.
+ * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 6 is supported by a timer instance.
+ * @if STM32F334x8
+ * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @elseif STM32F303xC
+ * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @elseif STM32F302x8
+ * CCR6 CCR6 LL_TIM_OC_GetCompareCH6
+ * @endif
+ * @param TIMx Timer instance
+ * @note CH6 channel is not available for all F3 devices
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+#endif /* TIM_CCR6_CCR6 */
+#if defined(TIM_CCR5_CCR5)
+/**
+ * @brief Select on which reference signal the OC5REF is combined to.
+ * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the combined 3-phase PWM mode.
+ * @if STM32F334x8
+ * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @elseif STM32F303xC
+ * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @elseif STM32F302x8
+ * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
+ * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
+ * @endif
+ * @param TIMx Timer instance
+ * @param GroupCH5 This parameter can be one of the following values:
+ * @arg @ref LL_TIM_GROUPCH5_NONE
+ * @arg @ref LL_TIM_GROUPCH5_OC1REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC2REFC
+ * @arg @ref LL_TIM_GROUPCH5_OC3REFC
+ * @note CH5 channel is not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+ MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
+}
+
+#endif /* TIM_CCR5_CCR5 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * CCER CC4NP LL_TIM_IC_Config
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * CCER CC4NP LL_TIM_IC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * CCER CC4NP LL_TIM_IC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+ * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a 32 bits counter.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+#if defined(TIM_CR2_MMS2)
+/**
+ * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
+ * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can be used for ADC synchronization.
+ * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
+ * @param TIMx Timer Instance
+ * @param ADCSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO2_RESET
+ * @arg @ref LL_TIM_TRGO2_ENABLE
+ * @arg @ref LL_TIM_TRGO2_UPDATE
+ * @arg @ref LL_TIM_TRGO2_CC1F
+ * @arg @ref LL_TIM_TRGO2_OC1
+ * @arg @ref LL_TIM_TRGO2_OC2
+ * @arg @ref LL_TIM_TRGO2_OC3
+ * @arg @ref LL_TIM_TRGO2_OC4
+ * @arg @ref LL_TIM_TRGO2_OC5
+ * @arg @ref LL_TIM_TRGO2_OC6
+ * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+ * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+ * @note OC5 and OC6 are not available for all F3 devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+#endif /* TIM_CR2_MMS2 */
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+#if defined(TIM_BDTR_BKF)
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
+ * BDTR BKF LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @param BreakFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
+}
+
+#else
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+}
+
+#endif /* TIM_BDTR_BKF */
+#if defined(TIM_BDTR_BK2E)
+/**
+ * @brief Enable the break 2 function.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Disable the break 2 function.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+ * @brief Configure the break 2 input.
+ * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a second break input.
+ * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
+ * BDTR BK2F LL_TIM_ConfigBRK2
+ * @param TIMx Timer instance
+ * @param Break2Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+ * @param Break2Filter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
+}
+
+#endif /* TIM_BDTR_BK2E */
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*)
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*)
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*)
+ * (*) value not defined in all devices
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+ MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+ * @{
+ */
+/**
+ * @brief Remap TIM inputs (input channel, internal/external triggers).
+ * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * a some timer inputs can be remapped.
+ * @if STM32F334x8
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F302x8
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM16_OR TI1_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F303xC
+ * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM8_OR ETR_RMP LL_TIM_SetRemap\n
+ * TIM20_OR ETR_RMP LL_TIM_SetRemap\n
+ * @elseif STM32F373xC
+ * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
+ * @endif
+ * @param TIMx Timer instance
+ * @param Remap Remap params depends on the TIMx. Description available only
+ * in CHM version of the User Manual (not in .pdf).
+ * Otherwise see Reference Manual description of OR registers.
+ *
+ * Below description summarizes "Timer Instance" and "Remap" param combinations:
+ *
+ * TIM1: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*)
+ *
+ * TIM8: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*)
+ *
+ * TIM14: any combination of TI1_RMP where (**)
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*)
+ * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*)
+ *
+ * TIM16: any combination of TI1_RMP where (**)
+ *
+ * . . TI1_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*)
+ * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*)
+ *
+ * TIM20: any combination of ETR_RMP where (**)
+ *
+ * . . ETR_RMP can be one of the following values
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*)
+ * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*)
+ *
+ * (*) Value not defined in all devices. \n
+ * (**) Register not available in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+ MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
+}
+
+/**
+ * @}
+ */
+
+#if defined(TIM_SMCR_OCCS)
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+ * @{
+ */
+/**
+ * @brief Set the OCREF clear input source
+ * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+ * @note This function can only be used in Output compare and PWM modes.
+ * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
+ * @param TIMx Timer instance
+ * @param OCRefClearInputSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
+ * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
+}
+/**
+ * @}
+ */
+#endif /* TIM_SMCR_OCCS */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+#if defined (TIM_SR_CC5IF)
+/**
+ * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
+ * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+ * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
+}
+
+#endif /* TIM_SR_CC5IF */
+#if defined (TIM_SR_CC6IF)
+/**
+ * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
+ * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+ * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
+}
+
+#endif /* TIM_SR_CC6IF */
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+}
+
+#if defined(TIM_SR_B2IF)
+/**
+ * @brief Clear the break 2 interrupt flag (B2IF).
+ * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+ * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+ * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
+}
+
+#endif /* TIM_SR_B2IF */
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+#if defined(TIM_EGR_B2G)
+/**
+ * @brief Generate break 2 event.
+ * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+#endif /* TIM_EGR_B2G */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_TIM_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_usart.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,448 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_usart.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_usart.h"
+#include "stm32f3xx_ll_rcc.h"
+#include "stm32f3xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#if defined(USART_7BITS_SUPPORT)
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+#else
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+#endif
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+#endif /* UART5 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+#if defined(STM32F303x8)||defined(STM32F334x8)||defined(STM32F328xx)||defined(STM32F301x8)||defined(STM32F302x8)||defined(STM32F318xx)
+ LL_RCC_ClocksTypeDef RCC_Clocks;
+#endif
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration -----------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration -----------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration -----------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ if (USARTx == USART1)
+ {
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+ }
+ else if (USARTx == USART2)
+ {
+#if defined (RCC_CFGR3_USART2SW)
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+#else
+ /* USART2 clock is PCLK */
+ LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+ periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif
+ }
+ else if (USARTx == USART3)
+ {
+#if defined (RCC_CFGR3_USART3SW)
+ periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+#else
+ /* USART3 clock is PCLK */
+ LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+ periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif
+ }
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
+ }
+#endif /* UART5 */
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+ }
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR2 Configuration -----------------------*/
+ /* If Clock signal has to be output */
+ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ {
+ /* Deactivate Clock signal delivery :
+ * - Disable Clock Output: USART_CR2_CLKEN cleared
+ */
+ LL_USART_DisableSCLKOutput(USARTx);
+ }
+ else
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Enable Clock Output: USART_CR2_CLKEN set
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_usart.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,3645 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_usart.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_USART_H
+#define __STM32F3xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_USART_WriteReg function
+ * @{
+ */
+#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
+#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
+#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
+#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
+#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
+#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
+#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
+#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
+#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
+#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
+#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
+#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
+#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
+#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
+#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
+#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
+#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
+#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
+#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
+#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
+#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
+#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE (uint32_t)0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE (uint32_t)0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE (uint32_t)0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#if defined(USART_7BITS_SUPPORT)
+#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#else
+#define LL_USART_DATAWIDTH_8B (uint32_t)0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 (uint32_t)0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE (uint32_t)0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 (uint32_t)0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+ * @{
+ */
+#define LL_USART_TXRX_STANDARD (uint32_t)0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_RXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+ * @{
+ */
+#define LL_USART_TXPIN_LEVEL_STANDARD (uint32_t)0x00000000U /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+ * @{
+ */
+#define LL_USART_BINARY_LOGIC_POSITIVE (uint32_t)0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+ * @{
+ */
+#define LL_USART_BITORDER_LSBFIRST (uint32_t)0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+ * @{
+ */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT (uint32_t)0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+ * @{
+ */
+#define LL_USART_ADDRESS_DETECT_4B (uint32_t)0x00000000U /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE (uint32_t)0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+ * @{
+ */
+#define LL_USART_WAKEUP_ON_ADDRESS (uint32_t)0x00000000U /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL (uint32_t)0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B (uint32_t)0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+ * @{
+ */
+#define LL_USART_DE_POLARITY_HIGH (uint32_t)0x00000000U /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+ * @{
+ */
+#define LL_USART_DMA_REG_DATA_TRANSMIT (uint32_t)0U /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE (uint32_t)1U /*!< Get address of data register used for reception */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_ISR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+ * @brief USART enabled in STOP Mode.
+ * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+ * USART clock selection is HSI or LSE in RCC.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_EnableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief USART disabled in STOP Mode.
+ * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_DisableInStopMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+ * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_SetDataWidth\n
+ * CR1 M1 LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ *
+ * (*) Values not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M0 LL_USART_GetDataWidth\n
+ * CR1 M1 LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ *
+ * (*) Values not available on all devices
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+ * @brief Allow switch between Mute Mode and Active mode
+ * @rmtoll CR1 MME LL_USART_EnableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
+ * @rmtoll CR1 MME LL_USART_DisableMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+ * @brief Indicate if switch between Mute Mode and Active mode is allowed
+ * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+}
+
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M0 LL_USART_ConfigCharacter\n
+ * CR1 M1 LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_7B (*)
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ *
+ * (*) Values not available on all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Configure TX/RX pins swapping setting.
+ * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
+ * @param USARTx USART Instance
+ * @param SwapConfig This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+ * @brief Retrieve TX/RX pins swapping configuration.
+ * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXRX_STANDARD
+ * @arg @ref LL_USART_TXRX_SWAPPED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+ * @brief Configure RX pin active level logic
+ * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve RX pin active level logic configuration
+ * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+ * @brief Configure TX pin active level logic
+ * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
+ * @param USARTx USART Instance
+ * @param PinInvMethod This parameter can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+ * @brief Retrieve TX pin active level logic configuration
+ * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+ * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+ * @brief Configure Binary data logic.
+ * @note Allow to define how Logical data from the data register are send/received :
+ * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+ * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @param DataLogic This parameter can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+ * @brief Retrieve Binary data configuration
+ * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+ * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+ * @brief Configure transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
+ * @param USARTx USART Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Return transfer bit order (either Less or Most Significant Bit First)
+ * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
+ * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+ * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_BITORDER_LSBFIRST
+ * @arg @ref LL_USART_BITORDER_MSBFIRST
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+ * @brief Enable Auto Baud-Rate Detection
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Disable Auto Baud-Rate Detection
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+ * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+}
+
+/**
+ * @brief Set Auto Baud-Rate mode bits
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @param AutoBaudRateMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+ * @brief Return Auto Baud-Rate mode
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+ */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+ * @brief Enable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Disable Receiver Timeout
+ * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+ * @brief Indicate if Receiver Timeout feature is enabled
+ * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+ * (b7-b4 should be set to 0)
+ * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+ * (This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with 7-bit address mark detection.
+ * The MSB of the character sent by the transmitter should be equal to 1.
+ * It may also be used for character detection during normal reception,
+ * Mute mode inactive (for example, end of block detection in ModBus protocol).
+ * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+ * value and CMF flag is set on match)
+ * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
+ * CR2 ADDM7 LL_USART_ConfigNodeAddress
+ * @param USARTx USART Instance
+ * @param AddressLen This parameter can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ * @param NodeAddress 4 or 7 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+ (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+ * @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
+ * @note If 4-bit Address Detection is selected in ADDM7,
+ * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * If 7-bit Address Detection is selected in ADDM7,
+ * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+ * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+ * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_ADDRESS_DETECT_4B
+ * @arg @ref LL_USART_ADDRESS_DETECT_7B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+ * @brief Enable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Disable Overrun detection
+ * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Indicate if Overrun detection is enabled
+ * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+}
+
+/**
+ * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_SetWKUPType
+ * @param USARTx USART Instance
+ * @param Type This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+ * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUS LL_USART_GetWKUPType
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+ * @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+ * @arg @ref LL_USART_WAKEUP_ON_RXNE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+ uint32_t BaudRate)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrtemp = 0x0U;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+ brrtemp = usartdiv & 0xFFF0U;
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ USARTx->BRR = brrtemp;
+ }
+ else
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrresult = 0x0U;
+
+ usartdiv = USARTx->BRR;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ if ((usartdiv & 0xFFF7U) != 0U)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ brrresult = (PeriphClk * 2U) / usartdiv;
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = PeriphClk / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+
+/**
+ * @brief Set Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_SetRxTimeout
+ * @param USARTx USART Instance
+ * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+ * @brief Get Receiver Time Out Value (expressed in nb of bits duration)
+ * @rmtoll RTOR RTO LL_USART_GetRxTimeout
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+ * @brief Set Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_SetBlockLength
+ * @param USARTx USART Instance
+ * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+ MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @brief Get Block Length value in reception
+ * @rmtoll RTOR BLEN LL_USART_GetBlockLength
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+ * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+ * In transmission mode, it specifies the number of automatic retransmission retries, before
+ * generating a transmission error (FE bit set).
+ * In reception mode, it specifies the number or erroneous reception trials, before generating a
+ * reception error (RXNE and PE bits set)
+ * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
+ * @param USARTx USART Instance
+ * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+ * @{
+ */
+
+/**
+ * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Return DEDT (Driver Enable De-Assertion Time)
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+ * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
+ * @param USARTx USART Instance
+ * @param Time Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Return DEAT (Driver Enable Assertion Time)
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
+ * @param USARTx USART Instance
+ * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+ * @brief Enable Driver Enable (DE) Mode
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_EnableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Disable Driver Enable (DE) Mode
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_DisableDEMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+ * @brief Indicate if Driver Enable (DE) Mode is enabled
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+}
+
+/**
+ * @brief Select Driver Enable Polarity
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
+ * @param USARTx USART Instance
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+ * @brief Return Driver Enable Polarity
+ * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * Driver Enable feature is supported by the USARTx instance.
+ * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DE_POLARITY_HIGH
+ * @arg @ref LL_USART_DE_POLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll ISR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll ISR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll ISR NF LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+}
+
+/**
+ * @brief Check if the USART Read Data Register Not Empty Flag is set or not
+ * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll ISR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+}
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty Flag is set or not
+ * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+}
+
+/**
+ * @brief Check if the USART CTS interrupt Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+}
+
+/**
+ * @brief Check if the USART Receiver Time Out Flag is set or not
+ * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+}
+
+/**
+ * @brief Check if the USART End Of Block Flag is set or not
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Error Flag is set or not
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+}
+
+/**
+ * @brief Check if the USART Auto-Baud Rate Flag is set or not
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+}
+
+/**
+ * @brief Check if the USART Busy Flag is set or not
+ * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+}
+
+/**
+ * @brief Check if the USART Character Match Flag is set or not
+ * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+}
+
+/**
+ * @brief Check if the USART Wake Up from stop mode Flag is set or not
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+}
+
+/**
+ * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
+ * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+}
+
+/**
+ * @brief Check if the USART Receive Enable Acknowledge Flag is set or not
+ * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+}
+
+
+/**
+ * @brief Clear Parity Error Flag
+ * @rmtoll ICR PECF LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @rmtoll ICR FECF LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @rmtoll ICR NCF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_NCF);
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll ICR TCCF LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+ * @brief Clear Receiver Time Out Flag
+ * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+ * @brief Clear End Of Block Flag
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+ * @brief Clear Character Match Flag
+ * @rmtoll ICR CMCF LL_USART_ClearFlag_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+ * @brief Clear Wake Up from stop mode Flag
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Enable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Enable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_EnableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Enable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Enable End Of Block Interrupt
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Enable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Disable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Disable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable Character Match Interrupt
+ * @rmtoll CR1 CMIE LL_USART_DisableIT_CM
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+ * @brief Disable Receiver Timeout Interrupt
+ * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+ * @brief Disable End Of Block Interrupt
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable Wake Up from Stop Mode Interrupt
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+ * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+ * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+ * @brief Check if the USART Character Match Interrupt is enabled or disabled.
+ * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+}
+
+/**
+ * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+ * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+}
+
+/**
+ * @brief Check if the USART End Of Block Interrupt is enabled or disabled.
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+ * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * Wake-up from Stop mode feature is supported by the USARTx instance.
+ * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+ * @brief Enable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Disable DMA Disabling on Reception Error
+ * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+ * @brief Indicate if DMA Disabling on Reception Error is disabled
+ * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
+ * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
+ * @param USARTx USART Instance
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+ * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+ {
+ /* return address of TDR register */
+ data_reg_addr = (uint32_t) &(USARTx->TDR);
+ }
+ else
+ {
+ /* return address of RDR register */
+ data_reg_addr = (uint32_t) &(USARTx->RDR);
+ }
+
+ return data_reg_addr;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll RDR RDR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->TDR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll TDR TDR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->TDR = Value & 0x1FFU;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request an Automatic Baud Rate measurement on next received data frame
+ * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * Auto Baud Rate detection feature is supported by the USARTx instance.
+ * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+}
+
+/**
+ * @brief Request Break sending
+ * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+}
+
+/**
+ * @brief Put USART in mute mode and set the RWU flag
+ * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+}
+
+/**
+ * @brief Request a Receive Data flush
+ * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+}
+
+/**
+ * @brief Request a Transmit data flush
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_utils.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,583 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_utils.c
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx_ll_rcc.h"
+#include "stm32f3xx_ll_utils.h"
+#include "stm32f3xx_ll_system.h"
+#include "stm32f3xx_ll_pwr.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+
+/* Defines used for PLL range */
+#define UTILS_PLL_OUTPUT_MAX ((uint32_t)72000000U) /*!< Frequency max for PLL output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000U) /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX ((uint32_t)32000000U) /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to SYSCLK Frequency */
+#define UTILS_LATENCY1_FREQ ((uint32_t)24000000U) /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY2_FREQ ((uint32_t)48000000U) /*!< SYSCLK frequency to set FLASH latency 2 */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_16))
+
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
+
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if (Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ }
+
+ while (Delay)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ Delay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz.
+ @endverbatim
+ @internal
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ (++) +-----------------------------------------------+
+ (++) | Latency | SYSCLK clock frequency (MHz) |
+ (++) |---------------|-------------------------------|
+ (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ (++) |---------------|-------------------------------|
+ (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ (++) |---------------|-------------------------------|
+ (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ (++) +-----------------------------------------------+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief This function configures system clock with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed 72MHz
+ * @note FLASH latency can be modified through this function.
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ /* Check PREDIV value */
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ /* Force PREDIV value to 2 */
+ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if (LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed 72MHz
+ * @note FLASH latency can be modified through this function.
+ * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ /* Check PREDIV value */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param Frequency SYSCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if (Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY2_FREQ)
+ {
+ /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY1_FREQ)
+ {
+ /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
+
+ /* Check different PLL parameters according to RM */
+ /* The application software must set correctly the PLL multiplication factor to
+ not exceed 72MHz */
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t sysclk_frequency_current = 0U;
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+ /* Calculate current SYSCLK frequency */
+ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+ if (sysclk_frequency_current < SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+
+ /* Update system clock configuration */
+ if (status == SUCCESS)
+ {
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if (sysclk_frequency_current > SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+
+ /* Update SystemCoreClock variable */
+ if (status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_utils.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_utils.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of UTILS LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_UTILS_H
+#define __STM32F3xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+#else
+ uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_wwdg.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32f3xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @version V1.4.0
+ * @date 16-December-2016
+ * @brief Header file of WWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F3xx_LL_WWDG_H
+#define __STM32F3xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f3xx.h"
+
+/** @addtogroup STM32F3xx_LL_Driver
+ * @{
+ */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
+ * @{
+ */
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
+ * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
+ * then it cannot be disabled again except by a reset.
+ * This bit is set by software and only cleared by hardware after a reset.
+ * When WDGA = 1, the watchdog can generate a reset.
+ * @rmtoll CR WDGA LL_WWDG_Enable
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+ * @brief Checks if Window Watchdog is enabled
+ * @rmtoll CR WDGA LL_WWDG_IsEnabled
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+ * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
+ * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+ * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+ * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+ * @rmtoll CR T LL_WWDG_SetCounter
+ * @param WWDGx WWDG Instance
+ * @param Counter 0..0x7F (7 bit counter value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+ MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+ * @brief Return current Watchdog Counter Value (7 bits counter value)
+ * @rmtoll CR T LL_WWDG_GetCounter
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Counter value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+ * @brief Set the time base of the prescaler (WDGTB).
+ * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+ * is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
+ * @param WWDGx WWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+ * @brief Return current Watchdog Prescaler Value
+ * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
+ * @param WWDGx WWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+ * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+ * @note This window value defines when write in the WWDG_CR register
+ * to program Watchdog counter is allowed.
+ * Watchdog counter value update must occur only when the counter value
+ * is lower than the Watchdog window register value.
+ * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+ * (in the control register) is refreshed before the downcounter has reached
+ * the watchdog window register value.
+ * Physically is possible to set the Window lower then 0x40 but it is not recommended.
+ * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+ * @rmtoll CFR W LL_WWDG_SetWindow
+ * @param WWDGx WWDG Instance
+ * @param Window 0x00..0x7F (7 bit Window value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+ * @brief Return current Watchdog Window Value (7 bits value)
+ * @rmtoll CFR W LL_WWDG_GetWindow
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Window value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+/**
+ * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+ * @note This bit is set by hardware when the counter has reached the value 0x40.
+ * It must be cleared by software by writing 0.
+ * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+ * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+ * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+ * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable the Early Wakeup Interrupt.
+ * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
+ * This interrupt is only cleared by hardware after a reset
+ * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+ * @brief Check if Early Wakeup Interrupt is enabled
+ * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* WWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F3xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F3/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC) {
- return;
- }
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F3/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
- *obj->reg_clr = obj->mask;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -275,14 +244,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ARCH_MAX/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -68,7 +68,6 @@ #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -208,14 +177,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device/system_stm32f4xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/device/system_stm32f4xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -100,6 +100,7 @@
* @{
*/
+extern void SystemInitPre(void);
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_B96B_F446VE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -72,7 +72,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -167,14 +136,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -252,14 +221,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F407VG/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -216,14 +185,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8, // kept for compilation, but not existing on LQFP144
- PortJ = 9, // kept for compilation, but not existing on LQFP144
- PortK = 10 // kept for compilation, but not existing on LQFP144
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/TOOLCHAIN_GCC_ARM/STM32F429ZI.ld Thu Feb 02 17:01:33 2017 +0000
@@ -1,16 +1,23 @@
-/* Linker script to configure memory regions. */
+M_VECTOR_RAM_SIZE = 0x400;
+
+/* Heap: 1/4 of RAM. Stack: 1/8 of RAM. */
+STACK_SIZE = 0x6000;
+HEAP_SIZE = 0xC000;
+
+/* Specify the memory areas */
MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048k
- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
+{
+ VECTORS (rx) : ORIGIN = 0x08000000, LENGTH = 0x400
+ FLASH (rx) : ORIGIN = 0x08000400, LENGTH = 2048k - 0x400
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192k
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
- *
+ *
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
@@ -37,10 +44,28 @@
SECTIONS
{
- .text :
+ .isr_vector :
{
+ __vector_table = .;
KEEP(*(.isr_vector))
+ . = ALIGN(4);
+ } > VECTORS
+
+ /* Note: The uVisor expects this section at a fixed location, as specified
+ * by the porting process configuration parameter:
+ * FLASH_OFFSET. */
+ __UVISOR_FLASH_OFFSET = 0x400;
+ __UVISOR_FLASH_START = ORIGIN(VECTORS) + __UVISOR_FLASH_OFFSET;
+ .text __UVISOR_FLASH_START :
+ {
+ /* uVisor code and data */
+ . = ALIGN(4);
+ __uvisor_main_start = .;
+ *(.uvisor.main)
+ __uvisor_main_end = .;
+
*(.text*)
+
KEEP(*(.init))
KEEP(*(.fini))
@@ -69,6 +94,7 @@
} > FLASH
__exidx_start = .;
+
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
@@ -78,8 +104,62 @@
__etext = .;
_sidata = .;
- .data : AT (__etext)
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > RAM
+
+ /* uVisor own memory and private box memories
+ /* Note: The uVisor expects this section at a fixed location, as specified
+ by the porting process configuration parameter: SRAM_OFFSET. */
+ __UVISOR_SRAM_OFFSET = 0x0;
+ __UVISOR_SRAM_START = ORIGIN(CCM) + __UVISOR_SRAM_OFFSET;
+ .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
{
+ . = ALIGN(32);
+ __uvisor_bss_start = .;
+
+ /* Protected uVisor own BSS section */
+ . = ALIGN(32);
+ __uvisor_bss_main_start = .;
+ KEEP(*(.keep.uvisor.bss.main))
+ . = ALIGN(32);
+ __uvisor_bss_main_end = .;
+
+ /* Protected uVisor boxes' static memories */
+ . = ALIGN(32);
+ __uvisor_bss_boxes_start = .;
+ KEEP(*(.keep.uvisor.bss.boxes))
+ . = ALIGN(32);
+ __uvisor_bss_boxes_end = .;
+
+ . = ALIGN(32);
+ __uvisor_bss_end = .;
+ } > CCM
+
+ /* Heap space for the page allocator
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the uVisor BSS section. Otherwise, ensure it is the
+ * first one after the VTOR relocation section. */
+ .page_heap (NOLOAD) :
+ {
+ . = ALIGN(32);
+ __uvisor_page_start = .;
+ KEEP(*(.keep.uvisor.page_heap))
+ . = ALIGN((1 << LOG2CEIL(LENGTH(RAM))) / 8);
+ __uvisor_page_end = .;
+ } > RAM
+
+ .data :
+ {
+ PROVIDE( __etext = LOADADDR(.data) );
+
__data_start__ = .;
_sdata = .;
*(vtable)
@@ -112,9 +192,54 @@
__data_end__ = .;
_edata = .;
+ } > RAM AT > FLASH
+
+ /* uVisor configuration section
+ * This section must be located after all other flash regions. */
+ .uvisor.secure :
+ {
+ . = ALIGN(32);
+ __uvisor_secure_start = .;
+
+ /* uVisor secure boxes configuration tables */
+ . = ALIGN(32);
+ __uvisor_cfgtbl_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl))
+ . = ALIGN(32);
+ __uvisor_cfgtbl_end = .;
+
+ /* Pointers to the uVisor secure boxes configuration tables */
+ /* Note: Do not add any further alignment here, as uVisor will need to
+ * have access to the exact list of pointers. */
+ __uvisor_cfgtbl_ptr_start = .;
+ KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
+ KEEP(*(.keep.uvisor.cfgtbl_ptr))
+ __uvisor_cfgtbl_ptr_end = .;
+
+ /* Pointers to all boxes register gateways. These are grouped here to
+ allow discoverability and firmware verification. */
+ __uvisor_register_gateway_ptr_start = .;
+ KEEP(*(.keep.uvisor.register_gateway_ptr))
+ __uvisor_register_gateway_ptr_end = .;
+
+ . = ALIGN(32);
+ __uvisor_secure_end = .;
+ } > FLASH
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
} > RAM
- .bss :
+ .bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
@@ -126,29 +251,27 @@
_ebss = .;
} > RAM
- .heap (COPY):
+ .heap (NOLOAD):
{
+ __uvisor_heap_start = .;
__end__ = .;
end = __end__;
- *(.heap*)
+ . += HEAP_SIZE;
__HeapLimit = .;
+ __uvisor_heap_end = .;
} > RAM
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __stack = __StackTop;
+ __StackLimit = __StackTop - STACK_SIZE;
+
+ ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+ /* Provide physical memory boundaries for uVisor. */
+ __uvisor_flash_start = ORIGIN(VECTORS);
+ __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
+ __uvisor_sram_start = ORIGIN(CCM);
+ __uvisor_sram_end = ORIGIN(CCM) + LENGTH(CCM);
+ __uvisor_public_sram_start = ORIGIN(RAM);
+ __uvisor_public_sram_end = ORIGIN(RAM) + LENGTH(RAM);
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Thu Feb 02 17:01:33 2017 +0000
@@ -72,10 +72,10 @@
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
+Reset_Handler:
+ ldr sp, =__stack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
@@ -93,6 +93,12 @@
bcc CopyDataInit
/* Call the clock system intitialization function.*/
+ bl SystemInitPre
+ bl HAL_InitPre
+#if defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)
+ ldr r0, =uvisor_init
+ blx r0
+#endif /* defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED) */
bl SystemInit
/* Call static constructors */
//bl __libc_init_array
@@ -130,7 +136,7 @@
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
- .word _estack
+ .word __stack
.word Reset_Handler
.word NMI_Handler
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/cmsis_nvic.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/cmsis_nvic.c Thu Feb 02 17:01:33 2017 +0000
@@ -33,7 +33,7 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
uint32_t i;
@@ -49,7 +49,7 @@
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/cmsis_nvic.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/cmsis_nvic.h Thu Feb 02 17:01:33 2017 +0000
@@ -45,8 +45,8 @@
extern "C" {
#endif
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
+void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t __NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/system_init_pre.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "stm32f4xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* note: if uVisor is present the definition must go in system_init_pre.c */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+/* this function is needed to peform hardware initialization that must happen
+ * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
+ * put here as it depends on some APIs that need uVisor to be enabled */
+void SystemInitPre(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/system_stm32f4xx.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/device/system_stm32f4xx.c Thu Feb 02 17:01:33 2017 +0000
@@ -187,10 +187,6 @@
*/
void SystemInit(void)
{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
@@ -214,13 +210,6 @@
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
/* Configure the Cube driver */
SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
HAL_Init();
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -75,7 +75,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -293,14 +262,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8,
- PortJ = 9,
- PortK = 10
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -75,7 +75,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -186,14 +155,6 @@
RF_RXTX_SW = PC_13
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_ELMO_F411RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -243,14 +212,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8, // kept for compilation, but not existing on WLCSP143
- PortJ = 9, // kept for compilation, but not existing on WLCSP143
- PortK = 10 // kept for compilation, but not existing on WLCSP143
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_F429_F439/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -74,7 +74,6 @@
RNG_HandleTypeDef handle;
};
-#include "gpio_object.h"
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -212,14 +181,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -150,14 +119,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -259,14 +228,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -176,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F401RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -176,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
-// PortD = 3,
-// PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F410RB/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -70,7 +70,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -176,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F411RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -17,51 +17,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -237,14 +198,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F412ZG/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -56,7 +56,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -176,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -71,7 +71,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 16) | ((CHANNEL & 0x1F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -244,14 +213,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446ZE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -71,7 +71,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,43 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-// See stm32f4xx_hal_gpio.h and stm32f4xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((INVERTED & 0x01) << 15) | ((CHANNEL & 0x0F) << 11) | ((AFNUM & 0x0F) << 7) | ((PUPD & 0x07) << 4) | ((MODE & 0x0F) << 0)))
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03,
PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07,
@@ -198,14 +167,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8,
- PortJ = 9,
- PortK = 10
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -70,7 +70,6 @@
int index;
};
-#include "gpio_object.h"
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -110,6 +110,7 @@ #endif }; +#define GPIO_IP_WITHOUT_BRR #include "gpio_object.h" #ifdef __cplusplus
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/hal_init_pre.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "stm32f4xx_hal.h"
+
+/* this function is needed to peform hardware initialization that must happen
+ * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
+ * put here as it depends on some APIs that need uVisor to be enabled */
+HAL_StatusTypeDef HAL_InitPre(void)
+{
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Return function status */
+ return HAL_OK;
+}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c Thu Feb 02 17:01:33 2017 +0000 @@ -179,9 +179,6 @@ __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY);
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h Thu Feb 02 17:01:33 2017 +0000
@@ -190,6 +190,7 @@
* @{
*/
/* Initialization and de-initialization functions ******************************/
+HAL_StatusTypeDef HAL_InitPre(void);
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
--- a/targets/TARGET_STM/TARGET_STM32F4/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set_clr = &gpio->BSRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F4/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,74 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set_clr = obj->mask;
- } else {
- *obj->reg_set_clr = obj->mask << 16;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -307,14 +268,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8,
- PortJ = 9,
- PortK = 10
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/stm32f746xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/stm32f746xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f746xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -314,7 +314,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -407,7 +406,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -854,7 +852,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1322,7 +1319,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -3667,7 +3664,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -3977,6 +3973,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6044,7 +6041,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6064,6 +6061,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -6639,7 +6639,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -8974,6 +8973,7 @@
+
/**
* @}
*/
@@ -9027,28 +9027,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -9059,14 +9059,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -9076,6 +9076,7 @@
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -9098,11 +9099,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -75,7 +75,8 @@
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
- !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
#define STM32F746xx /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
@@ -84,11 +85,16 @@
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
- STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
- STM32F769NG, STM32F769NI Devices */
- /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
- /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.1.0
+ * @brief CMSIS Device version number V1.1.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@@ -122,7 +128,15 @@
/** @addtogroup Device_Included
* @{
*/
-#if defined(STM32F756xx)
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/system_stm32f7xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/system_stm32f7xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.2 - * @date 21-September-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/system_stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/device/system_stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -76,7 +76,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PeripheralPins.c Thu Feb 02 17:01:33 2017 +0000
@@ -69,14 +69,15 @@
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
- {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA
+// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // used by Audio_SDA
+ {PB_7, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF11_I2C4)}, // used by Audio_SDA // CN1 pin 40
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SDA
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
- {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14/SCL
- {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15/SCL
+ {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // used by Audio_SCL // CN1 pin 44
{NC, NC, 0}
};
@@ -118,7 +119,7 @@
const PinMap PinMap_UART_TX[] = {
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // (used by stlink usb)
- // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it
+ // {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4 )}, // ARDUINO D13 - remove SB15 to use it // LD3
{PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, // ARDUINO D14
{PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D12
{PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // ARDUINO D1
@@ -139,7 +140,7 @@
};
const PinMap PinMap_UART_RTS[] = {
- {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1 )}, // ARDUINO D13
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1 )}, // ARDUINO D13 // LD3
{PB_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4 )}, // ARDUINO D12
// {PB_14, USART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3 )}, // ARDUINO D12
{PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5 )}, // ARDUINO D5
@@ -178,7 +179,7 @@
};
const PinMap PinMap_SPI_SCLK[] = {
- {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13
+ {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO D13 // LD3
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // SD card
// {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
// {PB_3, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)},
@@ -201,13 +202,13 @@
//*** CAN ***
const PinMap PinMap_CAN_RD[] = {
- {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D10
+ {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D15
{NC, NC, 0}
};
const PinMap PinMap_CAN_TD[] = {
- {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
- {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+ {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D13 // LD3
+ {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D14
{NC, NC, 0}
-};
\ No newline at end of file
+};
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -307,14 +268,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8, // kept for compilation
- PortJ = 9, // kept for compilation
- PortK = 10 // kept for compilation
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,54 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - -//======================================= - -#define DEVICE_ID_LENGTH 24 - - - - -#include "objects.h" - -#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S Thu Feb 02 17:01:33 2017 +0000 @@ -0,0 +1,500 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20080000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/TOOLCHAIN_ARM_MICRO/stm32f769ni.sct Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2016, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+; this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+; may be used to endorse or promote products derived from this software
+; without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32F769NI: 2048 KB FLASH (0x200000) + 512 KB SRAM (0x80000)
+LR_IROM1 0x08000000 0x200000 { ; load region size_region
+
+ ER_IROM1 0x08000000 0x200000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; Total: 126 vectors = 504 bytes (0x1F8) to be reserved in RAM
+ RW_IRAM1 (0x20000000+0x1F8) (0x80000-0x1F8) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+}
+
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/stm32f769xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/stm32f769xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f769xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -326,7 +326,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -453,7 +452,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -901,7 +899,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1584,7 +1581,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -4090,7 +4087,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -4417,6 +4413,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6504,7 +6501,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6524,6 +6521,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -7095,7 +7095,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -9435,6 +9434,7 @@
#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
/******************************************************************************/
/* */
/* JPEG Encoder/Decoder */
@@ -10882,28 +10882,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -10914,14 +10914,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -10935,6 +10935,7 @@
/****************************** MDIOS Instances ********************************/
#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -10958,11 +10959,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -75,7 +75,8 @@
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
- !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
@@ -84,11 +85,16 @@
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
- STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
-#define STM32F769xx /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
- STM32F769NG, STM32F769NI Devices */
- /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
- /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
+ #define STM32F769xx /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.1.0
+ * @brief CMSIS Device version number V1.1.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@@ -122,7 +128,15 @@
/** @addtogroup Device_Included
* @{
*/
-#if defined(STM32F756xx)
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f7xx.c
* @author MCD Application Team
- * @version V1.0.2
- * @date 21-September-2015
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
@@ -83,9 +83,7 @@
HAL_StatusTypeDef HAL_Init(void);
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
+#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
@@ -132,7 +130,7 @@
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
/**
@@ -736,6 +734,7 @@
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
// Enable power clock
__PWR_CLK_ENABLE();
@@ -750,13 +749,14 @@
{
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
}
- // Warning: this configuration is for a 8 MHz xtal clock only
+ // Warning: this configuration is for a 25 MHz xtal clock only
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
+ RCC_OscInitStruct.PLL.PLLR = 2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
@@ -768,7 +768,18 @@
{
return 0; // FAIL
}
-
+
+ /* Select PLLSAI output as USB clock source */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+ PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
+ PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
+ PeriphClkInitStruct.PLLSAI.PLLSAIQ = 7;
+ PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
+ if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ return 0; // FAIL
+ }
+
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
@@ -801,7 +812,7 @@
__PWR_CLK_ENABLE();
// Enable HSI oscillator and activate PLL with HSI as source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSICalibrationValue = 16;
@@ -811,7 +822,8 @@
RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
-
+ RCC_OscInitStruct.PLL.PLLR = 2;
+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/system_stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -75,7 +75,6 @@
RNG_HandleTypeDef handle;
};
-#include "gpio_object.h"
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -250,14 +211,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8, // kept for compilation
- PortJ = 9, // kept for compilation
- PortK = 10 // kept for compilation
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f746xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f746xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -314,7 +314,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -407,7 +406,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -854,7 +852,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1322,7 +1319,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -3667,7 +3664,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -3977,6 +3973,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6044,7 +6041,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6064,6 +6061,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -6639,7 +6639,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -8974,6 +8973,7 @@
+
/**
* @}
*/
@@ -9027,28 +9027,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -9059,14 +9059,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -9076,6 +9076,7 @@
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -9098,11 +9099,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F746ZG/device/stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -75,7 +75,8 @@
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
- !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
#define STM32F746xx /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
@@ -84,11 +85,16 @@
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
- STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
- STM32F769NG, STM32F769NI Devices */
- /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
- /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.1.0
+ * @brief CMSIS Device version number V1.1.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@@ -122,7 +128,15 @@
/** @addtogroup Device_Included
* @{
*/
-#if defined(STM32F756xx)
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f756xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f756xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -315,7 +315,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -408,7 +407,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -855,7 +853,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1394,7 +1391,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -3795,7 +3792,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -4105,6 +4101,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6231,7 +6228,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6251,6 +6248,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -6826,7 +6826,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -9161,6 +9160,7 @@
+
/**
* @}
*/
@@ -9214,28 +9214,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -9246,14 +9246,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -9263,6 +9263,7 @@
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -9285,11 +9286,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/TARGET_NUCLEO_F756ZG/device/stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -75,8 +75,9 @@
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
- !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
- #define STM32F756xx /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
+ #define STM32F756xx /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
@@ -84,11 +85,16 @@
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
- STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
- STM32F769NG, STM32F769NI Devices */
- /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
- /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.1.0
+ * @brief CMSIS Device version number V1.1.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@@ -122,7 +128,15 @@
/** @addtogroup Device_Included
* @{
*/
-#if defined(STM32F756xx)
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.2 - * @date 21-September-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/device/system_stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_F746_F756/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -76,7 +76,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H, 8=I, 9=J, A=K)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -250,14 +211,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8, // kept for compilation
- PortJ = 9, // kept for compilation
- PortK = 10 // kept for compilation
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/stm32f767xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/stm32f767xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f767xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
*
* This file contains:
@@ -325,7 +325,6 @@
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
-
/**
* @brief CRC calculation unit
*/
@@ -452,7 +451,6 @@
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;
-
/**
* @brief DMA2D Controller
*/
@@ -900,7 +898,6 @@
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
-
/**
* @brief SD host Interface
*/
@@ -1502,7 +1499,7 @@
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
@@ -4007,7 +4004,6 @@
/******************** Bit definition for DMA2D_BGCLUT register **************/
-
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
@@ -4334,6 +4330,7 @@
#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
+
/******************************************************************************/
/* */
/* Flexible Memory Controller */
@@ -6417,7 +6414,7 @@
#define RTC_CR_OSEL_1 0x00400000U
#define RTC_CR_POL 0x00100000U
#define RTC_CR_COSEL 0x00080000U
-#define RTC_CR_BCK 0x00040000U
+#define RTC_CR_BKP 0x00040000U
#define RTC_CR_SUB1H 0x00020000U
#define RTC_CR_ADD1H 0x00010000U
#define RTC_CR_TSIE 0x00008000U
@@ -6437,6 +6434,9 @@
#define RTC_CR_WUCKSEL_1 0x00000002U
#define RTC_CR_WUCKSEL_2 0x00000004U
+/* Legacy define */
+#define RTC_CR_BCK RTC_CR_BKP
+
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_ITSF 0x00020000U
#define RTC_ISR_RECALPF 0x00010000U
@@ -7008,7 +7008,6 @@
#define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
-
/******************************************************************************/
/* */
/* SD host Interface */
@@ -9348,6 +9347,7 @@
#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
+
/******************************************************************************/
/* */
/* JPEG Encoder/Decoder */
@@ -9606,28 +9606,28 @@
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
- ((__INSTANCE__) == GPIOB) || \
- ((__INSTANCE__) == GPIOC) || \
- ((__INSTANCE__) == GPIOD) || \
- ((__INSTANCE__) == GPIOE) || \
- ((__INSTANCE__) == GPIOF) || \
- ((__INSTANCE__) == GPIOG) || \
- ((__INSTANCE__) == GPIOH) || \
- ((__INSTANCE__) == GPIOI) || \
- ((__INSTANCE__) == GPIOJ) || \
- ((__INSTANCE__) == GPIOK))
+ ((__INSTANCE__) == GPIOB) || \
+ ((__INSTANCE__) == GPIOC) || \
+ ((__INSTANCE__) == GPIOD) || \
+ ((__INSTANCE__) == GPIOE) || \
+ ((__INSTANCE__) == GPIOF) || \
+ ((__INSTANCE__) == GPIOG) || \
+ ((__INSTANCE__) == GPIOH) || \
+ ((__INSTANCE__) == GPIOI) || \
+ ((__INSTANCE__) == GPIOJ) || \
+ ((__INSTANCE__) == GPIOK))
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
@@ -9638,14 +9638,14 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
- ((__INSTANCE__) == I2C2) || \
- ((__INSTANCE__) == I2C3) || \
- ((__INSTANCE__) == I2C4))
+ ((__INSTANCE__) == I2C2) || \
+ ((__INSTANCE__) == I2C3) || \
+ ((__INSTANCE__) == I2C4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3))
/******************************* LPTIM Instances ********************************/
#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
@@ -9659,6 +9659,7 @@
/****************************** MDIOS Instances ********************************/
#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
+
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
@@ -9682,11 +9683,11 @@
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
- ((__INSTANCE__) == SPI2) || \
- ((__INSTANCE__) == SPI3) || \
- ((__INSTANCE__) == SPI4) || \
- ((__INSTANCE__) == SPI5) || \
- ((__INSTANCE__) == SPI6))
+ ((__INSTANCE__) == SPI2) || \
+ ((__INSTANCE__) == SPI3) || \
+ ((__INSTANCE__) == SPI4) || \
+ ((__INSTANCE__) == SPI5) || \
+ ((__INSTANCE__) == SPI6))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -75,7 +75,8 @@
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
- !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx)
+ !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+ !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
@@ -83,12 +84,17 @@
/* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
-#define STM32F767xx /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
- STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI, STM32F768AI Devices */
+ #define STM32F767xx /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
- STM32F769NG, STM32F769NI Devices */
- /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI, STM32F778AI Devices */
- /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI Devices */
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+ STM32F722VC, STM32F722RC Devices */
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -105,11 +111,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.1.0
+ * @brief CMSIS Device version number V1.1.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
@@ -122,7 +128,15 @@
/** @addtogroup Device_Included
* @{
*/
-#if defined(STM32F756xx)
+#if defined(STM32F722xx)
+ #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+ #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+ #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+ #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/system_stm32f7xx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/system_stm32f7xx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.2 - * @date 21-September-2015 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/system_stm32f7xx.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/device/system_stm32f7xx.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_NUCLEO_F767ZI/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -75,7 +75,6 @@
RNG_HandleTypeDef handle;
};
-#include "gpio_object.h"
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -111,6 +111,7 @@ #endif }; +#define GPIO_IP_WITHOUT_BRR #include "gpio_object.h" #ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html Thu Feb 02 17:01:33 2017 +0000 @@ -676,7 +676,64 @@ <tr style=""> <td style="padding: 0in;" valign="top"> <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2> -<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 22-April-2016</span></h3> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.2 / 23-September-2016</span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates +to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + Cortex</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Move HAL_MPU_Disable() and + HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Clear the whole MPU control + register in HAL_MPU_Disable() API</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + CRC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_CRC_DeInit() + function to reset IDR register</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + DMA</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add a check on DMA stream + instance in HAL_DMA_DeInit() API</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul> + +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + DSI</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update + HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid + scratch in DSI_CCR register</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Fix wrong definitions in driver header file stm32f7_hal_eth.h</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the clearing of error flags</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + GPIO</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add GPIO_AF14_LTDC definition</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + I2C</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add I2C_FIRST_AND_NEXT_FRAME + for I2C Sequential Transfer Options</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL IRDA</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add IRDA_CLOCKSOURCE_UNDEFINED + define</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add + __HAL_IRDA_FLUSH_DRREGISTER() macro for IRDA DR register flush</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add macros for specific flag + clear <o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_FLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_PEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_FEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_NEFLAG() <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_OREFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_IRDA_CLEAR_IDLEFLAG()<o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new functions and call + backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmitCpltCallback()<o:p></o:p></span></li></ul></ul></ul> +<ul style="margin-top: 0cm;" type="square"><ul style="margin-top: 0cm;" type="square"><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_IRDA_AbortReceiveCpltCallback()<o:p></o:p></span></li></ul></ul></ul> +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + JPEG</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"> update </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update the output data + management when HAL_JPEG_Pause() is performed during the last data + sending</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update JPEG_FIFO_SIZE + definition</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + RCC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;"><o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Enable PWR only if necessary + for LSE configuration in HAL_RCC_OscConfig() API</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL RTC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update<o:p></o:p></span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update + HAL_RTCEx_SetTimeStamp_IT() function implementation to clear RTC + Timestamp flag<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update + HAL_RTCEx_SetTamper_IT() function implementation for better management of + different RTC tampers flags<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update + HAL_RTCEx_SetWakeUpTimer_IT() function implementation to clear wake up + timer flag</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL SMARTCARD</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Rename NACKState to NACKEnable + in the SMARTCARD_InitTypeDef structure</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add macros for specific flag + clear <o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_SMARTCARD_CLEAR_FLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_SMARTCARD_CLEAR_PEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_SMARTCARD_CLEAR_FEFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_SMARTCARD_CLEAR_NEFLAG() + <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_CLEAR_OREFLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_CLEAR_IDLEFLAG()<o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new functions and call backs + for Transfer Abort<o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortTransmitCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">SMARTCARD_AbortReceiveCpltCallback()<o:p></o:p></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL SPI</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update SPI_EndRxTxTransaction() function to RX FiFo at the end of each transaction</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add HAL_SPI_STATE_ABORT in the + HAL_SPI_StateTypeDef enum<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new functions and call + backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_SPI_Abort ()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_SPI_Abort_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_SPI_AbortCpltCallback()<br></span></li></ul></ul></ul> + +<span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span> + +<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + UART </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update<o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_UART_Receive_IT() + and HAL_UART_DMAStop() functions implementations to manage Parity error + interrupt<o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL + USART </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">update<o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_USART_Init() function by removing the clear of CLKEN bit</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_USART_Receive_IT() + and HAL_USART_DMAStop() functions implementations to manage Parity error + interrupt<o:p></o:p></span></li></ul></ul> +<ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span> update</span></li><ul style="margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update PENA bit clearing in + OTG_HPRT0 register</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul> +<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 01-July-2016</span></h3> +<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main +Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.</span> </li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL JPEG</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 22-April-2016</span></h3> <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Official release to add the support of <span style="font-weight: bold;">STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx</span> <span style="font-weight: bold;">and STM32F779xx</span> devices<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new HAL drivers for<span class="Apple-converted-space"> </span><span style="font-weight: bold;">DFSDM, DSI<span class="Apple-converted-space">, JPEG </span></span>and<span class="Apple-converted-space"> </span><span style="font-weight: bold;">MDIOS<span class="Apple-converted-space"> </span></span>peripherals</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Enhance HAL delay and timebase implementation</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** @@ -138,6 +138,7 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -150,6 +151,9 @@ #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT @@ -160,8 +164,16 @@ #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 @@ -344,6 +356,7 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 + /** * @} */ @@ -841,6 +854,8 @@ #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 +#define __DIV_LPUART UART_DIV_LPUART + #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK @@ -2637,10 +2652,22 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY -#if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE -#define RCC_IT_CSS RCC_IT_CSSHSE -#endif +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -68,11 +68,11 @@
* @{
*/
/**
- * @brief STM32F7xx HAL Driver version number V1.1.0
+ * @brief STM32F7xx HAL Driver version number V1.1.2
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ******************************************************************************
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@@ -804,7 +804,7 @@
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
- if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
+ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -381,10 +381,12 @@
/* Initialisation mode for the filter */
can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
-
+
+#if defined (CAN2)
/* Select the start slave bank */
can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
+#endif
/* Filter Deactivation */
can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@@ -88,6 +88,7 @@
* @{
*/
#ifdef HAL_CEC_MODULE_ENABLED
+#if defined (CEC)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -655,7 +656,8 @@
/**
* @}
- */
+ */
+#endif /* CEC */
#endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined (CEC)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -737,7 +739,9 @@
/**
* @}
*/
-
+
+#endif /* CEC */
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief HAL configuration file. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -270,6 +270,46 @@
#if (__MPU_PRESENT == 1)
/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0;
+}
+
+/**
+ * @brief Enables the MPU
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
+/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
@@ -291,6 +291,8 @@
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
@@ -401,53 +403,8 @@
#endif /* __MPU_PRESENT */
/**
- * @}
+ * @}
*/
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
- * @brief CORTEX private functions
- * @{
- */
-
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU */
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
- * @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged access to the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -214,6 +214,9 @@ /* Reset CRC calculation unit */ __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -100,18 +100,18 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+#if defined (CRYP)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYP_Private_define
@@ -3808,16 +3808,14 @@
/**
* @}
*/
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-
+/**
+ * @}
+ */
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
-/**
- * @}
- */
+#endif /* CRYP */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@@ -43,10 +43,10 @@
extern "C" {
#endif
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
+#if defined (CRYP)
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -521,7 +521,7 @@
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
+#endif /* CRYP */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@@ -102,7 +102,6 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
@@ -111,6 +110,8 @@
#ifdef HAL_CRYP_MODULE_ENABLED
+#if defined (CRYP)
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYPEx_Private_define
@@ -3027,12 +3028,15 @@
/**
* @}
*/
+
+#endif /* CRYP */
+
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
@@ -43,10 +43,11 @@
extern "C" {
#endif
-#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
+#if defined (CRYP)
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -206,7 +207,8 @@
* @}
*/
-#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
+#endif /* CRYP */
+
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -102,6 +102,7 @@ */ #ifdef HAL_DCMI_MODULE_ENABLED +#if defined (DCMI) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -892,6 +893,7 @@ /** * @} */ +#endif /* DCMI */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined (DCMI)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -615,6 +617,7 @@
/**
* @}
*/
+#endif /* DCMI */
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Empty file; This file is no longer used to handle the Black&White * feature. Its content is now moved to common files * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_def.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ******************************************************************************
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dfsdm.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -19,21 +19,25 @@
(#) Enable and configure the peripheral to be connected to the DMA Stream
(except for internal SRAM/FLASH memories: no initialization is
necessary) please refer to Reference manual for connection between peripherals
- and DMA requests .
+ and DMA requests.
(#) For a given Stream, program the required configuration through the following parameters:
Transfer Direction, Source and Destination data formats,
Circular, Normal or peripheral flow control mode, Stream Priority level,
Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+ -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+ __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
+ address and destination address and the Length of data to be transferred.
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
+ (+) Use HAL_DMA_Abort() function to abort the current transfer.
*** Interrupt mode IO operation ***
===================================
@@ -51,7 +55,7 @@
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
- (#) Use HAL_DMA_Abort() function to abort the current transfer
+ (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
@@ -72,9 +76,6 @@
(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
- (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
- (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
- (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
[..]
@@ -335,6 +336,9 @@
/* Return error status */
return HAL_BUSY;
}
+
+ /* Check the parameters */
+ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
@@ -613,13 +617,21 @@
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t temp;
+ uint32_t mask_cpltlevel;
uint32_t tickstart = HAL_GetTick();
uint32_t tmpisr;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs;
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* No transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
/* Polling mode not supported in circular mode and double buffering mode */
if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
{
@@ -631,18 +643,18 @@
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Transfer Complete flag */
- temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+ mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
}
else
{
/* Half Transfer Complete flag */
- temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+ mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
}
regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
tmpisr = regs->ISR;
- while((tmpisr & temp) == RESET )
+ while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
{
/* Check for the Timeout (Not applicable in circular mode)*/
if(Timeout != HAL_MAX_DELAY)
@@ -662,6 +674,9 @@
}
}
+ /* Get the ISR register value */
+ tmpisr = regs->ISR;
+
if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
/* Update error code */
@@ -707,8 +722,6 @@
return HAL_ERROR;
}
-
- status = HAL_ERROR;
}
/* Get the level transfer complete flag */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -138,6 +138,7 @@
*/
#ifdef HAL_DMA2D_MODULE_ENABLED
+#if defined (DMA2D)
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -589,8 +590,8 @@
/* Abort the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing 0 has no
- effect on START bitvalue). */
+ between the register read and the register write by the CPU (writing 0 has no
+ effect on START bitvalue) */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
/* Get tick */
@@ -638,7 +639,7 @@
/* Suspend the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing 0 has no
+ between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
@@ -693,7 +694,7 @@
/* Resume the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
- between the register read and the register write by the CPU (writing 0 has no
+ between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
@@ -1750,6 +1751,7 @@
/**
* @}
*/
+#endif /* DMA2D */
#endif /* HAL_DMA2D_MODULE_ENABLED */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined (DMA2D)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -624,6 +626,7 @@
* @}
*/
+#endif /* DMA2D */
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dsi.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief DSI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DSI peripheral:
@@ -222,7 +222,7 @@
/* Set the TX escape clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
- hdsi->Instance->CCR = hdsi->Init.TXEscapeCkdiv;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
@@ -1005,7 +1005,7 @@
/* Set the timeout clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
- hdsi->Instance->CCR = ((HostTimeouts->TimeoutCkdiv)<<8);
+ hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8);
/* High-speed transmission timeout */
hdsi->Instance->TCCR[0] &= ~DSI_TCCR0_HSTX_TOCNT;
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dsi.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of DSI HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -108,6 +108,7 @@ */ #ifdef HAL_ETH_MODULE_ENABLED +#if defined (ETH) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -2031,6 +2032,7 @@ * @} */ +#endif /* ETH */ #endif /* HAL_ETH_MODULE_ENABLED */ /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined (ETH)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -692,7 +694,7 @@
/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB ((uint32_t)5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+ #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
@@ -719,7 +721,7 @@
/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB ((uint32_t)5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+ #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
/**
@@ -2169,6 +2171,8 @@
/**
* @}
*/
+#endif /* ETH */
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -327,6 +327,9 @@
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
switch (pFlash.ProcedureOnGoing)
{
case FLASH_PROC_SECTERASE :
@@ -341,9 +344,6 @@
/* Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(temp);
- /* Clear pending flags (if any) */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-
/* Increment sector number */
temp = ++pFlash.Sector;
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
@@ -357,8 +357,6 @@
HAL_FLASH_EndOfOperationCallback(temp);
/* Sector Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
break;
}
@@ -370,8 +368,6 @@
HAL_FLASH_EndOfOperationCallback(0);
/* MAss Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
break;
}
@@ -382,8 +378,6 @@
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Programming procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
- /* Clear FLASH End of Operation pending bit */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
break;
}
default :
@@ -392,7 +386,7 @@
}
/* Check FLASH operation error flags */
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
switch (pFlash.ProcedureOnGoing)
{
@@ -423,8 +417,6 @@
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
- /* Clear FLASH error pending bits */
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR );
/*Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
@@ -641,13 +633,19 @@
}
}
- if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
- FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR )) != RESET)
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
+
+ /* Check FLASH End of Operation flag */
+ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+ {
+ /* Clear FLASH End of Operation pending bit */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+ }
/* If there is an error flag set */
return HAL_OK;
@@ -777,7 +775,12 @@
* @retval None
*/
static void FLASH_SetErrorCode(void)
-{
+{
+ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+ {
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+ }
+
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
@@ -798,10 +801,8 @@
pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
}
- if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
- {
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
- }
+ /* Clear error programming flags */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -136,7 +136,11 @@ #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ #define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + + +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -90,8 +90,8 @@
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
-#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define SECTOR_MASK 0xFFFFFF07U
+#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */
/**
* @}
*/
@@ -774,7 +774,7 @@
static uint32_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
- return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
+ return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U));
}
#endif /* FLASH_OPTCR_nDBANK */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
@@ -540,7 +540,7 @@
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
-#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 8 */
#if (FLASH_SECTOR_TOTAL == 24)
@@ -557,7 +557,7 @@
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
-#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 24 */
#if defined (FLASH_OPTCR_nDBANK)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@@ -280,7 +280,7 @@
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
+#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@@ -64,7 +64,9 @@
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
-
+/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief AF 0 selection
*/
@@ -188,7 +190,8 @@
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
+#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
+#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
@@ -231,7 +234,8 @@
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
-
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+/*----------------------------------------------------------------------------*/
/**
* @}
@@ -291,6 +295,8 @@
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
@@ -300,7 +306,9 @@
((__GPIOx__) == (GPIOG))? 6U :\
((__GPIOx__) == (GPIOH))? 7U :\
((__GPIOx__) == (GPIOI))? 8U :\
- ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+ ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
/**
* @}
*/
@@ -352,9 +360,9 @@
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))
#elif defined(STM32F745xx)
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
- ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
+ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
@@ -379,7 +387,7 @@
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
- ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
+ ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))
#elif defined(STM32F767xx) || defined(STM32F777xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
@@ -409,10 +417,11 @@
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
- ((AF) == GPIO_AF14_LTDC))
+ ((AF) == GPIO_AF14_LTDC))
#elif defined(STM32F769xx) || defined(STM32F779xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
@@ -441,6 +450,7 @@
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
@@ -472,6 +482,7 @@
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
+ ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -98,6 +98,9 @@
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
+ (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition, an then permit a call the same master sequential interface
+ several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
@@ -284,15 +287,17 @@
#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+/* Private define to centralize the enable/disable of Interrupts */
+#define I2C_XFER_TX_IT ((uint32_t)0x00000001U)
+#define I2C_XFER_RX_IT ((uint32_t)0x00000002U)
+#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004U)
-/* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT ((uint32_t)0x00000001)
-#define I2C_XFER_RX_IT ((uint32_t)0x00000002)
-#define I2C_XFER_LISTEN_IT ((uint32_t)0x00000004)
+#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011U)
+#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012U)
+#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012U)
-#define I2C_XFER_ERROR_IT ((uint32_t)0x00000011)
-#define I2C_XFER_CPLT_IT ((uint32_t)0x00000012)
-#define I2C_XFER_RELOAD_IT ((uint32_t)0x00000012)
+/* Private define Sequential Transfer Options default/reset value */
+#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
/**
* @}
*/
@@ -400,13 +405,13 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
+{
/* Check the I2C handle allocation */
if(hi2c == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
@@ -421,35 +426,34 @@
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
}
hi2c->State = HAL_I2C_STATE_BUSY;
-
+
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
-
+
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
-
+
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+
/* Configure I2Cx: Own Address1 and ack own address1 mode */
- hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if(hi2c->Init.OwnAddress1 != 0)
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- }
- else /* I2C_ADDRESSINGMODE_10BIT */
- {
- hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- }
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
-
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ }
+
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
@@ -458,15 +462,18 @@
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
+
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+ /* Disable Own Address2 before set the Own Address2 configuration */
+ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
-
+
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
@@ -613,7 +620,8 @@
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -736,7 +744,8 @@
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
@@ -1131,7 +1140,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1199,7 +1209,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1365,7 +1376,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -1449,7 +1461,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @retval HAL status
@@ -2510,7 +2523,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
@@ -2575,7 +2589,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress: Target device address. The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
* @param XferOptions: Options of Transfer, value of @ref I2C_XFEROPTIONS
@@ -2826,7 +2841,8 @@
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress: Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -247,8 +247,8 @@
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
-#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
@@ -660,6 +660,7 @@
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,14 +2,16 @@
******************************************************************************
* @file stm32f7xx_hal_irda.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the IrDA SIR ENDEC block (IrDA):
- * + Initialization and de-initialization methods
- * + IO operation methods
- * + Peripheral Control methods
+ * functionalities of the IrDA (Infrared Data Association) Peripheral
+ * (IRDA)
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral State and Errors functions
+ * + Peripheral Control functions
*
@verbatim
==============================================================================
@@ -18,35 +20,41 @@
[..]
The IRDA HAL driver can be used as follows:
- (#) Declare a IRDA_HandleTypeDef handle structure.
- (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
- (##) Enable the USARTx interface clock.
- (##) IRDA pins configuration:
- (+++) Enable the clock for the IRDA GPIOs.
- (+++) Configure these IRDA pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
+ (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
+ (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
+ in setting the associated USART or UART in IRDA mode:
+ (++) Enable the USARTx/UARTx interface clock.
+ (++) USARTx/UARTx pins configuration:
+ (+++) Enable the clock for the USARTx/UARTx GPIOs.
+ (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
+ (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
+ and HAL_IRDA_Receive_IT() APIs):
+ (+++) Configure the USARTx/UARTx interrupt priority.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
+ (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
and HAL_IRDA_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx stream.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Stream.
+ (+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
and Mode(Receiver/Transmitter) in the hirda Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_IRDA_MspInit() API.
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
+ by calling the customized HAL_IRDA_MspInit() API.
+
+ -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
+
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
@@ -135,49 +143,57 @@
* @brief HAL IRDA module driver
* @{
*/
+
#ifdef HAL_IRDA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Constants
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define TEACK_REACK_TIMEOUT 1000U
+#define IRDA_TEACK_REACK_TIMEOUT 1000U
#define HAL_IRDA_TXDMA_TIMEOUTVALUE 22000U
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE))
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
+
+/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -210,119 +226,123 @@
*/
/**
- * @brief Initializes the IRDA mode according to the specified
- * parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Initialize the IRDA mode according to the specified
+ * parameters in the IRDA_InitTypeDef and initialize the associated handle.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
- /* Check the USART/UART associated to the IRDA handle */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- if(hirda->gState == HAL_IRDA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hirda->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_IRDA_MspInit(hirda);
- }
+ if(hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hirda->Lock = HAL_UNLOCKED;
- hirda->gState = HAL_IRDA_STATE_BUSY;
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_IRDA_MspInit(hirda);
+ }
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
- /* Disable the Peripheral to update the configuration registers */
- __HAL_IRDA_DISABLE(hirda);
+ /* Disable the Peripheral to update the configuration registers */
+ __HAL_IRDA_DISABLE(hirda);
- /* Set the IRDA Communication parameters */
- IRDA_SetConfig(hirda);
+ /* Set the IRDA Communication parameters */
+ if (IRDA_SetConfig(hirda) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(hirda->Instance->CR3, USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_SCEN | USART_CR3_HDSEL);
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
- /* set the UART/USART in IRDA mode */
- SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
+ /* set the UART/USART in IRDA mode */
+ hirda->Instance->CR3 |= USART_CR3_IREN;
- /* Enable the Peripheral */
- __HAL_IRDA_ENABLE(hirda);
+ /* Enable the Peripheral */
+ __HAL_IRDA_ENABLE(hirda);
- /* TEACK and/or REACK to check before moving hirda->State to Ready */
- return (IRDA_CheckIdleState(hirda));
+ /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
+ return (IRDA_CheckIdleState(hirda));
}
/**
- * @brief DeInitializes the IRDA peripheral
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief DeInitialize the IRDA peripheral.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
- /* Check the IRDA handle allocation */
- if(hirda == NULL)
- {
- return HAL_ERROR;
- }
+ /* Check the IRDA handle allocation */
+ if(hirda == NULL)
+ {
+ return HAL_ERROR;
+ }
- /* Check the parameters */
- assert_param(IS_IRDA_INSTANCE(hirda->Instance));
+ /* Check the USART/UART associated to the IRDA handle */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- hirda->gState = HAL_IRDA_STATE_BUSY;
+ hirda->gState = HAL_IRDA_STATE_BUSY;
- /* DeInit the low level hardware */
- HAL_IRDA_MspDeInit(hirda);
- /* Disable the Peripheral */
- __HAL_IRDA_DISABLE(hirda);
+ /* DeInit the low level hardware */
+ HAL_IRDA_MspDeInit(hirda);
+ /* Disable the Peripheral */
+ __HAL_IRDA_DISABLE(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_RESET;
- hirda->RxState = HAL_IRDA_STATE_RESET;
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hirda);
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief IRDA MSP Init.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Initialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspInit could be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspInit can be implemented in the user file
+ */
}
/**
- * @brief IRDA MSP DeInit.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief DeInitialize the IRDA MSP.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IRDA_MspDeInit could be implemented in the user file
- */
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_IRDA_MspDeInit can be implemented in the user file
+ */
}
/**
@@ -330,14 +350,16 @@
*/
/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
- * @brief IRDA Transmit/Receive functions
+ * @brief IRDA Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
+ [..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
- [..]
+
+ [..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
@@ -345,23 +367,23 @@
could be corrupted.
(#) There are two modes of transfer:
- (++) Blocking mode: the communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: the communication is performed using Interrupts
- or DMA, these API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
+ (++) Blocking mode: the communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: the communication is performed using Interrupts
+ or DMA, these API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
- (#) Blocking mode API's are :
+ (#) Blocking mode APIs are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
+ (#) Non-Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
@@ -371,1186 +393,1268 @@
(#) Non-Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
+ (++) HAL_IRDA_DMAPause()
+ (++) HAL_IRDA_DMAResume()
+ (++) HAL_IRDA_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+ (++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
+ (++) HAL_IRDA_RxHalfCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_IRDA_Abort()
+ (+) HAL_IRDA_AbortTransmit()
+ (+) HAL_IRDA_AbortReceive()
+ (+) HAL_IRDA_Abort_IT()
+ (+) HAL_IRDA_AbortTransmit_IT()
+ (+) HAL_IRDA_AbortReceive_IT()
+
+ (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_IRDA_AbortCpltCallback()
+ (+) HAL_IRDA_AbortTransmitCpltCallback()
+ (+) HAL_IRDA_AbortReceiveCpltCallback()
+
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
- * @brief Sends an amount of data in blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Specify timeout value
+ * @brief Send an amount of data in blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
+ }
- /* Process Locked */
- __HAL_LOCK(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0U)
- {
- hirda->TxXferCount--;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+ while(hirda->TxXferCount > 0)
+ {
+ hirda->TxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData +=2;
- }
- else
- {
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
- }
- }
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ pData += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+ }
+ }
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Specify timeout value
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint16_t uhMask;
- uint32_t tickstart = 0U;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
- uhMask = hirda->Mask;
-
- /* Check data remaining to be received */
- while(hirda->RxXferCount > 0U)
- {
- hirda->RxXferCount--;
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2;
- }
- else
- {
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
- }
- }
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
- hirda->RxXferCount = Size;
-
- /* Computation of the mask to apply to the RDR register
- of the UART associated to the IRDA */
- IRDA_MASK_COMPUTATION(hirda);
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ uint16_t* tmp;
+ uint16_t uhMask;
+ uint32_t tickstart = 0;
- /* Enable the IRDA Data Register not empty Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Sends an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pTxBuffPtr = pData;
- hirda->TxXferSize = Size;
- hirda->TxXferCount = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->gState = HAL_IRDA_STATE_BUSY_TX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the IRDA transmit DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_FLAG_TC);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- return HAL_OK;
+ return HAL_ERROR;
}
- else
- {
- return HAL_BUSY;
- }
-}
-/**
- * @brief Receives an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hirda);
-
- hirda->pRxBuffPtr = pData;
- hirda->RxXferSize = Size;
-
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
-
- /* Set the IRDA DMA transfer complete callback */
- hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
- /* Set the IRDA DMA half transfer complete callback */
- hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
- /* Set the DMA error callback */
- hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
- /* Set the DMA abort callback */
- hirda->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, *(uint32_t*)tmp, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Enable the IRDA Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Pauses the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
/* Process Locked */
__HAL_LOCK(hirda);
- if((hirda->gState == HAL_IRDA_STATE_BUSY_TX)&&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+ uhMask = hirda->Mask;
+
+ /* Check data remaining to be received */
+ while(hirda->RxXferCount > 0)
{
- /* Disable the UART DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ hirda->RxXferCount--;
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) pData ;
+ *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pData +=2;
+ }
+ else
+ {
+ *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ }
}
- if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX)&&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Disable the UART DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+ hirda->RxXferCount = Size;
+
+ /* Computation of the mask to apply to the RDR register
+ of the UART associated to the IRDA */
+ IRDA_MASK_COMPUTATION(hirda);
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
- * @brief Resumes the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @brief Send an amount of data in DMA mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pTxBuffPtr = pData;
+ hirda->TxXferSize = Size;
+ hirda->TxXferCount = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the IRDA transmit DMA channel */
+ HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be received.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
+ * the parity bit (MSB position).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ hirda->pRxBuffPtr = pData;
+ hirda->RxXferSize = Size;
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Set the IRDA DMA transfer complete callback */
+ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
+
+ /* Set the IRDA DMA half transfer complete callback */
+ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
+
+ /* Set the DMA error callback */
+ hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+
+/**
+ * @brief Pause the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
+{
+ /* Process Locked */
+ __HAL_LOCK(hirda);
+
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Resume the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
{
- /* Process Locked */
- __HAL_LOCK(hirda);
+ /* Process Locked */
+ __HAL_LOCK(hirda);
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- /* Enable the UART DMA Tx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- }
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- /* Clear the Overrun flag before resuming the Rx transfer*/
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ /* Enable the IRDA DMA Tx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ /* Clear the Overrun flag before resuming the Rx transfer*/
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART DMA Rx request */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- }
+ /* Enable the IRDA DMA Rx request */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief Stops the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * @brief Stop the DMA Transfer.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
- /* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
- HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
- the stream and the corresponding call back is executed. */
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- /* Stop IRDA DMA Tx request if ongoing */
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ /* Abort the IRDA DMA Tx channel */
+ if(hirda->hdmatx != NULL)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmatx);
- }
- IRDA_EndTxTransfer(hirda);
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
}
- /* Stop IRDA DMA Rx request if ongoing */
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0;
+ hirda->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ return HAL_OK;
+}
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- HAL_DMA_Abort(hirda->hdmarx);
- }
- IRDA_EndRxTransfer(hirda);
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
}
- return HAL_OK;
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
}
/**
- * @brief DMA IRDA communication abort callback, when call by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0U;
- hirda->TxXferCount = 0U;
+ uint32_t abortcplt = 1;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
- HAL_IRDA_ErrorCallback(hirda);
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1;
+ }
+ else
+ {
+ abortcplt = 0;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0;
+ hirda->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+ }
+
+ return HAL_OK;
}
/**
- * @brief This function handles IRDA interrupt request.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable IRDA Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
- uint32_t isrflags, cr1its, cr3its, errorflags;
+ uint32_t isrflags = READ_REG(hirda->Instance->ISR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
- isrflags = READ_REG(hirda->Instance->ISR);
- cr1its = READ_REG(hirda->Instance->CR1);
- cr3its = READ_REG(hirda->Instance->CR3);
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
+ if (errorflags == RESET)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
+ }
- /* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ /* If some errors occur */
+ cr3its = READ_REG(hirda->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ {
+ /* IRDA parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
+
+ /* IRDA frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- /* Clear RXNE interrupt flag */
- __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
- }
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
+
+ /* IRDA noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
+
+ /* IRDA Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
- /* If some errors occur */
- if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+ /* Call IRDA Error Call back function if need be --------------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
- /* IRDA parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
- }
-
- /* IRDA frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- }
-
- /* IRDA noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- }
+ /* IRDA in mode Receiver ---------------------------------------------------*/
+ if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
- /* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- }
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
+ (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
- /* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ /* Disable the IRDA DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
- /* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((hirda->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
- /* Blocking error : transfer is aborted
- Set the IRDA state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- IRDA_EndRxTransfer(hirda);
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
- /* Disable the IRDA DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
- {
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
- {
- /* Set the IRDA DMA Abort callback :
- will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
- hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
- {
- /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
- hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Call user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- }
- }
- else
- {
- /* Non Blocking error : transfer could go on.
- Error is notified to user through user error callback */
- HAL_IRDA_ErrorCallback(hirda);
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- }
- }
- return;
+ } /* End if some error occurs */
- } /* End if some error occurs */
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ IRDA_Transmit_IT(hirda);
+ return;
+ }
- /* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
- {
- IRDA_Transmit_IT(hirda);
- return;
- }
+ /* IRDA in mode Transmitter (transmission end) -----------------------------*/
+ if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ {
+ IRDA_EndTransmit_IT(hirda);
+ return;
+ }
- /* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- IRDA_EndTransmit_IT(hirda);
- return;
- }
}
/**
- * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda: IRDA handle.
+ * @brief Tx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* At end of Tx process, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
- * @param hirda: IRDA handle.
- * @retval None
- */
-static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore huart->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-}
-
-/**
- * @brief Tx Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Tx Half Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Tx Half Transfer completed callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
+ * @brief Rx Transfer completed callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_TxCpltCallback can be implemented in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Rx Half Transfer complete callback.
+ * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Half Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval None
- */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_RxCpltCallback can be implemented in the user file
- */
-}
-
-/**
- * @brief IRDA error callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief IRDA error callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hirda);
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file
- */
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Receive Complete callback.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
}
/**
* @}
*/
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions
- * @brief IRDA control functions
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief IRDA State and Errors functions
*
@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to control the IRDA.
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IRDA peripheral.
- (+) IRDA_SetConfig() API is used to configure the IRDA communications parameters.
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of IrDA
+ communication process and also return Peripheral Errors occurred during communication process
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
+ of the IRDA peripheral handle.
+ (+) HAL_IRDA_GetError() checks in run-time errors that could occur during
+ communication.
+
@endverbatim
* @{
*/
/**
- * @brief Returns the IRDA state.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
-
- return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @brief Return the IRDA error code
- * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA.
-* @retval IRDA Error Code
-*/
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
-
- return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Configure the IRDA peripheral
- * @param hirda: irda handle
- * @retval None
- */
-static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tmpreg = 0x00000000U;
- uint32_t clocksource = 0x00000000U;
-
- /* Check the communication parameters */
- assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
- assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
- assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
- assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
- assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
- assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* Configure the IRDA Word Length, Parity and transfer Mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
- tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
-
- MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler);
+ /* Return IRDA handle state */
+ uint32_t temp1= 0x00, temp2 = 0x00;
+ temp1 = hirda->gState;
+ temp2 = hirda->RxState;
- /*-------------------------- USART BRR Configuration -----------------------*/
- IRDA_GETCLOCKSOURCE(hirda, clocksource);
- switch (clocksource)
- {
- case IRDA_CLOCKSOURCE_PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_PCLK2:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_SYSCLK:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
- break;
- case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2))/ hirda->Init.BaudRate);
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Check the IRDA Idle State
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
-{
- uint32_t tickstart = 0U;
-
- /* Initialize the IRDA ErrorCode */
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
-
- /* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- {
- /* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- /* Check if the Receiver is enabled */
- if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- /* Initialize the IRDA state*/
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @brief This function handles IRDA Communication Timeout.
- * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param Flag specifies the IRDA flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
-{
- /* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - Tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- hirda->gState= HAL_IRDA_STATE_READY;
- hirda->RxState= HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
- * @brief Send an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval IRDA Error Code
*/
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
- uint16_t* tmp;
-
- /* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- {
- if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
- {
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->RDR = (uint16_t)(*tmp & (uint16_t)0x01FFU);
- if(hirda->Init.Parity == IRDA_PARITY_NONE)
- {
- hirda->pTxBuffPtr += 2U;
- }
- else
- {
- hirda->pTxBuffPtr += 1U;
- }
- }
- else
- {
- hirda->Instance->RDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FFU);
- }
-
- if(--hirda->TxXferCount == 0U)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Wraps up transmission in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
- /* Disable the IRDA Transmit Complete Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Tx process is ended, restore hirda->gState to Ready */
- hirda->gState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receive an amount of data in non blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Receive_IT()
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @retval HAL status
- */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
- uint16_t uhdata;
- uint16_t uhMask = hirda->Mask;
-
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- {
- uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
- {
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
- *tmp = (uint16_t)(uhdata & uhMask);
- hirda->pRxBuffPtr +=2U;
- }
- else
- {
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
- }
-
- if(--hirda->RxXferCount == 0U)
- {
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the IRDA Parity Error Interrupt */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Rx process is completed, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
-
- HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
- }
- return HAL_OK;
- }
- else
- {
- /* Clear RXNE interrupt flag */
- __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief DMA IRDA Tx transfer completed callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode*/
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
- {
- hirda->TxXferCount = 0U;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- }
- /* DMA Circular mode */
- else
- {
- HAL_IRDA_TxCpltCallback(hirda);
- }
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_IRDA_TxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA Rx Transfer completed callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
- {
- hirda->RxXferCount = 0U;
-
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the IRDA CR3 register */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hirda->RxState to Ready */
- hirda->RxState = HAL_IRDA_STATE_READY;
- }
-
- HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_IRDA_RxHalfCpltCallback(hirda);
-}
-
-/**
- * @brief DMA IRDA communication error callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
-{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hirda->RxXferCount = 0U;
- hirda->TxXferCount = 0U;
-
- /* Stop IRDA DMA Tx request if ongoing */
- if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
- {
- IRDA_EndTxTransfer(hirda);
- }
-
- /* Stop IRDA DMA Rx request if ongoing */
- if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
- {
- IRDA_EndRxTransfer(hirda);
- }
-
- hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
-
- HAL_IRDA_ErrorCallback(hirda);
+ return hirda->ErrorCode;
}
/**
@@ -1561,7 +1665,581 @@
* @}
*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tmpreg = 0x00000000;
+ IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the communication parameters */
+ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
+ assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
+ assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
+ assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
+ assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Configure the IRDA Word Length, Parity and transfer Mode:
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
+
+ MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ switch (clocksource)
+ {
+ case IRDA_CLOCKSOURCE_PCLK1:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_PCLK2:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_HSI:
+ hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_SYSCLK:
+ hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_LSE:
+ hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ break;
+ case IRDA_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t tickstart = 0;
+
+ /* Initialize the IRDA ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ {
+ /* Wait until TEACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Check if the Receiver is enabled */
+ if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Initialize the IRDA state*/
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle IRDA Communication Timeout.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @param Flag Specifies the IRDA flag to check.
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+ /* Wait until flag is set */
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+
+/**
+ * @brief DMA IRDA transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
+ {
+ hirda->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
+ /* DMA Circular mode */
+ else
+ {
+ HAL_IRDA_TxCpltCallback(hirda);
+ }
+
+}
+
+/**
+ * @brief DMA IRDA transmit process half complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ HAL_IRDA_TxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* DMA Normal mode */
+ if ( HAL_IS_BIT_CLR(hdma->Instance->CR, DMA_SxCR_CIRC) )
+ {
+ hirda->RxXferCount = 0;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the IRDA CR3 register */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ }
+
+ HAL_IRDA_RxCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA receive process half complete callback.
+ * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ HAL_IRDA_RxHalfCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop IRDA DMA Tx request if ongoing */
+ if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hirda->TxXferCount = 0;
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hirda->RxXferCount = 0;
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ hirda->RxXferCount = 0;
+ hirda->TxXferCount = 0;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmarx != NULL)
+ {
+ if(hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0;
+ hirda->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmatx != NULL)
+ {
+ if(hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0;
+ hirda->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+
+ hirda->TxXferCount = 0;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Transmit_IT().
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ {
+ if(hirda->TxXferCount == 0)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pTxBuffPtr;
+ hirda->Instance->TDR = (*tmp & (uint16_t)0x01FF);
+ hirda->pTxBuffPtr += 2;
+ }
+ else
+ {
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFF);
+ }
+ hirda->TxXferCount--;
+
+ return HAL_OK;
+ }
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable the IRDA Transmit Complete Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_TxCpltCallback(hirda);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_IRDA_Receive_IT()
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint16_t* tmp;
+ uint16_t uhMask = hirda->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ hirda->pRxBuffPtr +=2;
+ }
+ else
+ {
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+ }
+
+ if(--hirda->RxXferCount == 0)
+ {
+ /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ HAL_IRDA_RxCpltCallback(hirda);
+
+ return HAL_OK;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
+
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @}
+ */
+
#endif /* HAL_IRDA_MODULE_ENABLED */
+/**
+ * @}
+ */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@@ -157,7 +157,8 @@
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x10 /*!< Undefined clock source */
}IRDA_ClockSourceTypeDef;
/**
@@ -173,13 +174,13 @@
uint16_t TxXferSize; /* IRDA Tx Transfer size */
- uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /* IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /* IRDA Rx Transfer size */
- uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /* IRDA Rx Transfer Counter */
uint16_t Mask; /* IRDA RX RDR register mask */
@@ -401,6 +402,60 @@
*/
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+/** @brief Flush the IRDA DR register.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0)
+
+/** @brief Clear the specified IRDA pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref IRDA_CLEAR_PEF
+ * @arg @ref IRDA_CLEAR_FEF
+ * @arg @ref IRDA_CLEAR_NEF
+ * @arg @ref IRDA_CLEAR_OREF
+ * @arg @ref IRDA_CLEAR_TCF
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the IRDA PE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
+
+
+/** @brief Clear the IRDA FE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
+
+/** @brief Clear the IRDA NE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
+
+/** @brief Clear the IRDA ORE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
+
+/** @brief Clear the IRDA IDLE pending flag.
+ * @param __HANDLE__: specifies the IRDA Handle.
+ * @retval None
+ */
+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
+
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__: specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
@@ -575,12 +630,24 @@
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -50,20 +50,20 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
- (+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
+ (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
- (+) Configure the IWDG prescaler and counter reload value. This reload
+ (++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (+) wait for status flags to be reset"
- (+) Depending on window parameter:
- (++) If Window Init parameter is same as Window register value,
- nothing more is done but reload counter value in order to exit
- function withy exact time base.
- (++) Else modify Window register. This will automatically reload
- watchdog counter.
+ (++) wait for status flags to be reset
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function withy exact time base.
+ (+++) Else modify Window register. This will automatically reload
+ watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_jpeg.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief JPEG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the JPEG encoder/decoder peripheral:
@@ -60,57 +60,57 @@
consumed by the peripheral and to ask for a new data chunk if the operation
(encoding/decoding) has not been complete yet.
- This CallBack should be implemented in the application side. It should
- call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
- or call HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_INPUT"
- to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
- application to provide a new input data chunk.
- Once the application succeed getting new data and if the input has been paused,
- the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
- input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
- If the application has ended feeding the HAL JPEG with input data (no more input data), the application
- Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
- with the parameter InDataLength set to zero.
+ (++) This CallBack should be implemented in the application side. It should
+ call the function HAL_JPEG_ConfigInputBuffer if new input data are available,
+ or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT
+ to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the
+ application to provide a new input data chunk.
+ Once the application succeed getting new data and if the input has been paused,
+ the application can call the function HAL_JPEG_ConfigInputBuffer to set the new
+ input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume.
+ If the application has ended feeding the HAL JPEG with input data (no more input data), the application
+ Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback)
+ with the parameter InDataLength set to zero.
- The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
- to the application to provide the input data (for encoding or decoding) by chunks.
- If the new input data chunk is not available (because data should be read from an input file
- for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
- Once the new input data chunk is available ( read from a file for example), the application
- can call the function "HAL_JPEG_ConfigInputBuffer" to provide the HAL with the new chunk
- then resume the JPEG HAL input by calling function "HAL_JPEG_Resume".
+ (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
+ to the application to provide the input data (for encoding or decoding) by chunks.
+ If the new input data chunk is not available (because data should be read from an input file
+ for example) the application can pause the JPEG input (using function HAL_JPEG_Pause)
+ Once the new input data chunk is available ( read from a file for example), the application
+ can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk
+ then resume the JPEG HAL input by calling function HAL_JPEG_Resume.
- The application can call functions HAL_JPEG_ConfigInputBuffer then "HAL_JPEG_Resume".
- any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available.
- However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
- (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
- Transferring the previous chunk buffer to the JPEG peripheral.
+ (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume.
+ any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available.
+ However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
+ (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended
+ Transferring the previous chunk buffer to the JPEG peripheral.
(#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver
has filled the given output buffer with the given size.
- This CallBack should be implemented in the application side. It should
- call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
- with the new output buffer location and size to be used to store next data chunk.
- if the application is not ready to provide the output chunk location then it can
- call the function "HAL_JPEG_Pause" with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
- to inform the JPEG HAL driver that it shall pause output data. Once the application
- is ready to receive the new data chunk (output buffer location free or available) it should call
- the function "HAL_JPEG_ConfigOutputBuffer" to provide the HAL JPEG driver
- with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
- to inform the HAL that it shall resume outputting data in the given output buffer.
+ (++) This CallBack should be implemented in the application side. It should
+ call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
+ with the new output buffer location and size to be used to store next data chunk.
+ if the application is not ready to provide the output chunk location then it can
+ call the function HAL_JPEG_Pause with parameter XferSelection set to "JPEG_PAUSE_RESUME_OUTPUT"
+ to inform the JPEG HAL driver that it shall pause output data. Once the application
+ is ready to receive the new data chunk (output buffer location free or available) it should call
+ the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver
+ with the new output chunk buffer location and size, then call "HAL_JPEG_Resume"
+ to inform the HAL that it shall resume outputting data in the given output buffer.
- The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
- the application to receive data from the JPEG peripheral by chunks. when a chunk
- is received, the application can pause the HAL JPEG output data to be able to process
- these received data (YCbCr to RGB conversion in case of decoding or data storage in case
- of encoding).
+ (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows
+ the application to receive data from the JPEG peripheral by chunks. when a chunk
+ is received, the application can pause the HAL JPEG output data to be able to process
+ these received data (YCbCr to RGB conversion in case of decoding or data storage in case
+ of encoding).
- The application can call functions HAL_JPEG_ ConfigOutputBuffer then "HAL_JPEG_Resume".
- any time (outside the HAL_JPEG_ DataReadyCallback) Once the output data buffer is free to use.
- However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
- (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
- Transferring the previous chunk buffer from the JPEG peripheral to the application.
+ (++) The application can call functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume.
+ any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use.
+ However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called
+ (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended
+ Transferring the previous chunk buffer from the JPEG peripheral to the application.
(#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has
ended the current JPEG encoding operation, and all output data has been transmitted
@@ -125,10 +125,10 @@
to retrieve the error codes.
(#) By default the HAL JPEG driver uses the default quantization tables
- as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
- User can change these default tables if necessary using the function "HAL_JPEG_SetUserQuantTables"
- Note that for decoding the quantization tables are automatically extracted from
- the JPEG header.
+ as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding.
+ User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables
+ Note that for decoding the quantization tables are automatically extracted from
+ the JPEG header.
(#) To control JPEG state you can use the following function: HAL_JPEG_GetState()
@@ -202,7 +202,7 @@
#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162U) /* Huffman AC table size : 162 codes*/
#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12U) /* Huffman AC table size : 12 codes*/
-#define JPEG_FIFO_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO size in words*/
+#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/
#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/
@@ -438,6 +438,7 @@
static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg);
static uint32_t JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg);
static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg);
+static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg);
static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma);
static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma);
static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma);
@@ -720,7 +721,7 @@
error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (uint32_t *)(hjpeg->Instance->QMEM2));
/*Use Quantization 1 table for component 1*/
- hjpeg->Instance->CONFR5 &= (~JPEG_CONFR6_QT);
+ hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT);
hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0;
/*Use Quantization 2 table for component 2*/
@@ -769,8 +770,8 @@
return HAL_ERROR;
}
/* Set the image size*/
- hjpeg->Instance->CONFR1 |= ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16); /* set the number of lines*/
- hjpeg->Instance->CONFR3 |= ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16); /* set the number of pixels per line*/
+ MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFF) << 16)); /* set the number of lines*/
+ MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFF) << 16)); /* set the number of pixels per line*/
if(hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/
{
@@ -1593,6 +1594,12 @@
assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection));
+ if(((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0) && ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0))
+ {
+ /* if nothing paused to resume return error*/
+ return HAL_ERROR;
+ }
+
if((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA)
{
@@ -1614,11 +1621,20 @@
}
if((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT)
{
- hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
- mask |= JPEG_DMA_ODMA;
- /* Start DMA FIFO Out transfer */
- HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);
+ if((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0)
+ {
+ JPEG_DMA_PollResidualData(hjpeg);
+ }
+ else
+ {
+ hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT);
+ mask |= JPEG_DMA_ODMA;
+
+ /* Start DMA FIFO Out transfer */
+ HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, hjpeg->OutDataLength >> 2);
+ }
+
}
JPEG_ENABLE_DMA(hjpeg,mask);
@@ -1758,7 +1774,7 @@
*
@verbatim
==============================================================================
- ##### JPEG Decode/Encode callback functions #####
+ ##### JPEG Decode and Encode callback functions #####
==============================================================================
[..] This section provides callback functions:
(+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback
@@ -1993,7 +2009,7 @@
{
uint32_t i, p, l, code, si;
- /* Figure C.1 Generation of table of Huffman code sizes */
+ /* Figure C.1: Generation of table of Huffman code sizes */
p = 0;
for (l = 0; l < 16; l++)
{
@@ -2011,7 +2027,7 @@
Huffsize[p] = 0;
*LastK = p;
- /* Figure C.2 Generation of table of Huffman codes */
+ /* Figure C.2: Generation of table of Huffman codes */
code = 0;
si = Huffsize[0];
p = 0;
@@ -2056,7 +2072,7 @@
return error;
}
- /* Figure C.3 Ordering procedure for encoding procedure code tables */
+ /* Figure C.3: Ordering procedure for encoding procedure code tables */
k=0;
while(k < lastK)
@@ -2227,7 +2243,7 @@
{
return error;
}
- /* Default values settings : 162167 FFFh , 168175 FD0hFD7h */
+ /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */
/* Locations 162:175 of each AC table contain information used internally by the core */
addressDef = address;
@@ -3155,8 +3171,7 @@
*/
static uint32_t JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg)
{
- uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut;
-
+ uint32_t tmpContext;
hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2);
/*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/
@@ -3166,6 +3181,51 @@
hjpeg->JpegOutCount = 0;
}
+ /*Check if remaining data in the output FIFO*/
+ if(__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0)
+ {
+ /*Stop Encoding/Decoding*/
+ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START;
+
+ tmpContext = hjpeg->Context;
+ /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/
+ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hjpeg);
+
+ /* Change the JPEG state */
+ hjpeg->State = HAL_JPEG_STATE_READY;
+
+ /*Call End of Encoding/Decoding callback */
+ if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE)
+ {
+ HAL_JPEG_DecodeCpltCallback(hjpeg);
+ }
+ else if((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_ENCODE)
+ {
+ HAL_JPEG_EncodeCpltCallback(hjpeg);
+ }
+ }
+ else if((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0)
+ {
+ JPEG_DMA_PollResidualData(hjpeg);
+
+ return JPEG_PROCESS_DONE;
+ }
+
+ return JPEG_PROCESS_ONGOING;
+}
+
+/**
+ * @brief Poll residual output data when DMA process (encoding/decoding)
+ * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains
+ * the configuration information for JPEG module
+ * @retval None.
+ */
+static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg)
+{
+ uint32_t tmpContext, count = JPEG_FIFO_SIZE, *pDataOut;
pDataOut = (uint32_t *)(hjpeg->pJpegOutBuffPtr + hjpeg->JpegOutCount);
while((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0) && (count > 0))
@@ -3213,9 +3273,6 @@
{
HAL_JPEG_EncodeCpltCallback(hjpeg);
}
-
-
- return JPEG_PROCESS_DONE;
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_jpeg.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of JPEG HAL module.
******************************************************************************
* @attention
@@ -128,7 +128,7 @@
DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */
- uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
+ uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@@ -24,29 +24,29 @@
HAL_LPTIM_MspInit():
(##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
(##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
- (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
- (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
- (+) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
+ (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
+ (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
+ (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
(#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
configures mainly:
(##) The instance: LPTIM1.
(##) Clock: the counter clock.
- - Source : it can be either the ULPTIM input (IN1) or one of
+ (+++) Source: it can be either the ULPTIM input (IN1) or one of
the internal clock; (APB, LSE, LSI or MSI).
- - Prescaler: select the clock divider.
+ (+++) Prescaler: select the clock divider.
(##) UltraLowPowerClock : To be used only if the ULPTIM is selected
as counter clock source.
- - Polarity: polarity of the active edge for the counter unit
+ (+++) Polarity: polarity of the active edge for the counter unit
if the ULPTIM input is selected.
- - SampleTime: clock sampling time to configure the clock glitch
+ (+++) SampleTime: clock sampling time to configure the clock glitch
filter.
(##) Trigger: How the counter start.
- - Source: trigger can be software or one of the hardware triggers.
- - ActiveEdge : only for hardware trigger.
- - SampleTime : trigger sampling time to configure the trigger
+ (+++) Source: trigger can be software or one of the hardware triggers.
+ (+++) ActiveEdge: only for hardware trigger.
+ (+++) SampleTime: trigger sampling time to configure the trigger
glitch filter.
- (##) OutputPolarity : 2 opposite polarities are possibles.
+ (##) OutputPolarity: 2 opposite polarities are possibles.
(##) UpdateMode: specifies whether the update of the autoreload and
the compare values is done immediately or after the end of current
period.
@@ -87,7 +87,7 @@
HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
already started in interruption mode.
- (#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+ (#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
@endverbatim
******************************************************************************
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@@ -44,15 +44,15 @@
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
- (#) Variant functions with _NoReload post fix allows to set the LTDC configuration/settings without immediate reload.
+ (#) Variant functions with "_NoReload" post fix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
- then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload
+ then applying(reload) these settings in one shot by calling the function "HAL_LTDC_Reload"
- After calling the _NoReload functions to set different color/format/layer settings,
- the program can call the function HAL_LTDC_Reload To apply(Reload) these settings.
- Function HAL_LTDC_Reload can be called with the parameter ReloadType
+ After calling the "_NoReload" functions to set different color/format/layer settings,
+ the program can call the function "HAL_LTDC_Reload" To apply(Reload) these settings.
+ Function "HAL_LTDC_Reload" can be called with the parameter "ReloadType"
set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
- Function HAL_LTDC_Reload can be called with the parameter ReloadType
+ Function "HAL_LTDC_Reload" can be called with the parameter "ReloadType"
set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
@@ -87,15 +87,13 @@
{
/* Retrieve signal polarities from DSI */
- /* The following polarities are inverted:
- LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
- LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
- LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+ /* The following polarity is inverted:
+ LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
- hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
- hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
+ hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
+ hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of LTDC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,23 +2,21 @@
******************************************************************************
* @file stm32f7xx_hal_mdios.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief MDIOS HAL module driver.
- *
* This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
- *
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
- The MDIOS HAL driver can be used as follow:
+ The MDIOS HAL driver can be used as follows:
(#) Declare a MDIOS_HandleTypeDef handle structure.
@@ -53,9 +51,9 @@
(##) a DOUTn register read by the Master
(##) an error occur
- (@) A callback is executed for each genereted interrupt, so the driver provide the following
+ -@@- A callback is executed for each genereted interrupt, so the driver provides the following
HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
- (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
+ -@@- HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_mdios.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of MDIOS HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -202,7 +202,7 @@
hpcd->State= HAL_PCD_STATE_READY;
/* Activate LPM */
- if (hpcd->Init.lpm_enable == 1)
+ if (hpcd->Init.lpm_enable ==1)
{
HAL_PCDEx_ActivateLPM(hpcd);
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief QSPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the QuadSPI interface (QSPI).
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -256,7 +256,7 @@
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
@@ -491,6 +491,9 @@
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+#if defined (RCC_PLLCFGR_PLLR)
+ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@@ -508,11 +511,21 @@
}
/* Configure the main PLL clock source, multiplication and division factors. */
- WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
- RCC_OscInitStruct->PLL.PLLM | \
- (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
+#if defined (RCC_PLLCFGR_PLLR)
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ,
+ RCC_OscInitStruct->PLL.PLLR);
+#else
+ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ RCC_OscInitStruct->PLL.PLLM,
+ RCC_OscInitStruct->PLL.PLLN,
+ RCC_OscInitStruct->PLL.PLLP,
+ RCC_OscInitStruct->PLL.PLLQ);
+#endif
+
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -109,6 +109,8 @@
@endverbatim
* @{
*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \
+ defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
@@ -814,6 +816,7 @@
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
}
}
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
@@ -1003,323 +1006,6 @@
return frequency;
}
-#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
-/**
- * @brief Initializes the RCC Oscillators according to the specified parameters in the
- * RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
- * contains the configuration information for the RCC Oscillators.
- * @note The PLL is not disabled when used as system clock.
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
- * supported by this function. User should request a transition to LSE Off
- * first and then LSE On or LSE Bypass.
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this function. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
- /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- {
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- {
- return HAL_ERROR;
- }
- }
- else
- {
- /* Set the new HSE configuration ---------------------------------------*/
- __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
- /* Check the HSE State */
- if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSE is bypassed or disabled */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*----------------------------- HSI Configuration --------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
- assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
- || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- {
- /* When HSI is used as system clock it will not disabled */
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- {
- return HAL_ERROR;
- }
- /* Otherwise, just the calibration is allowed */
- else
- {
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- }
- else
- {
- /* Check the HSI State */
- if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- {
- /* Enable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
- __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- }
- else
- {
- /* Disable the Internal High Speed oscillator (HSI). */
- __HAL_RCC_HSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- }
- /*------------------------------ LSI Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
- /* Check the LSI State */
- if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- {
- /* Enable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the Internal Low Speed oscillator (LSI). */
- __HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*------------------------------ LSE Configuration -------------------------*/
- if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- {
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR1 |= PWR_CR1_DBP;
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR1 & PWR_CR1_DBP) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Set the new LSE configuration -----------------------------------------*/
- __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- /* Check the LSE State */
- if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- /*-------------------------------- PLL Configuration -----------------------*/
- /* Check the parameters */
- assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
- if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- {
- /* Check if the PLL is used as system clock or not */
- if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- {
- /* Check the parameters */
- assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
- assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
- assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
- assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
- assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
- assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- /* Configure the main PLL clock source, multiplication and division factors. */
- __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- RCC_OscInitStruct->PLL.PLLM,
- RCC_OscInitStruct->PLL.PLLN,
- RCC_OscInitStruct->PLL.PLLP,
- RCC_OscInitStruct->PLL.PLLQ,
- RCC_OscInitStruct->PLL.PLLR);
-
- /* Enable the main PLL. */
- __HAL_RCC_PLL_ENABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* Disable the main PLL. */
- __HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
- tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
- while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- return HAL_ERROR;
- }
- }
- return HAL_OK;
-}
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
-
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -105,9 +105,12 @@
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
}RCC_PLLI2SInitTypeDef;
/**
@@ -122,11 +125,14 @@
uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 15.
This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
-
+
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
This parameter must be a number between Min_Data = 2 and Max_Data = 7.
This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
-
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+
uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
This parameter will be used only when PLLSAI is disabled */
@@ -273,12 +279,14 @@
#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
-#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
+#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
+#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \
+ defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
* @{
*/
@@ -289,6 +297,7 @@
/**
* @}
*/
+#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
* @{
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -515,7 +515,7 @@
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */
- hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -241,7 +241,10 @@
hrtc->Instance->CR = (uint32_t)tmpreg;
hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
- hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
+ hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
+
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
@@ -589,6 +592,22 @@
(uint32_t)RTC_TAMPCR_TAMP2MF | (uint32_t)RTC_TAMPCR_TAMP3MF);
hrtc->Instance->TAMPCR |= tmpreg;
+
+ if(sTamper->Tamper == RTC_TAMPER_1)
+ {
+ /* Clear RTC Tamper 1 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+ }
+ else if(sTamper->Tamper == RTC_TAMPER_2)
+ {
+ /* Clear RTC Tamper 2 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+ }
+ else
+ {
+ /* Clear RTC Tamper 3 flag */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+ }
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
@@ -1085,6 +1104,9 @@
EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
+ /* Clear RTC Wake Up timer Flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Empty file; This file is no longer used to set synchronization and * to get SAI block frequency. Its content is now moved to common files * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,24 +2,25 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State and Errors functions
- *
- @verbatim
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- The SMARTCARD HAL driver can be used as follow:
-
- (#) Declare a SMARTCARD_HandleTypeDef handle structure.
- (#) Associate a USART to the SMARTCARD handle hsc.
+ The SMARTCARD HAL driver can be used as follows:
+
+ (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+ (#) Associate a USART to the SMARTCARD handle hsmartcard.
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(##) Enable the USARTx interface clock.
(##) SMARTCARD pins configuration:
@@ -43,18 +44,66 @@
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
- error enabling or disabling in the hsc Init structure.
-
+ error enabling or disabling in the hsmartcard handle Init structure.
+
(#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
- in the hsc AdvancedInit structure.
+ in the hsmartcard handle AdvancedInit structure.
+
+ (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
+ [..]
+ (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+ [..]
+ [..] Three operation modes are available within this driver :
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
- (#) Initialize the SMARTCARD associated USART registers by calling
- the HAL_SMARTCARD_Init() API.
-
- [..]
- (@) HAL_SMARTCARD_Init() API also configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) by
- calling the customized HAL_SMARTCARD_MspInit() API.
-
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+ (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+ *** SMARTCARD HAL driver macros list ***
+ ========================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
@endverbatim
******************************************************************************
* @attention
@@ -94,211 +143,241 @@
*/
/** @defgroup SMARTCARD SMARTCARD
- * @brief HAL USART SMARTCARD module driver
+ * @brief HAL SMARTCARD module driver
* @{
*/
+
#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-#define TEACK_REACK_TIMEOUT 1000U
+#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U
#define HAL_SMARTCARD_TXDMA_TIMEOUTVALUE 22000U
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8))
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL))
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP))
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT))
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
/**
* @}
*/
-/* Private macros -------------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
+
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
-===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
+ ==============================================================================
+ ##### Initialization and Configuration functions #####
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to initialize the USART
+ This subsection provides a set of functions allowing to initialize the USARTx
associated to the SmartCard.
- (+) These parameters can be configured:
- (++) Baud Rate
- (++) Parity: parity should be enabled,
- Frame Length is fixed to 8 bits plus parity.
- (++) Receiver/transmitter modes
- (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
- (++) Prescaler value
- (++) Guard bit time
- (++) NACK enabling or disabling on transmission error
+ (+) These parameters can be configured:
+ (++) Baud Rate
+ (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+ (++) Receiver/transmitter modes
+ (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+ (++) Prescaler value
+ (++) Guard bit time
+ (++) NACK enabling or disabling on transmission error
- (+) The following advanced features can be configured as well:
- (++) TX and/or RX pin level inversion
- (++) data logical level inversion
- (++) RX and TX pins swap
- (++) RX overrun detection disabling
- (++) DMA disabling on RX error
- (++) MSB first on communication line
- (++) Time out enabling (and if activated, timeout value)
- (++) Block length
- (++) Auto-retry counter
-
- [..]
- The HAL_SMARTCARD_Init() API follow respectively the USART (a)synchronous configuration procedures
- (details for the procedures are available in reference manual).
+ (+) The following advanced features can be configured as well:
+ (++) TX and/or RX pin level inversion
+ (++) data logical level inversion
+ (++) RX and TX pins swap
+ (++) RX overrun detection disabling
+ (++) DMA disabling on RX error
+ (++) MSB first on communication line
+ (++) Time out enabling (and if activated, timeout value)
+ (++) Block length
+ (++) Auto-retry counter
+ [..]
+ The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+ (details for the procedures are available in reference manual).
@endverbatim
The USART frame format is given in the following table:
- +---------------------------------------------------------------+
- | M1M0 bits | PCE bit | USART frame |
- |-----------------------|---------------------------------------|
- | 01 | 1 | | SB | 8 bit data | PB | STB | |
- +---------------------------------------------------------------+
+ Table 1. USART frame format.
+ +---------------------------------------------------------------+
+ | M1M0 bits | PCE bit | USART frame |
+ |-----------------------|---------------------------------------|
+ | 01 | 1 | | SB | 8 bit data | PB | STB | |
+ +---------------------------------------------------------------+
+
* @{
*/
/**
- * @brief Initializes the SMARTCARD mode according to the specified
- * parameters in the SMARTCARD_InitTypeDef and create the associated handle .
- * @param hsc: SMARTCARD handle
+ * @brief Initialize the SMARTCARD mode according to the specified
+ * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsc == NULL)
+ if(hsmartcard == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-
- if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
- {
+ /* Check the USART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
- hsc->Lock = HAL_UNLOCKED;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_SMARTCARD_MspInit(hsc);
+ hsmartcard->Lock = HAL_UNLOCKED;
+
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_SMARTCARD_MspInit(hsmartcard);
}
-
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+ /* Disable the Peripheral to set smartcard mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable the Peripheral */
- __HAL_SMARTCARD_DISABLE(hsc);
+ /* In SmartCard mode, the following bits must be kept cleared:
+ - LINEN in the USART_CR2 register,
+ - HDSEL and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+ CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+ /* set the USART in SMARTCARD mode */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
/* Set the SMARTCARD Communication parameters */
- SMARTCARD_SetConfig(hsc);
+ if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Set the SMARTCARD transmission completion indication */
+ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
- if(hsc->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+ if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
{
- SMARTCARD_AdvFeatureConfig(hsc);
+ SMARTCARD_AdvFeatureConfig(hsmartcard);
}
- /* In SmartCard mode, the following bits must be kept cleared:
- - LINEN in the USART_CR2 register,
- - HDSEL and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* set the USART in SMARTCARD mode */
- SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);
-
- /* Enable the Peripheral */
- __HAL_SMARTCARD_ENABLE(hsc);
-
- /* TEACK and/or REACK to check before moving hsc->State to Ready */
- return (SMARTCARD_CheckIdleState(hsc));
+ /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+ return (SMARTCARD_CheckIdleState(hsmartcard));
}
/**
- * @brief DeInitializes the SMARTCARD peripheral
- * @param hsc: SMARTCARD handle
+ * @brief DeInitialize the SMARTCARD peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsc == NULL)
+ if(hsmartcard == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
+ /* Check the USART/UART associated to the SMARTCARD handle */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+ /* Disable the Peripheral */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ WRITE_REG(hsmartcard->Instance->CR1, 0x0);
+ WRITE_REG(hsmartcard->Instance->CR2, 0x0);
+ WRITE_REG(hsmartcard->Instance->CR3, 0x0);
+ WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
+ WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
/* DeInit the low level hardware */
- HAL_SMARTCARD_MspDeInit(hsc);
+ HAL_SMARTCARD_MspDeInit(hsmartcard);
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_RESET;
- hsc->RxState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hsc);
+ /* Process Unlock */
+ __HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
/**
- * @brief SMARTCARD MSP Init
- * @param hsc: SMARTCARD handle
+ * @brief Initialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit could be implemented in the user file
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspInit can be implemented in the user file
*/
}
/**
- * @brief SMARTCARD MSP DeInit
- * @param hsc: SMARTCARD handle
+ * @brief DeInitialize the SMARTCARD MSP.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit could be implemented in the user file
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_MspDeInit can be implemented in the user file
*/
}
@@ -306,100 +385,156 @@
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
- * @brief SMARTCARD Transmit and Receive functions
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
*
-@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
- (#) There are two modes of transfer:
- (+) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (+) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback()user callback will be executed when a communication error is detected
+ [..]
+ Smartcard is a single wire half duplex communication protocol.
+ The Smartcard interface is designed to support asynchronous protocol Smartcards as
+ defined in the ISO 7816-3 standard. The USART should be configured as:
+ (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+ [..]
+ (+) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non-Blocking mode: The communication is performed using Interrupts
+ or DMA, the relevant API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+ error is detected.
+
+ (+) Blocking mode APIs are :
+ (++) HAL_SMARTCARD_Transmit()
+ (++) HAL_SMARTCARD_Receive()
+
+ (+) Non Blocking mode APIs with Interrupt are :
+ (++) HAL_SMARTCARD_Transmit_IT()
+ (++) HAL_SMARTCARD_Receive_IT()
+ (++) HAL_SMARTCARD_IRQHandler()
- (#) Blocking mode API's are :
- (+) HAL_SMARTCARD_Transmit()
- (+) HAL_SMARTCARD_Receive()
-
- (#) Non-Blocking mode API's with Interrupt are :
- (+) HAL_SMARTCARD_Transmit_IT()
- (+) HAL_SMARTCARD_Receive_IT()
- (+) HAL_SMARTCARD_IRQHandler()
- (+) SMARTCARD_Transmit_IT()
- (+) SMARTCARD_Receive_IT()
+ (+) Non Blocking mode functions with DMA are :
+ (++) HAL_SMARTCARD_Transmit_DMA()
+ (++) HAL_SMARTCARD_Receive_DMA()
+
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (++) HAL_SMARTCARD_TxCpltCallback()
+ (++) HAL_SMARTCARD_RxCpltCallback()
+ (++) HAL_SMARTCARD_ErrorCallback()
+
+ (#) Non-Blocking mode transfers could be aborted using Abort API's :
+ (+) HAL_SMARTCARD_Abort()
+ (+) HAL_SMARTCARD_AbortTransmit()
+ (+) HAL_SMARTCARD_AbortReceive()
+ (+) HAL_SMARTCARD_Abort_IT()
+ (+) HAL_SMARTCARD_AbortTransmit_IT()
+ (+) HAL_SMARTCARD_AbortReceive_IT()
- (#) No-Blocking mode functions with DMA are :
- (+) HAL_SMARTCARD_Transmit_DMA()
- (+) HAL_SMARTCARD_Receive_DMA()
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+ (+) HAL_SMARTCARD_AbortCpltCallback()
+ (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (+) HAL_SMARTCARD_TxCpltCallback()
- (+) HAL_SMARTCARD_RxCpltCallback()
- (+) HAL_SMARTCARD_ErrorCallback()
-
+ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+ Errors are handled as follows :
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @brief Send an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ uint32_t tickstart = 0;
+
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hsc);
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
- while(hsc->TxXferCount > 0U)
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ while(hsmartcard->TxXferCount > 0)
{
- hsc->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- {
+ hsmartcard->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
- hsc->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
}
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- {
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ {
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ }
- /* At end of Tx process, restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
/* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_UNLOCK(hsmartcard);
return HAL_OK;
}
@@ -410,51 +545,111 @@
}
/**
- * @brief Receive an amount of data in blocking mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
+ * @brief Receive an amount of data in blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
-
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ uint32_t tickstart = 0;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hsc);
-
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- hsc->RxXferSize = Size;
- hsc->RxXferCount = Size;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
/* Check the remain data to be received */
- while(hsc->RxXferCount > 0U)
+ while(hsmartcard->RxXferCount > 0)
{
- hsc->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ hsmartcard->RxXferCount--;
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- *pData++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0x00FFU);
+ *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
}
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Send an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -465,40 +660,41 @@
}
/**
- * @brief Send an amount of data in interrupt mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Receive an amount of data in interrupt mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
- /* Check that a Tx process is not already ongoing */
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hsc);
+ __HAL_LOCK(hsmartcard);
- hsc->pTxBuffPtr = pData;
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
-
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
+ hsmartcard->RxXferCount = Size;
+
/* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
@@ -509,43 +705,68 @@
}
/**
- * @brief Receive an amount of data in interrupt mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @brief Send an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
- /* Check that a Rx process is not already ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ /* Check that a Tx process is not already ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hsc);
+ __HAL_LOCK(hsmartcard);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
+ hsmartcard->TxXferCount = Size;
+
+ /* Disable the Peripheral first to update mode for TX master */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- hsc->pRxBuffPtr = pData;
- hsc->RxXferSize = Size;
- hsc->RxXferCount = Size;
+ /* Disable Rx, enable Tx */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+ /* Set the SMARTCARD DMA transfer complete callback */
+ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
+ /* Set the SMARTCARD error callback */
+ hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+ /* Set the DMA abort callback */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
/* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+ __HAL_UNLOCK(hsmartcard);
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the SMARTCARD Data Register not empty Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
@@ -556,56 +777,58 @@
}
/**
- * @brief Send an amount of data in DMA mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @brief Receive an amount of data in DMA mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
+ * the received data contain the parity bit (MSB position).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp;
-
- /* Check that a Tx process is not already ongoing */
- if(hsc->gState == HAL_SMARTCARD_STATE_READY)
+ /* Check that a Rx process is not already ongoing */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(hsc);
+ __HAL_LOCK(hsmartcard);
- hsc->pTxBuffPtr = pData;
- hsc->TxXferSize = Size;
- hsc->TxXferCount = Size;
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+ hsmartcard->pRxBuffPtr = pData;
+ hsmartcard->RxXferSize = Size;
/* Set the SMARTCARD DMA transfer complete callback */
- hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+ hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+ /* Set the SMARTCARD DMA error callback */
+ hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
- /* Set the SMARTCARD error callback */
- hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
/* Set the DMA abort callback */
- hsc->hdmatx->XferAbortCallback = NULL;
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
- /* Enable the SMARTCARD transmit DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size);
-
- /* Clear the TC flag in the SR register by writing 0 to it */
- __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_FLAG_TC);
-
/* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
@@ -616,245 +839,759 @@
}
/**
- * @brief Receive an amount of data in DMA mode
- * @param hsc: SMARTCARD handle
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @note The SMARTCARD-associated USART parity is enabled (PCE = 1),
- * the received data contain the parity bit (MSB position)
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t *tmp;
-
- /* Check that a Rx process is not already ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmatx != NULL)
{
- return HAL_ERROR;
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmatx);
}
+ }
+
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
- /* Process Locked */
- __HAL_LOCK(hsc);
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
- hsc->pRxBuffPtr = pData;
- hsc->RxXferSize = Size;
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsmartcard->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
-
- /* Set the SMARTCARD DMA transfer complete callback */
- hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx and Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t abortcplt = 1;
+
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Set the SMARTCARD DMA error callback */
- hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
- /* Set the DMA abort callback */
- hsc->hdmatx->XferAbortCallback = NULL;
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
- /* Enable the DMA Stream */
- tmp = (uint32_t*)&pData;
- HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->RDR, *(uint32_t*)tmp, Size);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1;
+ }
+ else
+ {
+ abortcplt = 0;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if (abortcplt == 1)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Tx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
- return HAL_OK;
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0;
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+ }
}
else
{
- return HAL_BUSY;
+ /* Reset Tx transfer counter */
+ hsmartcard->TxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
}
+
+ return HAL_OK;
}
-
+
/**
- * @brief SMARTCARD interrupt requests handling.
- * @param hsc: SMARTCARD handle
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SMARTCARD Interrupts (Rx)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+
+ /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsmartcard->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t isrflags = READ_REG(hsc->Instance->ISR);
- uint32_t cr1its = READ_REG(hsc->Instance->CR1);
- uint32_t cr3its = READ_REG(hsc->Instance->CR3);
- uint32_t dmarequest = 0x00U;
- uint32_t errorflags = 0x00U;
+ uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
+ uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
+ uint32_t cr3its;
+ uint32_t errorflags;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if(errorflags == RESET)
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == RESET)
{
- /* SMARTCARD in mode Receiver -------------------------------------------------*/
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- SMARTCARD_Receive_IT(hsc);
+ SMARTCARD_Receive_IT(hsmartcard);
+ /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
return;
}
- }
+ }
/* If some errors occur */
- if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+ cr3its = READ_REG(hsmartcard->Instance->CR3);
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
{
- /* SMARTCARD parity error interrupt occurred ---------------------------*/
- if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- }
+ /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+ if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
- /* SMARTCARD frame error interrupt occurred ----------------------------*/
- if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
}
- /* SMARTCARD noise error interrupt occurred ----------------------------*/
- if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
}
- /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
- if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_ORE) != RESET) &&
+ (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ {
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
}
- /* Call the Error call Back in case of Errors */
- if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+
+ /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+ if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
{
- /* SMARTCARD in mode Receiver -----------------------------------------------*/
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be --------------------------*/
+ if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ---------------------------------------------------*/
if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- SMARTCARD_Receive_IT(hsc);
+ SMARTCARD_Receive_IT(hsmartcard);
}
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
- if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
- {
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+ || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+ {
/* Blocking error : transfer is aborted
- Set the SMARTCARD state ready to be able to start again the process,
- Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
- SMARTCARD_EndRxTransfer(hsc);
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsmartcard);
+
/* Disable the SMARTCARD DMA Rx request if enabled */
- if (HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
{
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel */
- if(hsc->hdmarx != NULL)
+ if(hsmartcard->hdmarx != NULL)
{
/* Set the SMARTCARD DMA Abort callback :
- will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
- hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
- if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
- /* Call Directly XferAbortCallback function in case of error */
- hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+ /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+ hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
}
}
else
{
/* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ }
+ }
+ /* other error type to be considered as blocking :
+ - Frame error in Transmission
+ */
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+ SMARTCARD_EndTxTransfer(hsmartcard);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+ hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
}
}
else
{
/* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
}
}
else
{
- /* Call user error callback */
- HAL_SMARTCARD_ErrorCallback(hsc);
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
}
}
return;
+
} /* End if some error occurs */
-
- /* SMARTCARD in mode Transmitter -------------------------------------------*/
- if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+
+ /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+ if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
{
- SMARTCARD_Transmit_IT(hsc);
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ __HAL_UNLOCK(hsmartcard);
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+ /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+ * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
return;
}
-
- /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
- {
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+ /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ {
+ SMARTCARD_Transmit_IT(hsmartcard);
+ return;
+ }
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_TxCpltCallback(hsc);
-
+ /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+ if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
return;
}
}
/**
- * @brief Tx Transfer completed callbacks
- * @param hsc: SMARTCARD handle
+ * @brief Tx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
- */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+ */
}
/**
- * @brief Rx Transfer completed callbacks
- * @param hsc: SMARTCARD handle
+ * @brief Rx Transfer completed callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
*/
}
/**
- * @brief SMARTCARD error callbacks
- * @param hsc: SMARTCARD handle
+ * @brief SMARTCARD error callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hsc);
-
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Receive Complete callback.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsmartcard);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
@@ -862,47 +1599,50 @@
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions
- * @brief SMARTCARD State functions
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
*
-@verbatim
- ===============================================================================
- ##### Peripheral State and Errors functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the SMARTCARD.
- (+) HAL_SMARTCARD_GetState() API is helpful to check in run-time the state of the SMARTCARD peripheral
- (+) SMARTCARD_SetConfig() API configures the SMARTCARD peripheral
- (+) SMARTCARD_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Errors functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to return the State of SmartCard
+ handle and also return Peripheral Errors occurred during communication process
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+ of the SMARTCARD peripheral.
+ (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+ communication.
@endverbatim
* @{
*/
-
/**
- * @brief return the SMARTCARD state
- * @param hsc: SMARTCARD handle
- * @retval HAL state
+ * @brief Return the SMARTCARD handle state.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle state
*/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hsc->gState;
- temp2 = hsc->RxState;
-
+ /* Return SMARTCARD handle state */
+ uint32_t temp1= 0x00, temp2 = 0x00;
+ temp1 = hsmartcard->gState;
+ temp2 = hsmartcard->RxState;
+
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
/**
- * @brief Return the SMARTCARD error code
- * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD.
- * @retval SMARTCARD Error Code
- */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
+ * @brief Return the SMARTCARD handle error code.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
{
- return hsc->ErrorCode;
+ return hsmartcard->ErrorCode;
}
/**
@@ -910,73 +1650,542 @@
*/
/**
- * @brief Send an amount of data in non blocking mode
- * @param hsc: SMARTCARD handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ uint32_t tmpreg = 0x00000000;
+ SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+ HAL_StatusTypeDef ret = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+ assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+ assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+ assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+ assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+ assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+ assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+ assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+ assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+ assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+ assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+ assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+ assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+ * Oversampling is forced to 16 (OVER8 = 0).
+ * Configure the Parity and Mode:
+ * set PS bit according to hsmartcard->Init.Parity value
+ * set TE and RE bits according to hsmartcard->Init.Mode value */
+ tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+ tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = hsmartcard->Init.StopBits;
+ /* Synchronous mode is activated by default */
+ tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+ tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
+ /* Configure
+ * - one-bit sampling method versus three samples' majority rule
+ * according to hsmartcard->Init.OneBitSampling
+ * - NACK transmission in case of parity error according
+ * to hsmartcard->Init.NACKEnable
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+ MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+ /*-------------------------- USART GTPR Configuration ----------------------*/
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+ /*-------------------------- USART RTOR Configuration ----------------------*/
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+ {
+ assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ }
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+ /*-------------------------- USART BRR Configuration -----------------------*/
+ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ switch (clocksource)
+ {
+ case SMARTCARD_CLOCKSOURCE_PCLK1:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_PCLK2:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_HSI:
+ hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_SYSCLK:
+ hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_LSE:
+ hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+ break;
+ case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check whether the set of advanced features to configure is properly set */
+ assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+ /* if required, configure TX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+ }
+
+ /* if required, configure RX pin active level inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+ }
+
+ /* if required, configure data inversion */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+ }
+
+ /* if required, configure RX/TX pins swap */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+ }
+
+ /* if required, configure RX overrun detection disabling */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ {
+ assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+ }
+
+ /* if required, configure DMA disabling on reception error */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+ }
+
+ /* if required, configure MSB first on communication line */
+ if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+ {
+ assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+ MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+ }
+
+}
+
+/**
+ * @brief Check the SMARTCARD Idle State.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
{
- if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ uint32_t tickstart = 0;
+
+ /* Initialize the SMARTCARD ErrorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Check if the Transmitter is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
- if(hsc->TxXferCount == 0)
+ /* Wait until TEACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Tx process is ended, restore hsmartcard->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
}
-
- HAL_SMARTCARD_TxCpltCallback(hsc);
-
- return HAL_OK;
}
- else
- {
- hsc->Instance->TDR = (*hsc->pTxBuffPtr++ & (uint8_t)0xFFU);
- hsc->TxXferCount--;
-
- return HAL_OK;
+ /* Check if the Receiver is enabled */
+ if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
}
+
+ /* Initialize the SMARTCARD states */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non blocking mode
- * @param hsc: SMARTCARD handle.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Receive_IT()
+ * @brief Handle SMARTCARD Communication Timeout.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @param Flag Specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- /* Check that a Rx process is ongoing */
- if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ /* Wait until flag is set */
+ while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
{
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->RDR & (uint8_t)0xFFU);
-
- if(--hsc->RxXferCount == 0)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
-
- /* Disable the SMARTCARD Parity Error Interrupt */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
-
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsc);
-
+ if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+ {
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+
+/**
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Tx process, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+ * @brief DMA SMARTCARD transmit process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->TxXferCount = 0;
+
+ /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+ * @brief DMA SMARTCARD receive process complete callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0;
+
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+ {
+ hsmartcard->TxXferCount = 0;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+ &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+ {
+ hsmartcard->RxXferCount = 0;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
+
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ hsmartcard->RxXferCount = 0;
+ hsmartcard->TxXferCount = 0;
+
+ HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmarx != NULL)
+ {
+ if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsmartcard->hdmatx != NULL)
+ {
+ if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsmartcard->TxXferCount = 0;
+ hsmartcard->RxXferCount = 0;
+
+ /* Reset errorCode */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+ hsmartcard->TxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+ /* Restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+ hsmartcard->RxXferCount = 0;
+
+ /* Clear the Error flags in the ICR register */
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+ /* Restore hsmartcard->RxState to Ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+ * @brief Send an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Check that a Tx process is ongoing */
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ {
+ if(hsmartcard->TxXferCount == 0)
+ {
+ /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
return HAL_OK;
}
-
- return HAL_OK;
+ else
+ {
+ hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+ hsmartcard->TxXferCount--;
+
+ return HAL_OK;
+ }
}
else
{
@@ -985,362 +2194,86 @@
}
/**
- * @brief Configure the SMARTCARD associated USART peripheral
- * @param hsc: SMARTCARD handle
- * @retval None
- */
-static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
-{
- uint32_t tmpreg = 0x00000000U;
- uint32_t clocksource = 0x00000000U;
-
- /* Check the parameters */
- assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
- assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
- assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
- assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
- assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
- assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
- assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
- assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
- assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
- assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling));
- assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState));
- assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable));
- assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount));
-
- /*-------------------------- USART CR1 Configuration -----------------------*/
- /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
- * Oversampling is forced to 16 (OVER8 = 0).
- * Configure the Parity and Mode:
- * set PS bit according to hsc->Init.Parity value
- * set TE and RE bits according to hsc->Init.Mode value */
- tmpreg = (uint32_t) hsc->Init.Parity | hsc->Init.Mode;
- /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor
- the bidirectional line to detect a NACK signal in case of parity error.
- Therefore, the receiver block must be enabled as well (RE bit must be set). */
- if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE))
- {
- tmpreg |= USART_CR1_RE;
- }
- tmpreg |= (uint32_t) hsc->Init.WordLength;
- MODIFY_REG(hsc->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
- /*-------------------------- USART CR2 Configuration -----------------------*/
- /* Stop bits are forced to 1.5 (STOP = 11) */
- tmpreg = hsc->Init.StopBits;
- /* Synchronous mode is activated by default */
- tmpreg |= (uint32_t) USART_CR2_CLKEN | hsc->Init.CLKPolarity;
- tmpreg |= (uint32_t) hsc->Init.CLKPhase | hsc->Init.CLKLastBit;
- tmpreg |= (uint32_t) hsc->Init.TimeOutEnable;
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_FIELDS, tmpreg);
-
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* Configure
- * - one-bit sampling method versus three samples' majority rule
- * according to hsc->Init.OneBitSampling
- * - NACK transmission in case of parity error according
- * to hsc->Init.NACKEnable
- * - autoretry counter according to hsc->Init.AutoRetryCount */
- tmpreg = (uint32_t) hsc->Init.OneBitSampling | hsc->Init.NACKState;
- tmpreg |= (uint32_t) (hsc->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
- MODIFY_REG(hsc->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
-
- /*-------------------------- USART GTPR Configuration ----------------------*/
- tmpreg = (uint32_t) (hsc->Init.Prescaler | (hsc->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsc->Instance->GTPR, (uint32_t)(USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
-
- /*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
- if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
- {
- assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
- tmpreg |= (uint32_t) hsc->Init.TimeOutValue;
- }
- MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
-
- /*-------------------------- USART BRR Configuration -----------------------*/
- SMARTCARD_GETCLOCKSOURCE(hsc, clocksource);
- switch (clocksource)
- {
- case SMARTCARD_CLOCKSOURCE_PCLK1:
- hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_PCLK2:
- hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_HSI:
- hsc->Instance->BRR = (uint16_t)((HSI_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_SYSCLK:
- hsc->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);
- break;
- case SMARTCARD_CLOCKSOURCE_LSE:
- hsc->Instance->BRR = (uint16_t)((LSE_VALUE + (hsc->Init.BaudRate/2))/ hsc->Init.BaudRate);
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Check the SMARTCARD Idle State
- * @param hsc: SMARTCARD handle
+ * @brief Wrap up transmission in non-blocking mode.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsc)
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tickstart = 0U;
-
- /* Initialize the SMARTCARD ErrorCode */
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
- /* Init tickstart for timeout managment*/
- tickstart = HAL_GetTick();
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
- /* Check if the Transmitter is enabled */
- if((hsc->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Check if a receive process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- /* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
- /* Check if the Receiver is enabled */
- if((hsc->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+
+ /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+ if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
{
- /* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+ /* Disable the Peripheral first to update modes */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ /* Enable the Peripheral */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
}
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- /* Initialize the SMARTCARD state*/
- hsc->gState= HAL_SMARTCARD_STATE_READY;
- hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
return HAL_OK;
}
/**
- * @brief Configure the SMARTCARD associated USART peripheral advanced features
- * @param hsc: SMARTCARD handle
- * @retval None
- */
-static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Check whether the set of advanced features to configure is properly set */
- assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsc->AdvancedInit.AdvFeatureInit));
-
- /* if required, configure TX pin active level inversion */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsc->AdvancedInit.TxPinLevelInvert));
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_TXINV, hsc->AdvancedInit.TxPinLevelInvert);
- }
-
- /* if required, configure RX pin active level inversion */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsc->AdvancedInit.RxPinLevelInvert));
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_RXINV, hsc->AdvancedInit.RxPinLevelInvert);
- }
-
- /* if required, configure data inversion */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsc->AdvancedInit.DataInvert));
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_DATAINV, hsc->AdvancedInit.DataInvert);
- }
-
- /* if required, configure RX/TX pins swap */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsc->AdvancedInit.Swap));
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_SWAP, hsc->AdvancedInit.Swap);
- }
-
- /* if required, configure RX overrun detection disabling */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- {
- assert_param(IS_SMARTCARD_OVERRUN(hsc->AdvancedInit.OverrunDisable));
- MODIFY_REG(hsc->Instance->CR3, USART_CR3_OVRDIS, hsc->AdvancedInit.OverrunDisable);
- }
-
- /* if required, configure DMA disabling on reception error */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsc->AdvancedInit.DMADisableonRxError));
- MODIFY_REG(hsc->Instance->CR3, USART_CR3_DDRE, hsc->AdvancedInit.DMADisableonRxError);
- }
-
- /* if required, configure MSB first on communication line */
- if(HAL_IS_BIT_SET(hsc->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
- {
- assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsc->AdvancedInit.MSBFirst));
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_MSBFIRST, hsc->AdvancedInit.MSBFirst);
- }
-}
-
-/**
- * @brief This function handles SMARTCARD Communication Timeout.
- * @param hsc SMARTCARD handle
- * @param Flag specifies the SMARTCARD flag to check.
- * @param Status The new Flag status (SET or RESET).
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
+ * @brief Receive an amount of data in non-blocking mode.
+ * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
+ /* Check that a Rx process is ongoing */
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+ if(--hsmartcard->RxXferCount == 0)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+ /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+ if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
- CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- hsc->gState= HAL_SMARTCARD_STATE_READY;
- hsc->RxState= HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- return HAL_TIMEOUT;
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
- }
- }
- return HAL_OK;
-}
-
-/*
- * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsc: SMARTCARD handle.
- * @retval None
- */
-static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable TXEIE and TCIE interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
- /* At end of Tx process, restore hsc->gState to Ready */
- hsc->gState = HAL_SMARTCARD_STATE_READY;
-}
-
-
-/**
- * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
- * @param hsc: SMARTCARD handle.
- * @retval None
- */
-static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
-{
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-}
-/**
- * @brief DMA SMARTCARD transmit process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->TxXferCount = 0;
-
- /* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
-}
+ /* Disable the SMARTCARD Parity Error Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
-/**
- * @brief DMA SMARTCARD receive process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0;
-
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
-
- /* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
- /* At end of Rx process, restore hsc->RxState to Ready */
- hsc->RxState = HAL_SMARTCARD_STATE_READY;
-
- HAL_SMARTCARD_RxCpltCallback(hsc);
-}
+ HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+ return HAL_OK;
+ }
-/**
- * @brief DMA SMARTCARD communication error callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0U;
- hsc->TxXferCount = 0U;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
-
- /* Stop SMARTCARD DMA Tx request if ongoing */
- if ( (hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) )
- {
- SMARTCARD_EndTxTransfer(hsc);
+ return HAL_OK;
}
-
- /* Stop SMARTCARD DMA Rx request if ongoing */
- if ( (hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) )
+ else
{
- SMARTCARD_EndRxTransfer(hsc);
- }
-
- HAL_SMARTCARD_ErrorCallback(hsc);
-}
+ /* Clear RXNE interrupt flag */
+ __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-/**
- * @brief DMA SMARTCARD communication abort callback, when call by HAL services on Error
- * (To be called at end of DMA Abort procedure following error occurrence).
- * @param hdma: DMA handle.
- * @retval None
- */
-static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
- SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0U;
- hsc->TxXferCount = 0U;
-
- HAL_SMARTCARD_ErrorCallback(hsc);
+ return HAL_BUSY;
+ }
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -54,25 +54,25 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
*/
-/**
+/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hsc->Init.BaudRate))) */
-
+ Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
- uint32_t StopBits; /*!< Specifies the number of stop bits @ref SMARTCARD_Stop_Bits.
- Only 1.5 stop bits are authorized in SmartCard mode. */
+ uint32_t StopBits; /*!< Specifies the number of stop bits.
+ This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@@ -101,9 +101,9 @@
uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time */
- uint32_t NACKState; /*!< Specifies whether the SmartCard NACK transmission is enabled
- in case of parity error.
- This parameter can be a value of @ref SMARTCARD_NACK_State */
+ uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
+ in case of parity error.
+ This parameter can be a value of @ref SMARTCARD_NACK_State */
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
@@ -122,7 +122,43 @@
}SMARTCARD_InitTypeDef;
-/**
+/**
+ * @brief SMARTCARD advanced features initalization structure definition
+ */
+typedef struct
+{
+ uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
+ advanced features may be initialized at the same time. This parameter
+ can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Tx_Inv */
+
+ uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
+ This parameter can be a value of @ref SMARTCARD_Rx_Inv */
+
+ uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
+ vs negative/inverted logic).
+ This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+ uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
+ This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+ uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
+ This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+ uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
+ This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+ uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
+ This parameter can be a value of @ref SMARTCARD_MSB_First */
+
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
* @brief HAL SMARTCARD State structures definition
* @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
* - gState contains SMARTCARD state information related to global Handle management
@@ -161,60 +197,27 @@
* b0 (not used)
* x : Should be set to 0.
*/
-typedef struct
-{
- uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
- advanced features may be initialized at the same time. This parameter
- can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
-
- uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Tx_Inv */
-
- uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref SMARTCARD_Rx_Inv */
-
- uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
- vs negative/inverted logic).
- This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
- uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
- This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
- uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
- This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
- uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
- This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
- uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
- This parameter can be a value of @ref SMARTCARD_MSB_First */
-}SMARTCARD_AdvFeatureInitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
typedef enum
{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
+ HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_SMARTCARD_StateTypeDef;
-
/**
* @brief SMARTCARD clock sources definition
*/
@@ -224,44 +227,45 @@
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10 /*!< undefined clock source */
}SMARTCARD_ClockSourceTypeDef;
-/**
+/**
* @brief SMARTCARD handle Structure definition
*/
typedef struct
{
- USART_TypeDef *Instance; /* USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- SMARTCARD_InitTypeDef Init; /* SmartCard communication parameters */
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /* SmartCard advanced features initialization parameters */
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
- uint8_t *pTxBuffPtr; /* Pointer to SmartCard Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
- uint16_t TxXferSize; /* SmartCard Tx Transfer size */
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- uint16_t TxXferCount; /* SmartCard Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to SmartCard Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
- uint16_t RxXferSize; /* SmartCard Rx Transfer size */
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- uint16_t RxXferCount; /* SmartCard Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
- DMA_HandleTypeDef *hdmatx; /* SmartCard Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* SmartCard Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /* SmartCard Error code */
@@ -619,6 +623,56 @@
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+/** @brief Clear the specified SMARTCARD pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be any combination of the following values:
+ * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
+ * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
+ * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ @if STM32L443xx
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
+ @endif
+ * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief Clear the SMARTCARD PE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief Clear the SMARTCARD FE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief Clear the SMARTCARD NE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief Clear the SMARTCARD ORE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief Clear the SMARTCARD IDLE pending flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @retval None
+ */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
/** @brief Enables the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
@@ -773,16 +827,28 @@
* @{
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -56,6 +56,83 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+ * @{
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5 bits)
+ * - XX : Interrupt source register (2 bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5 bits)
+ * @{
+ */
+
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
/** @brief Reports the SMARTCARD clock source.
@@ -147,6 +224,62 @@
} \
} while(0)
+/** @brief Set the Transmission Completion flag
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+ * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+ * to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+ * @retval None
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
+ { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } \
+ else \
+ { \
+ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+ } \
+ } while(0)
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } while(0)
+#endif
+
+/** @brief Return the transmission completion flag.
+ * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+ * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+ * reported.
+ * @retval Transmission completion flag
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
+#endif
+
+/**
+ * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+ * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
+ * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
+ ((__TXCOMPLETE__) == SMARTCARD_TC))
+#else
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
+#endif
+
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions ****************************/
/* IO operation functions *****************************************************/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -133,6 +133,7 @@ */ #ifdef HAL_SPDIFRX_MODULE_ENABLED +#if defined (SPDIFRX) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -1244,7 +1245,7 @@ /** * @} */ - +#endif /* SPDIFRX */ #endif /* HAL_SPDIFRX_MODULE_ENABLED */ /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spdifrx.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of SPDIFRX HAL module.
******************************************************************************
* @attention
@@ -43,6 +43,8 @@
extern "C" {
#endif
+#if defined (SPDIFRX)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@@ -545,6 +547,8 @@
/**
* @}
*/
+
+#endif /* SPDIFRX */
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_spi.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -31,12 +31,12 @@
(+++) Configure the SPIx interrupt priority
(+++) Enable the NVIC SPI IRQ handle
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
+ (+++) Configure the DMA Tx or Rx Stream/Channel
(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -52,6 +52,66 @@
(#) The CRC feature is not managed when the DMA circular mode is enabled
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +----------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==============================================================================================|
+ | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
+ | R |----------------|----------|----------|-----------|----------|-----------|----------|
+ | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
+ |=========|================|==========|==========|===========|==========|===========|==========|
+ | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
+ | |----------------|----------|----------|-----------|----------|-----------|----------|
+ | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
+ | X |----------------|----------|----------|-----------|----------|-----------|----------|
+ | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
+ +----------------------------------------------------------------------------------------------+
+ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ @note
+ (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
@endverbatim
******************************************************************************
@@ -102,7 +162,7 @@
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
-#define SPI_DEFAULT_TIMEOUT 50
+#define SPI_DEFAULT_TIMEOUT 100U
/**
* @}
*/
@@ -121,33 +181,38 @@
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
#if (USE_SPI_CRC != 0U)
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
-#endif
-static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
@@ -199,7 +264,7 @@
uint32_t frxth;
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
@@ -209,36 +274,28 @@
assert_param(IS_SPI_MODE(hspi->Init.Mode));
assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
- assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
- assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+ if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
+ {
+ assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
+ assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+ }
#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
- /* Align the CRC Length on the data size */
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
- {
- /* CRC Length aligned on the data size : value set by default */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
- }
- else
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
- }
- }
-#endif
-
- if(hspi->State == HAL_SPI_STATE_RESET)
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
+
+ if (hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
@@ -253,7 +310,7 @@
__HAL_SPI_DISABLE(hspi);
/* Align by default the rs fifo threshold on the data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
}
@@ -263,43 +320,66 @@
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
- if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
+ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
- /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Length aligned on the data size : value set by default */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
- Communication speed, First bit, CRC calculation state, CRC Length */
- hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
-
- if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ Communication speed, First bit, CRC calculation state */
+ WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
+ hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
+ hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
+#if (USE_SPI_CRC != 0U)
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- hspi->Instance->CR1|= SPI_CR1_CRCL;
+ hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
-
- /* Configure : NSS management */
- /* Configure : Rx Fifo Threshold */
- hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
- hspi->Init.DataSize ) | frxth;
+#endif /* USE_SPI_CRC */
+
+ /* Configure : NSS management, TI Mode and Rx Fifo Threshold */
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode |
+ hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
#if (USE_SPI_CRC != 0U)
- /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
-#endif
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State= HAL_SPI_STATE_READY;
+ hspi->State = HAL_SPI_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitialize the SPI peripheral.
+ * @brief De-Initialize the SPI peripheral.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
@@ -307,12 +387,12 @@
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
{
/* Check the SPI handle allocation */
- if(hspi == NULL)
+ if (hspi == NULL)
{
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check SPI Instance parameter */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
hspi->State = HAL_SPI_STATE_BUSY;
@@ -326,13 +406,14 @@
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
+ /* Release Lock */
__HAL_UNLOCK(hspi);
return HAL_OK;
}
/**
- * @brief SPI MSP Init
+ * @brief Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -343,12 +424,12 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_MspInit should be implemented in the user file
- */
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
}
/**
- * @brief SPI MSP DeInit
+ * @brief De-Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -385,13 +466,13 @@
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
exist for 1Line (simplex) and 2Lines (full duplex) modes.
@@ -411,21 +492,25 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
@@ -434,51 +519,55 @@
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* Transmit data in 16 Bit mode */
- while (hspi->TxXferCount > 0)
+ while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -489,28 +578,28 @@
/* Transmit data in 8 Bit mode */
else
{
- while (hspi->TxXferCount > 0)
+ while (hspi->TxXferCount > 0U)
{
/* Wait until TXE flag is set to send data */
- if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- if(hspi->TxXferCount > 1)
+ if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
hspi->TxXferCount--;
}
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -518,28 +607,27 @@
}
}
}
-
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -563,55 +651,62 @@
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg;
-#endif
- uint32_t tickstart = HAL_GetTick();
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the TransmitReceive process */
- /* Process Locked */
- return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
}
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL ) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
/* this is done to handle the CRCNEXT before the latest data */
hspi->RxXferCount--;
}
-#endif
-
- /* Set the Rx Fido threshold */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+#endif /* USE_SPI_CRC */
+
+ /* Set the Rx Fifo threshold */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -622,36 +717,37 @@
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
- /* Configure communication direction 1Line and enabled SPI if needed */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ /* Configure communication direction: 1Line */
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
{
/* Transfer loop */
- while(hspi->RxXferCount > 0)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
- (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
+ (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -662,19 +758,19 @@
else
{
/* Transfer loop */
- while(hspi->RxXferCount > 0)
+ while (hspi->RxXferCount > 0U)
{
/* Check the RXNE flag */
- if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
+ *((uint16_t *)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -685,13 +781,13 @@
#if (USE_SPI_CRC != 0U)
/* Handle the CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* freeze the CRC before the latest data */
- hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
/* Read the latest data */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* the latest data has not been received */
errorcode = HAL_TIMEOUT;
@@ -699,67 +795,70 @@
}
/* Receive last data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)pData) = hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
- *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*pData) = *(__IO uint8_t *)&hspi->Instance->DR;
}
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ /* Wait the CRC data */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- /* Flag Error*/
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ /* Read CRC to Flush DR and RXNE flag */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
-
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode = HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
-#endif
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-#endif
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -780,53 +879,72 @@
* @param Timeout: Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg;
-#endif
- uint32_t tickstart = HAL_GetTick();
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
-
HAL_StatusTypeDef errorcode = HAL_OK;
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferCount = Size;
hspi->RxXferSize = Size;
- hspi->pTxBuffPtr = pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferCount = Size;
hspi->TxXferSize = Size;
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -838,49 +956,56 @@
}
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
/* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
+#endif /* USE_SPI_CRC */
}
+
/* Check RXNE flag */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
hspi->RxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
+ /* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -890,48 +1015,54 @@
/* Transmit and Receive data in 8 Bit mode */
else
{
- while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ {
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*pTxData);
+ pTxData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* check TXE flag */
- if(txallowed && ((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)))
+ if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- if(hspi->TxXferCount > 1)
+ if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
hspi->TxXferCount--;
- /* Next Data is a reception (Rx). Tx not allowed */
+ }
+ /* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
- }
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if(((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
+#endif /* USE_SPI_CRC */
}
/* Wait until RXNE flag is reset */
- if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
+ if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount <= 1)
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount <= 1U)
{
/* set fiforxthreshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -939,13 +1070,13 @@
}
else
{
- (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
hspi->RxXferCount--;
- /* Next Data is a Transmission (Tx). Tx is allowed */
- txallowed = 1U;
}
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -955,60 +1086,63 @@
#if (USE_SPI_CRC != 0U)
/* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
-
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
-
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Clear CRC Flag */
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
errorcode = HAL_ERROR;
}
-#endif
+#endif /* USE_SPI_CRC */
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
errorcode = HAL_ERROR;
}
@@ -1030,36 +1164,40 @@
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- /* prepare the transfer */
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
- hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
hspi->TxISR = SPI_TxISR_16BIT;
}
@@ -1069,24 +1207,25 @@
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1109,86 +1248,87 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
+
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- /* Configure communication */
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this we call the TransmitReceive process */
- return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
- }
-
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
+
+ /* check the data size to adapt Rx threshold and the set the function for IT treatment */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
- else
- {
- hspi->CRCSize = 0;
- }
-
- hspi->TxISR = NULL;
- /* check the data size to adapt Rx threshold and the set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
- {
- /* set fiforxthresold according the reception data length: 16 bit */
+ /* set fiforxthreshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- /* set fiforxthresold according the reception data length: 8 bit */
+ /* set fiforxthreshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_8BIT;
}
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
SPI_RESET_CRC(hspi);
}
-#endif
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1211,77 +1351,84 @@
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- if(!((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if (!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- hspi->CRCSize = 0;
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- hspi->CRCSize = 1;
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
- {
- hspi->CRCSize = 2;
- }
- }
-
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pTxData;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
- hspi->pRxBuffPtr = pRxData;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
/* Set the function for IT treatment */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- hspi->RxISR = SPI_2linesRxISR_16BIT;
- hspi->TxISR = SPI_2linesTxISR_16BIT;
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
- hspi->RxISR = SPI_2linesRxISR_8BIT;
- hspi->TxISR = SPI_2linesTxISR_8BIT;
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
+ hspi->CRCSize = 1U;
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
+ {
+ hspi->CRCSize = 2U;
+ }
SPI_RESET_CRC(hspi);
}
-#endif
+ else
+ {
+ hspi->CRCSize = 0U;
+ }
+#endif /* USE_SPI_CRC */
/* check if packing mode is enabled and if there is more than 2 data to receive */
- if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
{
- /* set fiforxthresold according the reception data length: 16 bit */
+ /* set fiforxthreshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8 bit */
+ /* set fiforxthreshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -1289,7 +1436,7 @@
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
@@ -1312,45 +1459,52 @@
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pTxBuffPtr = pData;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
hspi->TxXferSize = Size;
hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_TX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Set the SPI TxDMA Half transfer complete callback */
hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
@@ -1361,40 +1515,39 @@
/* Set the DMA error callback */
hspi->hdmatx->XferErrorCallback = SPI_DMAError;
- /* Set the DMA abort callback */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
/* packing mode is enabled only if the DMA setting is HALWORD */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Check the even/odd of the data size + crc if enabled */
- if((hspi->TxXferCount & 0x1) == 0)
+ if ((hspi->TxXferCount & 0x1U) == 0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1);
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U);
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
}
}
- /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
- SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
- SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
-
- /* Enable the Tx DMA channel */
+ /* Enable the Tx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1409,7 +1562,7 @@
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @param pData: pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
* @retval HAL status
*/
@@ -1417,55 +1570,57 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
+ if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
+ }
+
/* Process Locked */
__HAL_LOCK(hspi);
- if(hspi->State != HAL_SPI_STATE_READY)
+ if (hspi->State != HAL_SPI_STATE_READY)
{
errorcode = HAL_BUSY;
goto error;
}
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
+ /* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->pRxBuffPtr = pData;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t *)NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
- /* the receive process is not supported in 2Lines direction master mode */
- /* in this case we call the TransmitReceive process */
- return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
- }
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
/* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
SPI_1LINE_RX(hspi);
}
#if (USE_SPI_CRC != 0U)
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* packing mode management is enabled by the DMA settings */
- if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
+ if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Restriction the DMA data received is not allowed in this mode */
errorcode = HAL_ERROR;
@@ -1473,7 +1628,7 @@
}
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -1493,26 +1648,25 @@
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
- /* Set the DMA abort callback */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-
- /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
- SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
- SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Enable the Rx DMA channel */
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
error:
/* Process Unlocked */
__HAL_UNLOCK(hspi);
@@ -1525,37 +1679,44 @@
* the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
* @param Size: amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
/* Process locked */
__HAL_LOCK(hspi);
- if(!((hspi->State == HAL_SPI_STATE_READY) ||
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))))
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if (!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
}
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
goto error;
}
- /* check if the transmit Receive function is not called by a receive master */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if (hspi->State != HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
}
+ /* Set the transaction information */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->pTxBuffPtr = (uint8_t *)pTxData;
hspi->TxXferSize = Size;
@@ -1564,111 +1725,108 @@
hspi->RxXferSize = Size;
hspi->RxXferCount = Size;
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
#if (USE_SPI_CRC != 0U)
- /* Reset CRC Calculation + increase the rxsize */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
/* the packing mode management is enabled by the DMA settings according the spi data size */
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8bit */
+ /* set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- if((hspi->TxXferSize & 0x1) == 0x0)
+ if ((hspi->TxXferSize & 0x1U) == 0x0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = hspi->TxXferCount >> 1;
+ hspi->TxXferCount = hspi->TxXferCount >> 1U;
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
- hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
+ hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
}
}
- if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* set fiforxthresold according the reception data length: 16bit */
+ /* set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
- if((hspi->RxXferCount & 0x1) == 0x0 )
+ if ((hspi->RxXferCount & 0x1U) == 0x0U)
{
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = hspi->RxXferCount >> 1;
+ hspi->RxXferCount = hspi->RxXferCount >> 1U;
}
else
{
SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
- hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
+ hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
}
}
}
- /* Set the SPI Rx DMA transfer complete callback if the transfer request is a
- reception request (RXNE) */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
/* Set the SPI Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
}
else
{
- /* Set the SPI Rx DMA Half transfer complete callback */
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
/* Set the DMA error callback */
hspi->hdmarx->XferErrorCallback = SPI_DMAError;
- /* Set the DMA abort callback */
- hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-
- /* Enable SPI Error interrupts, EIE: MODF, OVR, FE, FRE, CEC(depends on family) */
- SET_BIT(hspi->Instance->CR2, (SPI_CR2_ERRIE));
- SET_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream/Channel */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
- /* Enable the Rx DMA channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
-
/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
hspi->hdmatx->XferHalfCpltCallback = NULL;
- hspi->hdmatx->XferCpltCallback = NULL;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Set the DMA abort callback */
- hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-
- /* Enable the Tx DMA channel */
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream/Channel */
HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
/* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
}
+ /* Enable the SPI Error Interrupt Bit */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
/* Enable Tx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
@@ -1680,7 +1838,308 @@
}
/**
- * @brief Pause the DMA Transfer.
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return errorcode;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ HAL_StatusTypeDef errorcode;
+ uint32_t abortcplt ;
+
+ /* Initialized local variable */
+ errorcode = HAL_OK;
+ abortcplt = 1U;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ while (hspi->State != HAL_SPI_STATE_ABORT);
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if (abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check error during Abort procedure */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+ {
+ /* return HAL_Error in case of error during Abort procedure */
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+ }
+
+ return errorcode;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1700,7 +2159,7 @@
}
/**
- * @brief Resumes the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1720,7 +2179,7 @@
}
/**
- * @brief Stops the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
@@ -1728,18 +2187,18 @@
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
/* The Lock is not implemented on this API to allow the user application
- to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
- */
-
- /* Abort the SPI DMA tx Stream */
- if(hspi->hdmatx != NULL)
+ to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
+ */
+
+ /* Abort the SPI DMA tx Stream/Channel */
+ if (hspi->hdmatx != NULL)
{
HAL_DMA_Abort(hspi->hdmatx);
}
- /* Abort the SPI DMA rx Stream */
- if(hspi->hdmarx != NULL)
+ /* Abort the SPI DMA rx Stream/Channel */
+ if (hspi->hdmarx != NULL)
{
HAL_DMA_Abort(hspi->hdmarx);
}
@@ -1751,7 +2210,7 @@
}
/**
- * @brief This function handles SPI interrupt request.
+ * @brief Handle SPI interrupt request.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
@@ -1762,96 +2221,78 @@
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
- if(((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ if (((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
- /* SPI in mode Transmitter ---------------------------------------------------*/
- if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
- /* SPI in Error Treatment ---------------------------------------------------*/
- if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
{
- /* SPI Overrun error interrupt occurred -------------------------------------*/
- if((itflag & SPI_FLAG_OVR) != RESET)
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if ((itflag & SPI_FLAG_OVR) != RESET)
{
- if(hspi->State != HAL_SPI_STATE_BUSY_TX)
+ if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
else
{
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
return;
}
}
- /* SPI Mode Fault error interrupt occurred -------------------------------------*/
- if((itflag & SPI_FLAG_MODF) != RESET)
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if ((itflag & SPI_FLAG_MODF) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
- /* SPI Frame error interrupt occurred ----------------------------------------*/
- if((itflag & SPI_FLAG_FRE) != RESET)
+ /* SPI Frame error interrupt occurred ------------------------------------*/
+ if ((itflag & SPI_FLAG_FRE) != RESET)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
}
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- /* All SPI errors are treated as Blocking errors : transfer is aborted.
- Set the SPI state to ready so as to be able to restart the process,
- Disable Rx/Tx Interrupts, and disable DMA Rx/Tx requests, if ongoing */
-
- /* Disable TXE, RXNE, MODF, OVR, FRE, and CRCERR (Master mode fault, Overrun error, TI frame format error, CRC protocol error) interrupts */
- CLEAR_BIT(hspi->Instance->CR1, (SPI_CR2_RXNEIE | SPI_CR2_TXEIE | SPI_CR2_ERRIE));
- CLEAR_BIT(hspi->Instance->SR, (SPI_SR_FRE | SPI_SR_OVR | SPI_SR_MODF | SPI_SR_CRCERR));
-
- /* Restore SPI State to Ready */
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
hspi->State = HAL_SPI_STATE_READY;
-
/* Disable the SPI DMA requests if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
{
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
/* Abort the SPI DMA Rx channel */
- if(hspi->hdmarx != NULL)
+ if (hspi->hdmarx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
-
- /* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- /* Call Directly hspi->hdmarx->XferAbortCallback function in case of error */
- hspi->hdmarx->XferAbortCallback(hspi->hdmarx);
- }
+ HAL_DMA_Abort_IT(hspi->hdmarx);
}
/* Abort the SPI DMA Tx channel */
- if(hspi->hdmatx != NULL)
+ if (hspi->hdmatx != NULL)
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
-
- /* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- /* Call Directly hspi->hdmatx->XferAbortCallback function in case of error */
- hspi->hdmatx->XferAbortCallback(hspi->hdmatx);
- }
+ HAL_DMA_Abort_IT(hspi->hdmatx);
}
}
else
@@ -1860,6 +2301,7 @@
HAL_SPI_ErrorCallback(hspi);
}
}
+ return;
}
}
@@ -1875,8 +2317,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback should be implemented in the user file
- */
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
}
/**
@@ -1891,8 +2333,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback should be implemented in the user file
- */
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
}
/**
@@ -1907,8 +2349,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback should be implemented in the user file
- */
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
}
/**
@@ -1923,8 +2365,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
- */
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
}
/**
@@ -1939,8 +2381,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
- */
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
}
/**
@@ -1955,8 +2397,8 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
- */
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
}
/**
@@ -1971,11 +2413,26 @@
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback should be implemented in the user file
- */
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
*/
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
+ */
}
/**
@@ -1983,7 +2440,7 @@
*/
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
+ * @brief SPI control functions
*
@verbatim
===============================================================================
@@ -2017,6 +2474,7 @@
*/
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI ErrorCode */
return hspi->ErrorCode;
}
@@ -2024,13 +2482,12 @@
* @}
*/
-
/**
* @}
*/
/** @addtogroup SPI_Private_Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
@@ -2042,30 +2499,37 @@
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
/* DMA Normal Mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
/* Disable Tx DMA Request */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received data is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- hspi->TxXferCount = 0;
+ hspi->TxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -2082,69 +2546,81 @@
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode */
- if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg;
/* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- /* Wait until TXE flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ /* Wait until RXNE flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ /* Read CRC */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
else
{
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
-
- if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
}
}
-#endif
+#endif /* USE_SPI_CRC */
/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
- hspi->RxXferCount = 0;
+ hspi->RxXferCount = 0U;
hspi->State = HAL_SPI_STATE_READY;
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
-#endif
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
return;
@@ -2154,135 +2630,156 @@
}
/**
- * @brief DMA SPI transmit receive process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ uint32_t tickstart = 0U;
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg;
- /* CRC handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)
{
- if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
- {
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
- }
- else
- {
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- /* Error on the CRC reception */
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- }
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
- }
- }
-#endif
-
- /* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT) != HAL_OK)
- {
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- /* Disable Rx/Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
#if (USE_SPI_CRC != 0U)
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
-#endif
-
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- return;
+ /* CRC handling */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
+ tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ else
+ {
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check the end of the transaction */
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
}
HAL_SPI_TxRxCpltCallback(hspi);
}
/**
- * @brief DMA SPI half transmit process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
HAL_SPI_TxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI half receive process complete callback.
+ * @brief DMA SPI half receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
HAL_SPI_RxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI half transmit receive process complete callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
HAL_SPI_TxRxHalfCpltCallback(hspi);
}
/**
- * @brief DMA SPI communication error callback.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA SPI communication error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_ErrorCallback(hspi);
}
/**
- * @brief DMA SPI communication abort callback
- * (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
* @retval None
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
@@ -2290,6 +2787,131 @@
}
/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmarx != NULL)
+ {
+ if (hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Check if an Abort process is still ongoing */
+ if (hspi->hdmatx != NULL)
+ {
+ if (hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Check no error during Abort procedure */
+ if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
+ {
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ }
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_FREFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
@@ -2298,12 +2920,12 @@
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in packing mode */
- if(hspi->RxXferCount > 1)
+ if (hspi->RxXferCount > 1U)
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount -= 2;
- if(hspi->RxXferCount == 1)
+ hspi->RxXferCount -= 2U;
+ if (hspi->RxXferCount == 1U)
{
/* set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
@@ -2317,21 +2939,21 @@
}
/* check end of the reception */
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_2linesRxISR_8BITCRC;
return;
}
-#endif
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if(hspi->TxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2347,24 +2969,29 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
- UNUSED(tmpreg); /* To avoid GCC warning */
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
/* check end of the reception */
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
-
- if(hspi->TxXferCount == 0)
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
}
}
-#endif
+#endif /* USE_SPI_CRC */
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
@@ -2375,11 +3002,11 @@
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Transmit data in packing Bit mode */
- if(hspi->TxXferCount >= 2)
+ if (hspi->TxXferCount >= 2U)
{
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint16_t);
- hspi->TxXferCount -= 2;
+ hspi->TxXferCount -= 2U;
}
/* Transmit data in 8 Bit mode */
else
@@ -2389,19 +3016,23 @@
}
/* check the end of the transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
}
-#endif
+#endif /* USE_SPI_CRC */
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2417,24 +3048,24 @@
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_2linesRxISR_16BITCRC;
return;
}
-#endif
+#endif /* USE_SPI_CRC */
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2451,15 +3082,20 @@
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
SPI_CloseRxTx_ISR(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
@@ -2475,19 +3111,23 @@
hspi->TxXferCount--;
/* Enable CRC Transmission */
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ /* Set CRC Next Bit to send CRC */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
}
-#endif
+#endif /* USE_SPI_CRC */
/* Disable TXE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
- if(hspi->RxXferCount == 0)
+ if (hspi->RxXferCount == 0U)
{
SPI_CloseRxTx_ISR(hspi);
}
@@ -2503,19 +3143,22 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg;
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
-
- UNUSED(tmpreg); /* To avoid GCC warning */
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
hspi->CRCSize--;
- if(hspi->CRCSize == 0)
+ if (hspi->CRCSize == 0U)
{
SPI_CloseRx_ISR(hspi);
}
}
-#endif
+#endif /* USE_SPI_CRC */
/**
* @brief Manage the receive 8-bit in Interrupt context.
@@ -2530,21 +3173,21 @@
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
-
- if(hspi->RxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_8BITCRC;
return;
}
-#endif
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
@@ -2558,17 +3201,20 @@
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg;
-
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg); /* To avoid GCC warning */
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
SPI_CloseRx_ISR(hspi);
}
-#endif
+#endif /* USE_SPI_CRC */
/**
* @brief Manage the 16-bit receive in Interrupt context.
@@ -2581,22 +3227,24 @@
*((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
+
#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
- if(hspi->RxXferCount == 0)
+#endif /* USE_SPI_CRC */
+
+ if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
hspi->RxISR = SPI_RxISR_16BITCRC;
return;
}
-#endif
+#endif /* USE_SPI_CRC */
SPI_CloseRx_ISR(hspi);
}
}
@@ -2612,15 +3260,15 @@
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
@@ -2638,37 +3286,37 @@
hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
- if(hspi->TxXferCount == 0)
+ if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Enable CRC Transmission */
- hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-#endif
+#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
}
}
/**
* @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag : SPI flag to check
- * @param State : flag state to check
- * @param Timeout : Timeout duration
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param State: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
- while((hspi->Instance->SR & Flag) != State)
+ while ((hspi->Instance->SR & Flag) != State)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -2677,71 +3325,15 @@
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State= HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo : Fifo to check
- * @param State : Fifo state to check
- * @param Timeout : Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
-{
- __IO uint8_t tmpreg;
- uint32_t tickstart = HAL_GetTick();
-
- while((hspi->Instance->SR & Fifo) != State)
- {
- if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
- {
- tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
- UNUSED(tmpreg); /* To avoid GCC warning */
- }
-
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
SPI_RESET_CRC(hspi);
}
@@ -2755,37 +3347,102 @@
}
}
}
+
return HAL_OK;
}
/**
- * @brief Handle the check of the RX transaction complete.
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo: Fifo to check
+ * @param State: Fifo state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ __IO uint8_t tmpreg;
+
+ while ((hspi->Instance->SR & Fifo) != State)
+ {
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the check of the RX transaction complete.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout : Timeout duration
- * @retval None
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval None.
*/
-static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
}
/* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
/* Empty the FRLVL fifo */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
}
@@ -2795,62 +3452,69 @@
/**
* @brief Handle the check of the RXTX or TX transaction complete.
* @param hspi: SPI handle
- * @param Timeout : Timeout duration
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
*/
-static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
- /* Procedure to check the transaction complete */
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
+ /* Control if the TX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
- return HAL_TIMEOUT;
- }
- if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
- {
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
/* Control the BSY flag */
- if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
- hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
return HAL_OK;
}
/**
- * @brief Handle the end of the RXTX transaction.
+ * @brief Handle the end of the RXTX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
/* Disable ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
hspi->State = HAL_SPI_STATE_READY;
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
HAL_SPI_ErrorCallback(hspi);
}
else
{
-#endif
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
HAL_SPI_RxCpltCallback(hspi);
@@ -2868,11 +3532,11 @@
}
#if (USE_SPI_CRC != 0U)
}
-#endif
+#endif /* USE_SPI_CRC */
}
/**
- * @brief Handle the end of the RX transaction.
+ * @brief Handle the end of the RX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2883,23 +3547,24 @@
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
/* Check the end of the transaction */
- if(SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
hspi->State = HAL_SPI_STATE_READY;
+
#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
HAL_SPI_ErrorCallback(hspi);
}
else
{
-#endif
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+#endif /* USE_SPI_CRC */
+ if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
HAL_SPI_RxCpltCallback(hspi);
}
@@ -2909,34 +3574,39 @@
}
#if (USE_SPI_CRC != 0U)
}
-#endif
+#endif /* USE_SPI_CRC */
}
/**
- * @brief Handle the end of the TX transaction.
+ * @brief Handle the end of the TX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
/* Check the end of the transaction */
- if(SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT)!=HAL_OK)
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
- hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
hspi->State = HAL_SPI_STATE_READY;
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
}
@@ -2947,6 +3617,67 @@
}
/**
+ * @brief Handle abort a Rx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
+ * @brief Handle abort a Tx or Rx/Tx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+
+ if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ hspi->State = HAL_SPI_STATE_ABORT;
+}
+
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h Thu Feb 02 17:01:33 2017 +0000
@@ -1,9 +1,9 @@
- /**
+/**
******************************************************************************
* @file stm32f7xx_hal_spi.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -40,7 +40,7 @@
#define __STM32F7xx_HAL_SPI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -64,48 +64,48 @@
*/
typedef struct
{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
+ uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
- uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
+ uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
- uint32_t DataSize; /*!< Specifies the SPI data size.
+ uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
+ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
+ uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
+ uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
- uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
+ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
This parameter can be a value of @ref SPI_CRC_length */
- uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
+ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
@@ -114,57 +114,58 @@
} SPI_InitTypeDef;
/**
- * @brief HAL State structures definition
+ * @brief HAL SPI State structure definition
*/
typedef enum
{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing*/
- HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
-}HAL_SPI_StateTypeDef;
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
+ HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
+} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
- SPI_TypeDef *Instance; /* SPI registers base address */
+ SPI_TypeDef *Instance; /*!< SPI registers base address */
- SPI_InitTypeDef Init; /* SPI communication parameters */
+ SPI_InitTypeDef Init; /*!< SPI communication parameters */
- uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
- uint16_t TxXferSize; /* SPI Tx Transfer size */
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
- uint16_t TxXferCount; /* SPI Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
- uint16_t RxXferSize; /* SPI Rx Transfer size */
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
- uint16_t RxXferCount; /* SPI Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
- uint32_t CRCSize; /* SPI CRC size used for the transfer */
+ uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
- void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler */
+ void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
- void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler */
+ void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
- DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
- DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
- HAL_LockTypeDef Lock; /* Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
+ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
- __IO uint32_t ErrorCode; /* SPI Error code */
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
-}SPI_HandleTypeDef;
+} SPI_HandleTypeDef;
/**
* @}
@@ -179,19 +180,18 @@
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
-#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
-#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
-#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040U) /*!< Unknow Error error */
+#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001U) /*!< MODF error */
+#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002U) /*!< CRC error */
+#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004U) /*!< OVR error */
+#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008U) /*!< FRE error */
+#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_ABORT ((uint32_t)0x00000040U) /*!< Error during SPI Abort procedure */
/**
* @}
*/
-
/** @defgroup SPI_Mode SPI Mode
* @{
*/
@@ -214,19 +214,19 @@
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_4BIT ((uint32_t)0x0300U)
-#define SPI_DATASIZE_5BIT ((uint32_t)0x0400U)
-#define SPI_DATASIZE_6BIT ((uint32_t)0x0500U)
-#define SPI_DATASIZE_7BIT ((uint32_t)0x0600U)
-#define SPI_DATASIZE_8BIT ((uint32_t)0x0700U)
-#define SPI_DATASIZE_9BIT ((uint32_t)0x0800U)
-#define SPI_DATASIZE_10BIT ((uint32_t)0x0900U)
-#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00U)
-#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00U)
-#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00U)
-#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00U)
-#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00U)
-#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00U)
+#define SPI_DATASIZE_4BIT ((uint32_t)0x00000300U)
+#define SPI_DATASIZE_5BIT ((uint32_t)0x00000400U)
+#define SPI_DATASIZE_6BIT ((uint32_t)0x00000500U)
+#define SPI_DATASIZE_7BIT ((uint32_t)0x00000600U)
+#define SPI_DATASIZE_8BIT ((uint32_t)0x00000700U)
+#define SPI_DATASIZE_9BIT ((uint32_t)0x00000800U)
+#define SPI_DATASIZE_10BIT ((uint32_t)0x00000900U)
+#define SPI_DATASIZE_11BIT ((uint32_t)0x00000A00U)
+#define SPI_DATASIZE_12BIT ((uint32_t)0x00000B00U)
+#define SPI_DATASIZE_13BIT ((uint32_t)0x00000C00U)
+#define SPI_DATASIZE_14BIT ((uint32_t)0x00000D00U)
+#define SPI_DATASIZE_15BIT ((uint32_t)0x00000E00U)
+#define SPI_DATASIZE_16BIT ((uint32_t)0x00000F00U)
/**
* @}
*/
@@ -249,7 +249,7 @@
* @}
*/
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
@@ -283,7 +283,7 @@
* @}
*/
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
@@ -292,7 +292,7 @@
* @}
*/
-/** @defgroup SPI_TI_mode SPI TI mode
+/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000U)
@@ -340,10 +340,7 @@
* @}
*/
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
- * @brief SPI Interrupt definition
- * Elements values convention: 0xXXXXXXXX
- * - XXXXXXXX : Interrupt control mask
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@@ -353,23 +350,18 @@
* @}
*/
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
- * @brief Flag definition
- * Elements values convention: 0xXXXXYYYY
- * - XXXX : Flag register Index
- * - YYYY : Flag mask
+/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
-#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
/**
* @}
*/
@@ -377,10 +369,10 @@
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
*/
-#define SPI_FTLVL_EMPTY ((uint32_t)0x0000U)
-#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800U)
-#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000U)
-#define SPI_FTLVL_FULL ((uint32_t)0x1800U)
+#define SPI_FTLVL_EMPTY ((uint32_t)0x00000000U)
+#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x00000800U)
+#define SPI_FTLVL_HALF_FULL ((uint32_t)0x00001000U)
+#define SPI_FTLVL_FULL ((uint32_t)0x00001800U)
/**
* @}
@@ -389,34 +381,31 @@
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
-#define SPI_FRLVL_EMPTY ((uint32_t)0x0000U)
-#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200U)
-#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400U)
-#define SPI_FRLVL_FULL ((uint32_t)0x0600U)
-/**
- * @}
- */
-
+#define SPI_FRLVL_EMPTY ((uint32_t)0x00000000U)
+#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x00000200U)
+#define SPI_FRLVL_HALF_FULL ((uint32_t)0x00000400U)
+#define SPI_FRLVL_FULL ((uint32_t)0x00000600U)
/**
* @}
*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
-/** @brief Reset SPI handle state
- * @param __HANDLE__: SPI handle.
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-/** @brief Enables or disables the specified SPI interrupts.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Enable or disable the specified SPI interrupts.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
@@ -425,10 +414,10 @@
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__ : specifies the SPI interrupt source to check.
+ * @param __INTERRUPT__: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
@@ -437,11 +426,11 @@
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-/** @brief Checks whether the specified SPI flag is set or not.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__ : specifies the flag to check.
- * This parameter can be one of the following values:
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
@@ -455,63 +444,60 @@
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-/** @brief Clears the SPI CRCERR pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI CRCERR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-/** @brief Clears the SPI MODF pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI MODF pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0)
-/** @brief Clears the SPI OVR pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI OVR pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while(0)
-/** @brief Clears the SPI FRE pending flag.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Clear the SPI FRE pending flag.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- *
* @retval None
*/
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0)
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
+ }while(0)
-/** @brief Enables the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Enable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
-/** @brief Disables the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
@@ -521,27 +507,27 @@
* @}
*/
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
-/** @brief Sets the SPI transmit-only mode.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-/** @brief Sets the SPI receive-only mode.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-/** @brief Resets the CRC calculation of the SPI.
- * @param __HANDLE__ : specifies the SPI Handle.
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
@@ -551,14 +537,14 @@
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
- ((MODE) == SPI_DIRECTION_1LINE))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
@@ -580,19 +566,19 @@
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
@@ -609,25 +595,23 @@
((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
((LENGTH) == SPI_CRC_LENGTH_16BIT))
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF) && (((POLYNOMIAL)&0x1) != 0))
-
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions SPI Exported Functions
+/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-
-/* Initialization and de-initialization functions ****************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/**
@@ -637,20 +621,25 @@
/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
* @{
*/
-
-/* IO operation functions *****************************************************/
+/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
@@ -660,6 +649,7 @@
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
@@ -693,4 +683,7 @@
#endif /* __STM32F7xx_HAL_SPI_H */
+/**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -58,10 +58,10 @@
(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
@@ -1162,7 +1162,7 @@
* @brief Starts the PWM signal generation in interrupt mode.
* @param htim: pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel: TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -42,10 +42,10 @@
(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
- (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
+ (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
(##) TIM pins configuration
(+++) Enable the clock for the TIM GPIOs using the following function:
- __GPIOx_CLK_ENABLE();
+ __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
(#) The external Clock can be configured, if needed (the default clock is the
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_uart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -922,14 +922,11 @@
/* Process Unlocked */
__HAL_UNLOCK(huart);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Data Register not empty Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
+ /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
return HAL_OK;
}
@@ -1212,7 +1209,9 @@
}
/* If some errors occur */
- if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
{
/* UART parity error interrupt occurred -------------------------------------*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -230,13 +230,13 @@ uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ uint16_t Mask; /*!< UART Rx RDR register mask */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f7xx_hal_usart.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
* Peripheral (USART).
* + Initialization and de-initialization functions
@@ -29,19 +29,19 @@
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
(+++) Enable the NVIC USART IRQ handle.
- (+++) The specific USART interrupts (Transmission complete interrupt,
+ (+++) The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
(##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Stream.
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
@@ -221,7 +221,7 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
@@ -274,7 +274,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspInit can be implemented in the user file
*/
@@ -289,7 +289,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_MspDeInit can be implemented in the user file
*/
@@ -299,8 +299,8 @@
* @}
*/
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
*
@verbatim
===============================================================================
@@ -381,7 +381,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
-
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -452,7 +452,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -535,7 +535,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
-
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -675,15 +675,12 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART Data Register not empty Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -801,14 +798,14 @@
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
SET_BIT(husart->Instance->ISR, (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE | USART_ISR_ORE));
-
+
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -864,15 +861,15 @@
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
-
+
/* Set the DMA abort callback */
husart->hdmatx->XferAbortCallback = NULL;
-
+
/* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
is performed in DMA reception complete callback */
husart->hdmatx->XferHalfCpltCallback = NULL;
husart->hdmatx->XferCpltCallback = NULL;
-
+
/* Set the DMA error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
@@ -888,13 +885,13 @@
to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive mode */
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
/* Enable the USART Parity Error Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
+
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -916,7 +913,7 @@
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
+ * @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
* @param husart: USART handle
* @param pTxData: pointer to TX data buffer
* @param pRxData: pointer to RX data buffer
@@ -977,13 +974,13 @@
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_IT(husart, USART_FLAG_TC);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
/* Enable the USART Parity Error Interrupt */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
+
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1059,7 +1056,7 @@
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
-
+
/* Reenable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1094,9 +1091,9 @@
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
- HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
/* Stop USART DMA Tx request if ongoing */
@@ -1104,33 +1101,33 @@
(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
{
USART_EndTxTransfer(husart);
-
+
/* Abort the USART DMA Tx channel */
if(husart->hdmatx != NULL)
{
HAL_DMA_Abort(husart->hdmatx);
}
-
+
/* Disable the USART Tx DMA request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
-
+
/* Stop USART DMA Rx request if ongoing */
if ((husart->State == HAL_USART_STATE_BUSY_RX) &&
(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
{
USART_EndRxTransfer(husart);
-
+
/* Abort the USART DMA Rx channel */
if(husart->hdmarx != NULL)
{
HAL_DMA_Abort(husart->hdmarx);
}
-
+
/* Disable the USART Rx DMA request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
}
-
+
return HAL_OK;
}
@@ -1145,7 +1142,7 @@
uint32_t cr1its = READ_REG(husart->Instance->CR1);
uint32_t cr3its = READ_REG(husart->Instance->CR3);
uint32_t errorflags;
-
+
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
if (errorflags == RESET)
@@ -1163,39 +1160,41 @@
}
}
}
-
+
/* If some errors occur */
- if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE | USART_CR1_PEIE)) != RESET))
+ if( (errorflags != RESET)
+ && ( ((cr3its & USART_CR3_EIE) != RESET)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
{
-
+
/* USART parity error interrupt occurred ------------------------------------*/
if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
husart->ErrorCode |= HAL_USART_ERROR_PE;
}
-
+
/* USART frame error interrupt occurred -------------------------------------*/
if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
husart->ErrorCode |= HAL_USART_ERROR_FE;
}
-
+
/* USART noise error interrupt occurred -------------------------------------*/
if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
husart->ErrorCode |= HAL_USART_ERROR_NE;
}
-
+
/* USART Over-Run interrupt occurred ----------------------------------------*/
if(((isrflags & USART_ISR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
-
+
/* Call USART Error Call back function if need be --------------------------*/
if(husart->ErrorCode != HAL_USART_ERROR_NONE)
{
@@ -1204,29 +1203,29 @@
{
USART_Receive_IT(husart);
}
-
+
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
- {
+ {
/* Blocking error : transfer is aborted
Set the USART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
USART_EndRxTransfer(husart);
-
+
/* Disable the USART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
+
/* Abort the USART DMA Rx channel */
if(husart->hdmarx != NULL)
- {
- /* Set the USART DMA Abort callback :
+ {
+ /* Set the USART DMA Abort callback :
will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
-
+
/* Abort DMA RX */
if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
@@ -1248,16 +1247,16 @@
}
else
{
- /* Non Blocking error : transfer could go on.
+ /* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
HAL_USART_ErrorCallback(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
}
}
return;
-
+
} /* End if some error occurs */
-
+
/* USART in mode Transmitter -----------------------------------------------*/
if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
@@ -1271,7 +1270,7 @@
}
return;
}
-
+
/* USART in mode Transmitter (transmission end) -----------------------------*/
if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
@@ -1289,10 +1288,10 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_TxCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -1304,7 +1303,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_TxHalfCpltCallback can be implemented in the user file
*/
@@ -1319,7 +1318,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_USART_RxCpltCallback can be implemented in the user file
*/
@@ -1334,7 +1333,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_RxHalfCpltCallback can be implemented in the user file
*/
@@ -1349,7 +1348,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_TxRxCpltCallback can be implemented in the user file
*/
@@ -1364,31 +1363,31 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
-
+
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_USART_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief USART State and Errors functions
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief USART State and Errors functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to return the State of
+ This subsection provides a set of functions allowing to return the State of
USART communication
process, return Peripheral Errors occurred during communication process
- (+) HAL_USART_GetState() API can be helpful to check in run-time the state
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state
of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occurred during
- communication.
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+ communication.
@endverbatim
* @{
*/
@@ -1417,7 +1416,7 @@
/**
* @}
*/
-
+
/**
* @brief Simplex Send an amount of data in non-blocking mode.
@@ -1454,7 +1453,7 @@
}
else
{
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF);
}
husart->TxXferCount--;
@@ -1545,7 +1544,7 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
* Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT()
+ * interruptions have been enabled by HAL_USART_TransmitReceive_IT()
* @param husart: USART handle
* @retval HAL status
*/
@@ -1633,7 +1632,7 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
@@ -1645,21 +1644,21 @@
{
/* Disable the USART Transmit Complete Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
-
+
/* Disable the USART RXNE Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
-
+
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
-
+
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
+
husart->State= HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
+
return HAL_TIMEOUT;
}
}
@@ -1679,7 +1678,7 @@
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
- {
+ {
husart->TxXferCount = 0U;
if(husart->State == HAL_USART_STATE_BUSY_TX)
@@ -1726,9 +1725,9 @@
/* DMA Normal mode */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
- {
+ {
husart->RxXferCount = 0U;
-
+
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1789,21 +1788,21 @@
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
-
+
/* Stop USART DMA Tx request if ongoing */
if((husart->State == HAL_USART_STATE_BUSY_TX)
&&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
{
USART_EndTxTransfer(husart);
}
-
+
/* Stop USART DMA Rx request if ongoing */
if((husart->State == HAL_USART_STATE_BUSY_RX)
&&(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
{
USART_EndRxTransfer(husart);
}
-
+
husart->ErrorCode |= HAL_USART_ERROR_DMA;
husart->State= HAL_USART_STATE_READY;
@@ -1821,7 +1820,7 @@
USART_HandleTypeDef* husart = (USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
-
+
HAL_USART_ErrorCallback(husart);
}
@@ -1834,7 +1833,7 @@
{
/* At end of Tx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
-
+
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
}
@@ -1848,14 +1847,14 @@
{
/* At end of Rx process, restore husart->RxState to Ready */
husart->State = HAL_USART_STATE_READY;
-
+
/* Disable RXNE, PE and ERR interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
}
/**
- * @brief Configure the USART peripheral
+ * @brief Configure the USART peripheral
* @param husart: USART handle
* @retval None
*/
@@ -1866,36 +1865,36 @@
HAL_StatusTypeDef ret = HAL_OK;
uint16_t brrtemp = 0x0000U;
uint16_t usartdiv = 0x0000U;
-
+
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
- assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
+ assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
assert_param(IS_USART_PARITY(husart->Init.Parity));
assert_param(IS_USART_MODE(husart->Init.Mode));
- assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));
+ assert_param(IS_USART_OVERSAMPLING(husart->Init.OverSampling));
/*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity, Mode and OverSampling:
- * set the M bits according to husart->Init.WordLength value
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity, Mode and OverSampling:
+ * set the M bits according to husart->Init.WordLength value
* set PCE and PS bits according to husart->Init.Parity value
* set TE and RE bits according to husart->Init.Mode value
* force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
-
+
/*---------------------------- USART CR2 Configuration ---------------------*/
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
* set LBCL bit according to husart->Init.CLKLastBit value
* set STOP[13:12] bits according to husart->Init.StopBits value */
- tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
@@ -1927,13 +1926,13 @@
default:
ret = HAL_ERROR;
break;
- }
-
+ }
+
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
husart->Instance->BRR = brrtemp;
-
- return ret;
+
+ return ret;
}
/**
@@ -1944,41 +1943,41 @@
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
uint32_t tickstart = 0U;
-
+
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
-
+
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
-
+
/* Check if the Transmitter is enabled */
if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- husart->State= HAL_USART_STATE_TIMEOUT;
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ husart->State= HAL_USART_STATE_TIMEOUT;
return HAL_TIMEOUT;
- }
+ }
}
/* Check if the Receiver is enabled */
if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- husart->State= HAL_USART_STATE_TIMEOUT;
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ husart->State= HAL_USART_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
-
+
/* Initialize the USART state*/
husart->State= HAL_USART_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention @@ -141,13 +141,13 @@ uint16_t TxXferSize; /*!< USART Tx Transfer size */ - uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ uint16_t RxXferSize; /*!< USART Rx Transfer size */ - uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ uint16_t Mask; /*!< USART Rx RDR register mask */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c Thu Feb 02 17:01:33 2017 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_ll_usb.c
* @author MCD Application Team
- * @version V1.1.0
- * @date 22-April-2016
+ * @version V1.1.2
+ * @date 23-September-2016
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -703,6 +703,9 @@
}
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+
if (dma == 1)
{
USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
@@ -710,14 +713,11 @@
else
{
/* Enable the Tx FIFO Empty Interrupt for this EP */
- if (ep->xfer_len > 0)
+ if (ep->xfer_len > 0U)
{
- atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
+ USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
}
- }
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
+ }
}
else /* OUT endpoint */
{
@@ -1227,9 +1227,10 @@
__IO uint32_t hprt0;
hprt0 = USBx_HPRT0;
+ hprt0 |= USB_OTG_HPRT_PENA ;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
+ USB_OTG_HPRT_POCCHNG );
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
HAL_Delay (10); /* See Note #1 */
@@ -1250,8 +1251,10 @@
__IO uint32_t hprt0;
hprt0 = USBx_HPRT0;
- hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
- USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
+ hprt0 |= USB_OTG_HPRT_PENA ;
+
+ hprt0 &= ~(USB_OTG_HPRT_PCDET | USB_OTG_HPRT_PENCHNG |\
+ USB_OTG_HPRT_POCCHNG );
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
{
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h Thu Feb 02 17:01:33 2017 +0000 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 + * @version V1.1.2 + * @date 23-September-2016 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set_clr = &gpio->BSRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F7/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set_clr = obj->mask;
- } else {
- *obj->reg_set_clr = obj->mask << 16;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,68 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -171,14 +132,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -71,7 +71,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -155,14 +116,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -155,14 +116,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -61,7 +61,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -184,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -67,7 +67,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -184,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -71,7 +71,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L0/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32L0/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
- *obj->reg_clr = obj->mask;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,68 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -183,14 +144,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -183,14 +144,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -176,14 +137,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,51 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_IT_RISING (6)
-#define STM_MODE_IT_FALLING (7)
-#define STM_MODE_IT_RISING_FALLING (8)
-#define STM_MODE_EVT_RISING (9)
-#define STM_MODE_EVT_FALLING (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -213,14 +174,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -66,7 +66,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L1/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32L1/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
-#if defined(TARGET_STM32L152RC) || defined(TARGET_STM32L151RC) || defined (TARGET_STM32L151CC)
- *obj->reg_set = obj->mask << 16;
-#else
- *obj->reg_clr = obj->mask;
-#endif
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/PeripheralPins.h Mon Jan 16 15:03:32 2017 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,73 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** - -extern const PinMap PinMap_ADC[]; - -//*** DAC *** - -extern const PinMap PinMap_DAC[]; - -//*** I2C *** - -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; - -//*** PWM *** - -extern const PinMap PinMap_PWM[]; - -//*** SERIAL *** - -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; - -//*** SPI *** - -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; - -//*** CAN *** - -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; - -#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,52 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_ANALOG_ADC_CONTROL (6)
-#define STM_MODE_IT_RISING (7)
-#define STM_MODE_IT_FALLING (8)
-#define STM_MODE_IT_RISING_FALLING (9)
-#define STM_MODE_EVT_RISING (10)
-#define STM_MODE_EVT_FALLING (11)
-#define STM_MODE_EVT_RISING_FALLING (12)
-#define STM_MODE_IT_EVT_RESET (13)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00, // On P1/P2 connectors
PA_1 = 0x01, // On P1/P2 connectors
@@ -199,14 +159,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -76,7 +76,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,52 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_ANALOG_ADC_CONTROL (6)
-#define STM_MODE_IT_RISING (7)
-#define STM_MODE_IT_FALLING (8)
-#define STM_MODE_IT_RISING_FALLING (9)
-#define STM_MODE_EVT_RISING (10)
-#define STM_MODE_EVT_FALLING (11)
-#define STM_MODE_EVT_RISING_FALLING (12)
-#define STM_MODE_IT_EVT_RESET (13)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -185,14 +145,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/objects.h Mon Jan 16 15:03:32 2017 +0000 +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/objects.h Thu Feb 02 17:01:33 2017 +0000 @@ -76,7 +76,6 @@ }; #include "common_objects.h" -#include "gpio_object.h" #ifdef __cplusplus }
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/PinNames.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/PinNames.h Thu Feb 02 17:01:33 2017 +0000
@@ -31,52 +31,12 @@
#define MBED_PINNAMES_H
#include "cmsis.h"
+#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
-#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\
- ((PUPD & 0x07) << 4) |\
- ((AFNUM & 0x0F) << 7) |\
- ((CHANNEL & 0x1F) << 11) |\
- ((INVERTED & 0x01) << 16)))
-
-#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F)
-#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F)
-#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01)
-
-#define STM_MODE_INPUT (0)
-#define STM_MODE_OUTPUT_PP (1)
-#define STM_MODE_OUTPUT_OD (2)
-#define STM_MODE_AF_PP (3)
-#define STM_MODE_AF_OD (4)
-#define STM_MODE_ANALOG (5)
-#define STM_MODE_ANALOG_ADC_CONTROL (6)
-#define STM_MODE_IT_RISING (7)
-#define STM_MODE_IT_FALLING (8)
-#define STM_MODE_IT_RISING_FALLING (9)
-#define STM_MODE_EVT_RISING (10)
-#define STM_MODE_EVT_FALLING (11)
-#define STM_MODE_EVT_RISING_FALLING (12)
-#define STM_MODE_IT_EVT_RESET (13)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
@@ -157,14 +117,6 @@
NC = (int)0xFFFFFFFF
} PinName;
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrain = 3,
- PullDefault = PullNone
-} PinMode;
-
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/PortNames.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/objects.h Thu Feb 02 17:01:33 2017 +0000
@@ -75,7 +75,6 @@
RNG_HandleTypeDef handle;
};
-#include "gpio_object.h"
#include "common_objects.h"
#ifdef __cplusplus
--- a/targets/TARGET_STM/TARGET_STM32L4/gpio_api.c Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
- MBED_ASSERT(pin != (PinName)NC);
-
- pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
- if (pin == (PinName)NC)
- return;
-
- uint32_t port_index = STM_PORT(pin);
-
- // Enable GPIO clock
- uint32_t gpio_add = Set_GPIO_Clock(port_index);
- GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
- // Fill GPIO object structure for future use
- obj->mask = gpio_set(pin);
- obj->reg_in = &gpio->IDR;
- obj->reg_set = &gpio->BSRR;
- obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (direction == PIN_OUTPUT) {
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
- } else { // PIN_INPUT
- pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32L4/gpio_object.h Mon Jan 16 15:03:32 2017 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
- *obj->reg_clr = obj->mask;
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_STM/TARGET_STM32L4/pinmap.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/pinmap.c Thu Feb 02 17:01:33 2017 +0000
@@ -41,14 +41,14 @@
0x00000002, // 3 = GPIO_MODE_AF_PP
0x00000012, // 4 = GPIO_MODE_AF_OD
0x00000003, // 5 = GPIO_MODE_ANALOG
- 0x0000000B, // 6 = GPIO_MODE_ANALOG_ADC_CONTROL
- 0x10110000, // 7 = GPIO_MODE_IT_RISING
- 0x10210000, // 8 = GPIO_MODE_IT_FALLING
- 0x10310000, // 9 = GPIO_MODE_IT_RISING_FALLING
- 0x10120000, // 10 = GPIO_MODE_EVT_RISING
- 0x10220000, // 11 = GPIO_MODE_EVT_FALLING
- 0x10320000, // 12 = GPIO_MODE_EVT_RISING_FALLING
- 0x10000000 // 13 = Reset IT and EVT (not in STM32Cube HAL)
+ 0x10110000, // 6 = GPIO_MODE_IT_RISING
+ 0x10210000, // 7 = GPIO_MODE_IT_FALLING
+ 0x10310000, // 8 = GPIO_MODE_IT_RISING_FALLING
+ 0x10120000, // 9 = GPIO_MODE_EVT_RISING
+ 0x10220000, // 10 = GPIO_MODE_EVT_FALLING
+ 0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
+ 0x10000000, // 12 = Reset IT and EVT (not in STM32Cube HAL)
+ 0x0000000B //13 = GPIO_MODE_ANALOG_ADC_CONTROL
};
// Enable GPIO clock and return GPIO base address
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/gpio_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin) {
+ MBED_ASSERT(pin != (PinName)NC);
+
+ pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+ return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+ obj->pin = pin;
+ if (pin == (PinName)NC) {
+ return;
+ }
+
+ uint32_t port_index = STM_PORT(pin);
+
+ // Enable GPIO clock
+ uint32_t gpio_add = Set_GPIO_Clock(port_index);
+ GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+ // Fill GPIO object structure for future use
+ obj->mask = gpio_set(pin);
+ obj->reg_in = &gpio->IDR;
+ obj->reg_set = &gpio->BSRR;
+#ifdef GPIO_IP_WITHOUT_BRR
+ obj->reg_clr = &gpio->BSRR;
+#else
+ obj->reg_clr = &gpio->BRR;
+#endif
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (direction == PIN_OUTPUT) {
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+ } else { // PIN_INPUT
+ pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/gpio_object.h Thu Feb 02 17:01:33 2017 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Note: reg_clr might actually be same as reg_set.
+ * Depends on family whether BRR is available on top of BSRR
+ * if BRR does not exist, family shall define GPIO_DOES_NOT_HAVE_BRR
+ */
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+ __IO uint32_t *reg_in;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ if (value) {
+ *obj->reg_set = obj->mask;
+ } else {
+#ifdef GPIO_IP_WITHOUT_BRR
+ *obj->reg_clr = obj->mask << 16;
+#else
+ *obj->reg_clr = obj->mask;
+#endif
+ }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+ MBED_ASSERT(obj->pin != (PinName)NC);
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+ return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/targets/TARGET_STM/i2c_api.c Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_STM/i2c_api.c Thu Feb 02 17:01:33 2017 +0000
@@ -627,10 +627,9 @@
}
}
- /* Enable reload mode as we don't know how many bytes will eb sent */
- handle->Instance->CR2 |= I2C_CR2_RELOAD;
- /* Set transfer size to 1 */
- handle->Instance->CR2 |= (I2C_CR2_NBYTES & (1 << 16));
+ /* Enable reload mode as we don't know how many bytes will be sent */
+ /* and set transfer size to 1 */
+ tmpreg |= I2C_CR2_RELOAD | (I2C_CR2_NBYTES & (1 << 16));
/* Set the prepared configuration */
handle->Instance->CR2 = tmpreg;
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/TARGET_1024K/TOOLCHAIN_GCC_ARM/efm32gg.ld Thu Feb 02 17:01:33 2017 +0000
@@ -56,13 +56,12 @@
*/
ENTRY(Reset_Handler)
-/* Note: The uVisor expects the text section at a fixed location, as specified
- by the porting process configuration parameter: FLASH_OFFSET. */
-__UVISOR_TEXT_OFFSET = 0x100;
-__UVISOR_TEXT_START = ORIGIN(FLASH) + __UVISOR_TEXT_OFFSET;
-
SECTIONS
{
+ /* Note: The uVisor expects the text section at a fixed location, as specified
+ by the porting process configuration parameter: FLASH_OFFSET. */
+ __UVISOR_FLASH_OFFSET = 0x100;
+ __UVISOR_FLASH_START = ORIGIN(FLASH) + __UVISOR_FLASH_OFFSET;
.text :
{
KEEP(*(.vectors))
@@ -71,7 +70,7 @@
__end__ = .;
/* uVisor code and data */
- . = __UVISOR_TEXT_OFFSET;
+ . = __UVISOR_FLASH_OFFSET;
. = ALIGN(4);
__uvisor_main_start = .;
*(.uvisor.main)
@@ -147,24 +146,26 @@
} > FLASH
*/
- /* Ensure that the uVisor BSS section is put first in SRAM. */
+ /* uVisor own memory and private box memories
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the VTOR relocation section. */
/* Note: The uVisor expects this section at a fixed location, as specified
by the porting process configuration parameter: SRAM_OFFSET. */
__UVISOR_SRAM_OFFSET = 0x0;
- __UVISOR_BSS_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
- .uvisor.bss __UVISOR_BSS_START (NOLOAD):
+ __UVISOR_SRAM_START = ORIGIN(RAM) + __UVISOR_SRAM_OFFSET;
+ .uvisor.bss __UVISOR_SRAM_START (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;
- /* uVisor main BSS section */
+ /* Protected uVisor own BSS section */
. = ALIGN(32);
__uvisor_bss_main_start = .;
KEEP(*(.keep.uvisor.bss.main))
. = ALIGN(32);
__uvisor_bss_main_end = .;
- /* Secure boxes BSS section */
+ /* Protected uVisor boxes' static memories */
. = ALIGN(32);
__uvisor_bss_boxes_start = .;
KEEP(*(.keep.uvisor.bss.boxes))
@@ -175,15 +176,16 @@
__uvisor_bss_end = .;
} > RAM
- /* Heap space for the page allocator */
+ /* Heap space for the page allocator
+ /* If uVisor shares the SRAM with the OS/app, ensure that this section is
+ * the first one after the uVisor BSS section. Otherwise, ensure it is the
+ * first one after the VTOR relocation section. */
.page_heap (NOLOAD) :
{
. = ALIGN(32);
__uvisor_page_start = .;
KEEP(*(.keep.uvisor.page_heap))
-
. = ALIGN( (1 << LOG2CEIL(LENGTH(RAM))) / 8);
-
__uvisor_page_end = .;
} > RAM
@@ -284,10 +286,6 @@
__bss_end__ = .;
} > RAM
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __stack = __StackTop;
- __StackLimit = __StackTop - STACK_SIZE;
-
.heap (NOLOAD):
{
__uvisor_heap_start = .;
@@ -296,17 +294,21 @@
end = __end__;
_end = __end__;
. += HEAP_SIZE;
+ __HeapLimit = .;
+ __uvisor_heap_end = .;
} > RAM
- __HeapLimit = __StackLimit;
- __uvisor_heap_end = __StackLimit;
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __stack = __StackTop;
+ __StackLimit = __StackTop - STACK_SIZE;
+
+ ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
/* Provide physical memory boundaries for uVisor. */
__uvisor_flash_start = ORIGIN(FLASH);
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
__uvisor_sram_start = ORIGIN(RAM);
__uvisor_sram_end = ORIGIN(RAM) + LENGTH(RAM);
-
- /* Check if FLASH usage exceeds FLASH size. */
- ASSERT(LENGTH(FLASH) >= __uvisor_secure_end, "FLASH memory overflowed!")
+ __uvisor_public_sram_start = __uvisor_sram_start;
+ __uvisor_public_sram_end = __uvisor_sram_end;
}
--- a/targets/targets.json Mon Jan 16 15:03:32 2017 +0000
+++ b/targets/targets.json Thu Feb 02 17:01:33 2017 +0000
@@ -336,7 +336,7 @@
"default_lib": "small",
"release_versions": ["2"]
},
- "LPC4088": {
+ "MCU_LPC4088": {
"inherits": ["LPCTarget"],
"core": "Cortex-M4F",
"extra_labels": ["NXP", "LPC408X"],
@@ -346,11 +346,14 @@
"function": "LPC4088Code.binary_hook"
},
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
- "release_versions": ["2", "5"],
"device_name": "LPC4088FBD144"
},
+ "LPC4088": {
+ "inherits": ["MCU_LPC4088"],
+ "release_versions": ["2", "5"]
+ },
"LPC4088_DM": {
- "inherits": ["LPC4088"],
+ "inherits": ["MCU_LPC4088"],
"release_versions": ["2", "5"]
},
"LPC4330_M4": {
@@ -490,7 +493,7 @@
"macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"detect_code": ["0231"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
"device_name": "MK22DN512xxx5"
},
"K22F": {
@@ -1216,13 +1219,14 @@
"inherits": ["Target"],
"core": "Cortex-M7FD",
"extra_labels": ["STM", "STM32F7", "STM32F769", "STM32F769NI"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+ "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"default_toolchain": "ARM",
+ "supported_form_factors": ["ARDUINO"],
"detect_code": ["0817"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
- "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
+ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
"features": ["LWIP"],
- "release_versions": ["2"],
+ "release_versions": ["2", "5"],
"device_name": "STM32F769NI"
},
"DISCO_L476VG": {
@@ -1268,7 +1272,7 @@
"core": "Cortex-M4F",
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"extra_labels": ["STM", "STM32F4", "STM32F411RE"],
- "macros": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000","TRANSACTION_QUEUE_SIZE_SPI=2"],
+ "macros": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000","TRANSACTION_QUEUE_SIZE_SPI=2", "RTC_LSI=1"],
"post_binary_hook": {
"function": "MTSCode.combine_bins_mts_dragonfly",
"toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO"]
@@ -1625,6 +1629,24 @@
"extra_labels_add": ["DELTA_DFCM_NNN40"],
"macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
},
+ "DELTA_DFCM_NNN50": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_name": "nRF51822_xxAC"
+ },
+ "DELTA_DFCM_NNN50_BOOT": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_BOOT"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
+ "DELTA_DFCM_NNN50_OTA": {
+ "supported_form_factors": ["ARDUINO"],
+ "inherits": ["MCU_NRF51_32K_OTA"],
+ "extra_labels_add": ["DELTA_DFCM_NNN50"],
+ "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
+ },
"NRF51_DK_LEGACY": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF51_32K"],
@@ -1879,6 +1901,15 @@
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
"release_versions": ["2", "5"]
},
+ "MAX32630FTHR": {
+ "inherits": ["Target"],
+ "core": "Cortex-M4F",
+ "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132"],
+ "extra_labels": ["Maxim", "MAX32630"],
+ "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
+ "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
+ "release_versions": ["2", "5"]
+ },
"EFM32": {
"inherits": ["Target"],
"extra_labels": ["Silicon_Labs", "EFM32"],
@@ -2494,7 +2525,7 @@
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"],
- "overrides": {"uart_hwfc": 0},
+ "overrides": {"uart_hwfc": 0},
"device_name": "nRF52832_xxAA"
},
"UBLOX_EVK_NINA_B1": {