spi_ram.cpp

00001 #include "spi_ram.h"
00002 
00003 SRAM::SRAM(SPI& spiDef, PinName csiPin) : spi(spiDef), csi(csiPin)  {
00004     deselect();
00005 }
00006 
00007 void SRAM::select() {
00008     csi = 0;
00009 }
00010 
00011 void SRAM::deselect() {
00012     csi = 1;
00013 }
00014 
00015 void SRAM::writeStatus(char status) {
00016     select();
00017     spi.write(WRITE_STATUS);
00018     spi.write(status);
00019     deselect();
00020 }
00021  
00022 char SRAM::readStatus() {
00023     select();
00024     spi.write(READ_STATUS);
00025     char result = (char)spi.write(0);
00026     deselect();
00027     return result;
00028 }
00029  
00030 void SRAM::prepareCommand(char command, int address) {
00031     select();
00032     spi.write(command);
00033     spi.write(address >> 16);
00034     spi.write((address >> 8) & 0xFF);
00035     spi.write(address & 0xFF);
00036 }
00037 
00038 void SRAM::startWriteSequence() {
00039     select();
00040     writeStatus(SEQUENTIAL_MODE);
00041     prepareCommand(WRITE, 0);
00042 }
00043 
00044 void SRAM::writeSequence0(char c) {
00045     while (!(LPC_SSP0->SR & TNF));       // While TNF-Bit = 0, wait for FIFO
00046     LPC_SSP0->DR = c;                // Write to FIFO buffer
00047     while( !(LPC_SSP0->SR & RNE));
00048     uint8_t v = LPC_SSP0->DR;
00049 }
00050 
00051 void SRAM::writeSequence1(char c) {
00052     while (!(LPC_SSP1->SR & TNF));       // While TNF-Bit = 0, wait for FIFO
00053     LPC_SSP1->DR = c;                // Write to FIFO buffer
00054     while( !(LPC_SSP1->SR & RNE));
00055     uint8_t v = LPC_SSP1->DR;
00056 }
00057 
00058 void SRAM::startReadSequence() {
00059     select();
00060     writeStatus(SEQUENTIAL_MODE);
00061     prepareCommand(READ, 0);
00062 }
00063 
00064 char SRAM::readSequence0() {
00065     while (!(LPC_SSP0->SR & TNF));       // While TNF-Bit = 0, wait for FIFO
00066     LPC_SSP0->DR = 0;                // Write to FIFO buffer
00067     while( !(LPC_SSP0->SR & RNE));
00068     return LPC_SSP0->DR;
00069 }
00070 
00071 char SRAM::readSequence1() {
00072     while (!(LPC_SSP1->SR & TNF));       // While TNF-Bit = 0, wait for FIFO
00073     LPC_SSP1->DR = 0;                // Write to FIFO buffer
00074     while( !(LPC_SSP1->SR & RNE));
00075     return LPC_SSP1->DR;
00076 }
00077 
00078 void SRAM::stopSequence() {
00079     deselect();
00080     writeStatus(BYTE_MODE);
00081 }