seeed_can_defs.h

00001 /* seeed_can_defs.h
00002  * Copyright (c) 2013 Sophie Dexter
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 #ifndef SEEED_CAN_DEFS_H
00017 #define SEEED_CAN_DEFS_H
00018 
00019 #include "mbed.h"
00020 
00021 #ifdef __cplusplus
00022 extern "C" {
00023 #endif
00024 
00025     /** FRDM-KL25Z port pins used by Seeed Studios CAN-BUS Shield
00026      */
00027 #define SEEED_CAN_CS        PTD0
00028 #define SEEED_CAN_CLK       PTD1
00029 #define SEEED_CAN_MOSI      PTD2
00030 #define SEEED_CAN_MISO      PTD3
00031 #define SEEED_CAN_IRQ       PTD4
00032 #define SEEED_CAN_IO9       PTD5
00033     /** Define MCP2515 register addresses
00034      */
00035 #define MCP_RXF0SIDH        0x00
00036 #define MCP_RXF0SIDL        0x01
00037 #define MCP_RXF0EID8        0x02
00038 #define MCP_RXF0EID0        0x03
00039 #define MCP_RXF1SIDH        0x04
00040 #define MCP_RXF1SIDL        0x05
00041 #define MCP_RXF1EID8        0x06
00042 #define MCP_RXF1EID0        0x07
00043 #define MCP_RXF2SIDH        0x08
00044 #define MCP_RXF2SIDL        0x09
00045 #define MCP_RXF2EID8        0x0A
00046 #define MCP_RXF2EID0        0x0B
00047 #define MCP_CANSTAT         0x0E
00048 #define MCP_CANCTRL         0x0F
00049 #define MCP_RXF3SIDH        0x10
00050 #define MCP_RXF3SIDL        0x11
00051 #define MCP_RXF3EID8        0x12
00052 #define MCP_RXF3EID0        0x13
00053 #define MCP_RXF4SIDH        0x14
00054 #define MCP_RXF4SIDL        0x15
00055 #define MCP_RXF4EID8        0x16
00056 #define MCP_RXF4EID0        0x17
00057 #define MCP_RXF5SIDH        0x18
00058 #define MCP_RXF5SIDL        0x19
00059 #define MCP_RXF5EID8        0x1A
00060 #define MCP_RXF5EID0        0x1B
00061 #define MCP_TEC             0x1C
00062 #define MCP_REC             0x1D
00063 #define MCP_RXM0SIDH        0x20
00064 #define MCP_RXM0SIDL        0x21
00065 #define MCP_RXM0EID8        0x22
00066 #define MCP_RXM0EID0        0x23
00067 #define MCP_RXM1SIDH        0x24
00068 #define MCP_RXM1SIDL        0x25
00069 #define MCP_RXM1EID8        0x26
00070 #define MCP_RXM1EID0        0x27
00071 #define MCP_CNF3            0x28
00072 #define MCP_CNF2            0x29
00073 #define MCP_CNF1            0x2A
00074 #define MCP_CANINTE         0x2B
00075 #define MCP_CANINTF         0x2C
00076 #define MCP_EFLG            0x2D
00077 #define MCP_TXB0CTRL        0x30
00078 #define MCP_TXB1CTRL        0x40
00079 #define MCP_TXB2CTRL        0x50
00080 #define MCP_RXB0CTRL        0x60
00081 #define MCP_RXB0SIDH        0x61
00082 #define MCP_RXB1CTRL        0x70
00083 #define MCP_RXB1SIDH        0x71
00084     /** Define MCP2515 SPI Instructions
00085      */
00086 #define MCP_WRITE           0x02
00087 
00088 #define MCP_READ            0x03
00089 
00090 #define MCP_BITMOD          0x05
00091 
00092 #define MCP_WRITE_TX0       0x40
00093 #define MCP_WRITE_TX1       0x42
00094 #define MCP_WRITE_TX2       0x44
00095 
00096 #define MCP_RTS_TX0         0x81
00097 #define MCP_RTS_TX1         0x82
00098 #define MCP_RTS_TX2         0x84
00099 #define MCP_RTS_ALL         0x87
00100 
00101 #define MCP_READ_RX0        0x90
00102 #define MCP_READ_RX1        0x94
00103 
00104 #define MCP_READ_STATUS     0xA0
00105 
00106 #define MCP_RX_STATUS       0xB0
00107 
00108 #define MCP_RESET           0xC0
00109 
00110 //#define TIMEOUTVALUE        50
00111 //#define MCP_SIDH            0
00112 //#define MCP_SIDL            1
00113 //#define MCP_EID8            2
00114 //#define MCP_EID0            3
00115 
00116 #define MCP_TXB_EXIDE_M     0x08                                        /* In TXBnSIDL                  */
00117 #define MCP_DLC_MASK        0x0F                                        /* 4 LSBits                     */
00118 #define MCP_RTR_MASK        0x40                                        /* (1<<6) Bit 6                 */
00119 
00120 #define MCP_RXB_RX_ANY      0x60
00121 #define MCP_RXB_RX_EXT      0x40
00122 #define MCP_RXB_RX_STD      0x20
00123 #define MCP_RXB_RX_STDEXT   0x00
00124 #define MCP_RXB_RX_MASK     0x60
00125 #define MCP_RXB_BUKT_MASK   (1<<2)
00126     /** Bits in the TXBnCTRL registers.
00127      */
00128 #define MCP_TXB_TXBUFE_M    0x80
00129 #define MCP_TXB_ABTF_M      0x40
00130 #define MCP_TXB_MLOA_M      0x20
00131 #define MCP_TXB_TXERR_M     0x10
00132 #define MCP_TXB_TXREQ_M     0x08
00133 #define MCP_TXB_TXIE_M      0x04
00134 #define MCP_TXB_TXP10_M     0x03
00135 
00136 #define MCP_TXB_RTR_M       0x40                                        /* In TXBnDLC                   */
00137 #define MCP_RXB_IDE_M       0x08                                        /* In RXBnSIDL                  */
00138 #define MCP_RXB_RTR_M       0x40                                        /* In RXBnDLC                   */
00139 
00140     /** STATUS Command Values
00141      */
00142 #define MCP_STAT_RXIF_MASK  (0x03)
00143 #define MCP_STAT_RX0IF      (1<<0)
00144 #define MCP_STAT_RX1IF      (1<<1)
00145 #define MCP_STAT_TX0REQ     (1<<2)
00146 #define MCP_STAT_TX0IF      (1<<3)
00147 #define MCP_STAT_TX1REQ     (1<<4)
00148 #define MCP_STAT_TX1IF      (1<<5)
00149 #define MCP_STAT_TX2REQ     (1<<6)
00150 #define MCP_STAT_TX2IF      (1<<7)
00151 
00152     /** RX STATUS Command Values
00153      */
00154 #define MCP_RXSTAT_RXF_MASK (7<<0)
00155 #define MCP_RXSTAT_RXF0     (0<<0)
00156 #define MCP_RXSTAT_RXF1     (1<<0)
00157 #define MCP_RXSTAT_RXF2     (2<<0)
00158 #define MCP_RXSTAT_RXF3     (3<<0)
00159 #define MCP_RXSTAT_RXF4     (4<<0)
00160 #define MCP_RXSTAT_RXF5     (5<<0)
00161 #define MCP_RXSTAT_RXROF0   (6<<0)                                      // RXF0 rollover to RXB1
00162 #define MCP_RXSTAT_RXROF1   (7<<0)                                      // RXF1 rollover to RXB1
00163 #define MCP_RXSTAT_RTR      (1<<3)
00164 #define MCP_RXSTAT_IDE      (1<<4)
00165 #define MCP_RXSTAT_RXB_MASK (3<<6)
00166 #define MCP_RXSTAT_NONE     (0<<6)
00167 #define MCP_RXSTAT_RXB0     (1<<6)
00168 #define MCP_RXSTAT_RXB1     (2<<6)
00169 #define MCP_RXSTAT_BOTH     (3<<6)
00170 
00171     /** EFLG Register Values
00172      */
00173 #define MCP_EFLG_ALLMASK    (0xFF)                                      // All Bits
00174 #define MCP_EFLG_ERRORMASK  (0xF8)                                      // 5 MS-Bits
00175 #define MCP_EFLG_WARNMASK   (0x07)                                      // 3 LS-Bits
00176 #define MCP_EFLG_EWARN      (1<<0)
00177 #define MCP_EFLG_RXWAR      (1<<1)
00178 #define MCP_EFLG_TXWAR      (1<<2)
00179 #define MCP_EFLG_RXEP       (1<<3)
00180 #define MCP_EFLG_TXEP       (1<<4)
00181 #define MCP_EFLG_TXBO       (1<<5)
00182 #define MCP_EFLG_RX0OVR     (1<<6)
00183 #define MCP_EFLG_RX1OVR     (1<<7)
00184 
00185     /** CANCTRL Register Values
00186      */
00187 #define CLKOUT_PS1          (0<<0)
00188 #define CLKOUT_PS2          (1<<0)
00189 #define CLKOUT_PS4          (2<<0)
00190 #define CLKOUT_PS8          (3<<0)
00191 #define CLKOUT_ENABLE       (1<<2)
00192 #define CLKOUT_DISABLE      (0<<2)
00193 #define MODE_ONESHOT        (1<<3)
00194 #define ABORT_TX            (1<<4)
00195 #define MODE_NORMAL         (0<<5)
00196 #define MODE_SLEEP          (1<<5)
00197 #define MODE_LOOPBACK       (2<<5)
00198 #define MODE_LISTENONLY     (3<<5)
00199 #define MODE_CONFIG         (4<<5)
00200 #define MODE_POWERUP        (7<<5)
00201 #define MODE_MASK           (7<<5)
00202 
00203     /** Bit Rate timing
00204      */
00205 #define MCP_CLOCK_FREQ          16000000                                // 16 MHz Crystal frequency
00206 #define CAN_SYNCSEG             1                                       // CAN-BUS Sync segment is always 1 Time Quantum
00207 #define CAN_MAX_RATE            MCP_CLOCK_FREQ/(2 * MCP_MIN_TIME_QUANTA)
00208 #define CAN_MIN_RATE            MCP_CLOCK_FREQ/(2 * MCP_MAX_PRESCALER * MCP_MAX_TIME_QUANTA)
00209 #define MCP_MAX_TIME_QUANTA     25
00210 #define MCP_MIN_TIME_QUANTA     8
00211 #define MCP_MAX_PRESCALER       64
00212 #define MCP_MIN_PRESCALER       1
00213     /** CNF1 Register Values
00214      */
00215 #define SJW1                (0<<6)
00216 #define SJW2                (1<<6)
00217 #define SJW3                (2<<6)
00218 #define SJW4                (3<<6)
00219     /** CNF2 Register Values
00220      */
00221 #define BTLMODE             (1<<7)
00222 #define SAMPLE_1X           (0<<4)
00223 #define SAMPLE_3X           (1<<4)
00224     /** CNF3 Register Values
00225      */
00226 #define WAKFIL_ENABLE       (1<<4)
00227 #define WAKFIL_DISABLE      (0<<4)
00228 #define SOF_ENABLE          (1<<7)
00229 #define SOF_DISABLE         (0<<7)
00230     /** CANINTF Register Bits
00231      */
00232 #define MCP_NO_INTS         (0x00)                                      // Disable all interrupts
00233 #define MCP_ALL_INTS        (0xFF)                                      // All Bits
00234 #define MCP_RX_INTS         (MCP_RX1IF | MCP_RX0IF)                     // Enable all receive interrupts
00235 #define MCP_TX_INTS         (MCP_TX2IF | MCP_TX1IF | MCP_TX0IF)         // Enable all transmit interrupts
00236 #define MCP_RX0IF           (1<<0)
00237 #define MCP_RX1IF           (1<<1)
00238 #define MCP_TX0IF           (1<<2)
00239 #define MCP_TX1IF           (1<<3)
00240 #define MCP_TX2IF           (1<<4)
00241 #define MCP_ERRIF           (1<<5)
00242 #define MCP_WAKIF           (1<<6)
00243 #define MCP_MERRF           (1<<7)
00244 
00245 //#define MCP_RXBUF_0         (MCP_RXB0SIDH)
00246 //#define MCP_RXBUF_1         (MCP_RXB1SIDH)
00247 
00248 #ifdef __cplusplus
00249 };
00250 #endif
00251 
00252 #endif    // SEEED_CAN_DEFS_H
00253 /*********************************************************************************************************
00254   END FILE
00255 *********************************************************************************************************/