ICM_20948_ENUMERATIONS.h

00001 /*
00002 
00003 This file contains a useful c translation of the datasheet register map values
00004 
00005 */
00006 
00007 #ifndef _ICM_20948_ENUMERATIONS_H_
00008 #define _ICM_20948_ENUMERATIONS_H_
00009 
00010 #ifdef __cplusplus
00011 extern "C"
00012 {
00013 #endif /* __cplusplus */
00014 
00015   // // Generalized
00016   // REG_BANK_SEL = 0x7F,
00017 
00018   // // Gyroscope and Accelerometer
00019   // // User Bank 0
00020   // AGB0_REG_WHO_AM_I = 0x00,
00021   //    // Break
00022   // AGB0_REG_USER_CTRL = 0x03,
00023   //    // Break
00024   // AGB0_REG_LP_CONFIG = 0x05,
00025 
00026   typedef enum
00027   {
00028     ICM_20948_Sample_Mode_Continuous = 0x00,
00029     ICM_20948_Sample_Mode_Cycled,
00030   } ICM_20948_LP_CONFIG_CYCLE_e;
00031 
00032   // AGB0_REG_PWR_MGMT_1,
00033 
00034   typedef enum
00035   {
00036     ICM_20948_Clock_Internal_20MHz = 0x00,
00037     ICM_20948_Clock_Auto,
00038     ICM_20948_Clock_TimingReset = 0x07
00039   } ICM_20948_PWR_MGMT_1_CLKSEL_e;
00040 
00041   // AGB0_REG_PWR_MGMT_2,
00042   //    // Break
00043   // AGB0_REG_INT_PIN_CONFIG = 0x0F,
00044   // AGB0_REG_INT_ENABLE,
00045   // AGB0_REG_INT_ENABLE_1,
00046   // AGB0_REG_INT_ENABLE_2,
00047   // AGB0_REG_INT_ENABLE_3,
00048   //    // Break
00049   // AGB0_REG_I2C_MST_STATUS = 0x17,
00050   //    // Break
00051   // AGB0_REG_INT_STATUS = 0x19,
00052   // AGB0_REG_INT_STATUS_1,
00053   // AGB0_REG_INT_STATUS_2,
00054   // AGB0_REG_INT_STATUS_3,
00055   //    // Break
00056   // AGB0_REG_DELAY_TIMEH = 0x28,
00057   // AGB0_REG_DELAY_TIMEL,
00058   //    // Break
00059   // AGB0_REG_ACCEL_XOUT_H = 0x2D,
00060   // AGB0_REG_ACCEL_XOUT_L,
00061   // AGB0_REG_ACCEL_YOUT_H,
00062   // AGB0_REG_ACCEL_YOUT_L,
00063   // AGB0_REG_ACCEL_ZOUT_H,
00064   // AGB0_REG_ACCEL_ZOUT_L,
00065   // AGB0_REG_GYRO_XOUT_H,
00066   // AGB0_REG_GYRO_XOUT_L,
00067   // AGB0_REG_GYRO_YOUT_H,
00068   // AGB0_REG_GYRO_YOUT_L,
00069   // AGB0_REG_GYRO_ZOUT_H,
00070   // AGB0_REG_GYRO_ZOUT_L,
00071   // AGB0_REG_TEMP_OUT_H,
00072   // AGB0_REG_TEMP_OUT_L,
00073   // AGB0_REG_EXT_PERIPH_SENS_DATA_00,
00074   // AGB0_REG_EXT_PERIPH_SENS_DATA_01,
00075   // AGB0_REG_EXT_PERIPH_SENS_DATA_02,
00076   // AGB0_REG_EXT_PERIPH_SENS_DATA_03,
00077   // AGB0_REG_EXT_PERIPH_SENS_DATA_04,
00078   // AGB0_REG_EXT_PERIPH_SENS_DATA_05,
00079   // AGB0_REG_EXT_PERIPH_SENS_DATA_06,
00080   // AGB0_REG_EXT_PERIPH_SENS_DATA_07,
00081   // AGB0_REG_EXT_PERIPH_SENS_DATA_08,
00082   // AGB0_REG_EXT_PERIPH_SENS_DATA_09,
00083   // AGB0_REG_EXT_PERIPH_SENS_DATA_10,
00084   // AGB0_REG_EXT_PERIPH_SENS_DATA_11,
00085   // AGB0_REG_EXT_PERIPH_SENS_DATA_12,
00086   // AGB0_REG_EXT_PERIPH_SENS_DATA_13,
00087   // AGB0_REG_EXT_PERIPH_SENS_DATA_14,
00088   // AGB0_REG_EXT_PERIPH_SENS_DATA_15,
00089   // AGB0_REG_EXT_PERIPH_SENS_DATA_16,
00090   // AGB0_REG_EXT_PERIPH_SENS_DATA_17,
00091   // AGB0_REG_EXT_PERIPH_SENS_DATA_18,
00092   // AGB0_REG_EXT_PERIPH_SENS_DATA_19,
00093   // AGB0_REG_EXT_PERIPH_SENS_DATA_20,
00094   // AGB0_REG_EXT_PERIPH_SENS_DATA_21,
00095   // AGB0_REG_EXT_PERIPH_SENS_DATA_22,
00096   // AGB0_REG_EXT_PERIPH_SENS_DATA_23,
00097   //    // Break
00098   // AGB0_REG_FIFO_EN_1 = 0x66,
00099   // AGB0_REG_FIFO_EN_2,
00100   // AGB0_REG_FIFO_MODE,
00101   //    // Break
00102   // AGB0_REG_FIFO_COUNT_H = 0x70,
00103   // AGB0_REG_FIFO_COUNT_L,
00104   // AGB0_REG_FIFO_R_W,
00105   //    // Break
00106   // AGB0_REG_DATA_RDY_STATUS = 0x74,
00107   //    // Break
00108   // AGB0_REG_FIFO_CFG = 0x76,
00109   //    // Break
00110   // AGB0_REG_MEM_START_ADDR    = 0x7C,     // Hmm, Invensense thought they were sneaky not listing these locations on the datasheet...
00111   // AGB0_REG_MEM_R_W           = 0x7D,     // These three locations seem to be able to access some memory within the device
00112   // AGB0_REG_MEM_BANK_SEL      = 0x7E,     // And that location is also where the DMP image gets loaded
00113   // AGB0_REG_REG_BANK_SEL = 0x7F,
00114 
00115   // // Bank 1
00116   // AGB1_REG_SELF_TEST_X_GYRO = 0x02,
00117   // AGB1_REG_SELF_TEST_Y_GYRO,
00118   // AGB1_REG_SELF_TEST_Z_GYRO,
00119   //    // Break
00120   // AGB1_REG_SELF_TEST_X_ACCEL = 0x0E,
00121   // AGB1_REG_SELF_TEST_Y_ACCEL,
00122   // AGB1_REG_SELF_TEST_Z_ACCEL,
00123   //    // Break
00124   // AGB1_REG_XA_OFFS_H = 0x14,
00125   // AGB1_REG_XA_OFFS_L,
00126   //    // Break
00127   // AGB1_REG_YA_OFFS_H = 0x17,
00128   // AGB1_REG_YA_OFFS_L,
00129   //    // Break
00130   // AGB1_REG_ZA_OFFS_H = 0x1A,
00131   // AGB1_REG_ZA_OFFS_L,
00132   //    // Break
00133   // AGB1_REG_TIMEBASE_CORRECTION_PLL = 0x28,
00134   //    // Break
00135   // AGB1_REG_REG_BANK_SEL = 0x7F,
00136 
00137   // // Bank 2
00138   // AGB2_REG_GYRO_SMPLRT_DIV = 0x00,
00139 
00140   /*
00141 Gyro sample rate divider. Divides the internal sample rate to generate the sample
00142 rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate.
00143 NOTE: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and
00144 (0 < DLPF_CFG < 7).
00145 ODR is computed as follows:
00146 1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])
00147 */
00148 
00149   // AGB2_REG_GYRO_CONFIG_1,
00150 
00151   typedef enum
00152   { // Full scale range options in degrees per second
00153     dps250 = 0x00,
00154     dps500,
00155     dps1000,
00156     dps2000,
00157   } ICM_20948_GYRO_CONFIG_1_FS_SEL_e;
00158 
00159   typedef enum
00160   { // Format is dAbwB_nXbwY - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
00161     gyr_d196bw6_n229bw8 = 0x00,
00162     gyr_d151bw8_n187bw6,
00163     gyr_d119bw5_n154bw3,
00164     gyr_d51bw2_n73bw3,
00165     gyr_d23bw9_n35bw9,
00166     gyr_d11bw6_n17bw8,
00167     gyr_d5bw7_n8bw9,
00168     gyr_d361bw4_n376bw5,
00169   } ICM_20948_GYRO_CONFIG_1_DLPCFG_e;
00170 
00171   // AGB2_REG_GYRO_CONFIG_2,
00172   // AGB2_REG_XG_OFFS_USRH,
00173   // AGB2_REG_XG_OFFS_USRL,
00174   // AGB2_REG_YG_OFFS_USRH,
00175   // AGB2_REG_YG_OFFS_USRL,
00176   // AGB2_REG_ZG_OFFS_USRH,
00177   // AGB2_REG_ZG_OFFS_USRL,
00178   // AGB2_REG_ODR_ALIGN_EN,
00179   //    // Break
00180   // AGB2_REG_ACCEL_SMPLRT_DIV_1 = 0x10,
00181   // AGB2_REG_ACCEL_SMPLRT_DIV_2,
00182   // AGB2_REG_ACCEL_INTEL_CTRL,
00183   // AGB2_REG_ACCEL_WOM_THR,
00184   // AGB2_REG_ACCEL_CONFIG,
00185 
00186   typedef enum
00187   {
00188     gpm2 = 0x00,
00189     gpm4,
00190     gpm8,
00191     gpm16,
00192   } ICM_20948_ACCEL_CONFIG_FS_SEL_e;
00193 
00194   typedef enum
00195   { // Format is dAbwB_nXbwZ - A is integer part of 3db BW, B is fraction. X is integer part of nyquist bandwidth, Y is fraction
00196     acc_d246bw_n265bw = 0x00,
00197     acc_d246bw_n265bw_1,
00198     acc_d111bw4_n136bw,
00199     acc_d50bw4_n68bw8,
00200     acc_d23bw9_n34bw4,
00201     acc_d11bw5_n17bw,
00202     acc_d5bw7_n8bw3,
00203     acc_d473bw_n499bw,
00204   } ICM_20948_ACCEL_CONFIG_DLPCFG_e;
00205 
00206   // AGB2_REG_ACCEL_CONFIG_2,
00207   //    // Break
00208   // AGB2_REG_FSYNC_CONFIG = 0x52,
00209   // AGB2_REG_TEMP_CONFIG,
00210   // AGB2_REG_MOD_CTRL_USR,
00211   //    // Break
00212   // AGB2_REG_REG_BANK_SEL = 0x7F,
00213 
00214   // // Bank 3
00215   // AGB3_REG_I2C_MST_ODR_CONFIG = 0x00,
00216   // AGB3_REG_I2C_MST_CTRL,
00217   // AGB3_REG_I2C_MST_DELAY_CTRL,
00218   // AGB3_REG_I2C_PERIPH0_ADDR,
00219   // AGB3_REG_I2C_PERIPH0_REG,
00220   // AGB3_REG_I2C_PERIPH0_CTRL,
00221   // AGB3_REG_I2C_PERIPH0_DO,
00222   // AGB3_REG_I2C_PERIPH1_ADDR,
00223   // AGB3_REG_I2C_PERIPH1_REG,
00224   // AGB3_REG_I2C_PERIPH1_CTRL,
00225   // AGB3_REG_I2C_PERIPH1_DO,
00226   // AGB3_REG_I2C_PERIPH2_ADDR,
00227   // AGB3_REG_I2C_PERIPH2_REG,
00228   // AGB3_REG_I2C_PERIPH2_CTRL,
00229   // AGB3_REG_I2C_PERIPH2_DO,
00230   // AGB3_REG_I2C_PERIPH3_ADDR,
00231   // AGB3_REG_I2C_PERIPH3_REG,
00232   // AGB3_REG_I2C_PERIPH3_CTRL,
00233   // AGB3_REG_I2C_PERIPH3_DO,
00234   // AGB3_REG_I2C_PERIPH4_ADDR,
00235   // AGB3_REG_I2C_PERIPH4_REG,
00236   // AGB3_REG_I2C_PERIPH4_CTRL,
00237   // AGB3_REG_I2C_PERIPH4_DO,
00238   // AGB3_REG_I2C_PERIPH4_DI,
00239   //    // Break
00240   // AGB3_REG_REG_BANK_SEL = 0x7F,
00241 
00242   // // Magnetometer
00243   // M_REG_WIA2 = 0x01,
00244   //    // Break
00245   // M_REG_ST1 = 0x10,
00246   // M_REG_HXL,
00247   // M_REG_HXH,
00248   // M_REG_HYL,
00249   // M_REG_HYH,
00250   // M_REG_HZL,
00251   // M_REG_HZH,
00252   // M_REG_ST2,
00253   //    // Break
00254   // M_REG_CNTL2 = 0x31,
00255   // M_REG_CNTL3,
00256   // M_REG_TS1,
00257   // M_REG_TS2,
00258 
00259 #ifdef __cplusplus
00260 }
00261 #endif /* __cplusplus */
00262 
00263 #endif /* _ICM_20948_ENUMERATIONS_H_ */