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beacon.cpp
00001 //switch off the sync!!!!!!! 00002 //switch off the preamble!!!!!!! 00003 /*for crc in tx: 00004 regIrq2(0x28) : 00005 00006 regpacketconfig 1(0x37) : 00007 set crc detection/calc. on : | 0x10 00008 crcautoclearoff : | 0x08 00009 00010 for data whitening : regpacketconfig 1(0x37) :| 0x40 00011 for 00012 00013 00014 00015 */ 00016 // 6CC000 for 435 MHz 00017 //set all values as FF for checking on spectrum analyzer 00018 #include "beacon.h" 00019 #include "HK.h" 00020 Serial chavan(USBTX, USBRX); // tx, rx 00021 SPI spi(PTD6,PTD7,PTD5); // mosi, miso, sclk 00022 DigitalOut cs_bar(D5); //slave select or chip select 00023 //InterruptIn button(p9); 00024 //#define TIMES 16 00025 //Timer t; 00026 00027 /*void interrupt_func() 00028 { 00029 chavan.printf("INTERRUPT_FUNC TRIGGERED\n wait for 3 secs\n"); 00030 wait(3); 00031 00032 }*/ 00033 00034 extern ShortBeacy Shortbeacon; 00035 void writereg(uint8_t reg,uint8_t val) 00036 { 00037 cs_bar = 0; 00038 spi.write(reg | 0x80); 00039 spi.write(val); 00040 cs_bar = 1; 00041 } 00042 uint8_t readreg(uint8_t reg) 00043 { 00044 uint8_t val; 00045 cs_bar = 0; 00046 spi.write(reg & ~0x80); 00047 val = spi.write(0); 00048 cs_bar = 1; 00049 return val; 00050 } 00051 00052 void FUNC_BEA() { 00053 00054 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9) 00055 printf("\nBeacon function entered\n"); 00056 wait(0.02); //takes 10 ms for POR event + 10ms for safety 00057 00058 uint8_t byte_counter = 0; 00059 00060 /*struct Short_beacon{ 00061 uint8_t Voltage[1]; 00062 uint8_t AngularSpeed[2]; 00063 uint8_t SubsystemStatus[1]; 00064 uint8_t Temp[3]; 00065 uint8_t ErrorFlag[1]; 00066 }Shortbeacon = { {0x22}, {0x22, 0x33} , {0x00},{0x00,0x00,0x00}, {0xFE} }; 00067 */ 00068 //filling hk data 00069 //ShortBeacon Shortbeacon; 00070 uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]}; 00071 00072 //mask 00073 //uint8_t mask[] = {0x80, 0x40, 0x20,0x10,0x8,0x4,0x2,0x1}; 00074 00075 for(int i = 0; i < 15 ; i++) 00076 { 00077 chavan.printf("0x%X\n",(short_beacon[i])); 00078 } 00079 00080 spi.format(8,0); 00081 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw) 00082 cs_bar = 1; // Chip must be deselected 00083 00084 //initialization 00085 //Common configuration registers 00086 writereg(0x01,0x04); //sequencer on,standby mode 00087 writereg(0x02,0x08); //packet-mode used , ook modultion , no dc-shaping 00088 writereg(0x03,0x68); //1200bps datarate 00089 writereg(0x04,0x2B); //1200bps datarate 00090 writereg(0x07,0x6C); //Frequency MSB 00091 writereg(0x08,0xC0); //Frequency MID 00092 writereg(0x09,0x00); //Frequency LSB ....6C C0 00 for 435 MHZ 00093 00094 //Transmitter registers 00095 // RegPaLevel(default +13 dBm) 00096 00097 //IRQ and Pin Mapping Registers 00098 //no DIO mapped yet 00099 //regirq1(0x27): modeready (8th bit) will be checked for interrupts 00100 //regIrq2(0x28): fifothresh (5th bit) ,packetsent(3rd bit) will be checked for interrupts 00101 00102 //Packet Engine Registers 00103 writereg(0x2C,0x00); //set preamble 00104 writereg(0x2D,0x0A); //set preamble 00105 writereg(0x2E,0x80); //sync off 00106 writereg(0x2F,0x5E); //sync word 1 00107 writereg(0x37,0x08 | 0x40);// | 0x10); //packetconfig1, 0x40 for data whitening (only for testing) 00108 writereg(0x38,0x00); //payload length = 0 ... unlimited payload mode 00109 writereg(0x3C,0xB0); //fifothresh = 48 because we want it cleared once its 40!!!! 00110 //Initialization complete 00111 00112 //while(chavan.getc() == 't'){ 00113 //t.start(); 00114 //Filling Data into FIFO 64 BYTES : eff.32 bits = 4bytes //fread 00115 cs_bar = 0; 00116 spi.write(0x80);//fifo write access 00117 for(byte_counter=0 ; byte_counter<4; byte_counter++) 00118 { 00119 for(int i=7; i>=0 ; i--) 00120 { 00121 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0) 00122 //if((short_beacon[byte_counter] & mask[i]) != 0) 00123 { 00124 spi.write(0xFF); 00125 spi.write(0xFF); 00126 } 00127 else 00128 { 00129 spi.write(0x00); 00130 spi.write(0x00); 00131 } 00132 } 00133 } 00134 cs_bar = 1; //cs_bar 00135 00136 //Check for fifoThresh 00137 printf("\nfor loop executed\n"); 00138 while((readreg(0x28) & 0x20) != 0x20); 00139 printf("\nwhile loop executed\n"); 00140 //Highpower settings 00141 writereg(0x11,0x7F); //RegPalevel (20db) //~ 00142 writereg(0x13,0x0F); //RegOCP 00143 writereg(0x5A,0x5D); //RegTestPa1 00144 writereg(0x5C,0x7C); //RegTestPa2 00145 00146 //Set to Tx mode 00147 writereg(0x01,0x0C); 00148 00149 printf("\npre 2nd while loop\n"); 00150 //Check for fifoThresh 00151 while((readreg(0x28) & 0x20) != 0x00); 00152 printf("\n2nd while loop executed\n"); 00153 while(byte_counter!=15){ 00154 00155 //writing again 00156 cs_bar = 0; 00157 spi.write(0x80); 00158 for(int i=7; i>=0 ;i--) 00159 { 00160 if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0) 00161 //if((short_beacon[byte_counter] & mask[i]) != 0) 00162 { 00163 spi.write(0xFF); 00164 spi.write(0xFF); 00165 } 00166 else 00167 { 00168 spi.write(0x00); 00169 spi.write(0x00); 00170 } 00171 } 00172 cs_bar = 1; 00173 byte_counter++; 00174 00175 //Check for fifoThresh 00176 while((readreg(0x28) & 0x20) != 0x00); 00177 } 00178 printf("\n3rd big while loop executed\n"); 00179 //wait for packet sent bit to fire 00180 while((readreg(0x28) & 0x08) != 0x08); 00181 printf("\n4th while loop executed\n"); 00182 //chavan.printf("packet sent!!! \n"); 00183 00184 //Switch back to Standby Mode 00185 writereg(0x01,0x04); 00186 00187 //Lowpowermode 00188 writereg(0x11,0x9F); //RegPalevel (13db) 00189 writereg(0x13,0x1A); //RegOCP 00190 writereg(0x5A,0x55); //RegTestPa1(setting PA_BOOST on RFIO) 00191 writereg(0x5C,0x70); //RegTestPa2(setting PA_BOOST on RFIO) 00192 00193 //wait for modeready 00194 while((readreg(0x27)&0x80)!=0x80); 00195 00196 //t.stop(); 00197 //chavan.printf(" time taken to init + transmit = %f \n", t.read()) ; 00198 //} 00199 printf("\nBeacon function exiting\n"); 00200 }
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