Xuyi Wang / SSD1963

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SSD1963.cpp@1:74bac5f988d8, 2020-10-04 (annotated)

Committer:
sPymbed
Date:
Sun Oct 04 13:19:05 2020 +0000
Revision:
1:74bac5f988d8
Parent:
0:94df05e3330d
Child:
2:d8a9ebd28f0a
working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sPymbed 0:94df05e3330d 1 /*****************************************************************************
sPymbed 0:94df05e3330d 2 * Project : 7" TFT LCD 800x480 [AT070TN92]
sPymbed 0:94df05e3330d 3 * Compiler : mbed Online
sPymbed 0:94df05e3330d 4 * Type : Libraries
sPymbed 0:94df05e3330d 5 * Comment : Support mbed ST Nucleo Board.
sPymbed 0:94df05e3330d 6 * : Support Chip = SSD1963
sPymbed 0:94df05e3330d 7 * File : SSD1963.c
sPymbed 0:94df05e3330d 8 *
sPymbed 0:94df05e3330d 9 * Author : Mr.Thongchai Artsamart [Bird Techstep]
sPymbed 0:94df05e3330d 10 * E-Mail : t.artsamart@gmail.com
sPymbed 0:94df05e3330d 11 * : tbird_th@hotmail.com
sPymbed 0:94df05e3330d 12 * Start Date : 20/03/2014 [dd/mm/yyyy]
sPymbed 0:94df05e3330d 13 * Version Date : 20/03/2014 [dd/mm/yyyy]
sPymbed 0:94df05e3330d 14 * Licensed under a Creative Commons Attribution-ShareAlike 3.0 License.
sPymbed 0:94df05e3330d 15 *****************************************************************************
sPymbed 0:94df05e3330d 16 * Remark : Thank you -. no1wudi [CooCox]
sPymbed 0:94df05e3330d 17 * -.
sPymbed 0:94df05e3330d 18 *****************************************************************************/
sPymbed 0:94df05e3330d 19 #include "mbed.h"
sPymbed 0:94df05e3330d 20 #include "SSD1963.h"
sPymbed 0:94df05e3330d 21 //#include "tFontLCD.c"
sPymbed 0:94df05e3330d 22 //#include "stm32f4xx.h"
sPymbed 0:94df05e3330d 23
sPymbed 0:94df05e3330d 24 /*
sPymbed 0:94df05e3330d 25 #define HDP 799 // [ 799][ 799] Horizontal Display Period
sPymbed 0:94df05e3330d 26 #define HT 928 // [ 928][1000] Horizontal Total
sPymbed 0:94df05e3330d 27 #define HPS 46 // [ 46][ 51] LLINE Pulse Start Position
sPymbed 0:94df05e3330d 28 #define LPS 15 // [ 15][ 3] Horizontal Display Period Start Position
sPymbed 0:94df05e3330d 29 #define HPW 48 // [ 48][ 8] LLINE Pulse Width
sPymbed 0:94df05e3330d 30 #define VDP 479 // [ 479][ 479] Vertical Display Period
sPymbed 0:94df05e3330d 31 #define VT 525 // [ 525][ 530] Vertical Total
sPymbed 0:94df05e3330d 32 #define VPS 16 // [ 16][ 24] LFRAME Pulse Start Position
sPymbed 0:94df05e3330d 33 #define FPS 8 // [ 8][ 23] Vertical Display Period Start Position
sPymbed 0:94df05e3330d 34 #define VPW 16 // [ 16][ 3] LFRAME Pulse Width
sPymbed 0:94df05e3330d 35 */
sPymbed 0:94df05e3330d 36
sPymbed 1:74bac5f988d8 37 SSD1963::SSD1963(PinName CS, PinName RESET, PinName RS, PinName WR, BusInOut* DATA_PORT, PinName RD):
sPymbed 1:74bac5f988d8 38 _lcd_pin_cs( CS ), _lcd_pin_rs( RS ), _lcd_pin_reset( RESET ), _lcd_pin_wr( WR ), _lcd_pin_rd(RD)
sPymbed 1:74bac5f988d8 39 {
sPymbed 1:74bac5f988d8 40 begin();
sPymbed 0:94df05e3330d 41 }
sPymbed 0:94df05e3330d 42
sPymbed 1:74bac5f988d8 43 void SSD1963::Activate( void )
sPymbed 1:74bac5f988d8 44 {
sPymbed 1:74bac5f988d8 45 _lcd_pin_cs = LOW;
sPymbed 1:74bac5f988d8 46 }
sPymbed 0:94df05e3330d 47
sPymbed 1:74bac5f988d8 48 inline
sPymbed 1:74bac5f988d8 49 void SSD1963::Deactivate( void )
sPymbed 1:74bac5f988d8 50 {
sPymbed 1:74bac5f988d8 51 _lcd_pin_cs = HIGH;
sPymbed 0:94df05e3330d 52 }
sPymbed 0:94df05e3330d 53
sPymbed 0:94df05e3330d 54 void SSD1963::writeData(uint16_t data) {
sPymbed 1:74bac5f988d8 55 Activate();
sPymbed 1:74bac5f988d8 56 _lcd_pin_rs = HIGH;
sPymbed 1:74bac5f988d8 57 _lcd_pin_wr = LOW;
sPymbed 1:74bac5f988d8 58 _lcd_port->output();
sPymbed 1:74bac5f988d8 59 _lcd_port->write( data );
sPymbed 1:74bac5f988d8 60 wait_us(1);
sPymbed 1:74bac5f988d8 61 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 62 Deactivate();
sPymbed 0:94df05e3330d 63 }
sPymbed 0:94df05e3330d 64
sPymbed 0:94df05e3330d 65 void SSD1963::writeCommand(uint16_t cmd) {
sPymbed 1:74bac5f988d8 66 Activate();
sPymbed 1:74bac5f988d8 67 _lcd_pin_rs = LOW;
sPymbed 1:74bac5f988d8 68 _lcd_pin_wr = LOW;
sPymbed 1:74bac5f988d8 69 _lcd_port->output();
sPymbed 1:74bac5f988d8 70 _lcd_port->write( cmd );
sPymbed 1:74bac5f988d8 71 wait_us(1);
sPymbed 1:74bac5f988d8 72 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 73 _lcd_pin_rs = HIGH;
sPymbed 1:74bac5f988d8 74 Deactivate();
sPymbed 0:94df05e3330d 75 }
sPymbed 0:94df05e3330d 76
sPymbed 0:94df05e3330d 77 uint16_t SSD1963::readData(void) {
sPymbed 0:94df05e3330d 78 uint16_t data = 0x0000;
sPymbed 1:74bac5f988d8 79 Activate();
sPymbed 1:74bac5f988d8 80 _lcd_pin_rs = HIGH; _lcd_pin_rd = LOW;
sPymbed 0:94df05e3330d 81 wait_us(10);
sPymbed 1:74bac5f988d8 82 _lcd_port->input();
sPymbed 1:74bac5f988d8 83 data = _lcd_port->read() & 0xFFFF;
sPymbed 1:74bac5f988d8 84 wait_us(1);
sPymbed 1:74bac5f988d8 85 _lcd_pin_rd = HIGH;
sPymbed 1:74bac5f988d8 86 Deactivate();
sPymbed 0:94df05e3330d 87 return data;
sPymbed 0:94df05e3330d 88 }
sPymbed 0:94df05e3330d 89
sPymbed 0:94df05e3330d 90 void SSD1963::writeRegister(uint16_t addr, uint16_t data) {
sPymbed 0:94df05e3330d 91 writeCommand(addr);
sPymbed 0:94df05e3330d 92 writeData(data);
sPymbed 0:94df05e3330d 93 }
sPymbed 0:94df05e3330d 94
sPymbed 0:94df05e3330d 95 void SSD1963::reset(void) {
sPymbed 1:74bac5f988d8 96 _lcd_pin_reset = HIGH;
sPymbed 1:74bac5f988d8 97 wait_ms( 5 );
sPymbed 1:74bac5f988d8 98 _lcd_pin_reset = LOW;
sPymbed 1:74bac5f988d8 99 wait_ms( 15 );
sPymbed 1:74bac5f988d8 100 _lcd_pin_reset = HIGH;
sPymbed 1:74bac5f988d8 101 _lcd_pin_cs = HIGH;
sPymbed 1:74bac5f988d8 102 _lcd_pin_rd = HIGH;
sPymbed 1:74bac5f988d8 103 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 104 _lcd_pin_rs = HIGH;
sPymbed 0:94df05e3330d 105 }
sPymbed 0:94df05e3330d 106
sPymbed 0:94df05e3330d 107 void SSD1963::begin() {
sPymbed 0:94df05e3330d 108 reset();
sPymbed 0:94df05e3330d 109 wait_ms(10);
sPymbed 0:94df05e3330d 110 // Set PLL MN -------------------------------------------------------------
sPymbed 0:94df05e3330d 111 // @Parameters : 3
sPymbed 0:94df05e3330d 112 writeCommand(0xE2);
sPymbed 1:74bac5f988d8 113 writeData(0x01); // N[7:0] : Multiplier (N) of PLL. (POR = 00101101) b00100011
sPymbed 0:94df05e3330d 114 writeData(0x02); // M[3:0] : Divider (M) of PLL. (POR = 0011)
sPymbed 1:74bac5f988d8 115 writeData(0x54); // C[2] : Effectuate MN value (POR = 100) - Effectuate the multiplier and divider value
sPymbed 0:94df05e3330d 116
sPymbed 0:94df05e3330d 117 // Set PLL
sPymbed 0:94df05e3330d 118 // @Parameters : 1
sPymbed 0:94df05e3330d 119 writeCommand(0xE0);
sPymbed 0:94df05e3330d 120 writeData(0x01); // Use reference clock as system clock & Enable PLL
sPymbed 0:94df05e3330d 121 wait_us(100); // Wait 100us to let the PLL stable
sPymbed 0:94df05e3330d 122 writeCommand(0xE0); // Set PLL
sPymbed 0:94df05e3330d 123 writeData(0x03); // Use PLL output as system clock & Enable PLL
sPymbed 0:94df05e3330d 124 wait_us(100);
sPymbed 0:94df05e3330d 125
sPymbed 0:94df05e3330d 126 // Software Reset ---------------------------------------------------------
sPymbed 0:94df05e3330d 127 writeCommand(0x01);
sPymbed 0:94df05e3330d 128 wait_us(100);
sPymbed 0:94df05e3330d 129
sPymbed 0:94df05e3330d 130 // Set LSHIFT Frequency ---------------------------------------------------
sPymbed 0:94df05e3330d 131 // @Parameters : 3
sPymbed 0:94df05e3330d 132 writeCommand(0xE6); // Set LSHIFT Frequency
sPymbed 0:94df05e3330d 133 writeData(0x03); // LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings
sPymbed 0:94df05e3330d 134 writeData(0xFF); // LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings
sPymbed 0:94df05e3330d 135 writeData(0xFF); // LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings
sPymbed 0:94df05e3330d 136
sPymbed 0:94df05e3330d 137 // Set LCD Mode
sPymbed 0:94df05e3330d 138 // @Parameters : 7
sPymbed 0:94df05e3330d 139 writeCommand(0xB0);
sPymbed 0:94df05e3330d 140 /*
sPymbed 0:94df05e3330d 141 writeData(0x00); // A[5..0] TFT
sPymbed 0:94df05e3330d 142 //writeData(0x10);
sPymbed 0:94df05e3330d 143 writeData(0x00); // B[7..5] : Hsync+Vsync +DE mode & TFT mode
sPymbed 0:94df05e3330d 144 //writeData(0x80);
sPymbed 0:94df05e3330d 145 writeData((HDP>>8)&0xFF); // HPS[10:8] : Set the horizontal panel size (POR = 010)
sPymbed 0:94df05e3330d 146 writeData(HDP&0xFF); // HPS[7:0] : Set the horizontal panel size (POR = 01111111)
sPymbed 0:94df05e3330d 147 writeData((VDP>>8)&0xFF); // VPS[10:8] : Set the vertical panel size (POR = 001)
sPymbed 0:94df05e3330d 148 writeData(VDP&0xFF); // VPS[7:0] : Set the vertical panel size (POR = 11011111)
sPymbed 0:94df05e3330d 149 writeData(0x00); // G[5..0] : Even line RGB sequence & Odd line RGB sequence
sPymbed 0:94df05e3330d 150 */
sPymbed 0:94df05e3330d 151 writeData(0x10); // set 18-bit for 7" panel TY700TFT800480
sPymbed 0:94df05e3330d 152 writeData(0x80); // set TTL mode
sPymbed 0:94df05e3330d 153 writeData((DISP_HOR_RESOLUTION-1)>>8); //Set panel size
sPymbed 0:94df05e3330d 154 writeData(DISP_HOR_RESOLUTION-1);
sPymbed 0:94df05e3330d 155 writeData((DISP_VER_RESOLUTION-1)>>8);
sPymbed 0:94df05e3330d 156 writeData(DISP_VER_RESOLUTION-1);
sPymbed 0:94df05e3330d 157 writeData(0x00);
sPymbed 0:94df05e3330d 158
sPymbed 0:94df05e3330d 159
sPymbed 0:94df05e3330d 160 // Set Horizontal Period --------------------------------------------------
sPymbed 0:94df05e3330d 161 // @Parameters : 8
sPymbed 0:94df05e3330d 162 writeCommand(0xB4);
sPymbed 0:94df05e3330d 163 /*
sPymbed 0:94df05e3330d 164 writeData((HT>>8)&0xFF); // HT[10:8] : High byte of horizontal total period (display + non-display) in pixel clock
sPymbed 0:94df05e3330d 165 writeData(HT&0xFF); // HT[7:0] : Low byte of the horizontal total period (display + non-display) in pixel clock
sPymbed 0:94df05e3330d 166 writeData((HPS>>8)&0xFF); // HPS[10:8] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal
sPymbed 0:94df05e3330d 167 writeData(HPS&0xFF); // HPS[7:0] : Low byte of the non-display period between the start of the horizontal sync (LLINE) signal
sPymbed 0:94df05e3330d 168 writeData(HPW&0xFF); // HPW[6:0] : Set the horizontal sync pulse width (LLINE) in pixel clock
sPymbed 0:94df05e3330d 169 writeData((LPS>>8)&0xFF); // LPS[10:8] : Set the horizontal sync pulse (LLINE) start location in pixel clock
sPymbed 0:94df05e3330d 170 writeData(LPS&0xFF); // LPS[7:0] : Set the horizontal sync pulse width (LLINE) in start.
sPymbed 0:94df05e3330d 171 writeData(0x00); // LPSPP[1:0] : Set the horizontal sync pulse subpixel start position
sPymbed 0:94df05e3330d 172 */
sPymbed 0:94df05e3330d 173 #define HT (DISP_HOR_RESOLUTION+DISP_HOR_PULSE_WIDTH+DISP_HOR_BACK_PORCH+DISP_HOR_FRONT_PORCH)
sPymbed 0:94df05e3330d 174 writeData((HT-1)>>8);
sPymbed 0:94df05e3330d 175 writeData(HT-1);
sPymbed 0:94df05e3330d 176 #define HPS (DISP_HOR_PULSE_WIDTH+DISP_HOR_BACK_PORCH)
sPymbed 0:94df05e3330d 177 writeData((HPS-1)>>8);
sPymbed 0:94df05e3330d 178 writeData(HPS-1);
sPymbed 0:94df05e3330d 179 writeData(DISP_HOR_PULSE_WIDTH-1);
sPymbed 0:94df05e3330d 180 writeData(0x00);
sPymbed 0:94df05e3330d 181 writeData(0x00);
sPymbed 0:94df05e3330d 182 writeData(0x00);
sPymbed 0:94df05e3330d 183
sPymbed 0:94df05e3330d 184 // Set Vertical Period ----------------------------------------------------
sPymbed 0:94df05e3330d 185 // @Parameters : 7
sPymbed 0:94df05e3330d 186 writeCommand(0xB6);
sPymbed 0:94df05e3330d 187 /*
sPymbed 0:94df05e3330d 188 writeData((VT>>8)&0xFF); // VT[10:8] : High byte of the vertical total (display + non-display) period in lines
sPymbed 0:94df05e3330d 189 writeData(VT&0xFF); // VT[7:0] : Low byte of the vertical total (display + non-display) period in lines
sPymbed 0:94df05e3330d 190 writeData((VPS>>8)&0xFF); // VPS[10:8] : High byte the non-display period in lines between the start of the frame and the first display data in line
sPymbed 0:94df05e3330d 191 writeData(VPS&0xFF); // VPS[7:0] : The non-display period in lines between the start of the frame and the first display data in line
sPymbed 0:94df05e3330d 192 writeData(VPW&0xFF); // VPW[6:0] : Set the vertical sync pulse width (LFRAME) in lines
sPymbed 0:94df05e3330d 193 writeData((FPS>>8)&0xFF); // FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines
sPymbed 0:94df05e3330d 194 writeData(FPS&0xFF); // FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines
sPymbed 0:94df05e3330d 195 */
sPymbed 0:94df05e3330d 196 #define VT (DISP_VER_PULSE_WIDTH+DISP_VER_BACK_PORCH+DISP_VER_FRONT_PORCH+DISP_VER_RESOLUTION)
sPymbed 0:94df05e3330d 197 writeData((VT-1)>>8);
sPymbed 0:94df05e3330d 198 writeData(VT-1);
sPymbed 0:94df05e3330d 199 #define VSP (DISP_VER_PULSE_WIDTH+DISP_VER_BACK_PORCH)
sPymbed 0:94df05e3330d 200 writeData((VSP-1)>>8);
sPymbed 0:94df05e3330d 201 writeData(VSP-1);
sPymbed 0:94df05e3330d 202 writeData(DISP_VER_PULSE_WIDTH-1);
sPymbed 0:94df05e3330d 203 writeData(0x00);
sPymbed 0:94df05e3330d 204 writeData(0x00);
sPymbed 0:94df05e3330d 205
sPymbed 0:94df05e3330d 206 // Set GPIO Value ---------------------------------------------------------
sPymbed 0:94df05e3330d 207 // @Parameters : 1
sPymbed 0:94df05e3330d 208 writeCommand(0xBA);
sPymbed 0:94df05e3330d 209 writeData(0x05); // A[3..0] : GPIO[2:0] Output 1
sPymbed 0:94df05e3330d 210
sPymbed 0:94df05e3330d 211 // Set GPIO Configuration
sPymbed 0:94df05e3330d 212 // @Parameters : 2
sPymbed 0:94df05e3330d 213 writeCommand(0xB8);
sPymbed 0:94df05e3330d 214 writeData(0x07); // A[7..0] : GPIO3 = Input, GPIO[2:0] = Output
sPymbed 0:94df05e3330d 215 writeData(0x01); // B[0] : GPIO0 Normal
sPymbed 0:94df05e3330d 216
sPymbed 0:94df05e3330d 217 //Set pixel format, i.e. the bpp
sPymbed 0:94df05e3330d 218 writeCommand(0x3A);
sPymbed 0:94df05e3330d 219 writeData(0x55); // set 16bpp
sPymbed 0:94df05e3330d 220
sPymbed 0:94df05e3330d 221 // Set Address Mode -------------------------------------------------------
sPymbed 0:94df05e3330d 222 // @Parameters : 1
sPymbed 0:94df05e3330d 223 //writeCommand(0x36); // Set Rotation
sPymbed 0:94df05e3330d 224 //writeData(0x00); // A[7..0] : Set the read order from host processor to frame buffer by A[7:5] and A[3] and
sPymbed 0:94df05e3330d 225 // from frame buffer to the display panel by A[2:0] and A[4].
sPymbed 0:94df05e3330d 226 // A[7] : Page address order
sPymbed 0:94df05e3330d 227 // Set Pixel Data Interface -----------------------------------------------
sPymbed 0:94df05e3330d 228 // @Parameters : 1
sPymbed 0:94df05e3330d 229 writeCommand(0xF0); // A[2:0] : Pixel Data Interface Format
sPymbed 0:94df05e3330d 230 writeData(0x03); // 16-bit (565 format)
sPymbed 0:94df05e3330d 231 wait_us(100);
sPymbed 0:94df05e3330d 232
sPymbed 1:74bac5f988d8 233 writeCommand(0x34);
sPymbed 1:74bac5f988d8 234 wait_ms(1);
sPymbed 1:74bac5f988d8 235
sPymbed 0:94df05e3330d 236 // enter_partial_mode
sPymbed 0:94df05e3330d 237 //writeCommand(0x12); // Part of the display area is used for image display
sPymbed 0:94df05e3330d 238 // set_display_on
sPymbed 0:94df05e3330d 239 writeCommand(0x29); // Show the image on the display device
sPymbed 0:94df05e3330d 240
sPymbed 0:94df05e3330d 241 //writeCommand(0x2C);
sPymbed 0:94df05e3330d 242 }
sPymbed 0:94df05e3330d 243
sPymbed 0:94df05e3330d 244 void SSD1963::fillScreen(uint16_t color){
sPymbed 0:94df05e3330d 245 uint16_t start_x = 0;
sPymbed 0:94df05e3330d 246 uint16_t end_x = 799;
sPymbed 0:94df05e3330d 247 uint16_t start_y = 0;
sPymbed 0:94df05e3330d 248 uint16_t end_y = 479;
sPymbed 0:94df05e3330d 249
sPymbed 0:94df05e3330d 250 writeCommand(0x2A);
sPymbed 0:94df05e3330d 251 //nCS_LOW;
sPymbed 1:74bac5f988d8 252 writeData(start_x >> 8);
sPymbed 0:94df05e3330d 253 writeData(start_x);
sPymbed 1:74bac5f988d8 254 writeData(end_x >> 8);
sPymbed 0:94df05e3330d 255 writeData(end_x);
sPymbed 0:94df05e3330d 256 //nCS_HIGH;
sPymbed 0:94df05e3330d 257 writeCommand(0x2B);
sPymbed 0:94df05e3330d 258 //nCS_LOW;
sPymbed 1:74bac5f988d8 259 writeData(start_y >> 8);
sPymbed 0:94df05e3330d 260 writeData(start_y);
sPymbed 1:74bac5f988d8 261 writeData(end_y >> 8);
sPymbed 0:94df05e3330d 262 writeData(end_y);
sPymbed 0:94df05e3330d 263 //nCS_HIGH;
sPymbed 0:94df05e3330d 264
sPymbed 0:94df05e3330d 265 writeCommand(0x2C);
sPymbed 0:94df05e3330d 266
sPymbed 0:94df05e3330d 267 uint16_t i,j;
sPymbed 1:74bac5f988d8 268 for(i = 0; i < TFTWIDTH; i++){
sPymbed 1:74bac5f988d8 269 for (j = 0; j < TFTHEIGHT; j++){
sPymbed 0:94df05e3330d 270 writeData(color);
sPymbed 0:94df05e3330d 271 }
sPymbed 0:94df05e3330d 272 }
sPymbed 0:94df05e3330d 273 }
sPymbed 0:94df05e3330d 274
sPymbed 0:94df05e3330d 275 // - Color RGB R5 G6 B5 -------------------------------------------------------
sPymbed 0:94df05e3330d 276 uint16_t SSD1963::Color565(uint8_t r, uint8_t g, uint8_t b) {
sPymbed 0:94df05e3330d 277 uint16_t c;
sPymbed 0:94df05e3330d 278 c = r >> 3;
sPymbed 0:94df05e3330d 279 c <<= 6;
sPymbed 0:94df05e3330d 280 c |= g >> 2;
sPymbed 0:94df05e3330d 281 c <<= 5;
sPymbed 0:94df05e3330d 282 c |= b >> 3;
sPymbed 0:94df05e3330d 283 return c;
sPymbed 0:94df05e3330d 284 }
sPymbed 0:94df05e3330d 285
sPymbed 1:74bac5f988d8 286 uint8_t SSD1963::readID(void){
sPymbed 1:74bac5f988d8 287 writeCommand(0x0000);
sPymbed 1:74bac5f988d8 288 return readData();
sPymbed 1:74bac5f988d8 289 }