Revision 0:101fbacf126f, committed 2016-11-16

Comitter:

rulla

Date:

Wed Nov 16 10:37:49 2016 +0000

Child:

1:f5f5d7c979cf

Commit message:

11/2016

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/OV7670.cpp	Wed Nov 16 10:37:49 2016 +0000
@@ -0,0 +1,386 @@
+#include "mbed.h"
+#include "ov7670reg.h"
+#include "OV7670.h"
+
+ // capture request
+    void OV7670::CaptureNext(void)
+    {
+        CaptureReq = true ;
+        Busy = true ;
+        printf("CaptReq\n");
+    }
+    
+    // capture done? (with clear)
+    bool OV7670::CaptureDone(void)
+    {
+        bool result ;
+        if (Busy) {
+            result = false ;
+        } else {
+            result = Done ;
+            Done = false ;
+        }
+        return result ;
+    }
+
+    // write to camera
+    void OV7670::WriteReg(int addr,char data)
+    {
+        // WRITE 0x42,ADDR,DATA
+        //camera.write(OV7670_WRITE,d1,2) ;
+        camera.start() ;
+        camera.write(OV7670_WRITE) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(addr) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(data) ;
+        camera.stop() ;
+    }
+
+    // read from camera
+    char OV7670::ReadReg(int addr)
+    {
+ /*
+ char buff[20];
+ char buf[20];
+    buff[0] = addr;
+    buff[1] = OV7670_NOACK;
+
+    camera.write(OV7670_WRITE,buff,1);
+    camera.read(OV7670_WRITE+1,buf,1);
+    return buf[0];*/
+    int data ;
+
+        // WRITE 0x42,ADDR
+        camera.start() ;
+        camera.write(OV7670_WRITE) ;
+        wait_us(OV7670_WRITEWAIT);
+        camera.write(addr) ;
+        camera.stop() ;
+        wait_us(OV7670_WRITEWAIT);    
+
+        // WRITE 0x43,READ
+        camera.start() ;
+        camera.write(OV7670_READ) ;
+        wait_us(OV7670_WRITEWAIT);
+        data = camera.read(OV7670_NOACK) ;
+        camera.stop() ;
+    
+        return data ;
+    }
+
+    void OV7670::test(void) 
+    { 
+        printf("ResetMAMT\n");   
+    }
+    
+    void OV7670::Reset(void) 
+    { 
+        WriteReg(0x12,0x80) ; // RESET CAMERA
+        wait_ms(200) ;
+        printf("Reset\n");
+    }
+    
+    void OV7670::InitQQVGA(void) 
+    {
+       /*
+       //WriteReg(REG_COM7,0x80) ;
+        WriteReg(REG_CLKRC,0x80);
+        WriteReg(REG_COM11,0x1A) ;
+        WriteReg(REG_TSLB,0x04);
+        WriteReg(REG_TSLB,0x04);
+        WriteReg(REG_COM3,0x04) ;
+        WriteReg(REG_COM7,0x07) ;
+            WriteReg(REG_COM8,0x87) ;
+        //WriteReg(REG_RGB444, 0x00);
+        //WriteReg(REG_RGB444, 0x00);     // Disable RGB 444?
+        WriteReg(REG_COM15, 0xD0);      // Set RGB 565?
+*/
+
+        WriteReg(REG_CLKRC,0x80);
+        WriteReg(REG_COM11,0x1A) ;
+      //  WriteReg(REG_TSLB,0x04);
+        //WriteReg(REG_TSLB,0x04);
+        //WriteReg(REG_COM1,0x0) ;        
+        WriteReg(REG_COM3,0x04) ;
+        WriteReg(REG_COM7,0x04) ;
+        WriteReg(REG_COM14, 0x1a);
+        WriteReg(SCALING_XSC, 0x3a);
+        WriteReg(SCALING_YSC, 0x35);
+        WriteReg(SCALING_DCWCTR,0x22);
+        WriteReg(SCALING_PCLK_DIV,0xf2);
+        WriteReg(SCALING_PCLK_DELAY,0x02);
+          WriteReg(REG_COM8,0x87) ;
+     //   WriteReg(REG_RGB444, 0x02);
+       // WriteReg(REG_RGB444, 0x00);     // Disable RGB 444?
+        WriteReg(REG_COM15, 0xD0);      // Set RGB 565?
+        
+        WriteReg(REG_HSTART,0x16) ;
+        WriteReg(REG_HSTOP,0x04) ;
+        WriteReg(REG_HREF,0x24) ;
+        WriteReg(REG_VSTART,0x02) ;
+        WriteReg(REG_VSTOP,0x7a) ;
+        WriteReg(REG_VREF,0x0a) ;
+        WriteReg(REG_COM10,0x02) ;
+        WriteReg(REG_MVFP,0x27) ;
+
+        // COLOR SETTING
+        WriteReg(0x4f,0x80);
+        WriteReg(0x50,0x80);
+        WriteReg(0x51,0x00);
+        WriteReg(0x52,0x22);
+        WriteReg(0x53,0x5e);
+        WriteReg(0x54,0x80);
+        WriteReg(0x56,0x40);
+        WriteReg(0x58,0x9e);
+        WriteReg(0x59,0x88);
+        WriteReg(0x5a,0x88);
+        WriteReg(0x5b,0x44);
+        WriteReg(0x5c,0x67);
+        WriteReg(0x5d,0x49);
+        WriteReg(0x5e,0x0e);
+        WriteReg(0x69,0x00);
+        WriteReg(0x6a,0x40);
+        WriteReg(0x6b,0x0a);
+        WriteReg(0x6c,0x0a);
+        WriteReg(0x6d,0x55);
+        WriteReg(0x6e,0x11);
+        WriteReg(0x6f,0x9f);
+
+        WriteReg(0xb0,0x84);
+        //////////
+        
+        
+             
+        WriteReg(0x7a, 0x20);
+        WriteReg(0x7b, 0x1c);
+        WriteReg(0x7c, 0x28);
+        WriteReg(0x7d, 0x3c);
+        WriteReg(0x7e, 0x5a);
+        WriteReg(0x7f, 0x68);
+        WriteReg(0x80, 0x76);
+        WriteReg(0x81, 0x80);
+        WriteReg(0x82, 0x88);
+        WriteReg(0x83, 0x8f);
+        WriteReg(0x84, 0x96);
+        WriteReg(0x85, 0xa3);
+        WriteReg(0x86, 0xaf);
+        WriteReg(0x87, 0xc4);
+        WriteReg(0x88, 0xd7);
+        WriteReg(0x89, 0xe8);
+        
+        WriteReg(0x13, 0xe0);
+        WriteReg(0x00, 0x00);
+        WriteReg(0x10, 0x00);
+        WriteReg(0x0d, 0x40);
+        WriteReg(0x14, 0x18);
+        WriteReg(0xa5, 0x05);
+        WriteReg(0xab, 0x07);
+        WriteReg(0x24, 0x95);
+        WriteReg(0x25, 0x33);
+        WriteReg(0x26, 0xe3);
+        WriteReg(0x9f, 0x78);
+        WriteReg(0xa0, 0x68);
+        WriteReg(0xa1, 0x03);
+        WriteReg(0xa6, 0xd8);
+        WriteReg(0xa7, 0xd8);
+        WriteReg(0xa8, 0xf0);
+        WriteReg(0xa9, 0x90);
+        WriteReg(0xaa, 0x94);
+        WriteReg(0x13, 0xe5);
+        
+        WriteReg(0x0e, 0x61);
+        WriteReg(0x0f, 0x4b);
+        WriteReg(0x16, 0x02);
+
+        WriteReg(0x21, 0x02);
+        WriteReg(0x22, 0x91);
+        WriteReg(0x29, 0x07);
+        WriteReg(0x33, 0x0b);
+        WriteReg(0x35, 0x0b);
+        WriteReg(0x37, 0x1d);
+        WriteReg(0x38, 0x71);
+        WriteReg(0x39, 0x2a);
+        WriteReg(0x3c, 0x78);
+        WriteReg(0x4d, 0x40);
+        WriteReg(0x4e, 0x20);
+        WriteReg(0x69, 0x00);
+
+        WriteReg(0x74, 0x10);
+        WriteReg(0x8d, 0x4f);
+        WriteReg(0x8e, 0x00);
+        WriteReg(0x8f, 0x00);
+        WriteReg(0x90, 0x00);
+        WriteReg(0x91, 0x00);
+        WriteReg(0x92, 0x00);
+
+        WriteReg(0x96, 0x00);
+        WriteReg(0x9a, 0x80);
+        WriteReg(0xb0, 0x84);
+        WriteReg(0xb1, 0x0c);
+        WriteReg(0xb2, 0x0e);
+        WriteReg(0xb3, 0x82);
+        WriteReg(0xb8, 0x0a);
+        
+        WriteReg(0x43, 0x0a);
+        WriteReg(0x44, 0xf0);
+        WriteReg(0x45, 0x34);
+        WriteReg(0x46, 0x58);
+        WriteReg(0x47, 0x28);
+        WriteReg(0x48, 0x3a);
+        WriteReg(0x59, 0x88);
+        WriteReg(0x5a, 0x88);
+        WriteReg(0x5b, 0x44);
+        WriteReg(0x5c, 0x67);
+        WriteReg(0x5d, 0x49);
+        WriteReg(0x5e, 0x0e);
+        WriteReg(0x64, 0x04);
+        WriteReg(0x65, 0x20);
+        WriteReg(0x66, 0x05);
+        WriteReg(0x94, 0x04);
+        WriteReg(0x95, 0x08);
+
+        WriteReg(0x6c, 0x0a);
+        WriteReg(0x6d, 0x55);
+        WriteReg(0x6e, 0x11);
+        WriteReg(0x6f, 0x9f);
+        WriteReg(0x6a, 0x40);
+        WriteReg(0x01, 0x40);
+        WriteReg(0x02, 0x40);
+        WriteReg(0x13, 0xe7);
+        WriteReg(0x15, 0x02);
+
+        WriteReg(0x4f, 0x80);
+        WriteReg(0x50, 0x80);
+        WriteReg(0x51, 0x00);
+        WriteReg(0x52, 0x22);
+        WriteReg(0x53, 0x5e);
+        WriteReg(0x54, 0x80);
+        WriteReg(0x58, 0x9e);
+        
+        WriteReg(0x41, 0x08);
+        WriteReg(0x3f, 0x00);
+        WriteReg(0x75, 0x05);
+        WriteReg(0x76, 0xe1);
+        WriteReg(0x4c, 0x00);
+        WriteReg(0x77, 0x01);
+        WriteReg(0x3d, 0xc1);
+        WriteReg(0x4b, 0x09);
+        WriteReg(0xc9, 0x60);
+        WriteReg(0x41, 0x38);
+        WriteReg(0x56, 0x40);
+        
+        WriteReg(0x34, 0x11);
+        WriteReg(0x3b, 0x02);
+        WriteReg(0xa4, 0x88);
+        WriteReg(0x96, 0x00);
+        WriteReg(0x97, 0x30);
+        WriteReg(0x98, 0x20);
+        WriteReg(0x99, 0x30);
+        WriteReg(0x9a, 0x84);
+        WriteReg(0x9b, 0x29);
+        WriteReg(0x9c, 0x03);
+        WriteReg(0x9d, 0x4c);
+        WriteReg(0x9e, 0x3f);
+        WriteReg(0x78, 0x04);
+        
+        WriteReg(0x79, 0x01);
+        WriteReg(0xc8, 0xf0);
+        WriteReg(0x79, 0x0f);
+        WriteReg(0xc8, 0x00);
+        WriteReg(0x79, 0x10);
+        WriteReg(0xc8, 0x7e);
+        WriteReg(0x79, 0x0a);
+        WriteReg(0xc8, 0x80);
+        WriteReg(0x79, 0x0b);
+        WriteReg(0xc8, 0x01);
+        WriteReg(0x79, 0x0c);
+        WriteReg(0xc8, 0x0f);
+        WriteReg(0x79, 0x0d);
+        WriteReg(0xc8, 0x20);
+        WriteReg(0x79, 0x09);
+        WriteReg(0xc8, 0x80);
+        WriteReg(0x79, 0x02);
+        WriteReg(0xc8, 0xc0);
+        WriteReg(0x79, 0x03);
+        WriteReg(0xc8, 0x40);
+        WriteReg(0x79, 0x05);
+        WriteReg(0xc8, 0x30);
+        WriteReg(0x79, 0x26);
+        WriteReg(0x09, 0x03);
+        WriteReg(0x3b, 0x42);
+        
+        WriteReg(0xff, 0xff);   /* END MARKER */ 
+               
+        printf("Init\n");
+    }    
+
+
+
+    // vsync handler
+    void OV7670::VsyncHandler(void)
+    {
+        // Capture Enable
+        if (CaptureReq) {
+            wen = 1 ;
+            Done = false ;
+            CaptureReq = false ;
+        } else {
+            wen = 0 ;
+            if (Busy) {
+                Busy = false ;
+                Done = true ;
+            }
+        }
+
+        // Hline Counter
+        LastLines = LineCounter ;
+        LineCounter = 0 ;
+    }
+    
+    
+    // Data Read
+    int OV7670::ReadOneByte(void)
+    {
+        int result;
+        rclk = 1;
+        result = dataP;
+/*
+        // Shift the bits around to form the byte
+        int top = result >> 19;         // Isolate the top nibble
+        int middle = result >> 2;       // Isolate bits 2 & 3
+        result = result & 0x00000003;   // Isolate bits 0 & 1      
+        result += middle;
+        result += top;
+  */    
+    
+    //int middle= ((result)& 0xf00)>>4;
+    result= ((result&0x0f)|(((result)& 0xf00)>>4))&0xff;
+      //  int top=((result&0x01) << 7) | ((result&0x02) << 5) | ((result&0x04) << 3) | ((result&0x08) << 1) | ((result&0x10) >>1) | ((result&0x20) <<3) | ((result&0x40) >>5) | ((result&0x80) >>7);
+        int top=((result&0x01) << 7) | ((result&0x02) << 5) | ((result&0x04) << 3) | ((result&0x08) << 1) 
+              | ((result&0x10) >>1) | ((result&0x20) <<3) | ((result&0x40) >>5) | ((result&0x80) >>7);
+              
+        rclk = 0;
+        return top;
+    }
+    
+    // Data Start
+    void OV7670::ReadStart(void)
+    {        
+        rrst = 0 ;
+        oe = 0 ;
+        wait_us(1) ;
+        rclk = 0 ;
+        wait_us(1) ;
+        rclk = 1 ;
+        wait_us(1) ;        
+        rrst = 1 ;
+    }
+    
+    // Data Stop
+    void OV7670::ReadStop(void)
+    {
+        oe = 1 ;
+        ReadOneByte() ;
+        rclk = 1 ;
+    }
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/OV7670.h	Wed Nov 16 10:37:49 2016 +0000
@@ -0,0 +1,70 @@
+#include "mbed.h"
+#include "ov7670reg.h"
+
+#define OV7670_WRITE (0x42)
+#define OV7670_READ  (0x43)
+#define OV7670_WRITEWAIT (20)
+#define OV7670_NOACK (0)
+#define OV7670_REGMAX (201)
+#define OV7670_I2CFREQ (50000)
+
+
+//
+// OV7670 + FIFO AL422B camera board test
+//
+class OV7670 
+{
+    
+public:  
+volatile int LineCounter ;
+    volatile int LastLines ;
+    volatile bool CaptureReq ;
+    volatile bool Busy ;
+    volatile bool Done ;  
+        void CaptureNext(void);
+        bool CaptureDone(void);
+            void WriteReg(int addr,char data);
+        void Reset(void);
+        void test(void);
+        void InitQQVGA(void);
+            char ReadReg(int addr);
+    int ReadOneByte(void);
+    void ReadStart(void);
+    void ReadStop(void);
+    void VsyncHandler(void);
+    InterruptIn vsync;
+
+    OV7670(
+        PinName sda,// Camera I2C port
+        PinName scl,// Camera I2C port
+        PinName vs, // VSYNC
+        PinName hr, // HREF
+        PinName we, // WEN
+        PortName port, // 8bit bus port
+        int mask, // 0b0000_0M65_4000_0321_L000_0000_0000_0000 = 0x07878000
+        PinName rt, // /RRST
+        PinName o,  // /OE
+        PinName rc  // RCLK      
+        ) : camera(sda,scl),vsync(vs),href(hr),wen(we),dataP(port,mask),rrst(rt),oe(o),rclk(rc)
+    {
+        //camera.stop() ;
+        camera.frequency(OV7670_I2CFREQ) ;
+      //  camera.start() ;
+
+        CaptureReq = false ;
+        Busy = false ;
+        Done = false ;
+        LineCounter = 0 ;
+        rrst = 1 ;
+        oe = 1 ;
+        rclk = 1 ;
+        wen = 0 ;
+             vsync.rise(this,&OV7670::VsyncHandler) ;
+    }
+protected:
+    I2C camera ;
+    DigitalIn href;
+    DigitalOut wen ;
+    PortIn dataP;
+    DigitalOut rrst,oe,rclk ;
+    };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ov7670reg.h	Wed Nov 16 10:37:49 2016 +0000
@@ -0,0 +1,122 @@
+#define SCALING_XSC       0x70    /* Control 15 */
+#define SCALING_YSC       0x71
+#define SCALING_DCWCTR      0x72
+#define SCALING_PCLK_DIV    0x73
+#define SCALING_PCLK_DELAY  0xA2
+
+#define REG_GAIN        0x00    /* Gain lower 8 bits (rest in vref) */
+#define REG_BLUE        0x01    /* blue gain */
+#define REG_RED         0x02    /* red gain */
+#define REG_VREF        0x03    /* Pieces of GAIN, VSTART, VSTOP */
+#define REG_COM1        0x04    /* Control 1 */
+#define COM1_CCIR656    0x40    /* CCIR656 enable */
+#define REG_BAVE        0x05    /* U/B Average level */
+#define REG_GbAVE       0x06    /* Y/Gb Average level */
+#define REG_AECHH       0x07    /* AEC MS 5 bits */
+#define REG_RAVE        0x08    /* V/R Average level */
+#define REG_COM2        0x09    /* Control 2 */
+#define COM2_SSLEEP     0x10    /* Soft sleep mode */
+#define REG_PID         0x0a    /* Product ID MSB */
+#define REG_VER         0x0b    /* Product ID LSB */
+#define REG_COM3        0x0c    /* Control 3 */
+#define COM3_SWAP       0x40    /* Byte swap */
+#define COM3_SCALEEN    0x08    /* Enable scaling */
+#define COM3_DCWEN      0x04    /* Enable downsamp/crop/window */
+#define REG_COM4        0x0d    /* Control 4 */
+#define REG_COM5        0x0e    /* All "reserved" */
+#define REG_COM6        0x0f    /* Control 6 */
+#define REG_AECH        0x10    /* More bits of AEC value */
+#define REG_CLKRC       0x11    /* Clocl control */
+#define CLK_EXT         0x40    /* Use external clock directly */
+#define CLK_SCALE       0x3f    /* Mask for internal clock scale */
+#define REG_COM7        0x12    /* Control 7 */
+#define COM7_RESET      0x80    /* Register reset */
+#define COM7_FMT_MASK   0x38
+#define COM7_FMT_VGA    0x00
+#define COM7_FMT_CIF    0x20    /* CIF format */
+#define COM7_FMT_QVGA   0x10    /* QVGA format */
+#define COM7_FMT_QCIF   0x08    /* QCIF format */
+#define COM7_RGB        0x04    /* bits 0 and 2 - RGB format */
+#define COM7_YUV        0x00    /* YUV */
+#define COM7_BAYER      0x01    /* Bayer format */
+#define COM7_PBAYER     0x05    /* "Processed bayer" */
+#define REG_COM8        0x13    /* Control 8 */
+#define COM8_FASTAEC    0x80    /* Enable fast AGC/AEC */
+#define COM8_AECSTEP    0x40    /* Unlimited AEC step size */
+#define COM8_BFILT      0x20    /* Band filter enable */
+#define COM8_AGC        0x04    /* Auto gain enable */
+#define COM8_AWB        0x02    /* White balance enable */
+#define COM8_AEC        0x01    /* Auto exposure enable */
+#define REG_COM9        0x14    /* Control 9  - gain ceiling */
+#define REG_COM10       0x15    /* Control 10 */
+#define COM10_HSYNC     0x40    /* HSYNC instead of HREF */
+#define COM10_PCLK_HB   0x20    /* Suppress PCLK on horiz blank */
+#define COM10_HREF_REV  0x08    /* Reverse HREF */
+#define COM10_VS_LEAD   0x04    /* VSYNC on clock leading edge */
+#define COM10_VS_NEG    0x02    /* VSYNC negative */
+#define COM10_HS_NEG    0x01    /* HSYNC negative */
+#define REG_HSTART      0x17    /* Horiz start high bits */
+#define REG_HSTOP       0x18    /* Horiz stop high bits */
+#define REG_VSTART      0x19    /* Vert start high bits */
+#define REG_VSTOP       0x1a    /* Vert stop high bits */
+#define REG_PSHFT       0x1b    /* Pixel delay after HREF */
+#define REG_MIDH        0x1c    /* Manuf. ID high */
+#define REG_MIDL        0x1d    /* Manuf. ID low */
+#define REG_MVFP        0x1e    /* Mirror / vflip */
+#define MVFP_MIRROR     0x20    /* Mirror image */
+#define MVFP_FLIP       0x10    /* Vertical flip */
+#define REG_AEW         0x24    /* AGC upper limit */
+#define REG_AEB         0x25    /* AGC lower limit */
+#define REG_VPT         0x26    /* AGC/AEC fast mode op region */
+#define REG_HSYST       0x30    /* HSYNC rising edge delay */
+#define REG_HSYEN       0x31    /* HSYNC falling edge delay */
+#define REG_HREF        0x32    /* HREF pieces */
+#define REG_TSLB        0x3a    /* lots of stuff */
+#define TSLB_YLAST      0x04    /* UYVY or VYUY - see com13 */
+#define REG_COM11       0x3b    /* Control 11 */
+#define COM11_NIGHT     0x80    /* NIght mode enable */
+#define COM11_NMFR      0x60    /* Two bit NM frame rate */
+#define COM11_HZAUTO    0x10    /* Auto detect 50/60 Hz */
+#define COM11_50HZ      0x08    /* Manual 50Hz select */
+#define COM11_EXP       0x02
+#define REG_COM12       0x3c    /* Control 12 */
+#define COM12_HREF      0x80    /* HREF always */
+#define REG_COM13       0x3d    /* Control 13 */
+#define COM13_GAMMA     0x80    /* Gamma enable */
+#define COM13_UVSAT     0x40    /* UV saturation auto adjustment */
+#define COM13_UVSWAP    0x01    /* V before U - w/TSLB */
+#define REG_COM14       0x3e    /* Control 14 */
+#define COM14_DCWEN     0x10    /* DCW/PCLK-scale enable */
+#define REG_EDGE        0x3f    /* Edge enhancement factor */
+#define REG_COM15       0x40    /* Control 15 */
+#define COM15_R10F0     0x00    /* Data range 10 to F0 */
+#define COM15_R01FE     0x80    /*            01 to FE */
+#define COM15_R00FF     0xc0    /*            00 to FF */
+#define COM15_RGB565    0x10    /* RGB565 output */
+#define COM15_RGB555    0x30    /* RGB555 output */
+#define REG_COM16       0x41    /* Control 16 */
+#define COM16_AWBGAIN   0x08    /* AWB gain enable */
+#define REG_COM17       0x42    /* Control 17 */
+#define COM17_AECWIN    0xc0    /* AEC window - must match COM4 */
+#define COM17_CBAR      0x08    /* DSP Color bar */
+#define REG_CMATRIX_BASE 0x4f
+#define CMATRIX_LEN 6
+#define REG_CMATRIX_SIGN 0x58
+#define REG_BRIGHT      0x55    /* Brightness */
+#define REG_CONTRAS     0x56    /* Contrast control */
+#define REG_GFIX        0x69    /* Fix gain control */
+#define REG_REG76       0x76    /* OV's name */
+#define R76_BLKPCOR     0x80    /* Black pixel correction enable */
+#define R76_WHTPCOR     0x40    /* White pixel correction enable */
+#define REG_RGB444      0x8c    /* RGB 444 control */
+#define R444_ENABLE     0x02    /* Turn on RGB444, overrides 5x5 */
+#define R444_RGBX       0x01    /* Empty nibble at end */
+#define REG_HAECC1      0x9f    /* Hist AEC/AGC control 1 */
+#define REG_HAECC2      0xa0    /* Hist AEC/AGC control 2 */
+#define REG_BD50MAX     0xa5    /* 50hz banding step limit */
+#define REG_HAECC3      0xa6    /* Hist AEC/AGC control 3 */
+#define REG_HAECC4      0xa7    /* Hist AEC/AGC control 4 */
+#define REG_HAECC5      0xa8    /* Hist AEC/AGC control 5 */
+#define REG_HAECC6      0xa9    /* Hist AEC/AGC control 6 */
+#define REG_HAECC7      0xaa    /* Hist AEC/AGC control 7 */
+#define REG_BD60MAX     0xab    /* 60hz banding step limit */