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Fork of MMA8452Q by
Revision 1:a63e41016132, committed 2017-12-07
- Comitter:
- rsean10
- Date:
- Thu Dec 07 15:23:07 2017 +0000
- Parent:
- 0:b3305e3c9e73
- Commit message:
- this works i think;
Changed in this revision
MMA8452Q.cpp | Show annotated file Show diff for this revision Revisions of this file |
MMA8452Q.h | Show annotated file Show diff for this revision Revisions of this file |
diff -r b3305e3c9e73 -r a63e41016132 MMA8452Q.cpp --- a/MMA8452Q.cpp Thu Oct 19 12:53:02 2017 +0000 +++ b/MMA8452Q.cpp Thu Dec 07 15:23:07 2017 +0000 @@ -30,6 +30,7 @@ standby(); setScale(DEFAULT_FSR); setODR(DEFAULT_ODR); + //freefall(); //enable freefall active(); return true; @@ -73,6 +74,16 @@ writeRegister(REG_CTRL_REG1, c); // Write back to CONTROL register } +//Enabe Freefall interrupt +void MMA8452Q::freefall(uint8_t interrupt,uint8_t threshold) +{ + writeRegister(FF_CONFIG,0x38); // Configure for freefall + writeRegister(FF_THS,threshold); // Configure for threshold <"thresh"g + writeRegister(FF_COUNT,0x64); // Set debounce counter for 125ms + writeRegister(REG_CTRL_REG4,0x04); // enable interrupt in control register + writeRegister(REG_CTRL_REG5,interrupt); // set interrupt to hardware pin +} + // Read X registers float MMA8452Q::readX() {
diff -r b3305e3c9e73 -r a63e41016132 MMA8452Q.h --- a/MMA8452Q.h Thu Oct 19 12:53:02 2017 +0000 +++ b/MMA8452Q.h Thu Dec 07 15:23:07 2017 +0000 @@ -17,6 +17,12 @@ #define REG_WHO_AM_I 0x0D #define REG_XYZ_DATA_CFG 0x0E #define REG_CTRL_REG1 0x2A +#define REG_CTRL_REG4 0X2D +#define FF_CONFIG 0X15 +#define FF_THS 0X17 +#define FF_COUNT 0X18 +#define FF_SRC 0X16 +#define REG_CTRL_REG5 0X2E // WHO_AM_I check #define FACTORY_ID 0x2A @@ -39,6 +45,8 @@ // Init values #define DEFAULT_FSR SCALE_2G #define DEFAULT_ODR ODR_800HZ +#define DEFAULT_PIN 0X04 +#define DEFAULT_THRESH 0x03 // Class declaration @@ -53,6 +61,7 @@ void setODR(uint8_t odr); void standby(); void active(); + void freefall(uint8_t interrupt,uint8_t threshold); float readX(); float readY(); float readZ();