Reinhold Schaefer / mbed-src

mbed library sources

Dependents:   STM32F103C8T6-RangoTec STM32-103C8_Plantilla_USB

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c@441:8a0b45cd594f, 2014-12-16 (annotated)

Committer:
mbed_official
Date:
Tue Dec 16 08:15:08 2014 +0000
Revision:
441:8a0b45cd594f
Parent:
385:ef87175507f1 
Synchronized with git revision 67fbbf0b635d0c0d93fbe433306c537c2ad206aa



Full URL: https://github.com/mbedmicro/mbed/commit/67fbbf0b635d0c0d93fbe433306c537c2ad206aa/



Targets: nrf51 - updating app_timer.c from Norid'c SDKv7.1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 341:28d1f895c6fe 1 /**
mbed_official 341:28d1f895c6fe 2 ******************************************************************************
mbed_official 341:28d1f895c6fe 3 * @file system_stm32f4xx.c
mbed_official 341:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 341:28d1f895c6fe 5 * @version V2.1.0
mbed_official 341:28d1f895c6fe 6 * @date 19-June-2014
mbed_official 341:28d1f895c6fe 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 341:28d1f895c6fe 8 *
mbed_official 341:28d1f895c6fe 9 * This file provides two functions and one global variable to be called from
mbed_official 341:28d1f895c6fe 10 * user application:
mbed_official 341:28d1f895c6fe 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 341:28d1f895c6fe 12 * before branch to main program. This call is made inside
mbed_official 341:28d1f895c6fe 13 * the "startup_stm32f4xx.s" file.
mbed_official 341:28d1f895c6fe 14 *
mbed_official 341:28d1f895c6fe 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 341:28d1f895c6fe 16 * by the user application to setup the SysTick
mbed_official 341:28d1f895c6fe 17 * timer or configure other parameters.
mbed_official 341:28d1f895c6fe 18 *
mbed_official 341:28d1f895c6fe 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 341:28d1f895c6fe 20 * be called whenever the core clock is changed
mbed_official 341:28d1f895c6fe 21 * during program execution.
mbed_official 341:28d1f895c6fe 22 *
mbed_official 441:8a0b45cd594f 23 * This file configures the system clock as follows:
mbed_official 441:8a0b45cd594f 24 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 25 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
mbed_official 441:8a0b45cd594f 26 * | (external 8 MHz clock) | (external 8 MHz clock)
mbed_official 441:8a0b45cd594f 27 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 28 * SYSCLK(MHz) | 168 | 180
mbed_official 441:8a0b45cd594f 29 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 30 * AHBCLK (MHz) | 168 | 180
mbed_official 441:8a0b45cd594f 31 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 32 * APB1CLK (MHz) | 42 | 45
mbed_official 441:8a0b45cd594f 33 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 34 * APB2CLK (MHz) | 84 | 90
mbed_official 441:8a0b45cd594f 35 *--------------------------------------------------------------------------------------
mbed_official 441:8a0b45cd594f 36 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 441:8a0b45cd594f 37 *--------------------------------------------------------------------------------------
mbed_official 341:28d1f895c6fe 38 ******************************************************************************
mbed_official 341:28d1f895c6fe 39 * @attention
mbed_official 341:28d1f895c6fe 40 *
mbed_official 341:28d1f895c6fe 41 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 341:28d1f895c6fe 42 *
mbed_official 341:28d1f895c6fe 43 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 341:28d1f895c6fe 44 * are permitted provided that the following conditions are met:
mbed_official 341:28d1f895c6fe 45 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 341:28d1f895c6fe 46 * this list of conditions and the following disclaimer.
mbed_official 341:28d1f895c6fe 47 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 341:28d1f895c6fe 48 * this list of conditions and the following disclaimer in the documentation
mbed_official 341:28d1f895c6fe 49 * and/or other materials provided with the distribution.
mbed_official 341:28d1f895c6fe 50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 341:28d1f895c6fe 51 * may be used to endorse or promote products derived from this software
mbed_official 341:28d1f895c6fe 52 * without specific prior written permission.
mbed_official 341:28d1f895c6fe 53 *
mbed_official 341:28d1f895c6fe 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 341:28d1f895c6fe 55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 341:28d1f895c6fe 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 341:28d1f895c6fe 57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 341:28d1f895c6fe 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 341:28d1f895c6fe 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 341:28d1f895c6fe 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 341:28d1f895c6fe 61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 341:28d1f895c6fe 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 341:28d1f895c6fe 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 341:28d1f895c6fe 64 *
mbed_official 341:28d1f895c6fe 65 ******************************************************************************
mbed_official 341:28d1f895c6fe 66 */
mbed_official 341:28d1f895c6fe 67
mbed_official 341:28d1f895c6fe 68 /** @addtogroup CMSIS
mbed_official 341:28d1f895c6fe 69 * @{
mbed_official 341:28d1f895c6fe 70 */
mbed_official 341:28d1f895c6fe 71
mbed_official 341:28d1f895c6fe 72 /** @addtogroup stm32f4xx_system
mbed_official 341:28d1f895c6fe 73 * @{
mbed_official 341:28d1f895c6fe 74 */
mbed_official 341:28d1f895c6fe 75
mbed_official 341:28d1f895c6fe 76 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 341:28d1f895c6fe 77 * @{
mbed_official 341:28d1f895c6fe 78 */
mbed_official 341:28d1f895c6fe 79
mbed_official 341:28d1f895c6fe 80
mbed_official 341:28d1f895c6fe 81 #include "stm32f4xx.h"
mbed_official 441:8a0b45cd594f 82 #include "hal_tick.h"
mbed_official 341:28d1f895c6fe 83
mbed_official 341:28d1f895c6fe 84 #if !defined (HSE_VALUE)
mbed_official 341:28d1f895c6fe 85 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 341:28d1f895c6fe 86 #endif /* HSE_VALUE */
mbed_official 341:28d1f895c6fe 87
mbed_official 341:28d1f895c6fe 88 #if !defined (HSI_VALUE)
mbed_official 341:28d1f895c6fe 89 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 341:28d1f895c6fe 90 #endif /* HSI_VALUE */
mbed_official 341:28d1f895c6fe 91
mbed_official 341:28d1f895c6fe 92 /**
mbed_official 341:28d1f895c6fe 93 * @}
mbed_official 341:28d1f895c6fe 94 */
mbed_official 341:28d1f895c6fe 95
mbed_official 341:28d1f895c6fe 96 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 341:28d1f895c6fe 97 * @{
mbed_official 341:28d1f895c6fe 98 */
mbed_official 341:28d1f895c6fe 99
mbed_official 341:28d1f895c6fe 100 /**
mbed_official 341:28d1f895c6fe 101 * @}
mbed_official 341:28d1f895c6fe 102 */
mbed_official 341:28d1f895c6fe 103
mbed_official 341:28d1f895c6fe 104 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 341:28d1f895c6fe 105 * @{
mbed_official 341:28d1f895c6fe 106 */
mbed_official 341:28d1f895c6fe 107
mbed_official 341:28d1f895c6fe 108 /************************* Miscellaneous Configuration ************************/
mbed_official 341:28d1f895c6fe 109 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 341:28d1f895c6fe 110 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 341:28d1f895c6fe 111 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 341:28d1f895c6fe 112 /* #define DATA_IN_ExtSRAM */
mbed_official 341:28d1f895c6fe 113 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 341:28d1f895c6fe 114
mbed_official 341:28d1f895c6fe 115 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 341:28d1f895c6fe 116 /* #define DATA_IN_ExtSDRAM */
mbed_official 341:28d1f895c6fe 117 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 341:28d1f895c6fe 118
mbed_official 341:28d1f895c6fe 119 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 341:28d1f895c6fe 120 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 341:28d1f895c6fe 121 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 341:28d1f895c6fe 122
mbed_official 341:28d1f895c6fe 123 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 341:28d1f895c6fe 124 Internal SRAM. */
mbed_official 341:28d1f895c6fe 125 /* #define VECT_TAB_SRAM */
mbed_official 341:28d1f895c6fe 126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 341:28d1f895c6fe 127 This value must be a multiple of 0x200. */
mbed_official 341:28d1f895c6fe 128 /******************************************************************************/
mbed_official 341:28d1f895c6fe 129
mbed_official 341:28d1f895c6fe 130 /**
mbed_official 341:28d1f895c6fe 131 * @}
mbed_official 341:28d1f895c6fe 132 */
mbed_official 341:28d1f895c6fe 133
mbed_official 341:28d1f895c6fe 134 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 341:28d1f895c6fe 135 * @{
mbed_official 341:28d1f895c6fe 136 */
mbed_official 341:28d1f895c6fe 137
mbed_official 441:8a0b45cd594f 138 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
mbed_official 441:8a0b45cd594f 139 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
mbed_official 441:8a0b45cd594f 140 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
mbed_official 441:8a0b45cd594f 141
mbed_official 341:28d1f895c6fe 142 /**
mbed_official 341:28d1f895c6fe 143 * @}
mbed_official 341:28d1f895c6fe 144 */
mbed_official 341:28d1f895c6fe 145
mbed_official 341:28d1f895c6fe 146 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 341:28d1f895c6fe 147 * @{
mbed_official 341:28d1f895c6fe 148 */
mbed_official 341:28d1f895c6fe 149 /* This variable is updated in three ways:
mbed_official 341:28d1f895c6fe 150 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 341:28d1f895c6fe 151 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 341:28d1f895c6fe 152 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 341:28d1f895c6fe 153 Note: If you use this function to configure the system clock; then there
mbed_official 341:28d1f895c6fe 154 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 341:28d1f895c6fe 155 variable is updated automatically.
mbed_official 341:28d1f895c6fe 156 */
mbed_official 441:8a0b45cd594f 157 uint32_t SystemCoreClock = 168000000;
mbed_official 341:28d1f895c6fe 158 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 341:28d1f895c6fe 159
mbed_official 341:28d1f895c6fe 160 /**
mbed_official 341:28d1f895c6fe 161 * @}
mbed_official 341:28d1f895c6fe 162 */
mbed_official 341:28d1f895c6fe 163
mbed_official 341:28d1f895c6fe 164 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 341:28d1f895c6fe 165 * @{
mbed_official 341:28d1f895c6fe 166 */
mbed_official 341:28d1f895c6fe 167
mbed_official 341:28d1f895c6fe 168 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 341:28d1f895c6fe 169 static void SystemInit_ExtMemCtl(void);
mbed_official 341:28d1f895c6fe 170 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 341:28d1f895c6fe 171
mbed_official 341:28d1f895c6fe 172 /**
mbed_official 341:28d1f895c6fe 173 * @}
mbed_official 341:28d1f895c6fe 174 */
mbed_official 341:28d1f895c6fe 175
mbed_official 341:28d1f895c6fe 176 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 341:28d1f895c6fe 177 * @{
mbed_official 341:28d1f895c6fe 178 */
mbed_official 341:28d1f895c6fe 179
mbed_official 341:28d1f895c6fe 180 /**
mbed_official 341:28d1f895c6fe 181 * @brief Setup the microcontroller system
mbed_official 341:28d1f895c6fe 182 * Initialize the FPU setting, vector table location and External memory
mbed_official 341:28d1f895c6fe 183 * configuration.
mbed_official 341:28d1f895c6fe 184 * @param None
mbed_official 341:28d1f895c6fe 185 * @retval None
mbed_official 341:28d1f895c6fe 186 */
mbed_official 341:28d1f895c6fe 187 void SystemInit(void)
mbed_official 341:28d1f895c6fe 188 {
mbed_official 341:28d1f895c6fe 189 /* FPU settings ------------------------------------------------------------*/
mbed_official 341:28d1f895c6fe 190 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 341:28d1f895c6fe 191 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 341:28d1f895c6fe 192 #endif
mbed_official 341:28d1f895c6fe 193 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 341:28d1f895c6fe 194 /* Set HSION bit */
mbed_official 341:28d1f895c6fe 195 RCC->CR |= (uint32_t)0x00000001;
mbed_official 341:28d1f895c6fe 196
mbed_official 341:28d1f895c6fe 197 /* Reset CFGR register */
mbed_official 341:28d1f895c6fe 198 RCC->CFGR = 0x00000000;
mbed_official 341:28d1f895c6fe 199
mbed_official 341:28d1f895c6fe 200 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 341:28d1f895c6fe 201 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 341:28d1f895c6fe 202
mbed_official 341:28d1f895c6fe 203 /* Reset PLLCFGR register */
mbed_official 341:28d1f895c6fe 204 RCC->PLLCFGR = 0x24003010;
mbed_official 341:28d1f895c6fe 205
mbed_official 341:28d1f895c6fe 206 /* Reset HSEBYP bit */
mbed_official 341:28d1f895c6fe 207 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 341:28d1f895c6fe 208
mbed_official 341:28d1f895c6fe 209 /* Disable all interrupts */
mbed_official 341:28d1f895c6fe 210 RCC->CIR = 0x00000000;
mbed_official 341:28d1f895c6fe 211
mbed_official 341:28d1f895c6fe 212 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 341:28d1f895c6fe 213 SystemInit_ExtMemCtl();
mbed_official 341:28d1f895c6fe 214 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 341:28d1f895c6fe 215
mbed_official 341:28d1f895c6fe 216 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 341:28d1f895c6fe 217 #ifdef VECT_TAB_SRAM
mbed_official 341:28d1f895c6fe 218 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 341:28d1f895c6fe 219 #else
mbed_official 341:28d1f895c6fe 220 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 341:28d1f895c6fe 221 #endif
mbed_official 441:8a0b45cd594f 222
mbed_official 441:8a0b45cd594f 223 /* Configure the Cube driver */
mbed_official 441:8a0b45cd594f 224 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official 441:8a0b45cd594f 225 HAL_Init();
mbed_official 441:8a0b45cd594f 226
mbed_official 441:8a0b45cd594f 227 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 441:8a0b45cd594f 228 AHB/APBx prescalers and Flash settings */
mbed_official 441:8a0b45cd594f 229 SystemClock_Config();
mbed_official 441:8a0b45cd594f 230 SystemCoreClockUpdate();
mbed_official 441:8a0b45cd594f 231
mbed_official 441:8a0b45cd594f 232 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 441:8a0b45cd594f 233 TIM_MST_RESET_ON;
mbed_official 441:8a0b45cd594f 234 TIM_MST_RESET_OFF;
mbed_official 341:28d1f895c6fe 235 }
mbed_official 341:28d1f895c6fe 236
mbed_official 341:28d1f895c6fe 237 /**
mbed_official 341:28d1f895c6fe 238 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 341:28d1f895c6fe 239 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 341:28d1f895c6fe 240 * be used by the user application to setup the SysTick timer or configure
mbed_official 341:28d1f895c6fe 241 * other parameters.
mbed_official 341:28d1f895c6fe 242 *
mbed_official 341:28d1f895c6fe 243 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 341:28d1f895c6fe 244 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 341:28d1f895c6fe 245 * based on this variable will be incorrect.
mbed_official 341:28d1f895c6fe 246 *
mbed_official 341:28d1f895c6fe 247 * @note - The system frequency computed by this function is not the real
mbed_official 341:28d1f895c6fe 248 * frequency in the chip. It is calculated based on the predefined
mbed_official 341:28d1f895c6fe 249 * constant and the selected clock source:
mbed_official 341:28d1f895c6fe 250 *
mbed_official 341:28d1f895c6fe 251 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 341:28d1f895c6fe 252 *
mbed_official 341:28d1f895c6fe 253 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 341:28d1f895c6fe 254 *
mbed_official 341:28d1f895c6fe 255 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 341:28d1f895c6fe 256 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 341:28d1f895c6fe 257 *
mbed_official 341:28d1f895c6fe 258 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 341:28d1f895c6fe 259 * 16 MHz) but the real value may vary depending on the variations
mbed_official 341:28d1f895c6fe 260 * in voltage and temperature.
mbed_official 341:28d1f895c6fe 261 *
mbed_official 341:28d1f895c6fe 262 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 341:28d1f895c6fe 263 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 341:28d1f895c6fe 264 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 341:28d1f895c6fe 265 * may have wrong result.
mbed_official 341:28d1f895c6fe 266 *
mbed_official 341:28d1f895c6fe 267 * - The result of this function could be not correct when using fractional
mbed_official 341:28d1f895c6fe 268 * value for HSE crystal.
mbed_official 341:28d1f895c6fe 269 *
mbed_official 341:28d1f895c6fe 270 * @param None
mbed_official 341:28d1f895c6fe 271 * @retval None
mbed_official 341:28d1f895c6fe 272 */
mbed_official 341:28d1f895c6fe 273 void SystemCoreClockUpdate(void)
mbed_official 341:28d1f895c6fe 274 {
mbed_official 341:28d1f895c6fe 275 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 341:28d1f895c6fe 276
mbed_official 341:28d1f895c6fe 277 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 341:28d1f895c6fe 278 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 341:28d1f895c6fe 279
mbed_official 341:28d1f895c6fe 280 switch (tmp)
mbed_official 341:28d1f895c6fe 281 {
mbed_official 341:28d1f895c6fe 282 case 0x00: /* HSI used as system clock source */
mbed_official 341:28d1f895c6fe 283 SystemCoreClock = HSI_VALUE;
mbed_official 341:28d1f895c6fe 284 break;
mbed_official 341:28d1f895c6fe 285 case 0x04: /* HSE used as system clock source */
mbed_official 341:28d1f895c6fe 286 SystemCoreClock = HSE_VALUE;
mbed_official 341:28d1f895c6fe 287 break;
mbed_official 341:28d1f895c6fe 288 case 0x08: /* PLL used as system clock source */
mbed_official 341:28d1f895c6fe 289
mbed_official 341:28d1f895c6fe 290 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 341:28d1f895c6fe 291 SYSCLK = PLL_VCO / PLL_P
mbed_official 341:28d1f895c6fe 292 */
mbed_official 341:28d1f895c6fe 293 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 341:28d1f895c6fe 294 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 341:28d1f895c6fe 295
mbed_official 341:28d1f895c6fe 296 if (pllsource != 0)
mbed_official 341:28d1f895c6fe 297 {
mbed_official 341:28d1f895c6fe 298 /* HSE used as PLL clock source */
mbed_official 341:28d1f895c6fe 299 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 341:28d1f895c6fe 300 }
mbed_official 341:28d1f895c6fe 301 else
mbed_official 341:28d1f895c6fe 302 {
mbed_official 341:28d1f895c6fe 303 /* HSI used as PLL clock source */
mbed_official 341:28d1f895c6fe 304 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 341:28d1f895c6fe 305 }
mbed_official 341:28d1f895c6fe 306
mbed_official 341:28d1f895c6fe 307 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 341:28d1f895c6fe 308 SystemCoreClock = pllvco/pllp;
mbed_official 341:28d1f895c6fe 309 break;
mbed_official 341:28d1f895c6fe 310 default:
mbed_official 341:28d1f895c6fe 311 SystemCoreClock = HSI_VALUE;
mbed_official 341:28d1f895c6fe 312 break;
mbed_official 341:28d1f895c6fe 313 }
mbed_official 341:28d1f895c6fe 314 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 341:28d1f895c6fe 315 /* Get HCLK prescaler */
mbed_official 341:28d1f895c6fe 316 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 341:28d1f895c6fe 317 /* HCLK frequency */
mbed_official 341:28d1f895c6fe 318 SystemCoreClock >>= tmp;
mbed_official 341:28d1f895c6fe 319 }
mbed_official 341:28d1f895c6fe 320
mbed_official 341:28d1f895c6fe 321 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 341:28d1f895c6fe 322 /**
mbed_official 341:28d1f895c6fe 323 * @brief Setup the external memory controller.
mbed_official 341:28d1f895c6fe 324 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 341:28d1f895c6fe 325 * This function configures the external memories (SRAM/SDRAM)
mbed_official 341:28d1f895c6fe 326 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 341:28d1f895c6fe 327 * @param None
mbed_official 341:28d1f895c6fe 328 * @retval None
mbed_official 341:28d1f895c6fe 329 */
mbed_official 341:28d1f895c6fe 330 void SystemInit_ExtMemCtl(void)
mbed_official 341:28d1f895c6fe 331 {
mbed_official 341:28d1f895c6fe 332 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 341:28d1f895c6fe 333 #if defined (DATA_IN_ExtSDRAM)
mbed_official 341:28d1f895c6fe 334 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 341:28d1f895c6fe 335 register uint32_t index;
mbed_official 341:28d1f895c6fe 336
mbed_official 341:28d1f895c6fe 337 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 341:28d1f895c6fe 338 clock */
mbed_official 341:28d1f895c6fe 339 RCC->AHB1ENR |= 0x000001F8;
mbed_official 341:28d1f895c6fe 340
mbed_official 341:28d1f895c6fe 341 /* Connect PDx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 342 GPIOD->AFR[0] = 0x000000CC;
mbed_official 341:28d1f895c6fe 343 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 341:28d1f895c6fe 344 /* Configure PDx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 345 GPIOD->MODER = 0xA02A000A;
mbed_official 341:28d1f895c6fe 346 /* Configure PDx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 347 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 341:28d1f895c6fe 348 /* Configure PDx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 349 GPIOD->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 350 /* No pull-up, pull-down for PDx pins */
mbed_official 341:28d1f895c6fe 351 GPIOD->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 352
mbed_official 341:28d1f895c6fe 353 /* Connect PEx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 354 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 341:28d1f895c6fe 355 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 356 /* Configure PEx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 357 GPIOE->MODER = 0xAAAA800A;
mbed_official 341:28d1f895c6fe 358 /* Configure PEx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 359 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 341:28d1f895c6fe 360 /* Configure PEx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 361 GPIOE->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 362 /* No pull-up, pull-down for PEx pins */
mbed_official 341:28d1f895c6fe 363 GPIOE->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 364
mbed_official 341:28d1f895c6fe 365 /* Connect PFx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 366 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 367 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 368 /* Configure PFx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 369 GPIOF->MODER = 0xAA800AAA;
mbed_official 341:28d1f895c6fe 370 /* Configure PFx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 371 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 341:28d1f895c6fe 372 /* Configure PFx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 373 GPIOF->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 374 /* No pull-up, pull-down for PFx pins */
mbed_official 341:28d1f895c6fe 375 GPIOF->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 376
mbed_official 341:28d1f895c6fe 377 /* Connect PGx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 378 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 379 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 380 /* Configure PGx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 381 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 341:28d1f895c6fe 382 /* Configure PGx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 383 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 341:28d1f895c6fe 384 /* Configure PGx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 385 GPIOG->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 386 /* No pull-up, pull-down for PGx pins */
mbed_official 341:28d1f895c6fe 387 GPIOG->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 388
mbed_official 341:28d1f895c6fe 389 /* Connect PHx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 390 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 341:28d1f895c6fe 391 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 392 /* Configure PHx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 393 GPIOH->MODER = 0xAAAA08A0;
mbed_official 341:28d1f895c6fe 394 /* Configure PHx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 395 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 341:28d1f895c6fe 396 /* Configure PHx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 397 GPIOH->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 398 /* No pull-up, pull-down for PHx pins */
mbed_official 341:28d1f895c6fe 399 GPIOH->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 400
mbed_official 341:28d1f895c6fe 401 /* Connect PIx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 402 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 403 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 341:28d1f895c6fe 404 /* Configure PIx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 405 GPIOI->MODER = 0x0028AAAA;
mbed_official 341:28d1f895c6fe 406 /* Configure PIx pins speed to 50 MHz */
mbed_official 341:28d1f895c6fe 407 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 341:28d1f895c6fe 408 /* Configure PIx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 409 GPIOI->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 410 /* No pull-up, pull-down for PIx pins */
mbed_official 341:28d1f895c6fe 411 GPIOI->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 412
mbed_official 341:28d1f895c6fe 413 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 341:28d1f895c6fe 414 /* Enable the FMC interface clock */
mbed_official 341:28d1f895c6fe 415 RCC->AHB3ENR |= 0x00000001;
mbed_official 341:28d1f895c6fe 416
mbed_official 341:28d1f895c6fe 417 /* Configure and enable SDRAM bank1 */
mbed_official 341:28d1f895c6fe 418 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 341:28d1f895c6fe 419 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 341:28d1f895c6fe 420
mbed_official 341:28d1f895c6fe 421 /* SDRAM initialization sequence */
mbed_official 341:28d1f895c6fe 422 /* Clock enable command */
mbed_official 341:28d1f895c6fe 423 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 341:28d1f895c6fe 424 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 341:28d1f895c6fe 425 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 341:28d1f895c6fe 426 {
mbed_official 341:28d1f895c6fe 427 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 341:28d1f895c6fe 428 }
mbed_official 341:28d1f895c6fe 429
mbed_official 341:28d1f895c6fe 430 /* Delay */
mbed_official 341:28d1f895c6fe 431 for (index = 0; index<1000; index++);
mbed_official 341:28d1f895c6fe 432
mbed_official 341:28d1f895c6fe 433 /* PALL command */
mbed_official 341:28d1f895c6fe 434 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 341:28d1f895c6fe 435 timeout = 0xFFFF;
mbed_official 341:28d1f895c6fe 436 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 341:28d1f895c6fe 437 {
mbed_official 341:28d1f895c6fe 438 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 341:28d1f895c6fe 439 }
mbed_official 341:28d1f895c6fe 440
mbed_official 341:28d1f895c6fe 441 /* Auto refresh command */
mbed_official 341:28d1f895c6fe 442 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 341:28d1f895c6fe 443 timeout = 0xFFFF;
mbed_official 341:28d1f895c6fe 444 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 341:28d1f895c6fe 445 {
mbed_official 341:28d1f895c6fe 446 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 341:28d1f895c6fe 447 }
mbed_official 341:28d1f895c6fe 448
mbed_official 341:28d1f895c6fe 449 /* MRD register program */
mbed_official 341:28d1f895c6fe 450 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 341:28d1f895c6fe 451 timeout = 0xFFFF;
mbed_official 341:28d1f895c6fe 452 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 341:28d1f895c6fe 453 {
mbed_official 341:28d1f895c6fe 454 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 341:28d1f895c6fe 455 }
mbed_official 341:28d1f895c6fe 456
mbed_official 341:28d1f895c6fe 457 /* Set refresh count */
mbed_official 341:28d1f895c6fe 458 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 341:28d1f895c6fe 459 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 341:28d1f895c6fe 460
mbed_official 341:28d1f895c6fe 461 /* Disable write protection */
mbed_official 341:28d1f895c6fe 462 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 341:28d1f895c6fe 463 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 341:28d1f895c6fe 464 #endif /* DATA_IN_ExtSDRAM */
mbed_official 341:28d1f895c6fe 465 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 341:28d1f895c6fe 466
mbed_official 341:28d1f895c6fe 467 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 341:28d1f895c6fe 468 #if defined(DATA_IN_ExtSRAM)
mbed_official 341:28d1f895c6fe 469 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 341:28d1f895c6fe 470 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 341:28d1f895c6fe 471 RCC->AHB1ENR |= 0x00000078;
mbed_official 341:28d1f895c6fe 472
mbed_official 341:28d1f895c6fe 473 /* Connect PDx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 474 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 341:28d1f895c6fe 475 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 476 /* Configure PDx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 477 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 341:28d1f895c6fe 478 /* Configure PDx pins speed to 100 MHz */
mbed_official 341:28d1f895c6fe 479 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 341:28d1f895c6fe 480 /* Configure PDx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 481 GPIOD->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 482 /* No pull-up, pull-down for PDx pins */
mbed_official 341:28d1f895c6fe 483 GPIOD->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 484
mbed_official 341:28d1f895c6fe 485 /* Connect PEx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 486 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 341:28d1f895c6fe 487 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 341:28d1f895c6fe 488 /* Configure PEx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 489 GPIOE->MODER = 0xAAAA828A;
mbed_official 341:28d1f895c6fe 490 /* Configure PEx pins speed to 100 MHz */
mbed_official 341:28d1f895c6fe 491 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 341:28d1f895c6fe 492 /* Configure PEx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 493 GPIOE->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 494 /* No pull-up, pull-down for PEx pins */
mbed_official 341:28d1f895c6fe 495 GPIOE->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 496
mbed_official 341:28d1f895c6fe 497 /* Connect PFx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 498 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 341:28d1f895c6fe 499 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 341:28d1f895c6fe 500 /* Configure PFx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 501 GPIOF->MODER = 0xAA000AAA;
mbed_official 341:28d1f895c6fe 502 /* Configure PFx pins speed to 100 MHz */
mbed_official 341:28d1f895c6fe 503 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 341:28d1f895c6fe 504 /* Configure PFx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 505 GPIOF->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 506 /* No pull-up, pull-down for PFx pins */
mbed_official 341:28d1f895c6fe 507 GPIOF->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 508
mbed_official 341:28d1f895c6fe 509 /* Connect PGx pins to FMC Alternate function */
mbed_official 341:28d1f895c6fe 510 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 341:28d1f895c6fe 511 GPIOG->AFR[1] = 0x000000C0;
mbed_official 341:28d1f895c6fe 512 /* Configure PGx pins in Alternate function mode */
mbed_official 341:28d1f895c6fe 513 GPIOG->MODER = 0x00085AAA;
mbed_official 341:28d1f895c6fe 514 /* Configure PGx pins speed to 100 MHz */
mbed_official 341:28d1f895c6fe 515 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 341:28d1f895c6fe 516 /* Configure PGx pins Output type to push-pull */
mbed_official 341:28d1f895c6fe 517 GPIOG->OTYPER = 0x00000000;
mbed_official 341:28d1f895c6fe 518 /* No pull-up, pull-down for PGx pins */
mbed_official 341:28d1f895c6fe 519 GPIOG->PUPDR = 0x00000000;
mbed_official 341:28d1f895c6fe 520
mbed_official 341:28d1f895c6fe 521 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 341:28d1f895c6fe 522 /* Enable the FMC/FSMC interface clock */
mbed_official 341:28d1f895c6fe 523 RCC->AHB3ENR |= 0x00000001;
mbed_official 341:28d1f895c6fe 524
mbed_official 341:28d1f895c6fe 525 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 341:28d1f895c6fe 526 /* Configure and enable Bank1_SRAM2 */
mbed_official 341:28d1f895c6fe 527 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 341:28d1f895c6fe 528 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 341:28d1f895c6fe 529 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 341:28d1f895c6fe 530 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 341:28d1f895c6fe 531
mbed_official 341:28d1f895c6fe 532 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 341:28d1f895c6fe 533 /* Configure and enable Bank1_SRAM2 */
mbed_official 341:28d1f895c6fe 534 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 341:28d1f895c6fe 535 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 341:28d1f895c6fe 536 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 341:28d1f895c6fe 537 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 341:28d1f895c6fe 538
mbed_official 341:28d1f895c6fe 539 #endif /* DATA_IN_ExtSRAM */
mbed_official 341:28d1f895c6fe 540 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 341:28d1f895c6fe 541 }
mbed_official 341:28d1f895c6fe 542 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 441:8a0b45cd594f 543
mbed_official 441:8a0b45cd594f 544 /** System Clock Configuration
mbed_official 441:8a0b45cd594f 545 */
mbed_official 441:8a0b45cd594f 546 #if USE_SYSCLOCK_168 != 0
mbed_official 441:8a0b45cd594f 547 /*
mbed_official 441:8a0b45cd594f 548 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
mbed_official 441:8a0b45cd594f 549 * and SYSCLK=168MHZ
mbed_official 441:8a0b45cd594f 550 */
mbed_official 441:8a0b45cd594f 551 void SystemClock_Config(void)
mbed_official 441:8a0b45cd594f 552 {
mbed_official 441:8a0b45cd594f 553
mbed_official 441:8a0b45cd594f 554 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 441:8a0b45cd594f 555 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 441:8a0b45cd594f 556
mbed_official 441:8a0b45cd594f 557 __PWR_CLK_ENABLE();
mbed_official 441:8a0b45cd594f 558
mbed_official 441:8a0b45cd594f 559 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 441:8a0b45cd594f 560
mbed_official 441:8a0b45cd594f 561 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 441:8a0b45cd594f 562 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
mbed_official 441:8a0b45cd594f 563 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 441:8a0b45cd594f 564 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 441:8a0b45cd594f 565 RCC_OscInitStruct.PLL.PLLM = 8;
mbed_official 441:8a0b45cd594f 566 RCC_OscInitStruct.PLL.PLLN = 336;
mbed_official 441:8a0b45cd594f 567 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
mbed_official 441:8a0b45cd594f 568 RCC_OscInitStruct.PLL.PLLQ = 7;
mbed_official 441:8a0b45cd594f 569 HAL_RCC_OscConfig(&RCC_OscInitStruct);
mbed_official 441:8a0b45cd594f 570
mbed_official 441:8a0b45cd594f 571 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
mbed_official 441:8a0b45cd594f 572 |RCC_CLOCKTYPE_PCLK2;
mbed_official 441:8a0b45cd594f 573 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
mbed_official 441:8a0b45cd594f 574 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
mbed_official 441:8a0b45cd594f 575 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
mbed_official 441:8a0b45cd594f 576 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
mbed_official 441:8a0b45cd594f 577 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
mbed_official 441:8a0b45cd594f 578
mbed_official 441:8a0b45cd594f 579 }
mbed_official 441:8a0b45cd594f 580
mbed_official 441:8a0b45cd594f 581 #elif USE_SYSCLOCK_180 != 0
mbed_official 441:8a0b45cd594f 582 /*
mbed_official 441:8a0b45cd594f 583 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
mbed_official 441:8a0b45cd594f 584 * and SYSCLK=180MHZ
mbed_official 441:8a0b45cd594f 585 */
mbed_official 441:8a0b45cd594f 586 void SystemClock_Config(void)
mbed_official 441:8a0b45cd594f 587 {
mbed_official 441:8a0b45cd594f 588
mbed_official 441:8a0b45cd594f 589 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 441:8a0b45cd594f 590 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 441:8a0b45cd594f 591
mbed_official 441:8a0b45cd594f 592 __PWR_CLK_ENABLE();
mbed_official 441:8a0b45cd594f 593
mbed_official 441:8a0b45cd594f 594 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 441:8a0b45cd594f 595
mbed_official 441:8a0b45cd594f 596 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 441:8a0b45cd594f 597 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
mbed_official 441:8a0b45cd594f 598 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 441:8a0b45cd594f 599 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 441:8a0b45cd594f 600 RCC_OscInitStruct.PLL.PLLM = 8;
mbed_official 441:8a0b45cd594f 601 RCC_OscInitStruct.PLL.PLLN = 360;
mbed_official 441:8a0b45cd594f 602 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
mbed_official 441:8a0b45cd594f 603 RCC_OscInitStruct.PLL.PLLQ = 7;
mbed_official 441:8a0b45cd594f 604 HAL_RCC_OscConfig(&RCC_OscInitStruct);
mbed_official 441:8a0b45cd594f 605
mbed_official 441:8a0b45cd594f 606 HAL_PWREx_ActivateOverDrive();
mbed_official 441:8a0b45cd594f 607
mbed_official 441:8a0b45cd594f 608 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
mbed_official 441:8a0b45cd594f 609 |RCC_CLOCKTYPE_PCLK2;
mbed_official 441:8a0b45cd594f 610 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
mbed_official 441:8a0b45cd594f 611 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
mbed_official 441:8a0b45cd594f 612 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
mbed_official 441:8a0b45cd594f 613 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
mbed_official 441:8a0b45cd594f 614 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
mbed_official 441:8a0b45cd594f 615
mbed_official 441:8a0b45cd594f 616 }
mbed_official 441:8a0b45cd594f 617 #endif
mbed_official 441:8a0b45cd594f 618
mbed_official 341:28d1f895c6fe 619 /**
mbed_official 341:28d1f895c6fe 620 * @}
mbed_official 341:28d1f895c6fe 621 */
mbed_official 341:28d1f895c6fe 622
mbed_official 341:28d1f895c6fe 623 /**
mbed_official 341:28d1f895c6fe 624 * @}
mbed_official 341:28d1f895c6fe 625 */
mbed_official 341:28d1f895c6fe 626
mbed_official 341:28d1f895c6fe 627 /**
mbed_official 341:28d1f895c6fe 628 * @}
mbed_official 341:28d1f895c6fe 629 */
mbed_official 341:28d1f895c6fe 630 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/