Robert Lopez
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CMSIS5
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core_sc000.h
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00001 /**************************************************************************//** 00002 * @file core_sc000.h 00003 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 00004 * @version V5.0.3 00005 * @date 10. January 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_SC000_H_GENERIC 00032 #define __CORE_SC000_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup SC000 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS SC000 definitions */ 00066 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ 00069 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_SC (000U) /*!< Cortex secure core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_PCS_VFP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_SC000_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_SC000_H_DEPENDANT 00127 #define __CORE_SC000_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __SC000_REV 00136 #define __SC000_REV 0x0000U 00137 #warning "__SC000_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __MPU_PRESENT 00141 #define __MPU_PRESENT 0U 00142 #warning "__MPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __NVIC_PRIO_BITS 00146 #define __NVIC_PRIO_BITS 2U 00147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __Vendor_SysTickConfig 00151 #define __Vendor_SysTickConfig 0U 00152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00153 #endif 00154 #endif 00155 00156 /* IO definitions (access restrictions to peripheral registers) */ 00157 /** 00158 \defgroup CMSIS_glob_defs CMSIS Global Defines 00159 00160 <strong>IO Type Qualifiers</strong> are used 00161 \li to specify the access to peripheral variables. 00162 \li for automatic generation of peripheral register debug information. 00163 */ 00164 #ifdef __cplusplus 00165 #define __I volatile /*!< Defines 'read only' permissions */ 00166 #else 00167 #define __I volatile const /*!< Defines 'read only' permissions */ 00168 #endif 00169 #define __O volatile /*!< Defines 'write only' permissions */ 00170 #define __IO volatile /*!< Defines 'read / write' permissions */ 00171 00172 /* following defines should be used for structure members */ 00173 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00174 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00176 00177 /*@} end of group SC000 */ 00178 00179 00180 00181 /******************************************************************************* 00182 * Register Abstraction 00183 Core Register contain: 00184 - Core Register 00185 - Core NVIC Register 00186 - Core SCB Register 00187 - Core SysTick Register 00188 - Core MPU Register 00189 ******************************************************************************/ 00190 /** 00191 \defgroup CMSIS_core_register Defines and Type Definitions 00192 \brief Type definitions and defines for Cortex-M processor based devices. 00193 */ 00194 00195 /** 00196 \ingroup CMSIS_core_register 00197 \defgroup CMSIS_CORE Status and Control Registers 00198 \brief Core Register type definitions. 00199 @{ 00200 */ 00201 00202 /** 00203 \brief Union type to access the Application Program Status Register (APSR). 00204 */ 00205 typedef union 00206 { 00207 struct 00208 { 00209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00214 } b; /*!< Structure used for bit access */ 00215 uint32_t w; /*!< Type used for word access */ 00216 } APSR_Type; 00217 00218 /* APSR Register Definitions */ 00219 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00221 00222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00224 00225 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00227 00228 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00230 00231 00232 /** 00233 \brief Union type to access the Interrupt Program Status Register (IPSR). 00234 */ 00235 typedef union 00236 { 00237 struct 00238 { 00239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00241 } b; /*!< Structure used for bit access */ 00242 uint32_t w; /*!< Type used for word access */ 00243 } IPSR_Type; 00244 00245 /* IPSR Register Definitions */ 00246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00248 00249 00250 /** 00251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00252 */ 00253 typedef union 00254 { 00255 struct 00256 { 00257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00265 } b; /*!< Structure used for bit access */ 00266 uint32_t w; /*!< Type used for word access */ 00267 } xPSR_Type; 00268 00269 /* xPSR Register Definitions */ 00270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00272 00273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00275 00276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00278 00279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00281 00282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00284 00285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00287 00288 00289 /** 00290 \brief Union type to access the Control Registers (CONTROL). 00291 */ 00292 typedef union 00293 { 00294 struct 00295 { 00296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 00297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00299 } b; /*!< Structure used for bit access */ 00300 uint32_t w; /*!< Type used for word access */ 00301 } CONTROL_Type; 00302 00303 /* CONTROL Register Definitions */ 00304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00306 00307 /*@} end of group CMSIS_CORE */ 00308 00309 00310 /** 00311 \ingroup CMSIS_core_register 00312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00313 \brief Type definitions for the NVIC Registers 00314 @{ 00315 */ 00316 00317 /** 00318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00319 */ 00320 typedef struct 00321 { 00322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00323 uint32_t RESERVED0[31U]; 00324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00325 uint32_t RSERVED1[31U]; 00326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00327 uint32_t RESERVED2[31U]; 00328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00329 uint32_t RESERVED3[31U]; 00330 uint32_t RESERVED4[64U]; 00331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00332 } NVIC_Type; 00333 00334 /*@} end of group CMSIS_NVIC */ 00335 00336 00337 /** 00338 \ingroup CMSIS_core_register 00339 \defgroup CMSIS_SCB System Control Block (SCB) 00340 \brief Type definitions for the System Control Block Registers 00341 @{ 00342 */ 00343 00344 /** 00345 \brief Structure type to access the System Control Block (SCB). 00346 */ 00347 typedef struct 00348 { 00349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00355 uint32_t RESERVED0[1U]; 00356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00358 uint32_t RESERVED1[154U]; 00359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ 00360 } SCB_Type; 00361 00362 /* SCB CPUID Register Definitions */ 00363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00365 00366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00368 00369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00371 00372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00374 00375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00377 00378 /* SCB Interrupt Control State Register Definitions */ 00379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00381 00382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00384 00385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00387 00388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00390 00391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00393 00394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00396 00397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00399 00400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00402 00403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00405 00406 /* SCB Interrupt Control State Register Definitions */ 00407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00409 00410 /* SCB Application Interrupt and Reset Control Register Definitions */ 00411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00413 00414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00416 00417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00419 00420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00422 00423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00425 00426 /* SCB System Control Register Definitions */ 00427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00429 00430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00432 00433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00435 00436 /* SCB Configuration Control Register Definitions */ 00437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00439 00440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00442 00443 /* SCB System Handler Control and State Register Definitions */ 00444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00446 00447 /*@} end of group CMSIS_SCB */ 00448 00449 00450 /** 00451 \ingroup CMSIS_core_register 00452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00453 \brief Type definitions for the System Control and ID Register not in the SCB 00454 @{ 00455 */ 00456 00457 /** 00458 \brief Structure type to access the System Control and ID Register not in the SCB. 00459 */ 00460 typedef struct 00461 { 00462 uint32_t RESERVED0[2U]; 00463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00464 } SCnSCB_Type; 00465 00466 /* Auxiliary Control Register Definitions */ 00467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00469 00470 /*@} end of group CMSIS_SCnotSCB */ 00471 00472 00473 /** 00474 \ingroup CMSIS_core_register 00475 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00476 \brief Type definitions for the System Timer Registers. 00477 @{ 00478 */ 00479 00480 /** 00481 \brief Structure type to access the System Timer (SysTick). 00482 */ 00483 typedef struct 00484 { 00485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00489 } SysTick_Type; 00490 00491 /* SysTick Control / Status Register Definitions */ 00492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00494 00495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00497 00498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00500 00501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00503 00504 /* SysTick Reload Register Definitions */ 00505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00507 00508 /* SysTick Current Register Definitions */ 00509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00511 00512 /* SysTick Calibration Register Definitions */ 00513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00515 00516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00518 00519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00521 00522 /*@} end of group CMSIS_SysTick */ 00523 00524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00525 /** 00526 \ingroup CMSIS_core_register 00527 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00528 \brief Type definitions for the Memory Protection Unit (MPU) 00529 @{ 00530 */ 00531 00532 /** 00533 \brief Structure type to access the Memory Protection Unit (MPU). 00534 */ 00535 typedef struct 00536 { 00537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00542 } MPU_Type; 00543 00544 /* MPU Type Register Definitions */ 00545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00547 00548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00550 00551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00553 00554 /* MPU Control Register Definitions */ 00555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00557 00558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00560 00561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00563 00564 /* MPU Region Number Register Definitions */ 00565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00567 00568 /* MPU Region Base Address Register Definitions */ 00569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 00570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00571 00572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 00573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00574 00575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 00576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 00577 00578 /* MPU Region Attribute and Size Register Definitions */ 00579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 00580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00581 00582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 00583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00584 00585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 00586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00587 00588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 00589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00590 00591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 00592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00593 00594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 00595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00596 00597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 00598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00599 00600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 00601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00602 00603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 00604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00605 00606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 00607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 00608 00609 /*@} end of group CMSIS_MPU */ 00610 #endif 00611 00612 00613 /** 00614 \ingroup CMSIS_core_register 00615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 00617 Therefore they are not covered by the SC000 header file. 00618 @{ 00619 */ 00620 /*@} end of group CMSIS_CoreDebug */ 00621 00622 00623 /** 00624 \ingroup CMSIS_core_register 00625 \defgroup CMSIS_core_bitfield Core register bit field macros 00626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 00627 @{ 00628 */ 00629 00630 /** 00631 \brief Mask and shift a bit field value for use in a register bit range. 00632 \param[in] field Name of the register bit field. 00633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 00634 \return Masked and shifted value. 00635 */ 00636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 00637 00638 /** 00639 \brief Mask and shift a register value to extract a bit filed value. 00640 \param[in] field Name of the register bit field. 00641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 00642 \return Masked and shifted bit field value. 00643 */ 00644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 00645 00646 /*@} end of group CMSIS_core_bitfield */ 00647 00648 00649 /** 00650 \ingroup CMSIS_core_register 00651 \defgroup CMSIS_core_base Core Definitions 00652 \brief Definitions for base addresses, unions, and structures. 00653 @{ 00654 */ 00655 00656 /* Memory mapping of Core Hardware */ 00657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00661 00662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 00663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00666 00667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00670 #endif 00671 00672 /*@} */ 00673 00674 00675 00676 /******************************************************************************* 00677 * Hardware Abstraction Layer 00678 Core Function Interface contains: 00679 - Core NVIC Functions 00680 - Core SysTick Functions 00681 - Core Register Access Functions 00682 ******************************************************************************/ 00683 /** 00684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00685 */ 00686 00687 00688 00689 /* ########################## NVIC functions #################################### */ 00690 /** 00691 \ingroup CMSIS_Core_FunctionInterface 00692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00693 \brief Functions that manage interrupts and exceptions via the NVIC. 00694 @{ 00695 */ 00696 00697 #ifdef CMSIS_NVIC_VIRTUAL 00698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 00699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 00700 #endif 00701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 00702 #else 00703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ 00704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ 00705 #define NVIC_EnableIRQ __NVIC_EnableIRQ 00706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 00707 #define NVIC_DisableIRQ __NVIC_DisableIRQ 00708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 00709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 00710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 00711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ 00712 #define NVIC_SetPriority __NVIC_SetPriority 00713 #define NVIC_GetPriority __NVIC_GetPriority 00714 #define NVIC_SystemReset __NVIC_SystemReset 00715 #endif /* CMSIS_NVIC_VIRTUAL */ 00716 00717 #ifdef CMSIS_VECTAB_VIRTUAL 00718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 00720 #endif 00721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00722 #else 00723 #define NVIC_SetVector __NVIC_SetVector 00724 #define NVIC_GetVector __NVIC_GetVector 00725 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 00726 00727 #define NVIC_USER_IRQ_OFFSET 16 00728 00729 00730 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 00731 /* The following MACROS handle generation of the register offset and byte masks */ 00732 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00733 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00734 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00735 00736 00737 /** 00738 \brief Enable Interrupt 00739 \details Enables a device specific interrupt in the NVIC interrupt controller. 00740 \param [in] IRQn Device specific interrupt number. 00741 \note IRQn must not be negative. 00742 */ 00743 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 00744 { 00745 if ((int32_t)(IRQn) >= 0) 00746 { 00747 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00748 } 00749 } 00750 00751 00752 /** 00753 \brief Get Interrupt Enable status 00754 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 00755 \param [in] IRQn Device specific interrupt number. 00756 \return 0 Interrupt is not enabled. 00757 \return 1 Interrupt is enabled. 00758 \note IRQn must not be negative. 00759 */ 00760 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 00761 { 00762 if ((int32_t)(IRQn) >= 0) 00763 { 00764 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00765 } 00766 else 00767 { 00768 return(0U); 00769 } 00770 } 00771 00772 00773 /** 00774 \brief Disable Interrupt 00775 \details Disables a device specific interrupt in the NVIC interrupt controller. 00776 \param [in] IRQn Device specific interrupt number. 00777 \note IRQn must not be negative. 00778 */ 00779 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 00780 { 00781 if ((int32_t)(IRQn) >= 0) 00782 { 00783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00784 __DSB(); 00785 __ISB(); 00786 } 00787 } 00788 00789 00790 /** 00791 \brief Get Pending Interrupt 00792 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 00793 \param [in] IRQn Device specific interrupt number. 00794 \return 0 Interrupt status is not pending. 00795 \return 1 Interrupt status is pending. 00796 \note IRQn must not be negative. 00797 */ 00798 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 00799 { 00800 if ((int32_t)(IRQn) >= 0) 00801 { 00802 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00803 } 00804 else 00805 { 00806 return(0U); 00807 } 00808 } 00809 00810 00811 /** 00812 \brief Set Pending Interrupt 00813 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 00814 \param [in] IRQn Device specific interrupt number. 00815 \note IRQn must not be negative. 00816 */ 00817 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 00818 { 00819 if ((int32_t)(IRQn) >= 0) 00820 { 00821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00822 } 00823 } 00824 00825 00826 /** 00827 \brief Clear Pending Interrupt 00828 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 00829 \param [in] IRQn Device specific interrupt number. 00830 \note IRQn must not be negative. 00831 */ 00832 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00833 { 00834 if ((int32_t)(IRQn) >= 0) 00835 { 00836 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00837 } 00838 } 00839 00840 00841 /** 00842 \brief Set Interrupt Priority 00843 \details Sets the priority of a device specific interrupt or a processor exception. 00844 The interrupt number can be positive to specify a device specific interrupt, 00845 or negative to specify a processor exception. 00846 \param [in] IRQn Interrupt number. 00847 \param [in] priority Priority to set. 00848 \note The priority cannot be set for every processor exception. 00849 */ 00850 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00851 { 00852 if ((int32_t)(IRQn) >= 0) 00853 { 00854 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00855 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00856 } 00857 else 00858 { 00859 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00860 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00861 } 00862 } 00863 00864 00865 /** 00866 \brief Get Interrupt Priority 00867 \details Reads the priority of a device specific interrupt or a processor exception. 00868 The interrupt number can be positive to specify a device specific interrupt, 00869 or negative to specify a processor exception. 00870 \param [in] IRQn Interrupt number. 00871 \return Interrupt Priority. 00872 Value is aligned automatically to the implemented priority bits of the microcontroller. 00873 */ 00874 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 00875 { 00876 00877 if ((int32_t)(IRQn) >= 0) 00878 { 00879 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00880 } 00881 else 00882 { 00883 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00884 } 00885 } 00886 00887 00888 /** 00889 \brief Set Interrupt Vector 00890 \details Sets an interrupt vector in SRAM based interrupt vector table. 00891 The interrupt number can be positive to specify a device specific interrupt, 00892 or negative to specify a processor exception. 00893 VTOR must been relocated to SRAM before. 00894 \param [in] IRQn Interrupt number 00895 \param [in] vector Address of interrupt handler function 00896 */ 00897 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 00898 { 00899 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00900 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 00901 } 00902 00903 00904 /** 00905 \brief Get Interrupt Vector 00906 \details Reads an interrupt vector from interrupt vector table. 00907 The interrupt number can be positive to specify a device specific interrupt, 00908 or negative to specify a processor exception. 00909 \param [in] IRQn Interrupt number. 00910 \return Address of interrupt handler function 00911 */ 00912 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 00913 { 00914 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00915 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 00916 } 00917 00918 00919 /** 00920 \brief System Reset 00921 \details Initiates a system reset request to reset the MCU. 00922 */ 00923 __STATIC_INLINE void __NVIC_SystemReset(void) 00924 { 00925 __DSB(); /* Ensure all outstanding memory accesses included 00926 buffered write are completed before reset */ 00927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00928 SCB_AIRCR_SYSRESETREQ_Msk); 00929 __DSB(); /* Ensure completion of memory access */ 00930 00931 for(;;) /* wait until reset */ 00932 { 00933 __NOP(); 00934 } 00935 } 00936 00937 /*@} end of CMSIS_Core_NVICFunctions */ 00938 00939 00940 /* ########################## FPU functions #################################### */ 00941 /** 00942 \ingroup CMSIS_Core_FunctionInterface 00943 \defgroup CMSIS_Core_FpuFunctions FPU Functions 00944 \brief Function that provides FPU type. 00945 @{ 00946 */ 00947 00948 /** 00949 \brief get FPU type 00950 \details returns the FPU type 00951 \returns 00952 - \b 0: No FPU 00953 - \b 1: Single precision FPU 00954 - \b 2: Double + Single precision FPU 00955 */ 00956 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 00957 { 00958 return 0U; /* No FPU */ 00959 } 00960 00961 00962 /*@} end of CMSIS_Core_FpuFunctions */ 00963 00964 00965 00966 /* ################################## SysTick function ############################################ */ 00967 /** 00968 \ingroup CMSIS_Core_FunctionInterface 00969 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00970 \brief Functions that configure the System. 00971 @{ 00972 */ 00973 00974 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 00975 00976 /** 00977 \brief System Tick Configuration 00978 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 00979 Counter is in free running mode to generate periodic interrupts. 00980 \param [in] ticks Number of ticks between two interrupts. 00981 \return 0 Function succeeded. 00982 \return 1 Function failed. 00983 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00984 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00985 must contain a vendor-specific implementation of this function. 00986 */ 00987 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00988 { 00989 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 00990 { 00991 return (1UL); /* Reload value impossible */ 00992 } 00993 00994 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 00995 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 00996 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00997 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00998 SysTick_CTRL_TICKINT_Msk | 00999 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01000 return (0UL); /* Function successful */ 01001 } 01002 01003 #endif 01004 01005 /*@} end of CMSIS_Core_SysTickFunctions */ 01006 01007 01008 01009 01010 #ifdef __cplusplus 01011 } 01012 #endif 01013 01014 #endif /* __CORE_SC000_H_DEPENDANT */ 01015 01016 #endif /* __CMSIS_GENERIC */ 01017
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