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core_cm4.h

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00001 /**************************************************************************//**
00002  * @file     core_cm4.h
00003  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
00004  * @version  V5.0.5
00005  * @date     08. January 2018
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024 
00025 #if   defined ( __ICCARM__ )
00026   #pragma system_include         /* treat file as system include file for MISRA check */
00027 #elif defined (__clang__)
00028   #pragma clang system_header   /* treat file as system include file */
00029 #endif
00030 
00031 #ifndef __CORE_CM4_H_GENERIC
00032 #define __CORE_CM4_H_GENERIC
00033 
00034 #include <stdint.h>
00035 
00036 #ifdef __cplusplus
00037  extern "C" {
00038 #endif
00039 
00040 /**
00041   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00042   CMSIS violates the following MISRA-C:2004 rules:
00043 
00044    \li Required Rule 8.5, object/function definition in header file.<br>
00045      Function definitions in header files are used to allow 'inlining'.
00046 
00047    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00048      Unions are used for effective representation of core registers.
00049 
00050    \li Advisory Rule 19.7, Function-like macro defined.<br>
00051      Function-like macros are used to allow more efficient code.
00052  */
00053 
00054 
00055 /*******************************************************************************
00056  *                 CMSIS definitions
00057  ******************************************************************************/
00058 /**
00059   \ingroup Cortex_M4
00060   @{
00061  */
00062 
00063 #include "cmsis_version.h"
00064  
00065 /* CMSIS CM4 definitions */
00066 #define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
00067 #define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
00068 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
00069                                     __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
00070 
00071 #define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
00072 
00073 /** __FPU_USED indicates whether an FPU is used or not.
00074     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
00075 */
00076 #if defined ( __CC_ARM )
00077   #if defined __TARGET_FPU_VFP
00078     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00079       #define __FPU_USED       1U
00080     #else
00081       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00082       #define __FPU_USED       0U
00083     #endif
00084   #else
00085     #define __FPU_USED         0U
00086   #endif
00087 
00088 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
00089   #if defined __ARM_PCS_VFP
00090     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00091       #define __FPU_USED       1U
00092     #else
00093       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00094       #define __FPU_USED       0U
00095     #endif
00096   #else
00097     #define __FPU_USED         0U
00098   #endif
00099 
00100 #elif defined ( __GNUC__ )
00101   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00102     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00103       #define __FPU_USED       1U
00104     #else
00105       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00106       #define __FPU_USED       0U
00107     #endif
00108   #else
00109     #define __FPU_USED         0U
00110   #endif
00111 
00112 #elif defined ( __ICCARM__ )
00113   #if defined __ARMVFP__
00114     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00115       #define __FPU_USED       1U
00116     #else
00117       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00118       #define __FPU_USED       0U
00119     #endif
00120   #else
00121     #define __FPU_USED         0U
00122   #endif
00123 
00124 #elif defined ( __TI_ARM__ )
00125   #if defined __TI_VFP_SUPPORT__
00126     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00127       #define __FPU_USED       1U
00128     #else
00129       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00130       #define __FPU_USED       0U
00131     #endif
00132   #else
00133     #define __FPU_USED         0U
00134   #endif
00135 
00136 #elif defined ( __TASKING__ )
00137   #if defined __FPU_VFP__
00138     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00139       #define __FPU_USED       1U
00140     #else
00141       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00142       #define __FPU_USED       0U
00143     #endif
00144   #else
00145     #define __FPU_USED         0U
00146   #endif
00147 
00148 #elif defined ( __CSMC__ )
00149   #if ( __CSMC__ & 0x400U)
00150     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
00151       #define __FPU_USED       1U
00152     #else
00153       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00154       #define __FPU_USED       0U
00155     #endif
00156   #else
00157     #define __FPU_USED         0U
00158   #endif
00159 
00160 #endif
00161 
00162 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
00163 
00164 
00165 #ifdef __cplusplus
00166 }
00167 #endif
00168 
00169 #endif /* __CORE_CM4_H_GENERIC */
00170 
00171 #ifndef __CMSIS_GENERIC
00172 
00173 #ifndef __CORE_CM4_H_DEPENDANT
00174 #define __CORE_CM4_H_DEPENDANT
00175 
00176 #ifdef __cplusplus
00177  extern "C" {
00178 #endif
00179 
00180 /* check device defines and use defaults */
00181 #if defined __CHECK_DEVICE_DEFINES
00182   #ifndef __CM4_REV
00183     #define __CM4_REV               0x0000U
00184     #warning "__CM4_REV not defined in device header file; using default!"
00185   #endif
00186 
00187   #ifndef __FPU_PRESENT
00188     #define __FPU_PRESENT             0U
00189     #warning "__FPU_PRESENT not defined in device header file; using default!"
00190   #endif
00191 
00192   #ifndef __MPU_PRESENT
00193     #define __MPU_PRESENT             0U
00194     #warning "__MPU_PRESENT not defined in device header file; using default!"
00195   #endif
00196 
00197   #ifndef __NVIC_PRIO_BITS
00198     #define __NVIC_PRIO_BITS          3U
00199     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00200   #endif
00201 
00202   #ifndef __Vendor_SysTickConfig
00203     #define __Vendor_SysTickConfig    0U
00204     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00205   #endif
00206 #endif
00207 
00208 /* IO definitions (access restrictions to peripheral registers) */
00209 /**
00210     \defgroup CMSIS_glob_defs CMSIS Global Defines
00211 
00212     <strong>IO Type Qualifiers</strong> are used
00213     \li to specify the access to peripheral variables.
00214     \li for automatic generation of peripheral register debug information.
00215 */
00216 #ifdef __cplusplus
00217   #define   __I     volatile             /*!< Defines 'read only' permissions */
00218 #else
00219   #define   __I     volatile const       /*!< Defines 'read only' permissions */
00220 #endif
00221 #define     __O     volatile             /*!< Defines 'write only' permissions */
00222 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
00223 
00224 /* following defines should be used for structure members */
00225 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
00226 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
00227 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
00228 
00229 /*@} end of group Cortex_M4 */
00230 
00231 
00232 
00233 /*******************************************************************************
00234  *                 Register Abstraction
00235   Core Register contain:
00236   - Core Register
00237   - Core NVIC Register
00238   - Core SCB Register
00239   - Core SysTick Register
00240   - Core Debug Register
00241   - Core MPU Register
00242   - Core FPU Register
00243  ******************************************************************************/
00244 /**
00245   \defgroup CMSIS_core_register Defines and Type Definitions
00246   \brief Type definitions and defines for Cortex-M processor based devices.
00247 */
00248 
00249 /**
00250   \ingroup    CMSIS_core_register
00251   \defgroup   CMSIS_CORE  Status and Control Registers
00252   \brief      Core Register type definitions.
00253   @{
00254  */
00255 
00256 /**
00257   \brief  Union type to access the Application Program Status Register (APSR).
00258  */
00259 typedef union
00260 {
00261   struct
00262   {
00263     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
00264     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
00265     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
00266     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
00267     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00268     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00269     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00270     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00271   } b;                                   /*!< Structure used for bit  access */
00272   uint32_t w;                            /*!< Type      used for word access */
00273 } APSR_Type;
00274 
00275 /* APSR Register Definitions */
00276 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
00277 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
00278 
00279 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
00280 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
00281 
00282 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
00283 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
00284 
00285 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
00286 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
00287 
00288 #define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
00289 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
00290 
00291 #define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
00292 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
00293 
00294 
00295 /**
00296   \brief  Union type to access the Interrupt Program Status Register (IPSR).
00297  */
00298 typedef union
00299 {
00300   struct
00301   {
00302     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00303     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
00304   } b;                                   /*!< Structure used for bit  access */
00305   uint32_t w;                            /*!< Type      used for word access */
00306 } IPSR_Type;
00307 
00308 /* IPSR Register Definitions */
00309 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
00310 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
00311 
00312 
00313 /**
00314   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00315  */
00316 typedef union
00317 {
00318   struct
00319   {
00320     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00321     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
00322     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
00323     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
00324     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
00325     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
00326     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
00327     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
00328     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00329     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00330     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00331     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00332   } b;                                   /*!< Structure used for bit  access */
00333   uint32_t w;                            /*!< Type      used for word access */
00334 } xPSR_Type;
00335 
00336 /* xPSR Register Definitions */
00337 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
00338 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
00339 
00340 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
00341 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
00342 
00343 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
00344 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
00345 
00346 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
00347 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
00348 
00349 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
00350 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
00351 
00352 #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
00353 #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
00354 
00355 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
00356 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
00357 
00358 #define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
00359 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
00360 
00361 #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
00362 #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
00363 
00364 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
00365 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
00366 
00367 
00368 /**
00369   \brief  Union type to access the Control Registers (CONTROL).
00370  */
00371 typedef union
00372 {
00373   struct
00374   {
00375     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00376     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
00377     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
00378     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
00379   } b;                                   /*!< Structure used for bit  access */
00380   uint32_t w;                            /*!< Type      used for word access */
00381 } CONTROL_Type;
00382 
00383 /* CONTROL Register Definitions */
00384 #define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
00385 #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
00386 
00387 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
00388 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
00389 
00390 #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
00391 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
00392 
00393 /*@} end of group CMSIS_CORE */
00394 
00395 
00396 /**
00397   \ingroup    CMSIS_core_register
00398   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00399   \brief      Type definitions for the NVIC Registers
00400   @{
00401  */
00402 
00403 /**
00404   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00405  */
00406 typedef struct
00407 {
00408   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
00409         uint32_t RESERVED0[24U];
00410   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
00411         uint32_t RSERVED1[24U];
00412   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
00413         uint32_t RESERVED2[24U];
00414   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
00415         uint32_t RESERVED3[24U];
00416   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
00417         uint32_t RESERVED4[56U];
00418   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00419         uint32_t RESERVED5[644U];
00420   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
00421 }  NVIC_Type;
00422 
00423 /* Software Triggered Interrupt Register Definitions */
00424 #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
00425 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
00426 
00427 /*@} end of group CMSIS_NVIC */
00428 
00429 
00430 /**
00431   \ingroup  CMSIS_core_register
00432   \defgroup CMSIS_SCB     System Control Block (SCB)
00433   \brief    Type definitions for the System Control Block Registers
00434   @{
00435  */
00436 
00437 /**
00438   \brief  Structure type to access the System Control Block (SCB).
00439  */
00440 typedef struct
00441 {
00442   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
00443   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
00444   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
00445   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
00446   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
00447   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
00448   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00449   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
00450   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
00451   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
00452   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
00453   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
00454   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
00455   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
00456   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
00457   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
00458   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
00459   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
00460   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
00461         uint32_t RESERVED0[5U];
00462   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
00463 } SCB_Type;
00464 
00465 /* SCB CPUID Register Definitions */
00466 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
00467 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00468 
00469 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
00470 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00471 
00472 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
00473 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00474 
00475 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
00476 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00477 
00478 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
00479 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
00480 
00481 /* SCB Interrupt Control State Register Definitions */
00482 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
00483 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00484 
00485 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
00486 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00487 
00488 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
00489 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00490 
00491 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
00492 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00493 
00494 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
00495 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00496 
00497 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
00498 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00499 
00500 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
00501 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00502 
00503 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
00504 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00505 
00506 #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
00507 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00508 
00509 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
00510 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
00511 
00512 /* SCB Vector Table Offset Register Definitions */
00513 #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
00514 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00515 
00516 /* SCB Application Interrupt and Reset Control Register Definitions */
00517 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
00518 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00519 
00520 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
00521 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00522 
00523 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
00524 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00525 
00526 #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
00527 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00528 
00529 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
00530 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00531 
00532 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
00533 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00534 
00535 #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
00536 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
00537 
00538 /* SCB System Control Register Definitions */
00539 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
00540 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00541 
00542 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
00543 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00544 
00545 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
00546 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00547 
00548 /* SCB Configuration Control Register Definitions */
00549 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
00550 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00551 
00552 #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
00553 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00554 
00555 #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
00556 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00557 
00558 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
00559 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00560 
00561 #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
00562 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00563 
00564 #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
00565 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
00566 
00567 /* SCB System Handler Control and State Register Definitions */
00568 #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
00569 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00570 
00571 #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
00572 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00573 
00574 #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
00575 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00576 
00577 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
00578 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00579 
00580 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
00581 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00582 
00583 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
00584 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00585 
00586 #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
00587 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00588 
00589 #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
00590 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00591 
00592 #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
00593 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00594 
00595 #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
00596 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00597 
00598 #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
00599 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00600 
00601 #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
00602 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00603 
00604 #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
00605 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00606 
00607 #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
00608 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
00609 
00610 /* SCB Configurable Fault Status Register Definitions */
00611 #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
00612 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00613 
00614 #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
00615 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00616 
00617 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00618 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00619 
00620 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
00621 #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
00622 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
00623 
00624 #define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
00625 #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
00626 
00627 #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
00628 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
00629 
00630 #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
00631 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
00632 
00633 #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
00634 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
00635 
00636 #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
00637 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
00638 
00639 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
00640 #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
00641 #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
00642 
00643 #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
00644 #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
00645 
00646 #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
00647 #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
00648 
00649 #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
00650 #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
00651 
00652 #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
00653 #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
00654 
00655 #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
00656 #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
00657 
00658 #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
00659 #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
00660 
00661 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
00662 #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
00663 #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
00664 
00665 #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
00666 #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
00667 
00668 #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
00669 #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
00670 
00671 #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
00672 #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
00673 
00674 #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
00675 #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
00676 
00677 #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
00678 #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
00679 
00680 /* SCB Hard Fault Status Register Definitions */
00681 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
00682 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00683 
00684 #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
00685 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00686 
00687 #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
00688 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00689 
00690 /* SCB Debug Fault Status Register Definitions */
00691 #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
00692 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00693 
00694 #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
00695 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00696 
00697 #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
00698 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00699 
00700 #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
00701 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00702 
00703 #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
00704 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
00705 
00706 /*@} end of group CMSIS_SCB */
00707 
00708 
00709 /**
00710   \ingroup  CMSIS_core_register
00711   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00712   \brief    Type definitions for the System Control and ID Register not in the SCB
00713   @{
00714  */
00715 
00716 /**
00717   \brief  Structure type to access the System Control and ID Register not in the SCB.
00718  */
00719 typedef struct
00720 {
00721         uint32_t RESERVED0[1U];
00722   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
00723   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
00724 } SCnSCB_Type;
00725 
00726 /* Interrupt Controller Type Register Definitions */
00727 #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
00728 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
00729 
00730 /* Auxiliary Control Register Definitions */
00731 #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
00732 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
00733 
00734 #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
00735 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
00736 
00737 #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
00738 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00739 
00740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
00741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00742 
00743 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
00744 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
00745 
00746 /*@} end of group CMSIS_SCnotSCB */
00747 
00748 
00749 /**
00750   \ingroup  CMSIS_core_register
00751   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00752   \brief    Type definitions for the System Timer Registers.
00753   @{
00754  */
00755 
00756 /**
00757   \brief  Structure type to access the System Timer (SysTick).
00758  */
00759 typedef struct
00760 {
00761   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00762   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
00763   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
00764   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
00765 } SysTick_Type;
00766 
00767 /* SysTick Control / Status Register Definitions */
00768 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
00769 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00770 
00771 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
00772 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00773 
00774 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
00775 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00776 
00777 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
00778 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
00779 
00780 /* SysTick Reload Register Definitions */
00781 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
00782 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
00783 
00784 /* SysTick Current Register Definitions */
00785 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
00786 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
00787 
00788 /* SysTick Calibration Register Definitions */
00789 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
00790 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00791 
00792 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
00793 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00794 
00795 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
00796 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
00797 
00798 /*@} end of group CMSIS_SysTick */
00799 
00800 
00801 /**
00802   \ingroup  CMSIS_core_register
00803   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00804   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
00805   @{
00806  */
00807 
00808 /**
00809   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00810  */
00811 typedef struct
00812 {
00813   __OM  union
00814   {
00815     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
00816     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
00817     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
00818   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
00819         uint32_t RESERVED0[864U];
00820   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
00821         uint32_t RESERVED1[15U];
00822   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
00823         uint32_t RESERVED2[15U];
00824   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
00825         uint32_t RESERVED3[29U];
00826   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
00827   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
00828   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
00829         uint32_t RESERVED4[43U];
00830   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
00831   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
00832         uint32_t RESERVED5[6U];
00833   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00834   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00835   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00836   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00837   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00838   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00839   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00840   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00841   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00842   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00843   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00844   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00845 } ITM_Type;
00846 
00847 /* ITM Trace Privilege Register Definitions */
00848 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
00849 #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
00850 
00851 /* ITM Trace Control Register Definitions */
00852 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
00853 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00854 
00855 #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
00856 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00857 
00858 #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
00859 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00860 
00861 #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
00862 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00863 
00864 #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
00865 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00866 
00867 #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
00868 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00869 
00870 #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
00871 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00872 
00873 #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
00874 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00875 
00876 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
00877 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
00878 
00879 /* ITM Integration Write Register Definitions */
00880 #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
00881 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
00882 
00883 /* ITM Integration Read Register Definitions */
00884 #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
00885 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
00886 
00887 /* ITM Integration Mode Control Register Definitions */
00888 #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
00889 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
00890 
00891 /* ITM Lock Status Register Definitions */
00892 #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
00893 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00894 
00895 #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
00896 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00897 
00898 #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
00899 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
00900 
00901 /*@}*/ /* end of group CMSIS_ITM */
00902 
00903 
00904 /**
00905   \ingroup  CMSIS_core_register
00906   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00907   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
00908   @{
00909  */
00910 
00911 /**
00912   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00913  */
00914 typedef struct
00915 {
00916   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
00917   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
00918   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
00919   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
00920   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
00921   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
00922   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
00923   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
00924   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
00925   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
00926   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
00927         uint32_t RESERVED0[1U];
00928   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
00929   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
00930   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
00931         uint32_t RESERVED1[1U];
00932   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
00933   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
00934   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
00935         uint32_t RESERVED2[1U];
00936   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
00937   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
00938   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
00939 } DWT_Type;
00940 
00941 /* DWT Control Register Definitions */
00942 #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
00943 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00944 
00945 #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
00946 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00947 
00948 #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
00949 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00950 
00951 #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
00952 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00953 
00954 #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
00955 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00956 
00957 #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
00958 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00959 
00960 #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
00961 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00962 
00963 #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
00964 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00965 
00966 #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
00967 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00968 
00969 #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
00970 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00971 
00972 #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
00973 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00974 
00975 #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
00976 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00977 
00978 #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
00979 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00980 
00981 #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
00982 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00983 
00984 #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
00985 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00986 
00987 #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
00988 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00989 
00990 #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
00991 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00992 
00993 #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
00994 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
00995 
00996 /* DWT CPI Count Register Definitions */
00997 #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
00998 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
00999 
01000 /* DWT Exception Overhead Count Register Definitions */
01001 #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
01002 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
01003 
01004 /* DWT Sleep Count Register Definitions */
01005 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
01006 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
01007 
01008 /* DWT LSU Count Register Definitions */
01009 #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
01010 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
01011 
01012 /* DWT Folded-instruction Count Register Definitions */
01013 #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
01014 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
01015 
01016 /* DWT Comparator Mask Register Definitions */
01017 #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
01018 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
01019 
01020 /* DWT Comparator Function Register Definitions */
01021 #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
01022 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
01023 
01024 #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
01025 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
01026 
01027 #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
01028 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
01029 
01030 #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
01031 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
01032 
01033 #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
01034 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
01035 
01036 #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
01037 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
01038 
01039 #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
01040 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
01041 
01042 #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
01043 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
01044 
01045 #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
01046 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
01047 
01048 /*@}*/ /* end of group CMSIS_DWT */
01049 
01050 
01051 /**
01052   \ingroup  CMSIS_core_register
01053   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
01054   \brief    Type definitions for the Trace Port Interface (TPI)
01055   @{
01056  */
01057 
01058 /**
01059   \brief  Structure type to access the Trace Port Interface Register (TPI).
01060  */
01061 typedef struct
01062 {
01063   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
01064   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
01065         uint32_t RESERVED0[2U];
01066   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
01067         uint32_t RESERVED1[55U];
01068   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
01069         uint32_t RESERVED2[131U];
01070   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
01071   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
01072   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
01073         uint32_t RESERVED3[759U];
01074   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
01075   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
01076   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
01077         uint32_t RESERVED4[1U];
01078   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
01079   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
01080   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
01081         uint32_t RESERVED5[39U];
01082   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
01083   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
01084         uint32_t RESERVED7[8U];
01085   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
01086   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
01087 } TPI_Type;
01088 
01089 /* TPI Asynchronous Clock Prescaler Register Definitions */
01090 #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< @Deprecated TPI ACPR: PRESCALER Position */
01091 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< @Deprecated TPI ACPR: PRESCALER Mask */
01092 
01093 #define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
01094 #define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
01095 
01096 /* TPI Selected Pin Protocol Register Definitions */
01097 #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
01098 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
01099 
01100 /* TPI Formatter and Flush Status Register Definitions */
01101 #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
01102 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
01103 
01104 #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
01105 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
01106 
01107 #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
01108 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
01109 
01110 #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
01111 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
01112 
01113 /* TPI Formatter and Flush Control Register Definitions */
01114 #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
01115 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
01116 
01117 #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
01118 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
01119 
01120 /* TPI TRIGGER Register Definitions */
01121 #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
01122 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
01123 
01124 /* TPI Integration ETM Data Register Definitions (FIFO0) */
01125 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
01126 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
01127 
01128 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
01129 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
01130 
01131 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
01132 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
01133 
01134 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
01135 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
01136 
01137 #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
01138 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
01139 
01140 #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
01141 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
01142 
01143 #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
01144 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
01145 
01146 /* TPI ITATBCTR2 Register Definitions */
01147 #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
01148 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
01149 
01150 /* TPI Integration ITM Data Register Definitions (FIFO1) */
01151 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
01152 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
01153 
01154 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
01155 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
01156 
01157 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
01158 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
01159 
01160 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
01161 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01162 
01163 #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
01164 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01165 
01166 #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
01167 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01168 
01169 #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
01170 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
01171 
01172 /* TPI ITATBCTR0 Register Definitions */
01173 #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
01174 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
01175 
01176 /* TPI Integration Mode Control Register Definitions */
01177 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
01178 #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
01179 
01180 /* TPI DEVID Register Definitions */
01181 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
01182 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01183 
01184 #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
01185 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01186 
01187 #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
01188 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01189 
01190 #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
01191 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01192 
01193 #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
01194 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01195 
01196 #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
01197 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
01198 
01199 /* TPI DEVTYPE Register Definitions */
01200 #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
01201 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01202 
01203 #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
01204 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
01205 
01206 /*@}*/ /* end of group CMSIS_TPI */
01207 
01208 
01209 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
01210 /**
01211   \ingroup  CMSIS_core_register
01212   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01213   \brief    Type definitions for the Memory Protection Unit (MPU)
01214   @{
01215  */
01216 
01217 /**
01218   \brief  Structure type to access the Memory Protection Unit (MPU).
01219  */
01220 typedef struct
01221 {
01222   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
01223   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
01224   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
01225   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
01226   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
01227   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
01228   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01229   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
01230   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01231   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
01232   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01233 } MPU_Type;
01234 
01235 #define MPU_TYPE_RALIASES                  4U
01236 
01237 /* MPU Type Register Definitions */
01238 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
01239 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01240 
01241 #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
01242 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01243 
01244 #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
01245 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
01246 
01247 /* MPU Control Register Definitions */
01248 #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
01249 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01250 
01251 #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
01252 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01253 
01254 #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
01255 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
01256 
01257 /* MPU Region Number Register Definitions */
01258 #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
01259 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
01260 
01261 /* MPU Region Base Address Register Definitions */
01262 #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
01263 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01264 
01265 #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
01266 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01267 
01268 #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
01269 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
01270 
01271 /* MPU Region Attribute and Size Register Definitions */
01272 #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
01273 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01274 
01275 #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
01276 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01277 
01278 #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
01279 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01280 
01281 #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
01282 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01283 
01284 #define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
01285 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01286 
01287 #define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
01288 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01289 
01290 #define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
01291 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01292 
01293 #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
01294 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01295 
01296 #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
01297 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01298 
01299 #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
01300 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
01301 
01302 /*@} end of group CMSIS_MPU */
01303 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
01304 
01305 
01306 /**
01307   \ingroup  CMSIS_core_register
01308   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
01309   \brief    Type definitions for the Floating Point Unit (FPU)
01310   @{
01311  */
01312 
01313 /**
01314   \brief  Structure type to access the Floating Point Unit (FPU).
01315  */
01316 typedef struct
01317 {
01318         uint32_t RESERVED0[1U];
01319   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
01320   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
01321   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
01322   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
01323   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
01324 } FPU_Type;
01325 
01326 /* Floating-Point Context Control Register Definitions */
01327 #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
01328 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
01329 
01330 #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
01331 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
01332 
01333 #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
01334 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
01335 
01336 #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
01337 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
01338 
01339 #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
01340 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
01341 
01342 #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
01343 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
01344 
01345 #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
01346 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
01347 
01348 #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
01349 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
01350 
01351 #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
01352 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
01353 
01354 /* Floating-Point Context Address Register Definitions */
01355 #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
01356 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
01357 
01358 /* Floating-Point Default Status Control Register Definitions */
01359 #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
01360 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
01361 
01362 #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
01363 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
01364 
01365 #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
01366 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
01367 
01368 #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
01369 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
01370 
01371 /* Media and FP Feature Register 0 Definitions */
01372 #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
01373 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
01374 
01375 #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
01376 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
01377 
01378 #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
01379 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
01380 
01381 #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
01382 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
01383 
01384 #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
01385 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
01386 
01387 #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
01388 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
01389 
01390 #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
01391 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
01392 
01393 #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
01394 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
01395 
01396 /* Media and FP Feature Register 1 Definitions */
01397 #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
01398 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
01399 
01400 #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
01401 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
01402 
01403 #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
01404 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
01405 
01406 #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
01407 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
01408 
01409 /*@} end of group CMSIS_FPU */
01410 
01411 
01412 /**
01413   \ingroup  CMSIS_core_register
01414   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01415   \brief    Type definitions for the Core Debug Registers
01416   @{
01417  */
01418 
01419 /**
01420   \brief  Structure type to access the Core Debug Register (CoreDebug).
01421  */
01422 typedef struct
01423 {
01424   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
01425   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
01426   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
01427   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01428 } CoreDebug_Type;
01429 
01430 /* Debug Halting Control and Status Register Definitions */
01431 #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
01432 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01433 
01434 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
01435 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01436 
01437 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01438 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01439 
01440 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
01441 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01442 
01443 #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
01444 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01445 
01446 #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
01447 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01448 
01449 #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
01450 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01451 
01452 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01453 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01454 
01455 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
01456 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01457 
01458 #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
01459 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01460 
01461 #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
01462 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01463 
01464 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01465 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01466 
01467 /* Debug Core Register Selector Register Definitions */
01468 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
01469 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01470 
01471 #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
01472 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
01473 
01474 /* Debug Exception and Monitor Control Register Definitions */
01475 #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
01476 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01477 
01478 #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
01479 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01480 
01481 #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
01482 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01483 
01484 #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
01485 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01486 
01487 #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
01488 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01489 
01490 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
01491 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01492 
01493 #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
01494 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01495 
01496 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
01497 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01498 
01499 #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
01500 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01501 
01502 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
01503 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01504 
01505 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01506 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01507 
01508 #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
01509 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01510 
01511 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
01512 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01513 
01514 /*@} end of group CMSIS_CoreDebug */
01515 
01516 
01517 /**
01518   \ingroup    CMSIS_core_register
01519   \defgroup   CMSIS_core_bitfield     Core register bit field macros
01520   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
01521   @{
01522  */
01523 
01524 /**
01525   \brief   Mask and shift a bit field value for use in a register bit range.
01526   \param[in] field  Name of the register bit field.
01527   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
01528   \return           Masked and shifted value.
01529 */
01530 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
01531 
01532 /**
01533   \brief     Mask and shift a register value to extract a bit filed value.
01534   \param[in] field  Name of the register bit field.
01535   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
01536   \return           Masked and shifted bit field value.
01537 */
01538 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
01539 
01540 /*@} end of group CMSIS_core_bitfield */
01541 
01542 
01543 /**
01544   \ingroup    CMSIS_core_register
01545   \defgroup   CMSIS_core_base     Core Definitions
01546   \brief      Definitions for base addresses, unions, and structures.
01547   @{
01548  */
01549 
01550 /* Memory mapping of Core Hardware */
01551 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
01552 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
01553 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
01554 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
01555 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
01556 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
01557 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
01558 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
01559 
01560 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01561 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
01562 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
01563 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
01564 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
01565 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
01566 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
01567 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
01568 
01569 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
01570   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
01571   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
01572 #endif
01573 
01574 #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
01575 #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
01576 
01577 /*@} */
01578 
01579 
01580 
01581 /*******************************************************************************
01582  *                Hardware Abstraction Layer
01583   Core Function Interface contains:
01584   - Core NVIC Functions
01585   - Core SysTick Functions
01586   - Core Debug Functions
01587   - Core Register Access Functions
01588  ******************************************************************************/
01589 /**
01590   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01591 */
01592 
01593 
01594 
01595 /* ##########################   NVIC functions  #################################### */
01596 /**
01597   \ingroup  CMSIS_Core_FunctionInterface
01598   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01599   \brief    Functions that manage interrupts and exceptions via the NVIC.
01600   @{
01601  */
01602 
01603 #ifdef CMSIS_NVIC_VIRTUAL
01604   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
01605     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
01606   #endif
01607   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
01608 #else
01609   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
01610   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
01611   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
01612   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
01613   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
01614   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
01615   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
01616   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
01617   #define NVIC_GetActive              __NVIC_GetActive
01618   #define NVIC_SetPriority            __NVIC_SetPriority
01619   #define NVIC_GetPriority            __NVIC_GetPriority
01620   #define NVIC_SystemReset            __NVIC_SystemReset
01621 #endif /* CMSIS_NVIC_VIRTUAL */
01622 
01623 #ifdef CMSIS_VECTAB_VIRTUAL
01624   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01625    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
01626   #endif
01627   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01628 #else
01629   #define NVIC_SetVector              __NVIC_SetVector
01630   #define NVIC_GetVector              __NVIC_GetVector
01631 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
01632 
01633 #define NVIC_USER_IRQ_OFFSET          16
01634 
01635 
01636 
01637 /**
01638   \brief   Set Priority Grouping
01639   \details Sets the priority grouping field using the required unlock sequence.
01640            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01641            Only values from 0..7 are used.
01642            In case of a conflict between priority grouping and available
01643            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01644   \param [in]      PriorityGroup  Priority grouping field.
01645  */
01646 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01647 {
01648   uint32_t reg_value;
01649   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
01650 
01651   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01652   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
01653   reg_value  =  (reg_value                                   |
01654                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
01655                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
01656   SCB->AIRCR =  reg_value;
01657 }
01658 
01659 
01660 /**
01661   \brief   Get Priority Grouping
01662   \details Reads the priority grouping field from the NVIC Interrupt Controller.
01663   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01664  */
01665 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
01666 {
01667   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
01668 }
01669 
01670 
01671 /**
01672   \brief   Enable Interrupt
01673   \details Enables a device specific interrupt in the NVIC interrupt controller.
01674   \param [in]      IRQn  Device specific interrupt number.
01675   \note    IRQn must not be negative.
01676  */
01677 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
01678 {
01679   if ((int32_t)(IRQn) >= 0)
01680   {
01681     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
01682   }
01683 }
01684 
01685 
01686 /**
01687   \brief   Get Interrupt Enable status
01688   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
01689   \param [in]      IRQn  Device specific interrupt number.
01690   \return             0  Interrupt is not enabled.
01691   \return             1  Interrupt is enabled.
01692   \note    IRQn must not be negative.
01693  */
01694 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
01695 {
01696   if ((int32_t)(IRQn) >= 0)
01697   {
01698     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01699   }
01700   else
01701   {
01702     return(0U);
01703   }
01704 }
01705 
01706 
01707 /**
01708   \brief   Disable Interrupt
01709   \details Disables a device specific interrupt in the NVIC interrupt controller.
01710   \param [in]      IRQn  Device specific interrupt number.
01711   \note    IRQn must not be negative.
01712  */
01713 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
01714 {
01715   if ((int32_t)(IRQn) >= 0)
01716   {
01717     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
01718     __DSB();
01719     __ISB();
01720   }
01721 }
01722 
01723 
01724 /**
01725   \brief   Get Pending Interrupt
01726   \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
01727   \param [in]      IRQn  Device specific interrupt number.
01728   \return             0  Interrupt status is not pending.
01729   \return             1  Interrupt status is pending.
01730   \note    IRQn must not be negative.
01731  */
01732 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
01733 {
01734   if ((int32_t)(IRQn) >= 0)
01735   {
01736     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01737   }
01738   else
01739   {
01740     return(0U);
01741   }
01742 }
01743 
01744 
01745 /**
01746   \brief   Set Pending Interrupt
01747   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
01748   \param [in]      IRQn  Device specific interrupt number.
01749   \note    IRQn must not be negative.
01750  */
01751 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
01752 {
01753   if ((int32_t)(IRQn) >= 0)
01754   {
01755     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
01756   }
01757 }
01758 
01759 
01760 /**
01761   \brief   Clear Pending Interrupt
01762   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
01763   \param [in]      IRQn  Device specific interrupt number.
01764   \note    IRQn must not be negative.
01765  */
01766 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01767 {
01768   if ((int32_t)(IRQn) >= 0)
01769   {
01770     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
01771   }
01772 }
01773 
01774 
01775 /**
01776   \brief   Get Active Interrupt
01777   \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
01778   \param [in]      IRQn  Device specific interrupt number.
01779   \return             0  Interrupt status is not active.
01780   \return             1  Interrupt status is active.
01781   \note    IRQn must not be negative.
01782  */
01783 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
01784 {
01785   if ((int32_t)(IRQn) >= 0)
01786   {
01787     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01788   }
01789   else
01790   {
01791     return(0U);
01792   }
01793 }
01794 
01795 
01796 /**
01797   \brief   Set Interrupt Priority
01798   \details Sets the priority of a device specific interrupt or a processor exception.
01799            The interrupt number can be positive to specify a device specific interrupt,
01800            or negative to specify a processor exception.
01801   \param [in]      IRQn  Interrupt number.
01802   \param [in]  priority  Priority to set.
01803   \note    The priority cannot be set for every processor exception.
01804  */
01805 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01806 {
01807   if ((int32_t)(IRQn) >= 0)
01808   {
01809     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01810   }
01811   else
01812   {
01813     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01814   }
01815 }
01816 
01817 
01818 /**
01819   \brief   Get Interrupt Priority
01820   \details Reads the priority of a device specific interrupt or a processor exception.
01821            The interrupt number can be positive to specify a device specific interrupt,
01822            or negative to specify a processor exception.
01823   \param [in]   IRQn  Interrupt number.
01824   \return             Interrupt Priority.
01825                       Value is aligned automatically to the implemented priority bits of the microcontroller.
01826  */
01827 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
01828 {
01829 
01830   if ((int32_t)(IRQn) >= 0)
01831   {
01832     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
01833   }
01834   else
01835   {
01836     return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
01837   }
01838 }
01839 
01840 
01841 /**
01842   \brief   Encode Priority
01843   \details Encodes the priority for an interrupt with the given priority group,
01844            preemptive priority value, and subpriority value.
01845            In case of a conflict between priority grouping and available
01846            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01847   \param [in]     PriorityGroup  Used priority group.
01848   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01849   \param [in]       SubPriority  Subpriority value (starting from 0).
01850   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01851  */
01852 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01853 {
01854   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01855   uint32_t PreemptPriorityBits;
01856   uint32_t SubPriorityBits;
01857 
01858   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01859   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01860 
01861   return (
01862            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
01863            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
01864          );
01865 }
01866 
01867 
01868 /**
01869   \brief   Decode Priority
01870   \details Decodes an interrupt priority value with a given priority group to
01871            preemptive priority value and subpriority value.
01872            In case of a conflict between priority grouping and available
01873            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
01874   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01875   \param [in]     PriorityGroup  Used priority group.
01876   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01877   \param [out]     pSubPriority  Subpriority value (starting from 0).
01878  */
01879 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
01880 {
01881   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01882   uint32_t PreemptPriorityBits;
01883   uint32_t SubPriorityBits;
01884 
01885   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01886   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01887 
01888   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
01889   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
01890 }
01891 
01892 
01893 /**
01894   \brief   Set Interrupt Vector
01895   \details Sets an interrupt vector in SRAM based interrupt vector table.
01896            The interrupt number can be positive to specify a device specific interrupt,
01897            or negative to specify a processor exception.
01898            VTOR must been relocated to SRAM before.
01899   \param [in]   IRQn      Interrupt number
01900   \param [in]   vector    Address of interrupt handler function
01901  */
01902 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
01903 {
01904   uint32_t *vectors = (uint32_t *)SCB->VTOR;
01905   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
01906 }
01907 
01908 
01909 /**
01910   \brief   Get Interrupt Vector
01911   \details Reads an interrupt vector from interrupt vector table.
01912            The interrupt number can be positive to specify a device specific interrupt,
01913            or negative to specify a processor exception.
01914   \param [in]   IRQn      Interrupt number.
01915   \return                 Address of interrupt handler function
01916  */
01917 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
01918 {
01919   uint32_t *vectors = (uint32_t *)SCB->VTOR;
01920   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
01921 }
01922 
01923 
01924 /**
01925   \brief   System Reset
01926   \details Initiates a system reset request to reset the MCU.
01927  */
01928 __STATIC_INLINE void __NVIC_SystemReset(void)
01929 {
01930   __DSB();                                                          /* Ensure all outstanding memory accesses included
01931                                                                        buffered write are completed before reset */
01932   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
01933                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01934                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
01935   __DSB();                                                          /* Ensure completion of memory access */
01936 
01937   for(;;)                                                           /* wait until reset */
01938   {
01939     __NOP();
01940   }
01941 }
01942 
01943 /*@} end of CMSIS_Core_NVICFunctions */
01944 
01945 /* ##########################  MPU functions  #################################### */
01946 
01947 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
01948 
01949 #include "mpu_armv7.h"
01950 
01951 #endif
01952 
01953 
01954 /* ##########################  FPU functions  #################################### */
01955 /**
01956   \ingroup  CMSIS_Core_FunctionInterface
01957   \defgroup CMSIS_Core_FpuFunctions FPU Functions
01958   \brief    Function that provides FPU type.
01959   @{
01960  */
01961 
01962 /**
01963   \brief   get FPU type
01964   \details returns the FPU type
01965   \returns
01966    - \b  0: No FPU
01967    - \b  1: Single precision FPU
01968    - \b  2: Double + Single precision FPU
01969  */
01970 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
01971 {
01972   uint32_t mvfr0;
01973 
01974   mvfr0 = FPU->MVFR0;
01975   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
01976   {
01977     return 1U;           /* Single precision FPU */
01978   }
01979   else
01980   {
01981     return 0U;           /* No FPU */
01982   }
01983 }
01984 
01985 
01986 /*@} end of CMSIS_Core_FpuFunctions */
01987 
01988 
01989 
01990 /* ##################################    SysTick function  ############################################ */
01991 /**
01992   \ingroup  CMSIS_Core_FunctionInterface
01993   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01994   \brief    Functions that configure the System.
01995   @{
01996  */
01997 
01998 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
01999 
02000 /**
02001   \brief   System Tick Configuration
02002   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
02003            Counter is in free running mode to generate periodic interrupts.
02004   \param [in]  ticks  Number of ticks between two interrupts.
02005   \return          0  Function succeeded.
02006   \return          1  Function failed.
02007   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
02008            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
02009            must contain a vendor-specific implementation of this function.
02010  */
02011 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
02012 {
02013   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
02014   {
02015     return (1UL);                                                   /* Reload value impossible */
02016   }
02017 
02018   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
02019   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
02020   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
02021   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
02022                    SysTick_CTRL_TICKINT_Msk   |
02023                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
02024   return (0UL);                                                     /* Function successful */
02025 }
02026 
02027 #endif
02028 
02029 /*@} end of CMSIS_Core_SysTickFunctions */
02030 
02031 
02032 
02033 /* ##################################### Debug In/Output function ########################################### */
02034 /**
02035   \ingroup  CMSIS_Core_FunctionInterface
02036   \defgroup CMSIS_core_DebugFunctions ITM Functions
02037   \brief    Functions that access the ITM debug interface.
02038   @{
02039  */
02040 
02041 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
02042 #define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
02043 
02044 
02045 /**
02046   \brief   ITM Send Character
02047   \details Transmits a character via the ITM channel 0, and
02048            \li Just returns when no debugger is connected that has booked the output.
02049            \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
02050   \param [in]     ch  Character to transmit.
02051   \returns            Character to transmit.
02052  */
02053 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
02054 {
02055   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
02056       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
02057   {
02058     while (ITM->PORT[0U].u32 == 0UL)
02059     {
02060       __NOP();
02061     }
02062     ITM->PORT[0U].u8 = (uint8_t)ch;
02063   }
02064   return (ch);
02065 }
02066 
02067 
02068 /**
02069   \brief   ITM Receive Character
02070   \details Inputs a character via the external variable \ref ITM_RxBuffer.
02071   \return             Received character.
02072   \return         -1  No character pending.
02073  */
02074 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
02075 {
02076   int32_t ch = -1;                           /* no character available */
02077 
02078   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
02079   {
02080     ch = ITM_RxBuffer;
02081     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
02082   }
02083 
02084   return (ch);
02085 }
02086 
02087 
02088 /**
02089   \brief   ITM Check Character
02090   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
02091   \return          0  No character available.
02092   \return          1  Character available.
02093  */
02094 __STATIC_INLINE int32_t ITM_CheckChar (void)
02095 {
02096 
02097   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
02098   {
02099     return (0);                              /* no character available */
02100   }
02101   else
02102   {
02103     return (1);                              /*    character available */
02104   }
02105 }
02106 
02107 /*@} end of CMSIS_core_DebugFunctions */
02108 
02109 
02110 
02111 
02112 #ifdef __cplusplus
02113 }
02114 #endif
02115 
02116 #endif /* __CORE_CM4_H_DEPENDANT */
02117 
02118 #endif /* __CMSIS_GENERIC */
02119