Robert Lopez
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CMSIS5
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core_cm33.h
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00001 /**************************************************************************//** 00002 * @file core_cm33.h 00003 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File 00004 * @version V5.0.5 00005 * @date 08. January 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM33_H_GENERIC 00032 #define __CORE_CM33_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M33 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM33 definitions */ 00066 #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (33U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00075 */ 00076 #if defined ( __CC_ARM ) 00077 #if defined (__TARGET_FPU_VFP) 00078 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00079 #define __FPU_USED 1U 00080 #else 00081 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00082 #define __FPU_USED 0U 00083 #endif 00084 #else 00085 #define __FPU_USED 0U 00086 #endif 00087 00088 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00089 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00090 #define __DSP_USED 1U 00091 #else 00092 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00093 #define __DSP_USED 0U 00094 #endif 00095 #else 00096 #define __DSP_USED 0U 00097 #endif 00098 00099 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00100 #if defined (__ARM_PCS_VFP) 00101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00102 #define __FPU_USED 1U 00103 #else 00104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00105 #define __FPU_USED 0U 00106 #endif 00107 #else 00108 #define __FPU_USED 0U 00109 #endif 00110 00111 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00112 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00113 #define __DSP_USED 1U 00114 #else 00115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00116 #define __DSP_USED 0U 00117 #endif 00118 #else 00119 #define __DSP_USED 0U 00120 #endif 00121 00122 #elif defined ( __GNUC__ ) 00123 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00125 #define __FPU_USED 1U 00126 #else 00127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #define __FPU_USED 0U 00129 #endif 00130 #else 00131 #define __FPU_USED 0U 00132 #endif 00133 00134 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00135 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00136 #define __DSP_USED 1U 00137 #else 00138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00139 #define __DSP_USED 0U 00140 #endif 00141 #else 00142 #define __DSP_USED 0U 00143 #endif 00144 00145 #elif defined ( __ICCARM__ ) 00146 #if defined (__ARMVFP__) 00147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00148 #define __FPU_USED 1U 00149 #else 00150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00151 #define __FPU_USED 0U 00152 #endif 00153 #else 00154 #define __FPU_USED 0U 00155 #endif 00156 00157 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) 00158 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) 00159 #define __DSP_USED 1U 00160 #else 00161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 00162 #define __DSP_USED 0U 00163 #endif 00164 #else 00165 #define __DSP_USED 0U 00166 #endif 00167 00168 #elif defined ( __TI_ARM__ ) 00169 #if defined (__TI_VFP_SUPPORT__) 00170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00171 #define __FPU_USED 1U 00172 #else 00173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00174 #define __FPU_USED 0U 00175 #endif 00176 #else 00177 #define __FPU_USED 0U 00178 #endif 00179 00180 #elif defined ( __TASKING__ ) 00181 #if defined (__FPU_VFP__) 00182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00183 #define __FPU_USED 1U 00184 #else 00185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00186 #define __FPU_USED 0U 00187 #endif 00188 #else 00189 #define __FPU_USED 0U 00190 #endif 00191 00192 #elif defined ( __CSMC__ ) 00193 #if ( __CSMC__ & 0x400U) 00194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00195 #define __FPU_USED 1U 00196 #else 00197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00198 #define __FPU_USED 0U 00199 #endif 00200 #else 00201 #define __FPU_USED 0U 00202 #endif 00203 00204 #endif 00205 00206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00207 00208 00209 #ifdef __cplusplus 00210 } 00211 #endif 00212 00213 #endif /* __CORE_CM33_H_GENERIC */ 00214 00215 #ifndef __CMSIS_GENERIC 00216 00217 #ifndef __CORE_CM33_H_DEPENDANT 00218 #define __CORE_CM33_H_DEPENDANT 00219 00220 #ifdef __cplusplus 00221 extern "C" { 00222 #endif 00223 00224 /* check device defines and use defaults */ 00225 #if defined __CHECK_DEVICE_DEFINES 00226 #ifndef __CM33_REV 00227 #define __CM33_REV 0x0000U 00228 #warning "__CM33_REV not defined in device header file; using default!" 00229 #endif 00230 00231 #ifndef __FPU_PRESENT 00232 #define __FPU_PRESENT 0U 00233 #warning "__FPU_PRESENT not defined in device header file; using default!" 00234 #endif 00235 00236 #ifndef __MPU_PRESENT 00237 #define __MPU_PRESENT 0U 00238 #warning "__MPU_PRESENT not defined in device header file; using default!" 00239 #endif 00240 00241 #ifndef __SAUREGION_PRESENT 00242 #define __SAUREGION_PRESENT 0U 00243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 00244 #endif 00245 00246 #ifndef __DSP_PRESENT 00247 #define __DSP_PRESENT 0U 00248 #warning "__DSP_PRESENT not defined in device header file; using default!" 00249 #endif 00250 00251 #ifndef __NVIC_PRIO_BITS 00252 #define __NVIC_PRIO_BITS 3U 00253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00254 #endif 00255 00256 #ifndef __Vendor_SysTickConfig 00257 #define __Vendor_SysTickConfig 0U 00258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00259 #endif 00260 #endif 00261 00262 /* IO definitions (access restrictions to peripheral registers) */ 00263 /** 00264 \defgroup CMSIS_glob_defs CMSIS Global Defines 00265 00266 <strong>IO Type Qualifiers</strong> are used 00267 \li to specify the access to peripheral variables. 00268 \li for automatic generation of peripheral register debug information. 00269 */ 00270 #ifdef __cplusplus 00271 #define __I volatile /*!< Defines 'read only' permissions */ 00272 #else 00273 #define __I volatile const /*!< Defines 'read only' permissions */ 00274 #endif 00275 #define __O volatile /*!< Defines 'write only' permissions */ 00276 #define __IO volatile /*!< Defines 'read / write' permissions */ 00277 00278 /* following defines should be used for structure members */ 00279 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00280 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00282 00283 /*@} end of group Cortex_M33 */ 00284 00285 00286 00287 /******************************************************************************* 00288 * Register Abstraction 00289 Core Register contain: 00290 - Core Register 00291 - Core NVIC Register 00292 - Core SCB Register 00293 - Core SysTick Register 00294 - Core Debug Register 00295 - Core MPU Register 00296 - Core SAU Register 00297 - Core FPU Register 00298 ******************************************************************************/ 00299 /** 00300 \defgroup CMSIS_core_register Defines and Type Definitions 00301 \brief Type definitions and defines for Cortex-M processor based devices. 00302 */ 00303 00304 /** 00305 \ingroup CMSIS_core_register 00306 \defgroup CMSIS_CORE Status and Control Registers 00307 \brief Core Register type definitions. 00308 @{ 00309 */ 00310 00311 /** 00312 \brief Union type to access the Application Program Status Register (APSR). 00313 */ 00314 typedef union 00315 { 00316 struct 00317 { 00318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00326 } b; /*!< Structure used for bit access */ 00327 uint32_t w; /*!< Type used for word access */ 00328 } APSR_Type; 00329 00330 /* APSR Register Definitions */ 00331 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00333 00334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00336 00337 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00339 00340 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00342 00343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00345 00346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00348 00349 00350 /** 00351 \brief Union type to access the Interrupt Program Status Register (IPSR). 00352 */ 00353 typedef union 00354 { 00355 struct 00356 { 00357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00359 } b; /*!< Structure used for bit access */ 00360 uint32_t w; /*!< Type used for word access */ 00361 } IPSR_Type; 00362 00363 /* IPSR Register Definitions */ 00364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00366 00367 00368 /** 00369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00370 */ 00371 typedef union 00372 { 00373 struct 00374 { 00375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00386 } b; /*!< Structure used for bit access */ 00387 uint32_t w; /*!< Type used for word access */ 00388 } xPSR_Type; 00389 00390 /* xPSR Register Definitions */ 00391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00393 00394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00396 00397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00399 00400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00402 00403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00405 00406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 00407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 00408 00409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00411 00412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00414 00415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00417 00418 00419 /** 00420 \brief Union type to access the Control Registers (CONTROL). 00421 */ 00422 typedef union 00423 { 00424 struct 00425 { 00426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 00428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ 00429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ 00430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ 00431 } b; /*!< Structure used for bit access */ 00432 uint32_t w; /*!< Type used for word access */ 00433 } CONTROL_Type; 00434 00435 /* CONTROL Register Definitions */ 00436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ 00437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ 00438 00439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00441 00442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00444 00445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00447 00448 /*@} end of group CMSIS_CORE */ 00449 00450 00451 /** 00452 \ingroup CMSIS_core_register 00453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00454 \brief Type definitions for the NVIC Registers 00455 @{ 00456 */ 00457 00458 /** 00459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00460 */ 00461 typedef struct 00462 { 00463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00464 uint32_t RESERVED0[16U]; 00465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00466 uint32_t RSERVED1[16U]; 00467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00468 uint32_t RESERVED2[16U]; 00469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00470 uint32_t RESERVED3[16U]; 00471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00472 uint32_t RESERVED4[16U]; 00473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 00474 uint32_t RESERVED5[16U]; 00475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00476 uint32_t RESERVED6[580U]; 00477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00478 } NVIC_Type; 00479 00480 /* Software Triggered Interrupt Register Definitions */ 00481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00483 00484 /*@} end of group CMSIS_NVIC */ 00485 00486 00487 /** 00488 \ingroup CMSIS_core_register 00489 \defgroup CMSIS_SCB System Control Block (SCB) 00490 \brief Type definitions for the System Control Block Registers 00491 @{ 00492 */ 00493 00494 /** 00495 \brief Structure type to access the System Control Block (SCB). 00496 */ 00497 typedef struct 00498 { 00499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ 00524 uint32_t RESERVED3[92U]; 00525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00526 uint32_t RESERVED4[15U]; 00527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 00530 uint32_t RESERVED5[1U]; 00531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00532 uint32_t RESERVED6[1U]; 00533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00541 uint32_t RESERVED7[6U]; 00542 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 00543 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 00544 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 00545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 00546 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 00547 uint32_t RESERVED8[1U]; 00548 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 00549 } SCB_Type; 00550 00551 /* SCB CPUID Register Definitions */ 00552 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00554 00555 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00557 00558 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00560 00561 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00563 00564 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00566 00567 /* SCB Interrupt Control State Register Definitions */ 00568 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 00569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 00570 00571 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 00572 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 00573 00574 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00576 00577 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00579 00580 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00582 00583 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00585 00586 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 00587 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 00588 00589 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00590 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00591 00592 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00593 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00594 00595 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00596 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00597 00598 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00599 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00600 00601 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00602 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00603 00604 /* SCB Vector Table Offset Register Definitions */ 00605 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00606 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00607 00608 /* SCB Application Interrupt and Reset Control Register Definitions */ 00609 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00610 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00611 00612 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00613 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00614 00615 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00616 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00617 00618 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 00619 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 00620 00621 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 00622 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 00623 00624 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00625 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00626 00627 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 00628 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 00629 00630 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00631 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00632 00633 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00634 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00635 00636 /* SCB System Control Register Definitions */ 00637 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00638 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00639 00640 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 00641 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 00642 00643 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00644 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00645 00646 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00647 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00648 00649 /* SCB Configuration Control Register Definitions */ 00650 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 00651 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 00652 00653 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 00654 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 00655 00656 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 00657 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 00658 00659 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 00660 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 00661 00662 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00663 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00664 00665 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00666 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00667 00668 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00669 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00670 00671 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00672 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00673 00674 /* SCB System Handler Control and State Register Definitions */ 00675 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 00676 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 00677 00678 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ 00679 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ 00680 00681 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ 00682 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ 00683 00684 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00685 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00686 00687 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00688 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00689 00690 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00691 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00692 00693 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00694 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00695 00696 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00697 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00698 00699 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00700 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00701 00702 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00703 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00704 00705 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00706 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00707 00708 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00709 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00710 00711 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00712 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00713 00714 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00715 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00716 00717 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 00718 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 00719 00720 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ 00721 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ 00722 00723 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00724 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00725 00726 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 00727 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 00728 00729 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00730 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00731 00732 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00733 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00734 00735 /* SCB Configurable Fault Status Register Definitions */ 00736 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00737 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00738 00739 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00740 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00741 00742 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00743 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00744 00745 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00746 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00747 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00748 00749 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00750 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00751 00752 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00753 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00754 00755 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00756 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00757 00758 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00759 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00760 00761 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00762 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00763 00764 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00765 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00766 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00767 00768 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00769 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00770 00771 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00772 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00773 00774 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00775 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00776 00777 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00778 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00779 00780 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00781 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00782 00783 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00784 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00785 00786 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00787 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00788 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00789 00790 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00791 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00792 00793 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ 00794 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ 00795 00796 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00797 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00798 00799 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00800 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00801 00802 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00803 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00804 00805 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00806 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00807 00808 /* SCB Hard Fault Status Register Definitions */ 00809 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00810 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00811 00812 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00813 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00814 00815 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00816 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00817 00818 /* SCB Debug Fault Status Register Definitions */ 00819 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00820 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00821 00822 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00823 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00824 00825 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00826 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00827 00828 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00829 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00830 00831 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00832 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00833 00834 /* SCB Non-Secure Access Control Register Definitions */ 00835 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 00836 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 00837 00838 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 00839 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 00840 00841 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 00842 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ 00843 00844 /* SCB Cache Level ID Register Definitions */ 00845 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 00846 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00847 00848 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 00849 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 00850 00851 /* SCB Cache Type Register Definitions */ 00852 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 00853 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00854 00855 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 00856 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00857 00858 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 00859 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00860 00861 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 00862 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00863 00864 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 00865 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00866 00867 /* SCB Cache Size ID Register Definitions */ 00868 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 00869 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00870 00871 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 00872 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00873 00874 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 00875 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00876 00877 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 00878 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00879 00880 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 00881 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00882 00883 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 00884 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00885 00886 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 00887 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00888 00889 /* SCB Cache Size Selection Register Definitions */ 00890 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 00891 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00892 00893 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 00894 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00895 00896 /* SCB Software Triggered Interrupt Register Definitions */ 00897 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 00898 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00899 00900 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 00901 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 00902 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 00903 00904 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 00905 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 00906 00907 /* SCB D-Cache Clean by Set-way Register Definitions */ 00908 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 00909 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 00910 00911 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 00912 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 00913 00914 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 00915 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 00916 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 00917 00918 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 00919 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 00920 00921 /* Instruction Tightly-Coupled Memory Control Register Definitions */ 00922 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ 00923 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 00924 00925 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ 00926 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 00927 00928 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ 00929 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 00930 00931 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ 00932 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 00933 00934 /* Data Tightly-Coupled Memory Control Register Definitions */ 00935 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ 00936 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 00937 00938 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ 00939 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 00940 00941 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ 00942 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 00943 00944 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ 00945 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 00946 00947 /* AHBP Control Register Definitions */ 00948 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ 00949 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 00950 00951 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ 00952 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 00953 00954 /* L1 Cache Control Register Definitions */ 00955 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ 00956 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 00957 00958 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ 00959 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 00960 00961 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ 00962 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 00963 00964 /* AHBS Control Register Definitions */ 00965 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ 00966 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 00967 00968 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ 00969 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 00970 00971 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ 00972 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 00973 00974 /* Auxiliary Bus Fault Status Register Definitions */ 00975 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ 00976 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 00977 00978 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ 00979 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 00980 00981 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ 00982 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 00983 00984 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ 00985 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 00986 00987 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ 00988 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 00989 00990 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ 00991 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 00992 00993 /*@} end of group CMSIS_SCB */ 00994 00995 00996 /** 00997 \ingroup CMSIS_core_register 00998 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00999 \brief Type definitions for the System Control and ID Register not in the SCB 01000 @{ 01001 */ 01002 01003 /** 01004 \brief Structure type to access the System Control and ID Register not in the SCB. 01005 */ 01006 typedef struct 01007 { 01008 uint32_t RESERVED0[1U]; 01009 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 01010 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 01011 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 01012 } SCnSCB_Type; 01013 01014 /* Interrupt Controller Type Register Definitions */ 01015 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 01016 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 01017 01018 /*@} end of group CMSIS_SCnotSCB */ 01019 01020 01021 /** 01022 \ingroup CMSIS_core_register 01023 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 01024 \brief Type definitions for the System Timer Registers. 01025 @{ 01026 */ 01027 01028 /** 01029 \brief Structure type to access the System Timer (SysTick). 01030 */ 01031 typedef struct 01032 { 01033 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 01034 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 01035 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 01036 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 01037 } SysTick_Type; 01038 01039 /* SysTick Control / Status Register Definitions */ 01040 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 01041 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 01042 01043 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 01044 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 01045 01046 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 01047 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 01048 01049 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 01050 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 01051 01052 /* SysTick Reload Register Definitions */ 01053 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 01054 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 01055 01056 /* SysTick Current Register Definitions */ 01057 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 01058 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 01059 01060 /* SysTick Calibration Register Definitions */ 01061 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 01062 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 01063 01064 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 01065 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 01066 01067 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 01068 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 01069 01070 /*@} end of group CMSIS_SysTick */ 01071 01072 01073 /** 01074 \ingroup CMSIS_core_register 01075 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 01076 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 01077 @{ 01078 */ 01079 01080 /** 01081 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 01082 */ 01083 typedef struct 01084 { 01085 __OM union 01086 { 01087 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 01088 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 01089 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 01090 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 01091 uint32_t RESERVED0[864U]; 01092 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 01093 uint32_t RESERVED1[15U]; 01094 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 01095 uint32_t RESERVED2[15U]; 01096 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 01097 uint32_t RESERVED3[29U]; 01098 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 01099 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 01100 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 01101 uint32_t RESERVED4[43U]; 01102 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 01103 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 01104 uint32_t RESERVED5[1U]; 01105 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ 01106 uint32_t RESERVED6[4U]; 01107 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 01108 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 01109 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 01110 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 01111 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 01112 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 01113 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 01114 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 01115 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 01116 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 01117 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 01118 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 01119 } ITM_Type; 01120 01121 /* ITM Stimulus Port Register Definitions */ 01122 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ 01123 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ 01124 01125 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ 01126 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ 01127 01128 /* ITM Trace Privilege Register Definitions */ 01129 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 01130 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 01131 01132 /* ITM Trace Control Register Definitions */ 01133 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 01134 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 01135 01136 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ 01137 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ 01138 01139 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 01140 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 01141 01142 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ 01143 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ 01144 01145 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ 01146 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ 01147 01148 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 01149 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 01150 01151 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 01152 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01153 01154 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 01155 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01156 01157 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 01158 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01159 01160 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 01161 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01162 01163 /* ITM Integration Write Register Definitions */ 01164 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 01165 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 01166 01167 /* ITM Integration Read Register Definitions */ 01168 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 01169 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 01170 01171 /* ITM Integration Mode Control Register Definitions */ 01172 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 01173 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 01174 01175 /* ITM Lock Status Register Definitions */ 01176 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 01177 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01178 01179 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 01180 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01181 01182 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 01183 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01184 01185 /*@}*/ /* end of group CMSIS_ITM */ 01186 01187 01188 /** 01189 \ingroup CMSIS_core_register 01190 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01191 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01192 @{ 01193 */ 01194 01195 /** 01196 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01197 */ 01198 typedef struct 01199 { 01200 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01201 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01202 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01203 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01204 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01205 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01206 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01207 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01208 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01209 uint32_t RESERVED1[1U]; 01210 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01211 uint32_t RESERVED2[1U]; 01212 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01213 uint32_t RESERVED3[1U]; 01214 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01215 uint32_t RESERVED4[1U]; 01216 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01217 uint32_t RESERVED5[1U]; 01218 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01219 uint32_t RESERVED6[1U]; 01220 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01221 uint32_t RESERVED7[1U]; 01222 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01223 uint32_t RESERVED8[1U]; 01224 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 01225 uint32_t RESERVED9[1U]; 01226 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 01227 uint32_t RESERVED10[1U]; 01228 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 01229 uint32_t RESERVED11[1U]; 01230 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 01231 uint32_t RESERVED12[1U]; 01232 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 01233 uint32_t RESERVED13[1U]; 01234 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 01235 uint32_t RESERVED14[1U]; 01236 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 01237 uint32_t RESERVED15[1U]; 01238 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 01239 uint32_t RESERVED16[1U]; 01240 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 01241 uint32_t RESERVED17[1U]; 01242 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 01243 uint32_t RESERVED18[1U]; 01244 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 01245 uint32_t RESERVED19[1U]; 01246 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 01247 uint32_t RESERVED20[1U]; 01248 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 01249 uint32_t RESERVED21[1U]; 01250 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 01251 uint32_t RESERVED22[1U]; 01252 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 01253 uint32_t RESERVED23[1U]; 01254 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 01255 uint32_t RESERVED24[1U]; 01256 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 01257 uint32_t RESERVED25[1U]; 01258 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 01259 uint32_t RESERVED26[1U]; 01260 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 01261 uint32_t RESERVED27[1U]; 01262 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 01263 uint32_t RESERVED28[1U]; 01264 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 01265 uint32_t RESERVED29[1U]; 01266 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 01267 uint32_t RESERVED30[1U]; 01268 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 01269 uint32_t RESERVED31[1U]; 01270 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 01271 uint32_t RESERVED32[934U]; 01272 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01273 uint32_t RESERVED33[1U]; 01274 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ 01275 } DWT_Type; 01276 01277 /* DWT Control Register Definitions */ 01278 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 01279 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01280 01281 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 01282 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01283 01284 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 01285 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01286 01287 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 01288 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01289 01290 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 01291 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01292 01293 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ 01294 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ 01295 01296 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 01297 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01298 01299 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 01300 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01301 01302 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 01303 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01304 01305 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 01306 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01307 01308 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 01309 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01310 01311 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 01312 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01313 01314 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 01315 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01316 01317 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 01318 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01319 01320 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 01321 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01322 01323 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 01324 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01325 01326 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 01327 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01328 01329 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 01330 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01331 01332 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 01333 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01334 01335 /* DWT CPI Count Register Definitions */ 01336 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 01337 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01338 01339 /* DWT Exception Overhead Count Register Definitions */ 01340 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01341 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01342 01343 /* DWT Sleep Count Register Definitions */ 01344 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01345 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01346 01347 /* DWT LSU Count Register Definitions */ 01348 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01349 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01350 01351 /* DWT Folded-instruction Count Register Definitions */ 01352 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01353 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01354 01355 /* DWT Comparator Function Register Definitions */ 01356 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 01357 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 01358 01359 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01360 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01361 01362 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01363 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01364 01365 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 01366 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 01367 01368 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 01369 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 01370 01371 /*@}*/ /* end of group CMSIS_DWT */ 01372 01373 01374 /** 01375 \ingroup CMSIS_core_register 01376 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01377 \brief Type definitions for the Trace Port Interface (TPI) 01378 @{ 01379 */ 01380 01381 /** 01382 \brief Structure type to access the Trace Port Interface Register (TPI). 01383 */ 01384 typedef struct 01385 { 01386 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01387 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01388 uint32_t RESERVED0[2U]; 01389 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01390 uint32_t RESERVED1[55U]; 01391 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01392 uint32_t RESERVED2[131U]; 01393 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01394 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01395 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01396 uint32_t RESERVED3[759U]; 01397 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01398 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01399 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01400 uint32_t RESERVED4[1U]; 01401 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01402 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01403 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01404 uint32_t RESERVED5[39U]; 01405 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01406 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01407 uint32_t RESERVED7[8U]; 01408 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01409 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01410 } TPI_Type; 01411 01412 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01413 #define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ 01414 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ 01415 01416 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 01417 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 01418 01419 /* TPI Selected Pin Protocol Register Definitions */ 01420 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01421 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01422 01423 /* TPI Formatter and Flush Status Register Definitions */ 01424 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01425 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01426 01427 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01428 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01429 01430 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01431 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01432 01433 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01434 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01435 01436 /* TPI Formatter and Flush Control Register Definitions */ 01437 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01438 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01439 01440 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01441 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01442 01443 /* TPI TRIGGER Register Definitions */ 01444 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01445 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01446 01447 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01448 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01449 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01450 01451 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01452 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01453 01454 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01455 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01456 01457 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01458 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01459 01460 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01461 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01462 01463 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01464 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01465 01466 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01467 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01468 01469 /* TPI ITATBCTR2 Register Definitions */ 01470 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 01471 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01472 01473 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01474 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01475 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01476 01477 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01478 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01479 01480 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01481 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01482 01483 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01484 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01485 01486 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01487 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01488 01489 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01490 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01491 01492 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01493 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01494 01495 /* TPI ITATBCTR0 Register Definitions */ 01496 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 01497 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01498 01499 /* TPI Integration Mode Control Register Definitions */ 01500 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01501 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01502 01503 /* TPI DEVID Register Definitions */ 01504 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01505 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01506 01507 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01508 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01509 01510 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01511 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01512 01513 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01514 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01515 01516 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01517 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01518 01519 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01520 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01521 01522 /* TPI DEVTYPE Register Definitions */ 01523 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 01524 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01525 01526 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 01527 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01528 01529 /*@}*/ /* end of group CMSIS_TPI */ 01530 01531 01532 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01533 /** 01534 \ingroup CMSIS_core_register 01535 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01536 \brief Type definitions for the Memory Protection Unit (MPU) 01537 @{ 01538 */ 01539 01540 /** 01541 \brief Structure type to access the Memory Protection Unit (MPU). 01542 */ 01543 typedef struct 01544 { 01545 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01546 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01547 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 01548 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01549 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 01550 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ 01551 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ 01552 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ 01553 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ 01554 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ 01555 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ 01556 uint32_t RESERVED0[1]; 01557 union { 01558 __IOM uint32_t MAIR[2]; 01559 struct { 01560 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 01561 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 01562 }; 01563 }; 01564 } MPU_Type; 01565 01566 #define MPU_TYPE_RALIASES 4U 01567 01568 /* MPU Type Register Definitions */ 01569 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01570 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01571 01572 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01573 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01574 01575 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01576 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01577 01578 /* MPU Control Register Definitions */ 01579 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01580 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01581 01582 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01583 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01584 01585 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01586 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01587 01588 /* MPU Region Number Register Definitions */ 01589 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01590 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01591 01592 /* MPU Region Base Address Register Definitions */ 01593 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ 01594 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ 01595 01596 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 01597 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 01598 01599 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 01600 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 01601 01602 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 01603 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 01604 01605 /* MPU Region Limit Address Register Definitions */ 01606 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 01607 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 01608 01609 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 01610 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 01611 01612 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ 01613 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ 01614 01615 /* MPU Memory Attribute Indirection Register 0 Definitions */ 01616 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 01617 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 01618 01619 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 01620 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 01621 01622 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 01623 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 01624 01625 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 01626 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 01627 01628 /* MPU Memory Attribute Indirection Register 1 Definitions */ 01629 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 01630 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 01631 01632 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 01633 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 01634 01635 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 01636 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 01637 01638 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 01639 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 01640 01641 /*@} end of group CMSIS_MPU */ 01642 #endif 01643 01644 01645 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 01646 /** 01647 \ingroup CMSIS_core_register 01648 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 01649 \brief Type definitions for the Security Attribution Unit (SAU) 01650 @{ 01651 */ 01652 01653 /** 01654 \brief Structure type to access the Security Attribution Unit (SAU). 01655 */ 01656 typedef struct 01657 { 01658 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 01659 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 01660 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01661 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 01662 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 01663 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 01664 #else 01665 uint32_t RESERVED0[3]; 01666 #endif 01667 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ 01668 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ 01669 } SAU_Type; 01670 01671 /* SAU Control Register Definitions */ 01672 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 01673 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 01674 01675 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 01676 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 01677 01678 /* SAU Type Register Definitions */ 01679 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 01680 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 01681 01682 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 01683 /* SAU Region Number Register Definitions */ 01684 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 01685 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 01686 01687 /* SAU Region Base Address Register Definitions */ 01688 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 01689 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 01690 01691 /* SAU Region Limit Address Register Definitions */ 01692 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 01693 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 01694 01695 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 01696 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 01697 01698 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 01699 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 01700 01701 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 01702 01703 /* Secure Fault Status Register Definitions */ 01704 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ 01705 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ 01706 01707 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ 01708 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ 01709 01710 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ 01711 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ 01712 01713 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ 01714 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ 01715 01716 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ 01717 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ 01718 01719 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ 01720 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ 01721 01722 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ 01723 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ 01724 01725 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ 01726 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ 01727 01728 /*@} end of group CMSIS_SAU */ 01729 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 01730 01731 01732 /** 01733 \ingroup CMSIS_core_register 01734 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01735 \brief Type definitions for the Floating Point Unit (FPU) 01736 @{ 01737 */ 01738 01739 /** 01740 \brief Structure type to access the Floating Point Unit (FPU). 01741 */ 01742 typedef struct 01743 { 01744 uint32_t RESERVED0[1U]; 01745 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01746 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01747 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01748 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01749 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01750 } FPU_Type; 01751 01752 /* Floating-Point Context Control Register Definitions */ 01753 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01754 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01755 01756 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01757 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01758 01759 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 01760 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 01761 01762 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 01763 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 01764 01765 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ 01766 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ 01767 01768 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ 01769 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ 01770 01771 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ 01772 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ 01773 01774 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ 01775 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ 01776 01777 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01778 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01779 01780 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ 01781 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ 01782 01783 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01784 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01785 01786 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01787 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01788 01789 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01790 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01791 01792 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01793 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01794 01795 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ 01796 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ 01797 01798 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01799 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01800 01801 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01802 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01803 01804 /* Floating-Point Context Address Register Definitions */ 01805 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01806 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01807 01808 /* Floating-Point Default Status Control Register Definitions */ 01809 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01810 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01811 01812 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01813 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01814 01815 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01816 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01817 01818 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01819 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01820 01821 /* Media and FP Feature Register 0 Definitions */ 01822 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01823 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01824 01825 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01826 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01827 01828 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01829 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01830 01831 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01832 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01833 01834 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01835 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01836 01837 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01838 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01839 01840 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01841 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01842 01843 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01844 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01845 01846 /* Media and FP Feature Register 1 Definitions */ 01847 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01848 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01849 01850 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01851 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01852 01853 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01854 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01855 01856 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01857 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01858 01859 /*@} end of group CMSIS_FPU */ 01860 01861 01862 /** 01863 \ingroup CMSIS_core_register 01864 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01865 \brief Type definitions for the Core Debug Registers 01866 @{ 01867 */ 01868 01869 /** 01870 \brief Structure type to access the Core Debug Register (CoreDebug). 01871 */ 01872 typedef struct 01873 { 01874 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01875 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01876 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01877 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01878 uint32_t RESERVED4[1U]; 01879 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 01880 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 01881 } CoreDebug_Type; 01882 01883 /* Debug Halting Control and Status Register Definitions */ 01884 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01885 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01886 01887 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 01888 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 01889 01890 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01891 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01892 01893 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01894 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01895 01896 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01897 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01898 01899 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01900 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01901 01902 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01903 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01904 01905 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01906 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01907 01908 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01909 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01910 01911 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01912 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01913 01914 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01915 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01916 01917 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01918 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01919 01920 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01921 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01922 01923 /* Debug Core Register Selector Register Definitions */ 01924 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01925 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01926 01927 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01928 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01929 01930 /* Debug Exception and Monitor Control Register Definitions */ 01931 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01932 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01933 01934 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01935 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01936 01937 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01938 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01939 01940 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01941 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01942 01943 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01944 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01945 01946 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01947 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01948 01949 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01950 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01951 01952 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01953 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01954 01955 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01956 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01957 01958 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01959 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01960 01961 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01962 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01963 01964 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01965 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01966 01967 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01968 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01969 01970 /* Debug Authentication Control Register Definitions */ 01971 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 01972 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 01973 01974 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 01975 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 01976 01977 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 01978 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 01979 01980 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 01981 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 01982 01983 /* Debug Security Control and Status Register Definitions */ 01984 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 01985 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 01986 01987 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 01988 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 01989 01990 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 01991 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 01992 01993 /*@} end of group CMSIS_CoreDebug */ 01994 01995 01996 /** 01997 \ingroup CMSIS_core_register 01998 \defgroup CMSIS_core_bitfield Core register bit field macros 01999 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 02000 @{ 02001 */ 02002 02003 /** 02004 \brief Mask and shift a bit field value for use in a register bit range. 02005 \param[in] field Name of the register bit field. 02006 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 02007 \return Masked and shifted value. 02008 */ 02009 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 02010 02011 /** 02012 \brief Mask and shift a register value to extract a bit filed value. 02013 \param[in] field Name of the register bit field. 02014 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 02015 \return Masked and shifted bit field value. 02016 */ 02017 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 02018 02019 /*@} end of group CMSIS_core_bitfield */ 02020 02021 02022 /** 02023 \ingroup CMSIS_core_register 02024 \defgroup CMSIS_core_base Core Definitions 02025 \brief Definitions for base addresses, unions, and structures. 02026 @{ 02027 */ 02028 02029 /* Memory mapping of Core Hardware */ 02030 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 02031 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 02032 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 02033 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 02034 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 02035 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 02036 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 02037 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 02038 02039 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 02040 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 02041 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 02042 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 02043 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 02044 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 02045 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 02046 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 02047 02048 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02049 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 02050 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 02051 #endif 02052 02053 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02054 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 02055 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 02056 #endif 02057 02058 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 02059 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 02060 02061 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02062 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 02063 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 02064 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 02065 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 02066 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 02067 02068 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ 02069 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 02070 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 02071 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 02072 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 02073 02074 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02075 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 02076 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 02077 #endif 02078 02079 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ 02080 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ 02081 02082 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02083 /*@} */ 02084 02085 02086 02087 /******************************************************************************* 02088 * Hardware Abstraction Layer 02089 Core Function Interface contains: 02090 - Core NVIC Functions 02091 - Core SysTick Functions 02092 - Core Debug Functions 02093 - Core Register Access Functions 02094 ******************************************************************************/ 02095 /** 02096 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 02097 */ 02098 02099 02100 02101 /* ########################## NVIC functions #################################### */ 02102 /** 02103 \ingroup CMSIS_Core_FunctionInterface 02104 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 02105 \brief Functions that manage interrupts and exceptions via the NVIC. 02106 @{ 02107 */ 02108 02109 #ifdef CMSIS_NVIC_VIRTUAL 02110 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 02111 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 02112 #endif 02113 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 02114 #else 02115 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 02116 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 02117 #define NVIC_EnableIRQ __NVIC_EnableIRQ 02118 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 02119 #define NVIC_DisableIRQ __NVIC_DisableIRQ 02120 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 02121 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 02122 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 02123 #define NVIC_GetActive __NVIC_GetActive 02124 #define NVIC_SetPriority __NVIC_SetPriority 02125 #define NVIC_GetPriority __NVIC_GetPriority 02126 #define NVIC_SystemReset __NVIC_SystemReset 02127 #endif /* CMSIS_NVIC_VIRTUAL */ 02128 02129 #ifdef CMSIS_VECTAB_VIRTUAL 02130 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02131 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 02132 #endif 02133 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 02134 #else 02135 #define NVIC_SetVector __NVIC_SetVector 02136 #define NVIC_GetVector __NVIC_GetVector 02137 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 02138 02139 #define NVIC_USER_IRQ_OFFSET 16 02140 02141 02142 02143 /** 02144 \brief Set Priority Grouping 02145 \details Sets the priority grouping field using the required unlock sequence. 02146 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02147 Only values from 0..7 are used. 02148 In case of a conflict between priority grouping and available 02149 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02150 \param [in] PriorityGroup Priority grouping field. 02151 */ 02152 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 02153 { 02154 uint32_t reg_value; 02155 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02156 02157 reg_value = SCB->AIRCR; /* read old register configuration */ 02158 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02159 reg_value = (reg_value | 02160 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02161 (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ 02162 SCB->AIRCR = reg_value; 02163 } 02164 02165 02166 /** 02167 \brief Get Priority Grouping 02168 \details Reads the priority grouping field from the NVIC Interrupt Controller. 02169 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02170 */ 02171 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 02172 { 02173 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02174 } 02175 02176 02177 /** 02178 \brief Enable Interrupt 02179 \details Enables a device specific interrupt in the NVIC interrupt controller. 02180 \param [in] IRQn Device specific interrupt number. 02181 \note IRQn must not be negative. 02182 */ 02183 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 02184 { 02185 if ((int32_t)(IRQn) >= 0) 02186 { 02187 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02188 } 02189 } 02190 02191 02192 /** 02193 \brief Get Interrupt Enable status 02194 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 02195 \param [in] IRQn Device specific interrupt number. 02196 \return 0 Interrupt is not enabled. 02197 \return 1 Interrupt is enabled. 02198 \note IRQn must not be negative. 02199 */ 02200 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 02201 { 02202 if ((int32_t)(IRQn) >= 0) 02203 { 02204 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02205 } 02206 else 02207 { 02208 return(0U); 02209 } 02210 } 02211 02212 02213 /** 02214 \brief Disable Interrupt 02215 \details Disables a device specific interrupt in the NVIC interrupt controller. 02216 \param [in] IRQn Device specific interrupt number. 02217 \note IRQn must not be negative. 02218 */ 02219 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 02220 { 02221 if ((int32_t)(IRQn) >= 0) 02222 { 02223 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02224 __DSB(); 02225 __ISB(); 02226 } 02227 } 02228 02229 02230 /** 02231 \brief Get Pending Interrupt 02232 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 02233 \param [in] IRQn Device specific interrupt number. 02234 \return 0 Interrupt status is not pending. 02235 \return 1 Interrupt status is pending. 02236 \note IRQn must not be negative. 02237 */ 02238 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 02239 { 02240 if ((int32_t)(IRQn) >= 0) 02241 { 02242 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02243 } 02244 else 02245 { 02246 return(0U); 02247 } 02248 } 02249 02250 02251 /** 02252 \brief Set Pending Interrupt 02253 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 02254 \param [in] IRQn Device specific interrupt number. 02255 \note IRQn must not be negative. 02256 */ 02257 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 02258 { 02259 if ((int32_t)(IRQn) >= 0) 02260 { 02261 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02262 } 02263 } 02264 02265 02266 /** 02267 \brief Clear Pending Interrupt 02268 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 02269 \param [in] IRQn Device specific interrupt number. 02270 \note IRQn must not be negative. 02271 */ 02272 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 02273 { 02274 if ((int32_t)(IRQn) >= 0) 02275 { 02276 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02277 } 02278 } 02279 02280 02281 /** 02282 \brief Get Active Interrupt 02283 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 02284 \param [in] IRQn Device specific interrupt number. 02285 \return 0 Interrupt status is not active. 02286 \return 1 Interrupt status is active. 02287 \note IRQn must not be negative. 02288 */ 02289 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 02290 { 02291 if ((int32_t)(IRQn) >= 0) 02292 { 02293 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02294 } 02295 else 02296 { 02297 return(0U); 02298 } 02299 } 02300 02301 02302 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02303 /** 02304 \brief Get Interrupt Target State 02305 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02306 \param [in] IRQn Device specific interrupt number. 02307 \return 0 if interrupt is assigned to Secure 02308 \return 1 if interrupt is assigned to Non Secure 02309 \note IRQn must not be negative. 02310 */ 02311 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 02312 { 02313 if ((int32_t)(IRQn) >= 0) 02314 { 02315 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02316 } 02317 else 02318 { 02319 return(0U); 02320 } 02321 } 02322 02323 02324 /** 02325 \brief Set Interrupt Target State 02326 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02327 \param [in] IRQn Device specific interrupt number. 02328 \return 0 if interrupt is assigned to Secure 02329 1 if interrupt is assigned to Non Secure 02330 \note IRQn must not be negative. 02331 */ 02332 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 02333 { 02334 if ((int32_t)(IRQn) >= 0) 02335 { 02336 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02337 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02338 } 02339 else 02340 { 02341 return(0U); 02342 } 02343 } 02344 02345 02346 /** 02347 \brief Clear Interrupt Target State 02348 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 02349 \param [in] IRQn Device specific interrupt number. 02350 \return 0 if interrupt is assigned to Secure 02351 1 if interrupt is assigned to Non Secure 02352 \note IRQn must not be negative. 02353 */ 02354 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 02355 { 02356 if ((int32_t)(IRQn) >= 0) 02357 { 02358 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 02359 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02360 } 02361 else 02362 { 02363 return(0U); 02364 } 02365 } 02366 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02367 02368 02369 /** 02370 \brief Set Interrupt Priority 02371 \details Sets the priority of a device specific interrupt or a processor exception. 02372 The interrupt number can be positive to specify a device specific interrupt, 02373 or negative to specify a processor exception. 02374 \param [in] IRQn Interrupt number. 02375 \param [in] priority Priority to set. 02376 \note The priority cannot be set for every processor exception. 02377 */ 02378 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 02379 { 02380 if ((int32_t)(IRQn) >= 0) 02381 { 02382 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02383 } 02384 else 02385 { 02386 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02387 } 02388 } 02389 02390 02391 /** 02392 \brief Get Interrupt Priority 02393 \details Reads the priority of a device specific interrupt or a processor exception. 02394 The interrupt number can be positive to specify a device specific interrupt, 02395 or negative to specify a processor exception. 02396 \param [in] IRQn Interrupt number. 02397 \return Interrupt Priority. 02398 Value is aligned automatically to the implemented priority bits of the microcontroller. 02399 */ 02400 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 02401 { 02402 02403 if ((int32_t)(IRQn) >= 0) 02404 { 02405 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02406 } 02407 else 02408 { 02409 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02410 } 02411 } 02412 02413 02414 /** 02415 \brief Encode Priority 02416 \details Encodes the priority for an interrupt with the given priority group, 02417 preemptive priority value, and subpriority value. 02418 In case of a conflict between priority grouping and available 02419 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02420 \param [in] PriorityGroup Used priority group. 02421 \param [in] PreemptPriority Preemptive priority value (starting from 0). 02422 \param [in] SubPriority Subpriority value (starting from 0). 02423 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 02424 */ 02425 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 02426 { 02427 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02428 uint32_t PreemptPriorityBits; 02429 uint32_t SubPriorityBits; 02430 02431 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02432 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02433 02434 return ( 02435 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 02436 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 02437 ); 02438 } 02439 02440 02441 /** 02442 \brief Decode Priority 02443 \details Decodes an interrupt priority value with a given priority group to 02444 preemptive priority value and subpriority value. 02445 In case of a conflict between priority grouping and available 02446 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 02447 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 02448 \param [in] PriorityGroup Used priority group. 02449 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 02450 \param [out] pSubPriority Subpriority value (starting from 0). 02451 */ 02452 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 02453 { 02454 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02455 uint32_t PreemptPriorityBits; 02456 uint32_t SubPriorityBits; 02457 02458 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02459 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02460 02461 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 02462 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 02463 } 02464 02465 02466 /** 02467 \brief Set Interrupt Vector 02468 \details Sets an interrupt vector in SRAM based interrupt vector table. 02469 The interrupt number can be positive to specify a device specific interrupt, 02470 or negative to specify a processor exception. 02471 VTOR must been relocated to SRAM before. 02472 \param [in] IRQn Interrupt number 02473 \param [in] vector Address of interrupt handler function 02474 */ 02475 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 02476 { 02477 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02478 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 02479 } 02480 02481 02482 /** 02483 \brief Get Interrupt Vector 02484 \details Reads an interrupt vector from interrupt vector table. 02485 The interrupt number can be positive to specify a device specific interrupt, 02486 or negative to specify a processor exception. 02487 \param [in] IRQn Interrupt number. 02488 \return Address of interrupt handler function 02489 */ 02490 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 02491 { 02492 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02493 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 02494 } 02495 02496 02497 /** 02498 \brief System Reset 02499 \details Initiates a system reset request to reset the MCU. 02500 */ 02501 __STATIC_INLINE void __NVIC_SystemReset(void) 02502 { 02503 __DSB(); /* Ensure all outstanding memory accesses included 02504 buffered write are completed before reset */ 02505 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02506 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 02507 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 02508 __DSB(); /* Ensure completion of memory access */ 02509 02510 for(;;) /* wait until reset */ 02511 { 02512 __NOP(); 02513 } 02514 } 02515 02516 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02517 /** 02518 \brief Set Priority Grouping (non-secure) 02519 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. 02520 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 02521 Only values from 0..7 are used. 02522 In case of a conflict between priority grouping and available 02523 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02524 \param [in] PriorityGroup Priority grouping field. 02525 */ 02526 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) 02527 { 02528 uint32_t reg_value; 02529 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02530 02531 reg_value = SCB_NS->AIRCR; /* read old register configuration */ 02532 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 02533 reg_value = (reg_value | 02534 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02535 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 02536 SCB_NS->AIRCR = reg_value; 02537 } 02538 02539 02540 /** 02541 \brief Get Priority Grouping (non-secure) 02542 \details Reads the priority grouping field from the non-secure NVIC when in secure state. 02543 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 02544 */ 02545 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) 02546 { 02547 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 02548 } 02549 02550 02551 /** 02552 \brief Enable Interrupt (non-secure) 02553 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02554 \param [in] IRQn Device specific interrupt number. 02555 \note IRQn must not be negative. 02556 */ 02557 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 02558 { 02559 if ((int32_t)(IRQn) >= 0) 02560 { 02561 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02562 } 02563 } 02564 02565 02566 /** 02567 \brief Get Interrupt Enable status (non-secure) 02568 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 02569 \param [in] IRQn Device specific interrupt number. 02570 \return 0 Interrupt is not enabled. 02571 \return 1 Interrupt is enabled. 02572 \note IRQn must not be negative. 02573 */ 02574 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 02575 { 02576 if ((int32_t)(IRQn) >= 0) 02577 { 02578 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02579 } 02580 else 02581 { 02582 return(0U); 02583 } 02584 } 02585 02586 02587 /** 02588 \brief Disable Interrupt (non-secure) 02589 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 02590 \param [in] IRQn Device specific interrupt number. 02591 \note IRQn must not be negative. 02592 */ 02593 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 02594 { 02595 if ((int32_t)(IRQn) >= 0) 02596 { 02597 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02598 } 02599 } 02600 02601 02602 /** 02603 \brief Get Pending Interrupt (non-secure) 02604 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 02605 \param [in] IRQn Device specific interrupt number. 02606 \return 0 Interrupt status is not pending. 02607 \return 1 Interrupt status is pending. 02608 \note IRQn must not be negative. 02609 */ 02610 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 02611 { 02612 if ((int32_t)(IRQn) >= 0) 02613 { 02614 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02615 } 02616 else 02617 { 02618 return(0U); 02619 } 02620 } 02621 02622 02623 /** 02624 \brief Set Pending Interrupt (non-secure) 02625 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02626 \param [in] IRQn Device specific interrupt number. 02627 \note IRQn must not be negative. 02628 */ 02629 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 02630 { 02631 if ((int32_t)(IRQn) >= 0) 02632 { 02633 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02634 } 02635 } 02636 02637 02638 /** 02639 \brief Clear Pending Interrupt (non-secure) 02640 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 02641 \param [in] IRQn Device specific interrupt number. 02642 \note IRQn must not be negative. 02643 */ 02644 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 02645 { 02646 if ((int32_t)(IRQn) >= 0) 02647 { 02648 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 02649 } 02650 } 02651 02652 02653 /** 02654 \brief Get Active Interrupt (non-secure) 02655 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 02656 \param [in] IRQn Device specific interrupt number. 02657 \return 0 Interrupt status is not active. 02658 \return 1 Interrupt status is active. 02659 \note IRQn must not be negative. 02660 */ 02661 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 02662 { 02663 if ((int32_t)(IRQn) >= 0) 02664 { 02665 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 02666 } 02667 else 02668 { 02669 return(0U); 02670 } 02671 } 02672 02673 02674 /** 02675 \brief Set Interrupt Priority (non-secure) 02676 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02677 The interrupt number can be positive to specify a device specific interrupt, 02678 or negative to specify a processor exception. 02679 \param [in] IRQn Interrupt number. 02680 \param [in] priority Priority to set. 02681 \note The priority cannot be set for every non-secure processor exception. 02682 */ 02683 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 02684 { 02685 if ((int32_t)(IRQn) >= 0) 02686 { 02687 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02688 } 02689 else 02690 { 02691 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02692 } 02693 } 02694 02695 02696 /** 02697 \brief Get Interrupt Priority (non-secure) 02698 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 02699 The interrupt number can be positive to specify a device specific interrupt, 02700 or negative to specify a processor exception. 02701 \param [in] IRQn Interrupt number. 02702 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 02703 */ 02704 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 02705 { 02706 02707 if ((int32_t)(IRQn) >= 0) 02708 { 02709 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02710 } 02711 else 02712 { 02713 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02714 } 02715 } 02716 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 02717 02718 /*@} end of CMSIS_Core_NVICFunctions */ 02719 02720 /* ########################## MPU functions #################################### */ 02721 02722 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 02723 02724 #include "mpu_armv8.h" 02725 02726 #endif 02727 02728 /* ########################## FPU functions #################################### */ 02729 /** 02730 \ingroup CMSIS_Core_FunctionInterface 02731 \defgroup CMSIS_Core_FpuFunctions FPU Functions 02732 \brief Function that provides FPU type. 02733 @{ 02734 */ 02735 02736 /** 02737 \brief get FPU type 02738 \details returns the FPU type 02739 \returns 02740 - \b 0: No FPU 02741 - \b 1: Single precision FPU 02742 - \b 2: Double + Single precision FPU 02743 */ 02744 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 02745 { 02746 uint32_t mvfr0; 02747 02748 mvfr0 = FPU->MVFR0; 02749 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) 02750 { 02751 return 2U; /* Double + Single precision FPU */ 02752 } 02753 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 02754 { 02755 return 1U; /* Single precision FPU */ 02756 } 02757 else 02758 { 02759 return 0U; /* No FPU */ 02760 } 02761 } 02762 02763 02764 /*@} end of CMSIS_Core_FpuFunctions */ 02765 02766 02767 02768 /* ########################## SAU functions #################################### */ 02769 /** 02770 \ingroup CMSIS_Core_FunctionInterface 02771 \defgroup CMSIS_Core_SAUFunctions SAU Functions 02772 \brief Functions that configure the SAU. 02773 @{ 02774 */ 02775 02776 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02777 02778 /** 02779 \brief Enable SAU 02780 \details Enables the Security Attribution Unit (SAU). 02781 */ 02782 __STATIC_INLINE void TZ_SAU_Enable(void) 02783 { 02784 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 02785 } 02786 02787 02788 02789 /** 02790 \brief Disable SAU 02791 \details Disables the Security Attribution Unit (SAU). 02792 */ 02793 __STATIC_INLINE void TZ_SAU_Disable(void) 02794 { 02795 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 02796 } 02797 02798 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02799 02800 /*@} end of CMSIS_Core_SAUFunctions */ 02801 02802 02803 02804 02805 /* ################################## SysTick function ############################################ */ 02806 /** 02807 \ingroup CMSIS_Core_FunctionInterface 02808 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02809 \brief Functions that configure the System. 02810 @{ 02811 */ 02812 02813 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02814 02815 /** 02816 \brief System Tick Configuration 02817 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02818 Counter is in free running mode to generate periodic interrupts. 02819 \param [in] ticks Number of ticks between two interrupts. 02820 \return 0 Function succeeded. 02821 \return 1 Function failed. 02822 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02823 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02824 must contain a vendor-specific implementation of this function. 02825 */ 02826 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02827 { 02828 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02829 { 02830 return (1UL); /* Reload value impossible */ 02831 } 02832 02833 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02834 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02835 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02836 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02837 SysTick_CTRL_TICKINT_Msk | 02838 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02839 return (0UL); /* Function successful */ 02840 } 02841 02842 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 02843 /** 02844 \brief System Tick Configuration (non-secure) 02845 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 02846 Counter is in free running mode to generate periodic interrupts. 02847 \param [in] ticks Number of ticks between two interrupts. 02848 \return 0 Function succeeded. 02849 \return 1 Function failed. 02850 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02851 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 02852 must contain a vendor-specific implementation of this function. 02853 02854 */ 02855 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 02856 { 02857 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02858 { 02859 return (1UL); /* Reload value impossible */ 02860 } 02861 02862 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02863 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02864 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 02865 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02866 SysTick_CTRL_TICKINT_Msk | 02867 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02868 return (0UL); /* Function successful */ 02869 } 02870 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 02871 02872 #endif 02873 02874 /*@} end of CMSIS_Core_SysTickFunctions */ 02875 02876 02877 02878 /* ##################################### Debug In/Output function ########################################### */ 02879 /** 02880 \ingroup CMSIS_Core_FunctionInterface 02881 \defgroup CMSIS_core_DebugFunctions ITM Functions 02882 \brief Functions that access the ITM debug interface. 02883 @{ 02884 */ 02885 02886 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02887 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02888 02889 02890 /** 02891 \brief ITM Send Character 02892 \details Transmits a character via the ITM channel 0, and 02893 \li Just returns when no debugger is connected that has booked the output. 02894 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02895 \param [in] ch Character to transmit. 02896 \returns Character to transmit. 02897 */ 02898 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02899 { 02900 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02901 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02902 { 02903 while (ITM->PORT[0U].u32 == 0UL) 02904 { 02905 __NOP(); 02906 } 02907 ITM->PORT[0U].u8 = (uint8_t)ch; 02908 } 02909 return (ch); 02910 } 02911 02912 02913 /** 02914 \brief ITM Receive Character 02915 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02916 \return Received character. 02917 \return -1 No character pending. 02918 */ 02919 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02920 { 02921 int32_t ch = -1; /* no character available */ 02922 02923 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02924 { 02925 ch = ITM_RxBuffer; 02926 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02927 } 02928 02929 return (ch); 02930 } 02931 02932 02933 /** 02934 \brief ITM Check Character 02935 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02936 \return 0 No character available. 02937 \return 1 Character available. 02938 */ 02939 __STATIC_INLINE int32_t ITM_CheckChar (void) 02940 { 02941 02942 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02943 { 02944 return (0); /* no character available */ 02945 } 02946 else 02947 { 02948 return (1); /* character available */ 02949 } 02950 } 02951 02952 /*@} end of CMSIS_core_DebugFunctions */ 02953 02954 02955 02956 02957 #ifdef __cplusplus 02958 } 02959 #endif 02960 02961 #endif /* __CORE_CM33_H_DEPENDANT */ 02962 02963 #endif /* __CMSIS_GENERIC */ 02964
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