Robert Lopez
/
CMSIS5
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
core_cm0plus.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file core_cm0plus.h 00003 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 00004 * @version V5.0.4 00005 * @date 10. January 2018 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__clang__) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM0PLUS_H_GENERIC 00032 #define __CORE_CM0PLUS_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex-M0+ 00060 @{ 00061 */ 00062 00063 #include "cmsis_version.h" 00064 00065 /* CMSIS CM0+ definitions */ 00066 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 00067 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 00068 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ 00069 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 00070 00071 #define __CORTEX_M (0U) /*!< Cortex-M Core */ 00072 00073 /** __FPU_USED indicates whether an FPU is used or not. 00074 This core does not support an FPU at all 00075 */ 00076 #define __FPU_USED 0U 00077 00078 #if defined ( __CC_ARM ) 00079 #if defined __TARGET_FPU_VFP 00080 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00081 #endif 00082 00083 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00084 #if defined __ARM_PCS_VFP 00085 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00086 #endif 00087 00088 #elif defined ( __GNUC__ ) 00089 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00090 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00091 #endif 00092 00093 #elif defined ( __ICCARM__ ) 00094 #if defined __ARMVFP__ 00095 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00096 #endif 00097 00098 #elif defined ( __TI_ARM__ ) 00099 #if defined __TI_VFP_SUPPORT__ 00100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00101 #endif 00102 00103 #elif defined ( __TASKING__ ) 00104 #if defined __FPU_VFP__ 00105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00106 #endif 00107 00108 #elif defined ( __CSMC__ ) 00109 #if ( __CSMC__ & 0x400U) 00110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00111 #endif 00112 00113 #endif 00114 00115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00116 00117 00118 #ifdef __cplusplus 00119 } 00120 #endif 00121 00122 #endif /* __CORE_CM0PLUS_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_CM0PLUS_H_DEPENDANT 00127 #define __CORE_CM0PLUS_H_DEPENDANT 00128 00129 #ifdef __cplusplus 00130 extern "C" { 00131 #endif 00132 00133 /* check device defines and use defaults */ 00134 #if defined __CHECK_DEVICE_DEFINES 00135 #ifndef __CM0PLUS_REV 00136 #define __CM0PLUS_REV 0x0000U 00137 #warning "__CM0PLUS_REV not defined in device header file; using default!" 00138 #endif 00139 00140 #ifndef __MPU_PRESENT 00141 #define __MPU_PRESENT 0U 00142 #warning "__MPU_PRESENT not defined in device header file; using default!" 00143 #endif 00144 00145 #ifndef __VTOR_PRESENT 00146 #define __VTOR_PRESENT 0U 00147 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00148 #endif 00149 00150 #ifndef __NVIC_PRIO_BITS 00151 #define __NVIC_PRIO_BITS 2U 00152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00153 #endif 00154 00155 #ifndef __Vendor_SysTickConfig 00156 #define __Vendor_SysTickConfig 0U 00157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00158 #endif 00159 #endif 00160 00161 /* IO definitions (access restrictions to peripheral registers) */ 00162 /** 00163 \defgroup CMSIS_glob_defs CMSIS Global Defines 00164 00165 <strong>IO Type Qualifiers</strong> are used 00166 \li to specify the access to peripheral variables. 00167 \li for automatic generation of peripheral register debug information. 00168 */ 00169 #ifdef __cplusplus 00170 #define __I volatile /*!< Defines 'read only' permissions */ 00171 #else 00172 #define __I volatile const /*!< Defines 'read only' permissions */ 00173 #endif 00174 #define __O volatile /*!< Defines 'write only' permissions */ 00175 #define __IO volatile /*!< Defines 'read / write' permissions */ 00176 00177 /* following defines should be used for structure members */ 00178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00179 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00181 00182 /*@} end of group Cortex-M0+ */ 00183 00184 00185 00186 /******************************************************************************* 00187 * Register Abstraction 00188 Core Register contain: 00189 - Core Register 00190 - Core NVIC Register 00191 - Core SCB Register 00192 - Core SysTick Register 00193 - Core MPU Register 00194 ******************************************************************************/ 00195 /** 00196 \defgroup CMSIS_core_register Defines and Type Definitions 00197 \brief Type definitions and defines for Cortex-M processor based devices. 00198 */ 00199 00200 /** 00201 \ingroup CMSIS_core_register 00202 \defgroup CMSIS_CORE Status and Control Registers 00203 \brief Core Register type definitions. 00204 @{ 00205 */ 00206 00207 /** 00208 \brief Union type to access the Application Program Status Register (APSR). 00209 */ 00210 typedef union 00211 { 00212 struct 00213 { 00214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00219 } b; /*!< Structure used for bit access */ 00220 uint32_t w; /*!< Type used for word access */ 00221 } APSR_Type; 00222 00223 /* APSR Register Definitions */ 00224 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00226 00227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00229 00230 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00232 00233 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00235 00236 00237 /** 00238 \brief Union type to access the Interrupt Program Status Register (IPSR). 00239 */ 00240 typedef union 00241 { 00242 struct 00243 { 00244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00246 } b; /*!< Structure used for bit access */ 00247 uint32_t w; /*!< Type used for word access */ 00248 } IPSR_Type; 00249 00250 /* IPSR Register Definitions */ 00251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00253 00254 00255 /** 00256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00257 */ 00258 typedef union 00259 { 00260 struct 00261 { 00262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00270 } b; /*!< Structure used for bit access */ 00271 uint32_t w; /*!< Type used for word access */ 00272 } xPSR_Type; 00273 00274 /* xPSR Register Definitions */ 00275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00277 00278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00280 00281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00283 00284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00286 00287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00289 00290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00292 00293 00294 /** 00295 \brief Union type to access the Control Registers (CONTROL). 00296 */ 00297 typedef union 00298 { 00299 struct 00300 { 00301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00304 } b; /*!< Structure used for bit access */ 00305 uint32_t w; /*!< Type used for word access */ 00306 } CONTROL_Type; 00307 00308 /* CONTROL Register Definitions */ 00309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00311 00312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00314 00315 /*@} end of group CMSIS_CORE */ 00316 00317 00318 /** 00319 \ingroup CMSIS_core_register 00320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00321 \brief Type definitions for the NVIC Registers 00322 @{ 00323 */ 00324 00325 /** 00326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00327 */ 00328 typedef struct 00329 { 00330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00331 uint32_t RESERVED0[31U]; 00332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00333 uint32_t RSERVED1[31U]; 00334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00335 uint32_t RESERVED2[31U]; 00336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00337 uint32_t RESERVED3[31U]; 00338 uint32_t RESERVED4[64U]; 00339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00340 } NVIC_Type; 00341 00342 /*@} end of group CMSIS_NVIC */ 00343 00344 00345 /** 00346 \ingroup CMSIS_core_register 00347 \defgroup CMSIS_SCB System Control Block (SCB) 00348 \brief Type definitions for the System Control Block Registers 00349 @{ 00350 */ 00351 00352 /** 00353 \brief Structure type to access the System Control Block (SCB). 00354 */ 00355 typedef struct 00356 { 00357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00361 #else 00362 uint32_t RESERVED0; 00363 #endif 00364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00367 uint32_t RESERVED1; 00368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00370 } SCB_Type; 00371 00372 /* SCB CPUID Register Definitions */ 00373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00375 00376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00378 00379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00381 00382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00384 00385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00387 00388 /* SCB Interrupt Control State Register Definitions */ 00389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00391 00392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00394 00395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00397 00398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00400 00401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00403 00404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00406 00407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00409 00410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00412 00413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00415 00416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00417 /* SCB Interrupt Control State Register Definitions */ 00418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ 00419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00420 #endif 00421 00422 /* SCB Application Interrupt and Reset Control Register Definitions */ 00423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00425 00426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00428 00429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00431 00432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00434 00435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00437 00438 /* SCB System Control Register Definitions */ 00439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00441 00442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00444 00445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00447 00448 /* SCB Configuration Control Register Definitions */ 00449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00451 00452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00454 00455 /* SCB System Handler Control and State Register Definitions */ 00456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00458 00459 /*@} end of group CMSIS_SCB */ 00460 00461 00462 /** 00463 \ingroup CMSIS_core_register 00464 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00465 \brief Type definitions for the System Timer Registers. 00466 @{ 00467 */ 00468 00469 /** 00470 \brief Structure type to access the System Timer (SysTick). 00471 */ 00472 typedef struct 00473 { 00474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00478 } SysTick_Type; 00479 00480 /* SysTick Control / Status Register Definitions */ 00481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00483 00484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00486 00487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00489 00490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00492 00493 /* SysTick Reload Register Definitions */ 00494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00496 00497 /* SysTick Current Register Definitions */ 00498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00500 00501 /* SysTick Calibration Register Definitions */ 00502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00504 00505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00507 00508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00510 00511 /*@} end of group CMSIS_SysTick */ 00512 00513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00514 /** 00515 \ingroup CMSIS_core_register 00516 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00517 \brief Type definitions for the Memory Protection Unit (MPU) 00518 @{ 00519 */ 00520 00521 /** 00522 \brief Structure type to access the Memory Protection Unit (MPU). 00523 */ 00524 typedef struct 00525 { 00526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00531 } MPU_Type; 00532 00533 #define MPU_TYPE_RALIASES 1U 00534 00535 /* MPU Type Register Definitions */ 00536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 00537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00538 00539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 00540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00541 00542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 00543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00544 00545 /* MPU Control Register Definitions */ 00546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 00547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00548 00549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 00550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00551 00552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 00553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00554 00555 /* MPU Region Number Register Definitions */ 00556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 00557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00558 00559 /* MPU Region Base Address Register Definitions */ 00560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 00561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00562 00563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 00564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00565 00566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 00567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 00568 00569 /* MPU Region Attribute and Size Register Definitions */ 00570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 00571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00572 00573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 00574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00575 00576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 00577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00578 00579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 00580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00581 00582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 00583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00584 00585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 00586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00587 00588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 00589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00590 00591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 00592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00593 00594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 00595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00596 00597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 00598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 00599 00600 /*@} end of group CMSIS_MPU */ 00601 #endif 00602 00603 00604 /** 00605 \ingroup CMSIS_core_register 00606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 00608 Therefore they are not covered by the Cortex-M0+ header file. 00609 @{ 00610 */ 00611 /*@} end of group CMSIS_CoreDebug */ 00612 00613 00614 /** 00615 \ingroup CMSIS_core_register 00616 \defgroup CMSIS_core_bitfield Core register bit field macros 00617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 00618 @{ 00619 */ 00620 00621 /** 00622 \brief Mask and shift a bit field value for use in a register bit range. 00623 \param[in] field Name of the register bit field. 00624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 00625 \return Masked and shifted value. 00626 */ 00627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 00628 00629 /** 00630 \brief Mask and shift a register value to extract a bit filed value. 00631 \param[in] field Name of the register bit field. 00632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 00633 \return Masked and shifted bit field value. 00634 */ 00635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 00636 00637 /*@} end of group CMSIS_core_bitfield */ 00638 00639 00640 /** 00641 \ingroup CMSIS_core_register 00642 \defgroup CMSIS_core_base Core Definitions 00643 \brief Definitions for base addresses, unions, and structures. 00644 @{ 00645 */ 00646 00647 /* Memory mapping of Core Hardware */ 00648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00652 00653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00656 00657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00660 #endif 00661 00662 /*@} */ 00663 00664 00665 00666 /******************************************************************************* 00667 * Hardware Abstraction Layer 00668 Core Function Interface contains: 00669 - Core NVIC Functions 00670 - Core SysTick Functions 00671 - Core Register Access Functions 00672 ******************************************************************************/ 00673 /** 00674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00675 */ 00676 00677 00678 00679 /* ########################## NVIC functions #################################### */ 00680 /** 00681 \ingroup CMSIS_Core_FunctionInterface 00682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00683 \brief Functions that manage interrupts and exceptions via the NVIC. 00684 @{ 00685 */ 00686 00687 #ifdef CMSIS_NVIC_VIRTUAL 00688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 00689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 00690 #endif 00691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 00692 #else 00693 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ 00694 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ 00695 #define NVIC_EnableIRQ __NVIC_EnableIRQ 00696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 00697 #define NVIC_DisableIRQ __NVIC_DisableIRQ 00698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 00699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 00700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 00701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ 00702 #define NVIC_SetPriority __NVIC_SetPriority 00703 #define NVIC_GetPriority __NVIC_GetPriority 00704 #define NVIC_SystemReset __NVIC_SystemReset 00705 #endif /* CMSIS_NVIC_VIRTUAL */ 00706 00707 #ifdef CMSIS_VECTAB_VIRTUAL 00708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 00710 #endif 00711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 00712 #else 00713 #define NVIC_SetVector __NVIC_SetVector 00714 #define NVIC_GetVector __NVIC_GetVector 00715 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 00716 00717 #define NVIC_USER_IRQ_OFFSET 16 00718 00719 00720 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 00721 /* The following MACROS handle generation of the register offset and byte masks */ 00722 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00723 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00724 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00725 00726 00727 /** 00728 \brief Enable Interrupt 00729 \details Enables a device specific interrupt in the NVIC interrupt controller. 00730 \param [in] IRQn Device specific interrupt number. 00731 \note IRQn must not be negative. 00732 */ 00733 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 00734 { 00735 if ((int32_t)(IRQn) >= 0) 00736 { 00737 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00738 } 00739 } 00740 00741 00742 /** 00743 \brief Get Interrupt Enable status 00744 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 00745 \param [in] IRQn Device specific interrupt number. 00746 \return 0 Interrupt is not enabled. 00747 \return 1 Interrupt is enabled. 00748 \note IRQn must not be negative. 00749 */ 00750 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 00751 { 00752 if ((int32_t)(IRQn) >= 0) 00753 { 00754 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00755 } 00756 else 00757 { 00758 return(0U); 00759 } 00760 } 00761 00762 00763 /** 00764 \brief Disable Interrupt 00765 \details Disables a device specific interrupt in the NVIC interrupt controller. 00766 \param [in] IRQn Device specific interrupt number. 00767 \note IRQn must not be negative. 00768 */ 00769 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 00770 { 00771 if ((int32_t)(IRQn) >= 0) 00772 { 00773 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00774 __DSB(); 00775 __ISB(); 00776 } 00777 } 00778 00779 00780 /** 00781 \brief Get Pending Interrupt 00782 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 00783 \param [in] IRQn Device specific interrupt number. 00784 \return 0 Interrupt status is not pending. 00785 \return 1 Interrupt status is pending. 00786 \note IRQn must not be negative. 00787 */ 00788 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 00789 { 00790 if ((int32_t)(IRQn) >= 0) 00791 { 00792 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00793 } 00794 else 00795 { 00796 return(0U); 00797 } 00798 } 00799 00800 00801 /** 00802 \brief Set Pending Interrupt 00803 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 00804 \param [in] IRQn Device specific interrupt number. 00805 \note IRQn must not be negative. 00806 */ 00807 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 00808 { 00809 if ((int32_t)(IRQn) >= 0) 00810 { 00811 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00812 } 00813 } 00814 00815 00816 /** 00817 \brief Clear Pending Interrupt 00818 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 00819 \param [in] IRQn Device specific interrupt number. 00820 \note IRQn must not be negative. 00821 */ 00822 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00823 { 00824 if ((int32_t)(IRQn) >= 0) 00825 { 00826 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 00827 } 00828 } 00829 00830 00831 /** 00832 \brief Set Interrupt Priority 00833 \details Sets the priority of a device specific interrupt or a processor exception. 00834 The interrupt number can be positive to specify a device specific interrupt, 00835 or negative to specify a processor exception. 00836 \param [in] IRQn Interrupt number. 00837 \param [in] priority Priority to set. 00838 \note The priority cannot be set for every processor exception. 00839 */ 00840 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00841 { 00842 if ((int32_t)(IRQn) >= 0) 00843 { 00844 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00845 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00846 } 00847 else 00848 { 00849 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00850 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00851 } 00852 } 00853 00854 00855 /** 00856 \brief Get Interrupt Priority 00857 \details Reads the priority of a device specific interrupt or a processor exception. 00858 The interrupt number can be positive to specify a device specific interrupt, 00859 or negative to specify a processor exception. 00860 \param [in] IRQn Interrupt number. 00861 \return Interrupt Priority. 00862 Value is aligned automatically to the implemented priority bits of the microcontroller. 00863 */ 00864 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 00865 { 00866 00867 if ((int32_t)(IRQn) >= 0) 00868 { 00869 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00870 } 00871 else 00872 { 00873 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 00874 } 00875 } 00876 00877 00878 /** 00879 \brief Set Interrupt Vector 00880 \details Sets an interrupt vector in SRAM based interrupt vector table. 00881 The interrupt number can be positive to specify a device specific interrupt, 00882 or negative to specify a processor exception. 00883 VTOR must been relocated to SRAM before. 00884 If VTOR is not present address 0 must be mapped to SRAM. 00885 \param [in] IRQn Interrupt number 00886 \param [in] vector Address of interrupt handler function 00887 */ 00888 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 00889 { 00890 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00891 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00892 #else 00893 uint32_t *vectors = (uint32_t *)0x0U; 00894 #endif 00895 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 00896 } 00897 00898 00899 /** 00900 \brief Get Interrupt Vector 00901 \details Reads an interrupt vector from interrupt vector table. 00902 The interrupt number can be positive to specify a device specific interrupt, 00903 or negative to specify a processor exception. 00904 \param [in] IRQn Interrupt number. 00905 \return Address of interrupt handler function 00906 */ 00907 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 00908 { 00909 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 00910 uint32_t *vectors = (uint32_t *)SCB->VTOR; 00911 #else 00912 uint32_t *vectors = (uint32_t *)0x0U; 00913 #endif 00914 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 00915 00916 } 00917 00918 00919 /** 00920 \brief System Reset 00921 \details Initiates a system reset request to reset the MCU. 00922 */ 00923 __STATIC_INLINE void __NVIC_SystemReset(void) 00924 { 00925 __DSB(); /* Ensure all outstanding memory accesses included 00926 buffered write are completed before reset */ 00927 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00928 SCB_AIRCR_SYSRESETREQ_Msk); 00929 __DSB(); /* Ensure completion of memory access */ 00930 00931 for(;;) /* wait until reset */ 00932 { 00933 __NOP(); 00934 } 00935 } 00936 00937 /*@} end of CMSIS_Core_NVICFunctions */ 00938 00939 /* ########################## MPU functions #################################### */ 00940 00941 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 00942 00943 #include "mpu_armv7.h" 00944 00945 #endif 00946 00947 /* ########################## FPU functions #################################### */ 00948 /** 00949 \ingroup CMSIS_Core_FunctionInterface 00950 \defgroup CMSIS_Core_FpuFunctions FPU Functions 00951 \brief Function that provides FPU type. 00952 @{ 00953 */ 00954 00955 /** 00956 \brief get FPU type 00957 \details returns the FPU type 00958 \returns 00959 - \b 0: No FPU 00960 - \b 1: Single precision FPU 00961 - \b 2: Double + Single precision FPU 00962 */ 00963 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 00964 { 00965 return 0U; /* No FPU */ 00966 } 00967 00968 00969 /*@} end of CMSIS_Core_FpuFunctions */ 00970 00971 00972 00973 /* ################################## SysTick function ############################################ */ 00974 /** 00975 \ingroup CMSIS_Core_FunctionInterface 00976 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00977 \brief Functions that configure the System. 00978 @{ 00979 */ 00980 00981 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 00982 00983 /** 00984 \brief System Tick Configuration 00985 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 00986 Counter is in free running mode to generate periodic interrupts. 00987 \param [in] ticks Number of ticks between two interrupts. 00988 \return 0 Function succeeded. 00989 \return 1 Function failed. 00990 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00991 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00992 must contain a vendor-specific implementation of this function. 00993 */ 00994 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00995 { 00996 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 00997 { 00998 return (1UL); /* Reload value impossible */ 00999 } 01000 01001 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01002 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01003 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01004 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01005 SysTick_CTRL_TICKINT_Msk | 01006 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01007 return (0UL); /* Function successful */ 01008 } 01009 01010 #endif 01011 01012 /*@} end of CMSIS_Core_SysTickFunctions */ 01013 01014 01015 01016 01017 #ifdef __cplusplus 01018 } 01019 #endif 01020 01021 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 01022 01023 #endif /* __CMSIS_GENERIC */ 01024
Generated on Tue Jul 12 2022 16:47:29 by
1.7.2