Robert Lopez
Aded CMSIS5 DSP and NN folder. Needs some work
Embed:
(wiki syntax)
Show/hide line numbers
cmsis_iccarm.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file cmsis_iccarm.h 00003 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file 00004 * @version V5.0.6 00005 * @date 02. March 2018 00006 ******************************************************************************/ 00007 00008 //------------------------------------------------------------------------------ 00009 // 00010 // Copyright (c) 2017-2018 IAR Systems 00011 // 00012 // Licensed under the Apache License, Version 2.0 (the "License") 00013 // you may not use this file except in compliance with the License. 00014 // You may obtain a copy of the License at 00015 // http://www.apache.org/licenses/LICENSE-2.0 00016 // 00017 // Unless required by applicable law or agreed to in writing, software 00018 // distributed under the License is distributed on an "AS IS" BASIS, 00019 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00020 // See the License for the specific language governing permissions and 00021 // limitations under the License. 00022 // 00023 //------------------------------------------------------------------------------ 00024 00025 00026 #ifndef __CMSIS_ICCARM_H__ 00027 #define __CMSIS_ICCARM_H__ 00028 00029 #ifndef __ICCARM__ 00030 #error This file should only be compiled by ICCARM 00031 #endif 00032 00033 #pragma system_include 00034 00035 #define __IAR_FT _Pragma("inline=forced") __intrinsic 00036 00037 #if (__VER__ >= 8000000) 00038 #define __ICCARM_V8 1 00039 #else 00040 #define __ICCARM_V8 0 00041 #endif 00042 00043 #ifndef __ALIGNED 00044 #if __ICCARM_V8 00045 #define __ALIGNED(x) __attribute__((aligned(x))) 00046 #elif (__VER__ >= 7080000) 00047 /* Needs IAR language extensions */ 00048 #define __ALIGNED(x) __attribute__((aligned(x))) 00049 #else 00050 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. 00051 #define __ALIGNED(x) 00052 #endif 00053 #endif 00054 00055 00056 /* Define compiler macros for CPU architecture, used in CMSIS 5. 00057 */ 00058 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ 00059 /* Macros already defined */ 00060 #else 00061 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) 00062 #define __ARM_ARCH_8M_MAIN__ 1 00063 #elif defined(__ARM8M_BASELINE__) 00064 #define __ARM_ARCH_8M_BASE__ 1 00065 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' 00066 #if __ARM_ARCH == 6 00067 #define __ARM_ARCH_6M__ 1 00068 #elif __ARM_ARCH == 7 00069 #if __ARM_FEATURE_DSP 00070 #define __ARM_ARCH_7EM__ 1 00071 #else 00072 #define __ARM_ARCH_7M__ 1 00073 #endif 00074 #endif /* __ARM_ARCH */ 00075 #endif /* __ARM_ARCH_PROFILE == 'M' */ 00076 #endif 00077 00078 /* Alternativ core deduction for older ICCARM's */ 00079 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ 00080 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) 00081 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) 00082 #define __ARM_ARCH_6M__ 1 00083 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) 00084 #define __ARM_ARCH_7M__ 1 00085 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) 00086 #define __ARM_ARCH_7EM__ 1 00087 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) 00088 #define __ARM_ARCH_8M_BASE__ 1 00089 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) 00090 #define __ARM_ARCH_8M_MAIN__ 1 00091 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) 00092 #define __ARM_ARCH_8M_MAIN__ 1 00093 #else 00094 #error "Unknown target." 00095 #endif 00096 #endif 00097 00098 00099 00100 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 00101 #define __IAR_M0_FAMILY 1 00102 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 00103 #define __IAR_M0_FAMILY 1 00104 #else 00105 #define __IAR_M0_FAMILY 0 00106 #endif 00107 00108 00109 #ifndef __ASM 00110 #define __ASM __asm 00111 #endif 00112 00113 #ifndef __INLINE 00114 #define __INLINE inline 00115 #endif 00116 00117 #ifndef __NO_RETURN 00118 #if __ICCARM_V8 00119 #define __NO_RETURN __attribute__((__noreturn__)) 00120 #else 00121 #define __NO_RETURN _Pragma("object_attribute=__noreturn") 00122 #endif 00123 #endif 00124 00125 #ifndef __PACKED 00126 #if __ICCARM_V8 00127 #define __PACKED __attribute__((packed, aligned(1))) 00128 #else 00129 /* Needs IAR language extensions */ 00130 #define __PACKED __packed 00131 #endif 00132 #endif 00133 00134 #ifndef __PACKED_STRUCT 00135 #if __ICCARM_V8 00136 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 00137 #else 00138 /* Needs IAR language extensions */ 00139 #define __PACKED_STRUCT __packed struct 00140 #endif 00141 #endif 00142 00143 #ifndef __PACKED_UNION 00144 #if __ICCARM_V8 00145 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 00146 #else 00147 /* Needs IAR language extensions */ 00148 #define __PACKED_UNION __packed union 00149 #endif 00150 #endif 00151 00152 #ifndef __RESTRICT 00153 #define __RESTRICT __restrict 00154 #endif 00155 00156 #ifndef __STATIC_INLINE 00157 #define __STATIC_INLINE static inline 00158 #endif 00159 00160 #ifndef __FORCEINLINE 00161 #define __FORCEINLINE _Pragma("inline=forced") 00162 #endif 00163 00164 #ifndef __STATIC_FORCEINLINE 00165 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE 00166 #endif 00167 00168 #ifndef __UNALIGNED_UINT16_READ 00169 #pragma language=save 00170 #pragma language=extended 00171 __IAR_FT uint16_t __iar_uint16_read(void const *ptr) 00172 { 00173 return *(__packed uint16_t*)(ptr); 00174 } 00175 #pragma language=restore 00176 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) 00177 #endif 00178 00179 00180 #ifndef __UNALIGNED_UINT16_WRITE 00181 #pragma language=save 00182 #pragma language=extended 00183 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) 00184 { 00185 *(__packed uint16_t*)(ptr) = val;; 00186 } 00187 #pragma language=restore 00188 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) 00189 #endif 00190 00191 #ifndef __UNALIGNED_UINT32_READ 00192 #pragma language=save 00193 #pragma language=extended 00194 __IAR_FT uint32_t __iar_uint32_read(void const *ptr) 00195 { 00196 return *(__packed uint32_t*)(ptr); 00197 } 00198 #pragma language=restore 00199 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) 00200 #endif 00201 00202 #ifndef __UNALIGNED_UINT32_WRITE 00203 #pragma language=save 00204 #pragma language=extended 00205 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) 00206 { 00207 *(__packed uint32_t*)(ptr) = val;; 00208 } 00209 #pragma language=restore 00210 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) 00211 #endif 00212 00213 #ifndef __UNALIGNED_UINT32 /* deprecated */ 00214 #pragma language=save 00215 #pragma language=extended 00216 __packed struct __iar_u32 { uint32_t v; }; 00217 #pragma language=restore 00218 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) 00219 #endif 00220 00221 #ifndef __USED 00222 #if __ICCARM_V8 00223 #define __USED __attribute__((used)) 00224 #else 00225 #define __USED _Pragma("__root") 00226 #endif 00227 #endif 00228 00229 #ifndef __WEAK 00230 #if __ICCARM_V8 00231 #define __WEAK __attribute__((weak)) 00232 #else 00233 #define __WEAK _Pragma("__weak") 00234 #endif 00235 #endif 00236 00237 00238 #ifndef __ICCARM_INTRINSICS_VERSION__ 00239 #define __ICCARM_INTRINSICS_VERSION__ 0 00240 #endif 00241 00242 #if __ICCARM_INTRINSICS_VERSION__ == 2 00243 00244 #if defined(__CLZ) 00245 #undef __CLZ 00246 #endif 00247 #if defined(__REVSH) 00248 #undef __REVSH 00249 #endif 00250 #if defined(__RBIT) 00251 #undef __RBIT 00252 #endif 00253 #if defined(__SSAT) 00254 #undef __SSAT 00255 #endif 00256 #if defined(__USAT) 00257 #undef __USAT 00258 #endif 00259 00260 #include "iccarm_builtin.h" 00261 00262 #define __disable_fault_irq __iar_builtin_disable_fiq 00263 #define __disable_irq __iar_builtin_disable_interrupt 00264 #define __enable_fault_irq __iar_builtin_enable_fiq 00265 #define __enable_irq __iar_builtin_enable_interrupt 00266 #define __arm_rsr __iar_builtin_rsr 00267 #define __arm_wsr __iar_builtin_wsr 00268 00269 00270 #define __get_APSR() (__arm_rsr("APSR")) 00271 #define __get_BASEPRI() (__arm_rsr("BASEPRI")) 00272 #define __get_CONTROL() (__arm_rsr("CONTROL")) 00273 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) 00274 00275 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 00276 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 00277 #define __get_FPSCR() (__arm_rsr("FPSCR")) 00278 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) 00279 #else 00280 #define __get_FPSCR() ( 0 ) 00281 #define __set_FPSCR(VALUE) ((void)VALUE) 00282 #endif 00283 00284 #define __get_IPSR() (__arm_rsr("IPSR")) 00285 #define __get_MSP() (__arm_rsr("MSP")) 00286 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00287 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00288 // without main extensions, the non-secure MSPLIM is RAZ/WI 00289 #define __get_MSPLIM() (0U) 00290 #else 00291 #define __get_MSPLIM() (__arm_rsr("MSPLIM")) 00292 #endif 00293 #define __get_PRIMASK() (__arm_rsr("PRIMASK")) 00294 #define __get_PSP() (__arm_rsr("PSP")) 00295 00296 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00297 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00298 // without main extensions, the non-secure PSPLIM is RAZ/WI 00299 #define __get_PSPLIM() (0U) 00300 #else 00301 #define __get_PSPLIM() (__arm_rsr("PSPLIM")) 00302 #endif 00303 00304 #define __get_xPSR() (__arm_rsr("xPSR")) 00305 00306 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) 00307 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) 00308 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) 00309 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) 00310 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) 00311 00312 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00313 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00314 // without main extensions, the non-secure MSPLIM is RAZ/WI 00315 #define __set_MSPLIM(VALUE) ((void)(VALUE)) 00316 #else 00317 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) 00318 #endif 00319 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) 00320 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) 00321 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00322 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 00323 // without main extensions, the non-secure PSPLIM is RAZ/WI 00324 #define __set_PSPLIM(VALUE) ((void)(VALUE)) 00325 #else 00326 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) 00327 #endif 00328 00329 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) 00330 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) 00331 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) 00332 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) 00333 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) 00334 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) 00335 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) 00336 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) 00337 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) 00338 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) 00339 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) 00340 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) 00341 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) 00342 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) 00343 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) 00344 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) 00345 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) 00346 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) 00347 00348 #define __NOP __iar_builtin_no_operation 00349 00350 #define __CLZ __iar_builtin_CLZ 00351 #define __CLREX __iar_builtin_CLREX 00352 00353 #define __DMB __iar_builtin_DMB 00354 #define __DSB __iar_builtin_DSB 00355 #define __ISB __iar_builtin_ISB 00356 00357 #define __LDREXB __iar_builtin_LDREXB 00358 #define __LDREXH __iar_builtin_LDREXH 00359 #define __LDREXW __iar_builtin_LDREX 00360 00361 #define __RBIT __iar_builtin_RBIT 00362 #define __REV __iar_builtin_REV 00363 #define __REV16 __iar_builtin_REV16 00364 00365 __IAR_FT int16_t __REVSH(int16_t val) 00366 { 00367 return (int16_t) __iar_builtin_REVSH(val); 00368 } 00369 00370 #define __ROR __iar_builtin_ROR 00371 #define __RRX __iar_builtin_RRX 00372 00373 #define __SEV __iar_builtin_SEV 00374 00375 #if !__IAR_M0_FAMILY 00376 #define __SSAT __iar_builtin_SSAT 00377 #endif 00378 00379 #define __STREXB __iar_builtin_STREXB 00380 #define __STREXH __iar_builtin_STREXH 00381 #define __STREXW __iar_builtin_STREX 00382 00383 #if !__IAR_M0_FAMILY 00384 #define __USAT __iar_builtin_USAT 00385 #endif 00386 00387 #define __WFE __iar_builtin_WFE 00388 #define __WFI __iar_builtin_WFI 00389 00390 #if __ARM_MEDIA__ 00391 #define __SADD8 __iar_builtin_SADD8 00392 #define __QADD8 __iar_builtin_QADD8 00393 #define __SHADD8 __iar_builtin_SHADD8 00394 #define __UADD8 __iar_builtin_UADD8 00395 #define __UQADD8 __iar_builtin_UQADD8 00396 #define __UHADD8 __iar_builtin_UHADD8 00397 #define __SSUB8 __iar_builtin_SSUB8 00398 #define __QSUB8 __iar_builtin_QSUB8 00399 #define __SHSUB8 __iar_builtin_SHSUB8 00400 #define __USUB8 __iar_builtin_USUB8 00401 #define __UQSUB8 __iar_builtin_UQSUB8 00402 #define __UHSUB8 __iar_builtin_UHSUB8 00403 #define __SADD16 __iar_builtin_SADD16 00404 #define __QADD16 __iar_builtin_QADD16 00405 #define __SHADD16 __iar_builtin_SHADD16 00406 #define __UADD16 __iar_builtin_UADD16 00407 #define __UQADD16 __iar_builtin_UQADD16 00408 #define __UHADD16 __iar_builtin_UHADD16 00409 #define __SSUB16 __iar_builtin_SSUB16 00410 #define __QSUB16 __iar_builtin_QSUB16 00411 #define __SHSUB16 __iar_builtin_SHSUB16 00412 #define __USUB16 __iar_builtin_USUB16 00413 #define __UQSUB16 __iar_builtin_UQSUB16 00414 #define __UHSUB16 __iar_builtin_UHSUB16 00415 #define __SASX __iar_builtin_SASX 00416 #define __QASX __iar_builtin_QASX 00417 #define __SHASX __iar_builtin_SHASX 00418 #define __UASX __iar_builtin_UASX 00419 #define __UQASX __iar_builtin_UQASX 00420 #define __UHASX __iar_builtin_UHASX 00421 #define __SSAX __iar_builtin_SSAX 00422 #define __QSAX __iar_builtin_QSAX 00423 #define __SHSAX __iar_builtin_SHSAX 00424 #define __USAX __iar_builtin_USAX 00425 #define __UQSAX __iar_builtin_UQSAX 00426 #define __UHSAX __iar_builtin_UHSAX 00427 #define __USAD8 __iar_builtin_USAD8 00428 #define __USADA8 __iar_builtin_USADA8 00429 #define __SSAT16 __iar_builtin_SSAT16 00430 #define __USAT16 __iar_builtin_USAT16 00431 #define __UXTB16 __iar_builtin_UXTB16 00432 #define __UXTAB16 __iar_builtin_UXTAB16 00433 #define __SXTB16 __iar_builtin_SXTB16 00434 #define __SXTAB16 __iar_builtin_SXTAB16 00435 #define __SMUAD __iar_builtin_SMUAD 00436 #define __SMUADX __iar_builtin_SMUADX 00437 #define __SMMLA __iar_builtin_SMMLA 00438 #define __SMLAD __iar_builtin_SMLAD 00439 #define __SMLADX __iar_builtin_SMLADX 00440 #define __SMLALD __iar_builtin_SMLALD 00441 #define __SMLALDX __iar_builtin_SMLALDX 00442 #define __SMUSD __iar_builtin_SMUSD 00443 #define __SMUSDX __iar_builtin_SMUSDX 00444 #define __SMLSD __iar_builtin_SMLSD 00445 #define __SMLSDX __iar_builtin_SMLSDX 00446 #define __SMLSLD __iar_builtin_SMLSLD 00447 #define __SMLSLDX __iar_builtin_SMLSLDX 00448 #define __SEL __iar_builtin_SEL 00449 #define __QADD __iar_builtin_QADD 00450 #define __QSUB __iar_builtin_QSUB 00451 #define __PKHBT __iar_builtin_PKHBT 00452 #define __PKHTB __iar_builtin_PKHTB 00453 #endif 00454 00455 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 00456 00457 #if __IAR_M0_FAMILY 00458 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 00459 #define __CLZ __cmsis_iar_clz_not_active 00460 #define __SSAT __cmsis_iar_ssat_not_active 00461 #define __USAT __cmsis_iar_usat_not_active 00462 #define __RBIT __cmsis_iar_rbit_not_active 00463 #define __get_APSR __cmsis_iar_get_APSR_not_active 00464 #endif 00465 00466 00467 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 00468 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 00469 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active 00470 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active 00471 #endif 00472 00473 #ifdef __INTRINSICS_INCLUDED 00474 #error intrinsics.h is already included previously! 00475 #endif 00476 00477 #include <intrinsics.h> 00478 00479 #if __IAR_M0_FAMILY 00480 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 00481 #undef __CLZ 00482 #undef __SSAT 00483 #undef __USAT 00484 #undef __RBIT 00485 #undef __get_APSR 00486 00487 __STATIC_INLINE uint8_t __CLZ(uint32_t data) 00488 { 00489 if (data == 0U) { return 32U; } 00490 00491 uint32_t count = 0U; 00492 uint32_t mask = 0x80000000U; 00493 00494 while ((data & mask) == 0U) 00495 { 00496 count += 1U; 00497 mask = mask >> 1U; 00498 } 00499 return count; 00500 } 00501 00502 __STATIC_INLINE uint32_t __RBIT(uint32_t v) 00503 { 00504 uint8_t sc = 31U; 00505 uint32_t r = v; 00506 for (v >>= 1U; v; v >>= 1U) 00507 { 00508 r <<= 1U; 00509 r |= v & 1U; 00510 sc--; 00511 } 00512 return (r << sc); 00513 } 00514 00515 __STATIC_INLINE uint32_t __get_APSR(void) 00516 { 00517 uint32_t res; 00518 __asm("MRS %0,APSR" : "=r" (res)); 00519 return res; 00520 } 00521 00522 #endif 00523 00524 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 00525 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 00526 #undef __get_FPSCR 00527 #undef __set_FPSCR 00528 #define __get_FPSCR() (0) 00529 #define __set_FPSCR(VALUE) ((void)VALUE) 00530 #endif 00531 00532 #pragma diag_suppress=Pe940 00533 #pragma diag_suppress=Pe177 00534 00535 #define __enable_irq __enable_interrupt 00536 #define __disable_irq __disable_interrupt 00537 #define __NOP __no_operation 00538 00539 #define __get_xPSR __get_PSR 00540 00541 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) 00542 00543 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) 00544 { 00545 return __LDREX((unsigned long *)ptr); 00546 } 00547 00548 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) 00549 { 00550 return __STREX(value, (unsigned long *)ptr); 00551 } 00552 #endif 00553 00554 00555 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 00556 #if (__CORTEX_M >= 0x03) 00557 00558 __IAR_FT uint32_t __RRX(uint32_t value) 00559 { 00560 uint32_t result; 00561 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); 00562 return(result); 00563 } 00564 00565 __IAR_FT void __set_BASEPRI_MAX(uint32_t value) 00566 { 00567 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); 00568 } 00569 00570 00571 #define __enable_fault_irq __enable_fiq 00572 #define __disable_fault_irq __disable_fiq 00573 00574 00575 #endif /* (__CORTEX_M >= 0x03) */ 00576 00577 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) 00578 { 00579 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); 00580 } 00581 00582 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 00583 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 00584 00585 __IAR_FT uint32_t __get_MSPLIM(void) 00586 { 00587 uint32_t res; 00588 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00589 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 00590 // without main extensions, the non-secure MSPLIM is RAZ/WI 00591 res = 0U; 00592 #else 00593 __asm volatile("MRS %0,MSPLIM" : "=r" (res)); 00594 #endif 00595 return res; 00596 } 00597 00598 __IAR_FT void __set_MSPLIM(uint32_t value) 00599 { 00600 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00601 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 00602 // without main extensions, the non-secure MSPLIM is RAZ/WI 00603 (void)value; 00604 #else 00605 __asm volatile("MSR MSPLIM,%0" :: "r" (value)); 00606 #endif 00607 } 00608 00609 __IAR_FT uint32_t __get_PSPLIM(void) 00610 { 00611 uint32_t res; 00612 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00613 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 00614 // without main extensions, the non-secure PSPLIM is RAZ/WI 00615 res = 0U; 00616 #else 00617 __asm volatile("MRS %0,PSPLIM" : "=r" (res)); 00618 #endif 00619 return res; 00620 } 00621 00622 __IAR_FT void __set_PSPLIM(uint32_t value) 00623 { 00624 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 00625 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 00626 // without main extensions, the non-secure PSPLIM is RAZ/WI 00627 (void)value; 00628 #else 00629 __asm volatile("MSR PSPLIM,%0" :: "r" (value)); 00630 #endif 00631 } 00632 00633 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) 00634 { 00635 uint32_t res; 00636 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); 00637 return res; 00638 } 00639 00640 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) 00641 { 00642 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); 00643 } 00644 00645 __IAR_FT uint32_t __TZ_get_PSP_NS(void) 00646 { 00647 uint32_t res; 00648 __asm volatile("MRS %0,PSP_NS" : "=r" (res)); 00649 return res; 00650 } 00651 00652 __IAR_FT void __TZ_set_PSP_NS(uint32_t value) 00653 { 00654 __asm volatile("MSR PSP_NS,%0" :: "r" (value)); 00655 } 00656 00657 __IAR_FT uint32_t __TZ_get_MSP_NS(void) 00658 { 00659 uint32_t res; 00660 __asm volatile("MRS %0,MSP_NS" : "=r" (res)); 00661 return res; 00662 } 00663 00664 __IAR_FT void __TZ_set_MSP_NS(uint32_t value) 00665 { 00666 __asm volatile("MSR MSP_NS,%0" :: "r" (value)); 00667 } 00668 00669 __IAR_FT uint32_t __TZ_get_SP_NS(void) 00670 { 00671 uint32_t res; 00672 __asm volatile("MRS %0,SP_NS" : "=r" (res)); 00673 return res; 00674 } 00675 __IAR_FT void __TZ_set_SP_NS(uint32_t value) 00676 { 00677 __asm volatile("MSR SP_NS,%0" :: "r" (value)); 00678 } 00679 00680 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) 00681 { 00682 uint32_t res; 00683 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); 00684 return res; 00685 } 00686 00687 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) 00688 { 00689 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); 00690 } 00691 00692 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) 00693 { 00694 uint32_t res; 00695 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); 00696 return res; 00697 } 00698 00699 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) 00700 { 00701 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); 00702 } 00703 00704 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) 00705 { 00706 uint32_t res; 00707 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); 00708 return res; 00709 } 00710 00711 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) 00712 { 00713 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); 00714 } 00715 00716 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) 00717 { 00718 uint32_t res; 00719 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); 00720 return res; 00721 } 00722 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) 00723 { 00724 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); 00725 } 00726 00727 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) 00728 { 00729 uint32_t res; 00730 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); 00731 return res; 00732 } 00733 00734 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) 00735 { 00736 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); 00737 } 00738 00739 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 00740 00741 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 00742 00743 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) 00744 00745 #if __IAR_M0_FAMILY 00746 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 00747 { 00748 if ((sat >= 1U) && (sat <= 32U)) 00749 { 00750 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 00751 const int32_t min = -1 - max ; 00752 if (val > max) 00753 { 00754 return max; 00755 } 00756 else if (val < min) 00757 { 00758 return min; 00759 } 00760 } 00761 return val; 00762 } 00763 00764 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 00765 { 00766 if (sat <= 31U) 00767 { 00768 const uint32_t max = ((1U << sat) - 1U); 00769 if (val > (int32_t)max) 00770 { 00771 return max; 00772 } 00773 else if (val < 0) 00774 { 00775 return 0U; 00776 } 00777 } 00778 return (uint32_t)val; 00779 } 00780 #endif 00781 00782 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 00783 00784 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) 00785 { 00786 uint32_t res; 00787 __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 00788 return ((uint8_t)res); 00789 } 00790 00791 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) 00792 { 00793 uint32_t res; 00794 __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 00795 return ((uint16_t)res); 00796 } 00797 00798 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) 00799 { 00800 uint32_t res; 00801 __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 00802 return res; 00803 } 00804 00805 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) 00806 { 00807 __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 00808 } 00809 00810 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) 00811 { 00812 __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 00813 } 00814 00815 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) 00816 { 00817 __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); 00818 } 00819 00820 #endif /* (__CORTEX_M >= 0x03) */ 00821 00822 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 00823 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 00824 00825 00826 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) 00827 { 00828 uint32_t res; 00829 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00830 return ((uint8_t)res); 00831 } 00832 00833 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) 00834 { 00835 uint32_t res; 00836 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00837 return ((uint16_t)res); 00838 } 00839 00840 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) 00841 { 00842 uint32_t res; 00843 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00844 return res; 00845 } 00846 00847 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) 00848 { 00849 __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); 00850 } 00851 00852 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) 00853 { 00854 __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); 00855 } 00856 00857 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) 00858 { 00859 __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); 00860 } 00861 00862 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) 00863 { 00864 uint32_t res; 00865 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00866 return ((uint8_t)res); 00867 } 00868 00869 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) 00870 { 00871 uint32_t res; 00872 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00873 return ((uint16_t)res); 00874 } 00875 00876 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) 00877 { 00878 uint32_t res; 00879 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); 00880 return res; 00881 } 00882 00883 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 00884 { 00885 uint32_t res; 00886 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); 00887 return res; 00888 } 00889 00890 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 00891 { 00892 uint32_t res; 00893 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); 00894 return res; 00895 } 00896 00897 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 00898 { 00899 uint32_t res; 00900 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); 00901 return res; 00902 } 00903 00904 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 00905 00906 #undef __IAR_FT 00907 #undef __IAR_M0_FAMILY 00908 #undef __ICCARM_V8 00909 00910 #pragma diag_default=Pe940 00911 #pragma diag_default=Pe177 00912 00913 #endif /* __CMSIS_ICCARM_H__ */ 00914
Generated on Tue Jul 12 2022 16:47:28 by
1.7.2