arm_nnsupportfunctions.h

00001 /*
00002  * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /* ----------------------------------------------------------------------
00020  * Project:      CMSIS NN Library
00021  * Title:        arm_nnsupportfunctions.h
00022  * Description:  Public header file of support functions for CMSIS NN Library
00023  *
00024  * $Date:        17. January 2018
00025  * $Revision:    V.1.0.0
00026  *
00027  * Target Processor:  Cortex-M cores
00028  * -------------------------------------------------------------------- */
00029 
00030 #ifndef _ARM_NNSUPPORTFUNCTIONS_H_
00031 #define _ARM_NNSUPPORTFUNCTIONS_H_
00032 
00033 #include "../../DSP/include/arm_math.h"
00034 #include "../../DSP/include/arm_common_tables.h"
00035 #include "../../Core/include/cmsis_armclang.h"
00036 //#include <cstring>
00037 
00038 #ifdef __cplusplus
00039 extern    "C"
00040 {
00041 #endif
00042 
00043 /**
00044  * @brief Union for SIMD access of Q31/Q15/Q7 types
00045  */
00046 union arm_nnword
00047 {
00048     q31_t     word;
00049                /**< Q31 type */
00050     q15_t     half_words[2];
00051                /**< Q15 type */
00052     q7_t      bytes[4];
00053                /**< Q7 type */
00054 };
00055 
00056 /**
00057  * @brief Struct for specifying activation function types
00058  *
00059  */
00060 typedef enum
00061 {
00062     ARM_SIGMOID = 0,
00063                 /**< Sigmoid activation function */
00064     ARM_TANH = 1,
00065              /**< Tanh activation function */
00066 } arm_nn_activation_type;
00067 
00068 /**
00069  * @defgroup nndata_convert Neural Network Data Conversion Functions
00070  *
00071  * Perform data type conversion in-between neural network operations
00072  *
00073  */
00074 
00075 /**
00076  * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift 
00077  * @param[in]       *pSrc points to the Q7 input vector    
00078  * @param[out]      *pDst points to the Q15 output vector   
00079  * @param[in]       blockSize length of the input vector    
00080  * @return none.    
00081  *
00082  */
00083 
00084 void      arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
00085 
00086 /**
00087  * @brief  Converts the elements of the Q7 vector to reordered Q15 vector without left-shift
00088  * @param[in]       *pSrc points to the Q7 input vector    
00089  * @param[out]      *pDst points to the Q15 output vector   
00090  * @param[in]       blockSize length of the input vector    
00091  * @return none.    
00092  *
00093  */
00094 
00095 void      arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize);
00096 
00097 #if defined (ARM_MATH_DSP)
00098 
00099 /**
00100  * @brief read and expand one Q7 word into two Q15 words
00101  */
00102 
00103 __STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2)
00104 {
00105         q31_t     inA = *__SIMD32(source)++;
00106         q31_t     inAbuf1 = __SXTB16(__ROR(inA, 8));
00107         q31_t     inAbuf2 = __SXTB16(inA);
00108 
00109 #ifndef ARM_MATH_BIG_ENDIAN
00110         *out2 = __PKHTB(inAbuf1, inAbuf2, 16);
00111         *out1 = __PKHBT(inAbuf2, inAbuf1, 16);
00112 #else
00113         *out1 = __PKHTB(inAbuf1, inAbuf2, 16);
00114         *out2 = __PKHBT(inAbuf2, inAbuf1, 16);
00115 #endif
00116 
00117         return source;
00118 }
00119 
00120 /**
00121  * @brief read and expand one Q7 word into two Q15 words with reordering
00122  */
00123 
00124 __STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2)
00125 {
00126         q31_t     inA = *__SIMD32(source)++;
00127 #ifndef ARM_MATH_BIG_ENDIAN
00128         *out2 = __SXTB16(__ROR(inA, 8));
00129         *out1 = __SXTB16(inA);
00130 #else
00131         *out1 = __SXTB16(__ROR(inA, 8));
00132         *out2 = __SXTB16(inA);
00133 #endif
00134 
00135         return source;
00136 }
00137 #endif
00138 
00139 /**
00140  * @brief defition to adding rouding offset
00141  */
00142 #ifndef ARM_NN_TRUNCATE
00143     #define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) )
00144 #else
00145     #define NN_ROUND(out_shift) 0
00146 #endif
00147 
00148 #ifdef __cplusplus
00149 }
00150 #endif
00151 
00152 #endif
00153