arm_convolve_HWC_q7_RGB.c

00001 /*
00002  * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /* ----------------------------------------------------------------------
00020  * Project:      CMSIS NN Library
00021  * Title:        arm_convolve_HWC_q7_RGB.c
00022  * Description:  Q7 version of convolution for RGB image
00023  *
00024  * $Date:        17. January 2018
00025  * $Revision:    V.1.0.0
00026  *
00027  * Target Processor:  Cortex-M cores
00028  *
00029  * -------------------------------------------------------------------- */
00030 #include "arm_math.h"
00031 #include "arm_nnfunctions.h"
00032 
00033 /**
00034  *  @ingroup groupNN
00035  */
00036 
00037 /**
00038  * @addtogroup NNConv
00039  * @{
00040  */
00041 
00042   /**
00043    * @brief Q7 convolution function for RGB image
00044    * @param[in]       Im_in       pointer to input tensor
00045    * @param[in]       dim_im_in   input tensor dimention
00046    * @param[in]       ch_im_in    number of input tensor channels
00047    * @param[in]       wt          pointer to kernel weights
00048    * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
00049    * @param[in]       dim_kernel  filter kernel size
00050    * @param[in]       padding     padding sizes
00051    * @param[in]       stride      convolution stride
00052    * @param[in]       bias        pointer to bias
00053    * @param[in]       bias_shift  amount of left-shift for bias
00054    * @param[in]       out_shift   amount of right-shift for output
00055    * @param[in,out]   Im_out      pointer to output tensor
00056    * @param[in]       dim_im_out  output tensor dimension
00057    * @param[in,out]   bufferA     pointer to buffer space for input
00058    * @param[in,out]   bufferB     pointer to buffer space for output
00059    * @return     The function returns either
00060    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
00061    *
00062    * @details
00063    *
00064    * <b>Buffer size:</b>
00065    *
00066    * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
00067    *
00068    * bufferB size: 0
00069    *
00070    * <b>Input dimension constraints:</b>
00071    *
00072    * ch_im_in equals 3
00073    *
00074    * This kernel is written exclusively for convolution with ch_im_in
00075    * equals 3. This applies on the first layer of CNNs which has input
00076    * image with RGB format.
00077    */
00078 
00079 arm_status
00080 arm_convolve_HWC_q7_RGB(const q7_t * Im_in,
00081                         const uint16_t dim_im_in,
00082                         const uint16_t ch_im_in,
00083                         const q7_t * wt,
00084                         const uint16_t ch_im_out,
00085                         const uint16_t dim_kernel,
00086                         const uint16_t padding,
00087                         const uint16_t stride,
00088                         const q7_t * bias,
00089                         const uint16_t bias_shift,
00090                         const uint16_t out_shift,
00091                         q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB)
00092 {
00093 
00094 #if defined (ARM_MATH_DSP)
00095     /* Run the following code for Cortex-M4 and Cortex-M7 */
00096     int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
00097 
00098     /*
00099      *  Here we use bufferA as q15_t internally as computation are done with q15_t level
00100      *  im2col are done to output in q15_t format from q7_t input
00101      */
00102     q15_t    *pBuffer = bufferA;
00103     q7_t     *pOut = Im_out;
00104 
00105     // check if number of input channels is 3
00106     if (ch_im_in != 3)
00107     {
00108         return ARM_MATH_SIZE_MISMATCH;
00109     }
00110     // This part implements the im2col function
00111     for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
00112     {
00113         for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
00114         {
00115             for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
00116             {
00117                 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
00118                 {
00119                     if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
00120                     {
00121                         /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */
00122                         *__SIMD32(pBuffer) = 0x0;
00123                         *(pBuffer + 2) = 0;
00124                         pBuffer += 3;
00125                     } else
00126                     {
00127                         /* 
00128                          * Equivalent to:
00129                          *  arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3);
00130                          */
00131 
00132                         const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3;
00133                         q31_t     buf = *__SIMD32(pPixel);
00134 
00135                         union arm_nnword top;
00136                         union arm_nnword bottom;
00137 
00138                         top.word = __SXTB16(buf);
00139                         bottom.word = __SXTB16(__ROR(buf, 8));
00140 
00141 #ifndef ARM_MATH_BIG_ENDIAN
00142                         /*
00143                          *  little-endian, | omit | 3rd  | 2nd  | 1st  |
00144                          *                MSB                         LSB
00145                          *   top | 3rd | 1st |; bottom | omit | 2nd |
00146                          *
00147                          *  version 1, need to swap 2nd and 3rd weight
00148                          * *__SIMD32(pBuffer) = top.word;
00149                          * *(pBuffer+2) = bottom.half_words[0];
00150                          *
00151                          *  version 2, no weight shuffling required
00152                          */
00153                         *pBuffer++ = top.half_words[0];
00154                         *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0);
00155 #else
00156                         /*
00157                          *  big-endian,    | 1st  | 2nd  | 3rd  | omit | 
00158                          *                MSB                         LSB
00159                          *  top | 2nd | omit |; bottom | 1st | 3rd |
00160                          * 
00161                          *  version 1, need to swap 2nd and 3rd weight
00162                          * *__SIMD32(pBuffer) = bottom.word;
00163                          * *(pBuffer+2) = top.half_words[1];
00164                          * 
00165                          *  version 2, no weight shuffling required
00166                          */
00167                         *pBuffer++ = bottom.half_words[0];
00168                         *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0);
00169 #endif
00170                         pBuffer += 2;
00171                     }
00172                 }
00173             }
00174 
00175             if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel)
00176             {
00177                 pOut =
00178                     arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
00179                                                   ch_im_out,
00180                                                   3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
00181 
00182                 /* counter reset */
00183                 pBuffer = bufferA;
00184             }
00185         }
00186     }
00187 
00188     /* left-over because odd number of output pixels */
00189     if (pBuffer != bufferA)
00190     {
00191         const q7_t *pA = wt;
00192         int       i;
00193 
00194         for (i = 0; i < ch_im_out; i++)
00195         {
00196             q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
00197             q15_t    *pB = bufferA;
00198             /* basically each time it process 4 entries */
00199             uint16_t  colCnt = 3 * dim_kernel * dim_kernel >> 2;
00200 
00201             while (colCnt)
00202             {
00203 
00204                 q31_t     inA1, inA2;
00205                 q31_t     inB1, inB2;
00206 
00207                 pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
00208 
00209                 inB1 = *__SIMD32(pB)++;
00210                 sum = __SMLAD(inA1, inB1, sum);
00211                 inB2 = *__SIMD32(pB)++;
00212                 sum = __SMLAD(inA2, inB2, sum);
00213 
00214                 colCnt--;
00215             }
00216             colCnt = 3 * dim_kernel * dim_kernel & 0x3;
00217             while (colCnt)
00218             {
00219                 q7_t      inA1 = *pA++;
00220                 q15_t     inB1 = *pB++;
00221                 sum += inA1 * inB1;
00222                 colCnt--;
00223             }
00224             *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
00225         }
00226     }
00227 #else
00228     /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
00229 
00230     uint16_t  i, j, k, l, m, n;
00231     int       conv_out;
00232     signed char in_row, in_col;
00233 
00234     // check if number of input channels is 3
00235     if (ch_im_in != 3)
00236     {
00237         return ARM_MATH_SIZE_MISMATCH;
00238     }
00239 
00240     for (i = 0; i < ch_im_out; i++)
00241     {
00242         for (j = 0; j < dim_im_out; j++)
00243         {
00244             for (k = 0; k < dim_im_out; k++)
00245             {
00246                 conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift);
00247                 for (m = 0; m < dim_kernel; m++)
00248                 {
00249                     for (n = 0; n < dim_kernel; n++)
00250                     {
00251                         /* if-for implementation */
00252                         in_row = stride * j + m - padding;
00253                         in_col = stride * k + n - padding;
00254                         if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
00255                         {
00256                             for (l = 0; l < ch_im_in; l++)
00257                             {
00258                                 conv_out +=
00259                                     Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
00260                                           l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
00261                                                                                             n) * ch_im_in + l];
00262                             }
00263                         }
00264                     }
00265                 }
00266                 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
00267             }
00268         }
00269     }
00270 
00271 #endif                          /* ARM_MATH_DSP */
00272 
00273     /* Return to application */
00274     return (ARM_MATH_SUCCESS);
00275 }
00276 
00277 /**
00278  * @} end of NNConv group
00279  */
00280