arm_convolve_HWC_q15_basic.c

00001 /*
00002  * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
00003  *
00004  * SPDX-License-Identifier: Apache-2.0
00005  *
00006  * Licensed under the Apache License, Version 2.0 (the License); you may
00007  * not use this file except in compliance with the License.
00008  * You may obtain a copy of the License at
00009  *
00010  * www.apache.org/licenses/LICENSE-2.0
00011  *
00012  * Unless required by applicable law or agreed to in writing, software
00013  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00014  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00015  * See the License for the specific language governing permissions and
00016  * limitations under the License.
00017  */
00018 
00019 /* ----------------------------------------------------------------------
00020  * Project:      CMSIS NN Library
00021  * Title:        arm_convolve_HWC_q15_basic.c
00022  * Description:  Q15 version of convolution
00023  *
00024  * $Date:        17. January 2018
00025  * $Revision:    V.1.0.0
00026  *
00027  * Target Processor:  Cortex-M cores
00028  *
00029  * -------------------------------------------------------------------- */
00030 
00031 #include "arm_math.h"
00032 #include "arm_nnfunctions.h"
00033 
00034 /**
00035  *  @ingroup groupNN
00036  */
00037 
00038 /**
00039  * @addtogroup NNConv
00040  * @{
00041  */
00042 
00043   /**
00044    * @brief Basic Q15 convolution function
00045    * @param[in]       Im_in       pointer to input tensor
00046    * @param[in]       dim_im_in   input tensor dimention
00047    * @param[in]       ch_im_in    number of input tensor channels
00048    * @param[in]       wt          pointer to kernel weights
00049    * @param[in]       ch_im_out   number of filters, i.e., output tensor channels
00050    * @param[in]       dim_kernel  filter kernel size
00051    * @param[in]       padding     padding sizes
00052    * @param[in]       stride      convolution stride
00053    * @param[in]       bias        pointer to bias
00054    * @param[in]       bias_shift  amount of left-shift for bias
00055    * @param[in]       out_shift   amount of right-shift for output
00056    * @param[in,out]   Im_out      pointer to output tensor
00057    * @param[in]       dim_im_out  output tensor dimension
00058    * @param[in,out]   bufferA     pointer to buffer space for input
00059    * @param[in,out]   bufferB     pointer to buffer space for output
00060    * @return     The function returns <code>ARM_MATH_SUCCESS</code> 
00061    *
00062    * @details
00063    *
00064    * <b>Buffer size:</b>
00065    *
00066    * bufferA size: ch_im_in*dim_kernel*dim_kernel
00067    *
00068    * bufferB size: 0
00069    *
00070    * This basic version is designed to work for any input tensor and weight
00071    * dimension. 
00072    */
00073 
00074 arm_status
00075 arm_convolve_HWC_q15_basic(const q15_t * Im_in,
00076                            const uint16_t dim_im_in,
00077                            const uint16_t ch_im_in,
00078                            const q15_t * wt,
00079                            const uint16_t ch_im_out,
00080                            const uint16_t dim_kernel,
00081                            const uint16_t padding,
00082                            const uint16_t stride,
00083                            const q15_t * bias,
00084                            const uint16_t bias_shift,
00085                            const uint16_t out_shift,
00086                            q15_t * Im_out, 
00087                            const uint16_t dim_im_out, 
00088                            q15_t * bufferA, 
00089                            q7_t * bufferB)
00090 {
00091 
00092 #if defined (ARM_MATH_DSP)
00093     /* Run the following code for Cortex-M4 and Cortex-M7 */
00094 
00095     int16_t   i_out_y, i_out_x, i_ker_y, i_ker_x;
00096 
00097     uint16_t  im2col_out_pixel_index = 0;
00098     q15_t    *pBuffer = bufferA;
00099     q15_t    *pOut = Im_out;
00100     q15_t    *im_buffer = bufferA;
00101     const q15_t *pA;
00102     int       i;
00103 
00104     /* This part implements the im2col function */
00105     for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
00106     {
00107         for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
00108         {
00109             for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
00110             {
00111                 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
00112                 {
00113                     if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
00114                     {
00115                         /* Filling 0 for out-of-bound paddings */
00116                         /* arm_fill_q15(0, pBuffer, ch_im_in); */
00117                         memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
00118                     } else
00119                     {
00120                         /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */
00121                         memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in);
00122                     }
00123                     pBuffer += ch_im_in;
00124                 }
00125             }
00126 
00127             pA = wt;
00128             for (i = 0; i < ch_im_out; i++)
00129             {
00130                 q31_t     sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
00131                 q15_t    *pB = im_buffer;
00132                 uint16_t  colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
00133                 while (colCnt)
00134                 {
00135                     q31_t     inA1 = *__SIMD32(pA)++;
00136                     q31_t     inB1 = *__SIMD32(pB)++;
00137                     q31_t     inA2 = *__SIMD32(pA)++;
00138                     q31_t     inB2 = *__SIMD32(pB)++;
00139 
00140                     sum = __SMLAD(inA1, inB1, sum);
00141                     sum = __SMLAD(inA2, inB2, sum);
00142 
00143                     colCnt--;
00144                 }
00145                 colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
00146                 while (colCnt)
00147                 {
00148                     q15_t     inA1 = *pA++;
00149                     q15_t     inB1 = *pB++;
00150                     sum += inA1 * inB1;
00151                     colCnt--;
00152                 }
00153                 *pOut = (q15_t) __SSAT((sum >> out_shift), 16);
00154                 pOut++;
00155             }
00156 
00157             /* counter reset */
00158             pBuffer = im_buffer;
00159             im2col_out_pixel_index++;
00160         }
00161     }
00162 
00163 #else
00164     /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
00165     uint16_t  i, j, k, l, m, n;
00166     int       conv_out;
00167     signed char in_row, in_col;
00168 
00169     for (i = 0; i < ch_im_out; i++)
00170     {
00171         for (j = 0; j < dim_im_out; j++)
00172         {
00173             for (k = 0; k < dim_im_out; k++)
00174             {
00175                 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
00176                 for (m = 0; m < dim_kernel; m++)
00177                 {
00178                     for (n = 0; n < dim_kernel; n++)
00179                     {
00180                         in_row = stride * j + m - padding;
00181                         in_col = stride * k + n - padding;
00182                         if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
00183                         {
00184                             for (l = 0; l < ch_im_in; l++)
00185                             {
00186                                 conv_out +=
00187                                     Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
00188                                           l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
00189                                                                                             n) * ch_im_in + l];
00190                             }
00191                         }
00192                     }
00193                 }
00194                 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16);
00195             }
00196         }
00197     }
00198 
00199 #endif                          /* ARM_MATH_DSP */
00200 
00201     /* Return to application */
00202     return ARM_MATH_SUCCESS;
00203 }
00204 
00205 /**
00206  * @} end of NNConv group
00207  */
00208