arm_cmplx_dot_prod_q31.c

00001 /* ----------------------------------------------------------------------
00002  * Project:      CMSIS DSP Library
00003  * Title:        arm_cmplx_dot_prod_q31.c
00004  * Description:  Q31 complex dot product
00005  *
00006  * $Date:        27. January 2017
00007  * $Revision:    V.1.5.1
00008  *
00009  * Target Processor: Cortex-M cores
00010  * -------------------------------------------------------------------- */
00011 /*
00012  * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
00013  *
00014  * SPDX-License-Identifier: Apache-2.0
00015  *
00016  * Licensed under the Apache License, Version 2.0 (the License); you may
00017  * not use this file except in compliance with the License.
00018  * You may obtain a copy of the License at
00019  *
00020  * www.apache.org/licenses/LICENSE-2.0
00021  *
00022  * Unless required by applicable law or agreed to in writing, software
00023  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00024  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00025  * See the License for the specific language governing permissions and
00026  * limitations under the License.
00027  */
00028 
00029 #include "arm_math.h"
00030 
00031 /**
00032  * @ingroup groupCmplxMath
00033  */
00034 
00035 /**
00036  * @addtogroup cmplx_dot_prod
00037  * @{
00038  */
00039 
00040 /**
00041  * @brief  Q31 complex dot product
00042  * @param  *pSrcA points to the first input vector
00043  * @param  *pSrcB points to the second input vector
00044  * @param  numSamples number of complex samples in each vector
00045  * @param  *realResult real part of the result returned here
00046  * @param  *imagResult imaginary part of the result returned here
00047  * @return none.
00048  *
00049  * <b>Scaling and Overflow Behavior:</b>
00050  * \par
00051  * The function is implemented using an internal 64-bit accumulator.
00052  * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
00053  * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
00054  * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
00055  * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
00056  * Input down scaling is not required.
00057  */
00058 
00059 void arm_cmplx_dot_prod_q31(
00060   q31_t * pSrcA,
00061   q31_t * pSrcB,
00062   uint32_t numSamples,
00063   q63_t * realResult,
00064   q63_t * imagResult)
00065 {
00066   q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
00067   q31_t a0,b0,c0,d0;
00068 
00069 #if defined (ARM_MATH_DSP)
00070 
00071   /* Run the below code for Cortex-M4 and Cortex-M3 */
00072   uint32_t blkCnt;                               /* loop counter */
00073 
00074 
00075   /*loop Unrolling */
00076   blkCnt = numSamples >> 2U;
00077 
00078   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
00079    ** a second loop below computes the remaining 1 to 3 samples. */
00080   while (blkCnt > 0U)
00081   {
00082       a0 = *pSrcA++;
00083       b0 = *pSrcA++;
00084       c0 = *pSrcB++;
00085       d0 = *pSrcB++;
00086 
00087       real_sum += ((q63_t)a0 * c0) >> 14;
00088       imag_sum += ((q63_t)a0 * d0) >> 14;
00089       real_sum -= ((q63_t)b0 * d0) >> 14;
00090       imag_sum += ((q63_t)b0 * c0) >> 14;
00091 
00092       a0 = *pSrcA++;
00093       b0 = *pSrcA++;
00094       c0 = *pSrcB++;
00095       d0 = *pSrcB++;
00096 
00097       real_sum += ((q63_t)a0 * c0) >> 14;
00098       imag_sum += ((q63_t)a0 * d0) >> 14;
00099       real_sum -= ((q63_t)b0 * d0) >> 14;
00100       imag_sum += ((q63_t)b0 * c0) >> 14;
00101 
00102       a0 = *pSrcA++;
00103       b0 = *pSrcA++;
00104       c0 = *pSrcB++;
00105       d0 = *pSrcB++;
00106 
00107       real_sum += ((q63_t)a0 * c0) >> 14;
00108       imag_sum += ((q63_t)a0 * d0) >> 14;
00109       real_sum -= ((q63_t)b0 * d0) >> 14;
00110       imag_sum += ((q63_t)b0 * c0) >> 14;
00111 
00112       a0 = *pSrcA++;
00113       b0 = *pSrcA++;
00114       c0 = *pSrcB++;
00115       d0 = *pSrcB++;
00116 
00117       real_sum += ((q63_t)a0 * c0) >> 14;
00118       imag_sum += ((q63_t)a0 * d0) >> 14;
00119       real_sum -= ((q63_t)b0 * d0) >> 14;
00120       imag_sum += ((q63_t)b0 * c0) >> 14;
00121 
00122       /* Decrement the loop counter */
00123       blkCnt--;
00124   }
00125 
00126   /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.
00127    ** No loop unrolling is used. */
00128   blkCnt = numSamples % 0x4U;
00129 
00130   while (blkCnt > 0U)
00131   {
00132       a0 = *pSrcA++;
00133       b0 = *pSrcA++;
00134       c0 = *pSrcB++;
00135       d0 = *pSrcB++;
00136 
00137       real_sum += ((q63_t)a0 * c0) >> 14;
00138       imag_sum += ((q63_t)a0 * d0) >> 14;
00139       real_sum -= ((q63_t)b0 * d0) >> 14;
00140       imag_sum += ((q63_t)b0 * c0) >> 14;
00141 
00142       /* Decrement the loop counter */
00143       blkCnt--;
00144   }
00145 
00146 #else
00147 
00148   /* Run the below code for Cortex-M0 */
00149 
00150   while (numSamples > 0U)
00151   {
00152       a0 = *pSrcA++;
00153       b0 = *pSrcA++;
00154       c0 = *pSrcB++;
00155       d0 = *pSrcB++;
00156 
00157       real_sum += ((q63_t)a0 * c0) >> 14;
00158       imag_sum += ((q63_t)a0 * d0) >> 14;
00159       real_sum -= ((q63_t)b0 * d0) >> 14;
00160       imag_sum += ((q63_t)b0 * c0) >> 14;
00161 
00162       /* Decrement the loop counter */
00163       numSamples--;
00164   }
00165 
00166 #endif /* #if defined (ARM_MATH_DSP) */
00167 
00168   /* Store the real and imaginary results in 16.48 format  */
00169   *realResult = real_sum;
00170   *imagResult = imag_sum;
00171 }
00172 
00173 /**
00174  * @} end of cmplx_dot_prod group
00175  */
00176