arm_cmplx_dot_prod_q15.c

00001 /* ----------------------------------------------------------------------
00002  * Project:      CMSIS DSP Library
00003  * Title:        arm_cmplx_dot_prod_q15.c
00004  * Description:  Processing function for the Q15 Complex Dot product
00005  *
00006  * $Date:        27. January 2017
00007  * $Revision:    V.1.5.1
00008  *
00009  * Target Processor: Cortex-M cores
00010  * -------------------------------------------------------------------- */
00011 /*
00012  * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
00013  *
00014  * SPDX-License-Identifier: Apache-2.0
00015  *
00016  * Licensed under the Apache License, Version 2.0 (the License); you may
00017  * not use this file except in compliance with the License.
00018  * You may obtain a copy of the License at
00019  *
00020  * www.apache.org/licenses/LICENSE-2.0
00021  *
00022  * Unless required by applicable law or agreed to in writing, software
00023  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00024  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00025  * See the License for the specific language governing permissions and
00026  * limitations under the License.
00027  */
00028 
00029 #include "arm_math.h"
00030 
00031 /**
00032  * @ingroup groupCmplxMath
00033  */
00034 
00035 /**
00036  * @addtogroup cmplx_dot_prod
00037  * @{
00038  */
00039 
00040 /**
00041  * @brief  Q15 complex dot product
00042  * @param  *pSrcA points to the first input vector
00043  * @param  *pSrcB points to the second input vector
00044  * @param  numSamples number of complex samples in each vector
00045  * @param  *realResult real part of the result returned here
00046  * @param  *imagResult imaginary part of the result returned here
00047  * @return none.
00048  *
00049  * <b>Scaling and Overflow Behavior:</b>
00050  * \par
00051  * The function is implemented using an internal 64-bit accumulator.
00052  * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
00053  * These are accumulated in a 64-bit accumulator with 34.30 precision.
00054  * As a final step, the accumulators are converted to 8.24 format.
00055  * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.
00056  */
00057 
00058 void arm_cmplx_dot_prod_q15(
00059   q15_t * pSrcA,
00060   q15_t * pSrcB,
00061   uint32_t numSamples,
00062   q31_t * realResult,
00063   q31_t * imagResult)
00064 {
00065   q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
00066   q15_t a0,b0,c0,d0;
00067 
00068 #if defined (ARM_MATH_DSP)
00069 
00070   /* Run the below code for Cortex-M4 and Cortex-M3 */
00071   uint32_t blkCnt;                               /* loop counter */
00072 
00073 
00074   /*loop Unrolling */
00075   blkCnt = numSamples >> 2U;
00076 
00077   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
00078    ** a second loop below computes the remaining 1 to 3 samples. */
00079   while (blkCnt > 0U)
00080   {
00081       a0 = *pSrcA++;
00082       b0 = *pSrcA++;
00083       c0 = *pSrcB++;
00084       d0 = *pSrcB++;
00085 
00086       real_sum += (q31_t)a0 * c0;
00087       imag_sum += (q31_t)a0 * d0;
00088       real_sum -= (q31_t)b0 * d0;
00089       imag_sum += (q31_t)b0 * c0;
00090 
00091       a0 = *pSrcA++;
00092       b0 = *pSrcA++;
00093       c0 = *pSrcB++;
00094       d0 = *pSrcB++;
00095 
00096       real_sum += (q31_t)a0 * c0;
00097       imag_sum += (q31_t)a0 * d0;
00098       real_sum -= (q31_t)b0 * d0;
00099       imag_sum += (q31_t)b0 * c0;
00100 
00101       a0 = *pSrcA++;
00102       b0 = *pSrcA++;
00103       c0 = *pSrcB++;
00104       d0 = *pSrcB++;
00105 
00106       real_sum += (q31_t)a0 * c0;
00107       imag_sum += (q31_t)a0 * d0;
00108       real_sum -= (q31_t)b0 * d0;
00109       imag_sum += (q31_t)b0 * c0;
00110 
00111       a0 = *pSrcA++;
00112       b0 = *pSrcA++;
00113       c0 = *pSrcB++;
00114       d0 = *pSrcB++;
00115 
00116       real_sum += (q31_t)a0 * c0;
00117       imag_sum += (q31_t)a0 * d0;
00118       real_sum -= (q31_t)b0 * d0;
00119       imag_sum += (q31_t)b0 * c0;
00120 
00121       /* Decrement the loop counter */
00122       blkCnt--;
00123   }
00124 
00125   /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
00126    ** No loop unrolling is used. */
00127   blkCnt = numSamples % 0x4U;
00128 
00129   while (blkCnt > 0U)
00130   {
00131       a0 = *pSrcA++;
00132       b0 = *pSrcA++;
00133       c0 = *pSrcB++;
00134       d0 = *pSrcB++;
00135 
00136       real_sum += (q31_t)a0 * c0;
00137       imag_sum += (q31_t)a0 * d0;
00138       real_sum -= (q31_t)b0 * d0;
00139       imag_sum += (q31_t)b0 * c0;
00140 
00141       /* Decrement the loop counter */
00142       blkCnt--;
00143   }
00144 
00145 #else
00146 
00147   /* Run the below code for Cortex-M0 */
00148 
00149   while (numSamples > 0U)
00150   {
00151       a0 = *pSrcA++;
00152       b0 = *pSrcA++;
00153       c0 = *pSrcB++;
00154       d0 = *pSrcB++;
00155 
00156       real_sum += a0 * c0;
00157       imag_sum += a0 * d0;
00158       real_sum -= b0 * d0;
00159       imag_sum += b0 * c0;
00160 
00161 
00162       /* Decrement the loop counter */
00163       numSamples--;
00164   }
00165 
00166 #endif /* #if defined (ARM_MATH_DSP) */
00167 
00168   /* Store the real and imaginary results in 8.24 format  */
00169   /* Convert real data in 34.30 to 8.24 by 6 right shifts */
00170   *realResult = (q31_t) (real_sum >> 6);
00171   /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
00172   *imagResult = (q31_t) (imag_sum >> 6);
00173 }
00174 
00175 /**
00176  * @} end of cmplx_dot_prod group
00177  */
00178