arm_add_q15.c

00001 /* ----------------------------------------------------------------------
00002  * Project:      CMSIS DSP Library
00003  * Title:        arm_add_q15.c
00004  * Description:  Q15 vector addition
00005  *
00006  * $Date:        27. January 2017
00007  * $Revision:    V.1.5.1
00008  *
00009  * Target Processor: Cortex-M cores
00010  * -------------------------------------------------------------------- */
00011 /*
00012  * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
00013  *
00014  * SPDX-License-Identifier: Apache-2.0
00015  *
00016  * Licensed under the Apache License, Version 2.0 (the License); you may
00017  * not use this file except in compliance with the License.
00018  * You may obtain a copy of the License at
00019  *
00020  * www.apache.org/licenses/LICENSE-2.0
00021  *
00022  * Unless required by applicable law or agreed to in writing, software
00023  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00024  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00025  * See the License for the specific language governing permissions and
00026  * limitations under the License.
00027  */
00028 
00029 #include "arm_math.h"
00030 
00031 /**
00032  * @ingroup groupMath
00033  */
00034 
00035 /**
00036  * @addtogroup BasicAdd
00037  * @{
00038  */
00039 
00040 /**
00041  * @brief Q15 vector addition.
00042  * @param[in]       *pSrcA points to the first input vector
00043  * @param[in]       *pSrcB points to the second input vector
00044  * @param[out]      *pDst points to the output vector
00045  * @param[in]       blockSize number of samples in each vector
00046  * @return none.
00047  *
00048  * <b>Scaling and Overflow Behavior:</b>
00049  * \par
00050  * The function uses saturating arithmetic.
00051  * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
00052  */
00053 
00054 void arm_add_q15(
00055   q15_t * pSrcA,
00056   q15_t * pSrcB,
00057   q15_t * pDst,
00058   uint32_t blockSize)
00059 {
00060   uint32_t blkCnt;                               /* loop counter */
00061 
00062 #if defined (ARM_MATH_DSP)
00063 
00064 /* Run the below code for Cortex-M4 and Cortex-M3 */
00065   q31_t inA1, inA2, inB1, inB2;
00066 
00067   /*loop Unrolling */
00068   blkCnt = blockSize >> 2U;
00069 
00070   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.
00071    ** a second loop below computes the remaining 1 to 3 samples. */
00072   while (blkCnt > 0U)
00073   {
00074     /* C = A + B */
00075     /* Add and then store the results in the destination buffer. */
00076     inA1 = *__SIMD32(pSrcA)++;
00077     inA2 = *__SIMD32(pSrcA)++;
00078     inB1 = *__SIMD32(pSrcB)++;
00079     inB2 = *__SIMD32(pSrcB)++;
00080 
00081     *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
00082     *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
00083 
00084     /* Decrement the loop counter */
00085     blkCnt--;
00086   }
00087 
00088   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
00089    ** No loop unrolling is used. */
00090   blkCnt = blockSize % 0x4U;
00091 
00092   while (blkCnt > 0U)
00093   {
00094     /* C = A + B */
00095     /* Add and then store the results in the destination buffer. */
00096     *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
00097 
00098     /* Decrement the loop counter */
00099     blkCnt--;
00100   }
00101 
00102 #else
00103 
00104   /* Run the below code for Cortex-M0 */
00105 
00106 
00107 
00108   /* Initialize blkCnt with number of samples */
00109   blkCnt = blockSize;
00110 
00111   while (blkCnt > 0U)
00112   {
00113     /* C = A + B */
00114     /* Add and then store the results in the destination buffer. */
00115     *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
00116 
00117     /* Decrement the loop counter */
00118     blkCnt--;
00119   }
00120 
00121 #endif /* #if defined (ARM_MATH_DSP) */
00122 
00123 
00124 }
00125 
00126 /**
00127  * @} end of BasicAdd group
00128  */
00129