Revision 0:284f8f17c02e, committed 2010-11-15

Comitter:

rkris

Date:

Mon Nov 15 05:38:28 2010 +0000

Commit message:

Changed in this revision

diff -r 000000000000 -r 284f8f17c02e main.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Mon Nov 15 05:38:28 2010 +0000
@@ -0,0 +1,578 @@
+#include "mbed.h"
+#include "nRF2401LP.h"
+
+SPI spi_2(p5, p6, p7); // mosi, miso, sclk
+SPI spi_1(p11, p12, p13); // mosi, miso, sclk
+
+DigitalOut csn_2(p8);
+DigitalOut ce_2(p9);
+
+DigitalOut csn_1(p14);
+DigitalOut ce_1(p15);
+
+LocalFileSystem local("local");  
+FILE *fp;
+
+char * regNames[] = 
+{
+  "CONFIG",
+  "EN_AA",
+  "EN_RXADDR",
+  "SETUP_AW",
+  "SETUP_RETR",
+  "RF_CH",
+  "RF_SETUP",
+  "STATUS",
+  "OBSERVE_TX",
+  "RPD",
+  "RX_ADDR_P0",
+  "RX_ADDR_P1",
+  "RX_ADDR_P2",
+  "RX_ADDR_P3",
+  "RX_ADDR_P4",
+  "RX_ADDR_P5",
+  "TX_ADDR",
+  "RX_PW_P0",
+  "RX_PW_P1",
+  "RX_PW_P2",
+  "RX_PW_P3",
+  "RX_PW_P4",
+  "RX_PW_P5",
+  "FIFO_STATUS"
+  };
+ 
+
+void readReg(SPI *spi_p, DigitalOut *csn_p, int regIdx, int byteCnt, unsigned int *reg_p);
+
+void writeReg(SPI *spi_p, DigitalOut *csn_p, int regIdx, int byteCnt, unsigned int *reg_p)
+{
+    int idx;
+    // Executable in power down or standby modes only.
+    
+    (*csn_p) = 0;
+    wait_ms(1);
+    (*csn_p) = 1;
+    wait_ms(1);
+    (*csn_p) = 0;
+    wait_ms(1);
+    
+    spi_p->write(NRF24L01P_SPI_CMD_WR_REG | regIdx);
+    for (idx=0; idx<byteCnt; idx++)
+    {
+         wait_ms(1);
+         fprintf(fp, "\n <%s> : Writing 0x%x to register <%d> \n", 
+                 __FUNCTION__, reg_p[idx], regIdx);
+         spi_p->write(reg_p[idx]);
+    }
+    
+    wait_ms(1);
+    
+    // Deselect the device
+    (*csn_p) = 1;      
+}    
+
+int selectChannel(SPI *spi_p, DigitalOut *csn_p, int chnIdx)
+{
+   unsigned int byte = chnIdx & 0x7f;
+   
+   fprintf(fp, "\n <%s> : Chan<%d>/<%d MHZ> \n", __FUNCTION__, chnIdx, 2400 + chnIdx);
+   
+   // The RF channel frequency is set by the RF_CH register according to the following 
+   // formula:   F0= 2400 + RF_CH    [In MHz]
+   // The programming resolution of the RF channel frequency setting is 1MHz.
+   
+   writeReg(spi_p, csn_p, NRF24L01P_REG_RF_CH, 1, &byte); 
+   
+   return 0;
+}
+
+
+int selectDataRate(SPI *spi_p, DigitalOut *csn_p, int dataRateKbps)
+{
+   unsigned int regVal;
+   
+   // The air data rate is set by the RF_DR bit in the RF_SETUP register. A transmitter 
+   // and a receiver must be programmed with the same air data rate to communicate with 
+   // each other.
+   
+   readReg(spi_p, csn_p, NRF24L01P_REG_RF_SETUP, 1, &regVal);
+   
+   switch (dataRateKbps)
+   {           
+      case NRF24L01P_DR_1_MBPS:     
+           fprintf(fp, "\n 1000 Kbps data rate selected ... \n");
+           // Set RF_DR_LOW to 0 and RF_DR_HIGH to 0
+           regVal &= ~(NRF24L01P_RF_SETUP_REG_DR_LOW_BIT | NRF24L01P_RF_SETUP_REG_DR_HIGH_BIT);
+           break;
+           
+      case NRF24L01P_DR_2_MBPS:        
+           fprintf(fp, "\n 2000 Kbps data rate selected ... \n");
+           // Set RF_DR_LOW to 0 and RF_DR_HIGH to 1
+           regVal |=  NRF24L01P_RF_SETUP_REG_DR_HIGH_BIT; 
+           regVal &= ~NRF24L01P_RF_SETUP_REG_DR_LOW_BIT;
+           break;
+       
+      case NRF24L01P_DR_250_KBPS:         
+      default:
+           fprintf(fp, "\n 250 Kbps data rate selected ... \n");
+           // Set RF_DR_LOW to 1 and RF_DR_HIGH to 0
+           regVal |=  NRF24L01P_RF_SETUP_REG_DR_LOW_BIT;   
+           regVal &= ~NRF24L01P_RF_SETUP_REG_DR_HIGH_BIT;        
+           break;         
+   }
+
+   writeReg(spi_p, csn_p, NRF24L01P_REG_RF_SETUP, 1, &regVal); 
+   
+   return 1;
+}
+
+
+
+int selectTxPower(SPI *spi_p, DigitalOut *csn_p, int txPower)
+{
+   unsigned int regVal;
+   
+   readReg(spi_p, csn_p, NRF24L01P_REG_RF_SETUP, 1, &regVal);
+
+   regVal &= ~(REG_BIT_1 | REG_BIT_2);
+   switch (txPower)
+   {
+      case NRF24L01P_TX_PWR_MINUS_18_DB:           
+           break;
+
+      case NRF24L01P_TX_PWR_MINUS_12_DB:
+           regVal |= REG_BIT_1;
+           break;
+
+      case NRF24L01P_TX_PWR_MINUS_6_DB:
+           regVal |= REG_BIT_2;
+           break;
+
+      case NRF24L01P_TX_PWR_ZERO_DB:     
+           regVal |= REG_BIT_1;
+           regVal |= REG_BIT_2;
+      default:
+           break;         
+   }
+
+   writeReg(spi_p, csn_p, NRF24L01P_REG_RF_SETUP, 1, &regVal); 
+   
+   return 1;
+}
+
+int setRadioOpnMode(SPI *spi_p, DigitalOut *csn_p, int radioMode)
+{
+   unsigned int regVal;
+
+   readReg(spi_p, csn_p, NRF24L01P_REG_CONFIG, 1, &regVal);
+  
+   switch (radioMode)
+   {
+      case NRF24L01P_MODE_POWER_DOWN:
+           regVal &= ~REG_BIT_1;
+           break;
+
+      case NRF24L01P_MODE_STANDBY:  // POWER UP
+           regVal |= REG_BIT_1;
+           break;
+      
+      case NRF24L01P_MODE_TX:
+           regVal &= ~REG_BIT_0;
+           break;
+
+      case NRF24L01P_MODE_RX:
+           regVal |= REG_BIT_0;
+           break;
+
+      default:
+           return 0;
+   }
+
+   writeReg(spi_p, csn_p, NRF24L01P_REG_CONFIG, 1, &regVal);
+
+   return 1;
+}
+
+int setUpPktRx(SPI *spi_p, DigitalOut *csn_p, DigitalOut *ce_p)
+{
+    unsigned int regVal;
+    unsigned int nodeAddr[5] = {0x15, 0x26, 0x37, 0x48, 0x59}; 
+  
+    // Select RX by setting the PRIM_RX bit in the CONFIG register to high. 
+   
+    readReg(spi_p, csn_p, NRF24L01P_REG_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_FIFO_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : FIFO Status <0x%x> \n", __FUNCTION__, regVal); 
+    
+    // writeReg(spi_p, csn_p, NRF24L01P_REG_TX_ADDR, 5, nodeAddr);
+ 
+    (*ce_p) = 0;
+    
+    regVal = 32;
+    writeReg(spi_p, csn_p, NRF24L01P_REG_RX_PW_P0, 1, &regVal);
+    writeReg(spi_p, csn_p, NRF24L01P_REG_RX_PW_P1, 1, &regVal);
+    writeReg(spi_p, csn_p, NRF24L01P_REG_RX_PW_P2, 1, &regVal);
+    writeReg(spi_p, csn_p, NRF24L01P_REG_RX_PW_P3, 1, &regVal);
+    writeReg(spi_p, csn_p, NRF24L01P_REG_RX_PW_P4, 1, &regVal);
+    
+    wait_ms(100); 
+    
+    setRadioOpnMode(spi_p, csn_p, NRF24L01P_MODE_STANDBY);
+  
+    wait_ms(100);    
+  
+    // Set config bit PRIM_RX high
+    setRadioOpnMode(spi_p, csn_p, NRF24L01P_MODE_RX);
+
+    wait_ms(100);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_CONFIG, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Config <0x%x> \n", __FUNCTION__, regVal);  
+    
+    regVal = 0x3f;
+    writeReg(spi_p, csn_p, NRF24L01P_REG_EN_RX_ADDR, 1, &regVal);
+    // Start Active RX mode by setting CE high. After 130ìs nRF24L01+ monitors the 
+   // air for incoming communication.   
+    wait_ms(100);
+    (*ce_p) = 1;
+    
+    wait_ms(100);
+    
+    readReg(spi_p, csn_p, NRF24L01P_REG_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_FIFO_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : FIFO Status <0x%x> \n", __FUNCTION__, regVal); 
+     
+    return 0; 
+}
+
+int txPacket(SPI *spi_p, DigitalOut *csn_p, DigitalOut *ce_p, unsigned int *txBuff, unsigned int pktLen)
+{
+   unsigned int regVal;
+
+    /*
+     * The TX mode is an active mode for transmitting packets. To enter this mode, 
+     * the nRF24L01+ must have the PWR_UP bit set high, PRIM_RX bit set low, a 
+     * payload in the TX FIFO and a high pulse on the CE for more than 10ìs.
+     */
+
+    /*
+     * You can write to the TX FIFO using these three commands; 
+     * W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode.
+     */
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_FIFO_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+
+    (*ce_p) = 0;
+   
+    setRadioOpnMode(spi_p, csn_p, NRF24L01P_MODE_STANDBY);
+ 
+    wait_ms(10);
+
+    // Set config bit PRIM_RX low
+    setRadioOpnMode(spi_p, csn_p, NRF24L01P_MODE_TX);
+
+    wait_ms(10);
+    
+    selectTxPower(spi_p, csn_p, NRF24L01P_TX_PWR_ZERO_DB);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_CONFIG, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Config <0x%x> \n", __FUNCTION__, regVal);
+    
+    // Now clock the payload into the nRF24L01+
+    
+    writeReg(spi_p, csn_p, NRF24L01P_SPI_CMD_WR_TX_PYLD, pktLen, txBuff); 
+    
+    // A high pulse on CE starts the transmission. The minimum pulse width on CE is 10ìs.
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_FIFO_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : FIFO Status <0x%x> \n", __FUNCTION__, regVal);
+
+    (*ce_p) = 1;
+ 
+    wait_ms(1);
+
+    (*ce_p) = 0;
+
+    wait_ms(1);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : Status <0x%x> \n", __FUNCTION__, regVal);
+
+    readReg(spi_p, csn_p, NRF24L01P_REG_FIFO_STATUS, 1, &regVal); 
+    fprintf(fp, "\n <%s> : FIFO Status <0x%x> \n", __FUNCTION__, regVal);
+
+    return 0;
+}
+
+
+int getSelectedChannel(SPI *spi_p, DigitalOut *csn_p)
+{
+    unsigned int byte;
+    readReg(spi_p, csn_p, NRF24L01P_REG_RF_CH, 1, &byte);
+    return byte;
+}
+
+void readReg( SPI *spi_p, DigitalOut *csn_p, int regIdx, int byteCnt, unsigned int *reg_p)
+{
+    int idx;
+    
+    (*csn_p) = 0;
+    wait_ms(1);
+    (*csn_p) = 1;
+    wait_ms(1);
+    (*csn_p) = 0;
+    wait_ms(1);
+
+
+    spi_p->write(NRF24L01P_SPI_CMD_RD_REG | regIdx);
+ 
+    for (idx=0; idx<byteCnt; idx++)
+    {
+        // Send a dummy byte to receive the contents of the register
+        reg_p[idx] = spi_p->write(0x00);
+    }
+    
+    wait_ms(1);
+    
+    // Deselect the device
+    (*csn_p) = 1;   
+}
+
+int main() 
+{
+  
+    unsigned int byte, idx;
+    int regIdx;
+    unsigned int spi_1_rxAddrP0[RF24L01P_RX_ADDR_REG_LEN];
+    unsigned int spi_2_rxAddrP0[RF24L01P_RX_ADDR_REG_LEN];
+    unsigned int spi_1_txAddr[RF24L01P_RX_ADDR_REG_LEN];
+    unsigned int spi_2_txAddr[RF24L01P_RX_ADDR_REG_LEN];
+    unsigned int txBuff[32] = {0x12, 0x34, 0x56, 0x78};
+    unsigned int rxBuff[32];
+    unsigned int addr[5];
+
+    for (idx=0; idx<10; idx++)
+    {
+       ce_1 = 0x1;
+       ce_2 = 0x1;
+       csn_1 = 0x1;
+       csn_2 = 0x1;
+       wait_ms(100);
+       ce_1 = 0x0;
+       ce_2 = 0x0;
+       csn_1 = 0x0;
+       csn_2 = 0x0;
+       wait_ms(100);
+    }
+
+    csn_1 = 0x1;
+    csn_2 = 0x1;
+    ce_1 = 0x0;
+    ce_2 = 0x0;
+
+    fp = fopen("/local/spi.dat", "w");  
+    if (fp == NULL)
+        return 1;
+        
+    ce_1 = 0x0;
+    ce_2 = 0x0;        
+        
+    // Setup the spi for 8 bit data, high steady state clock,
+    // second edge capture, with a 1kHz clock rate
+    spi_1.format(8, 0);   // CPOL 0 and CPHA 0    
+    spi_1.frequency(1000000);
+   
+    spi_2.format(8, 0);   // CPOL 0 and CPHA 0    
+    spi_2.frequency(1000000);   
+    
+    readReg(&spi_1, &ce_1, NRF24L01P_REG_RF_SETUP, 1, &byte);
+    fprintf(fp, "\n SPI1 :  RF Seup : Value<0x%x> \n", (unsigned int)byte);
+    
+    selectChannel(&spi_1, &csn_1, 15);
+    selectChannel(&spi_2, &csn_2, 15);
+
+    byte = 0x0;
+    writeReg(&spi_1, &csn_1, NRF24L01P_REG_EN_AA, 1, &byte); 
+    writeReg(&spi_2, &csn_2, NRF24L01P_REG_EN_AA, 1, &byte); 
+   
+    readReg(&spi_2, &csn_2, NRF24L01P_REG_RX_ADDR_P0, 5, &addr[0]);
+    for (idx=0; idx<5; idx++)
+         fprintf(fp, "\n SP1_2 : RX_ADDR_P0 <%d> : <0x%x> ", idx, addr[idx]); 
+         
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_TX_ADDR, 5, &addr[0]);
+    for (idx=0; idx<5; idx++)
+         fprintf(fp, "\n SP1_1 : TX_ADDR <%d> : <0x%x> ", idx, addr[idx]); 
+            
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+         readReg(&spi_1, &csn_1, regIdx, 1, &byte);
+         fprintf(fp, "\n <1> SPI_1 : Reg<%d>/<%s> : Value<0x%x> \n", regIdx, regNames[regIdx], (unsigned int)byte);
+    }
+        
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_DYNPD, 1, &byte);
+    fprintf(fp, "\n <1> SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_DYNPD, (unsigned int)byte);
+    
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_FEATURE, 1, &byte);
+    fprintf(fp, "\n <1> SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_FEATURE, (unsigned int)byte);    
+
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+         readReg(&spi_2, &csn_2, regIdx, 1, &byte);
+         fprintf(fp, "\n <1> SPI_2 : Reg<%d>/<%s> : Value<0x%x> \n", regIdx, regNames[regIdx], (unsigned int)byte);
+    }        
+   
+    readReg(&spi_2, &csn_2, NRF24L01P_REG_DYNPD, 1, &byte);
+    fprintf(fp, "\n <1> SPI_2 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_DYNPD, (unsigned int)byte);
+    
+    readReg(&spi_2, &csn_2, NRF24L01P_REG_FEATURE, 1, &byte);
+    fprintf(fp, "\n <1> SPI_2 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_FEATURE, (unsigned int)byte);    
+
+   
+    
+    selectDataRate(&spi_1, &csn_1, NRF24L01P_DR_250_KBPS); 
+    selectDataRate(&spi_2, &csn_2, NRF24L01P_DR_250_KBPS);
+    
+    setUpPktRx(&spi_2, &csn_2, &ce_2);
+    
+    txPacket(&spi_1, &csn_1, &ce_1, txBuff, 32);
+    
+    wait_ms(1000);
+    
+    // ce_2 = 0;
+    
+#if 0    
+    readReg(&spi_2, &csn_2, NRF24L01P_RE_RX_ADDR_P0, 5, &spi_2_rxAddrP0[0]);
+    for (idx=0; idx<RF24L01P_RX_ADDR_REG_LEN; idx++)
+    {
+         fprintf(fp, "\n SPI_2 : Reg<%d>/Idx<%d> : Value<0x%x> \n", 
+                 NRF24L01P_REG_RX_ADDR_P0, idx, (unsigned int)spi_1_rxAddrP0[idx]);
+    }
+    
+    readReg(&spi_2, &csn_2, NRF24L01P_REG_RX_ADDR_P0, 5, &spi_2_rxAddrP0[0]);
+    for (idx=0; idx<RF24L01P_RX_ADDR_REG_LEN; idx++)
+    {
+         fprintf(fp, "\n SPI_2 : Reg<%d>/Idx<%d> : Value<0x%x> \n", 
+                 NRF24L01P_REG_RX_ADDR_P0, idx, (unsigned int)spi_2_rxAddrP0[idx]);
+    }
+    
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_TX_ADDR, 5, &spi_1_txAddr[0]);
+    for (idx=0; idx<RF24L01P_TX_ADDR_REG_LEN; idx++)
+    {
+         fprintf(fp, "\n SPI_1 : Reg<%d>/Idx<%d> : Value<0x%x> \n", 
+                 NRF24L01P_REG_TX_ADDR, idx, (unsigned int)spi_2_rxAddrP0[idx]);
+    }
+    
+    readReg(&spi_2, &csn_2, NRF24L01P_REG_TX_ADDR, 5, &spi_2_txAddr[0]);
+    for (idx=0; idx<RF24L01P_TX_ADDR_REG_LEN; idx++)
+    {
+         fprintf(fp, "\n SPI_2 : Reg<%d>/Idx<%d> : Value<0x%x> \n", 
+                 NRF24L01P_REG_TX_ADDR, idx, (unsigned int)spi_2_rxAddrP0[idx]);
+    }    
+#endif
+
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+         readReg(&spi_1, &csn_1, regIdx, 1, &byte);
+         fprintf(fp, "\n <1> SPI_1 : Reg<%d>/<%s> : Value<0x%x> \n", regIdx, regNames[regIdx], (unsigned int)byte);
+    }
+    
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+         readReg(&spi_2, &csn_2, regIdx, 1, &byte);
+         fprintf(fp, "\n <1> SPI_2 : Reg<%d>/<%s> : Value<0x%x> \n", regIdx, regNames[regIdx], (unsigned int)byte);
+    }        
+  
+
+#if 0  
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_RF_CH, 1, &byte);
+    fprintf(fp, "\n SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_RF_CH, (unsigned int)byte); 
+    selectChannel(&spi_1, &csn_1, 5);
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_RF_CH, 1, &byte);
+    fprintf(fp, "\n SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_RF_CH, (unsigned int)byte); 
+    
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_RF_SETUP, 1, &byte);
+    fprintf(fp, "\n SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_RF_SETUP, (unsigned int)byte); 
+    selectDataRate(&spi_1, &csn_1, NRF24L01P_DR_250_KBPS);
+    readReg(&spi_1, &csn_1, NRF24L01P_REG_RF_SETUP, 1, &byte);
+    fprintf(fp, "\n SPI_1 : Reg<%d> : Value<0x%x> \n", NRF24L01P_REG_RF_SETUP, (unsigned int)byte); 
+       
+    fprintf(fp, "\n SPI_1 : Selected Channel <%d> \n", getSelectedChannel(&spi_1, &csn_1)); 
+    
+    fprintf(fp, "\n SPI_2 : Selected Channel <%d> \n", getSelectedChannel(&spi_2, &csn_2)); 
+ #endif
+    
+ #if 0
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+    // Every new command must be started by a high to low transition on CSN.
+
+    // Select the device by seting chip select low
+
+    csn_1 = 0;
+    wait_ms(1);
+    csn_1 = 1;
+    wait_ms(1);
+    csn_1 = 0;
+    wait_ms(1);
+
+    spi_1.write(NRF24L01P_SPI_CMD_RD_REG | regIdx);
+
+    // Send a dummy byte to receive the contents of the register
+    byte = spi_1.write(0x00);
+   
+    wait_ms(1);
+    
+    // Deselect the device
+    csn_1 = 1;
+    
+
+    fprintf(fp, "\n SPI_1 : Reg<%d> : Value<0x%x> \n", regIdx, (unsigned int)byte);
+    }
+    
+    spi_2.format(8, 0);   // CPOL 0 and CPHA 0
+    
+    spi_2.frequency(1000000);
+    
+    for (regIdx = NRF24L01P_REG_CONFIG; regIdx <= NRF24L01P_REG_FIFO_STATUS; regIdx++)
+    {
+    // Every new command must be started by a high to low transition on CSN.
+
+    // Select the device by seting chip select low
+
+    csn_2 = 0;
+    wait_ms(1);
+    csn_2 = 1;
+    wait_ms(1);
+    csn_2 = 0;
+    wait_ms(1);
+
+    spi_2.write(NRF24L01P_SPI_CMD_RD_REG | regIdx);
+
+    // Send a dummy byte to receive the contents of the register
+    byte = spi_2.write(0x00);
+   
+    wait_ms(1);
+    
+    // Deselect the device
+    csn_2 = 1;
+    
+
+    fprintf(fp, "\n SPI_2 : Reg<%d> : Value<0x%x> \n", regIdx, (unsigned int)byte);
+    }
+ #endif
+     
+    fclose(fp);
+}
+

diff -r 000000000000 -r 284f8f17c02e mbed.bld
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Mon Nov 15 05:38:28 2010 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/e2ac27c8e93e

diff -r 000000000000 -r 284f8f17c02e nRF2401LP.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nRF2401LP.h	Mon Nov 15 05:38:28 2010 +0000
@@ -0,0 +1,99 @@
+#ifndef __NRF24L01P_H__
+#define __NRF24L01P_H__
+
+/*
+ * You can configure the nRF24L01+ in power down, standby, RX or TX mode.
+ */
+#define NRF24L01P_MODE_UNKNOWN      0x0
+#define NRF24L01P_MODE_POR          0x1
+#define NRF24L01P_MODE_POWER_DOWN   0x2
+#define NRF24L01P_MODE_STANDBY      0x3
+#define NRF24L01P_MODE_RX           0x4
+#define NRF24L01P_MODE_TX           0x5
+
+#define REG_BIT_0    (1 << 0)
+#define REG_BIT_1    (1 << 1)
+#define REG_BIT_2    (1 << 2)
+#define REG_BIT_3    (1 << 3)
+#define REG_BIT_4    (1 << 4)
+#define REG_BIT_5    (1 << 5)
+#define REG_BIT_6    (1 << 6)
+#define REG_BIT_7    (1 << 7)
+
+#define  NRF24L01P_TX_PWR_MINUS_18_DB  0x0
+#define  NRF24L01P_TX_PWR_MINUS_12_DB  0x1
+#define  NRF24L01P_TX_PWR_MINUS_6_DB   0x2
+#define  NRF24L01P_TX_PWR_ZERO_DB      0x3
+
+/*
+ * The following FIFOs are present in nRF24L01+:
+ *  > TX three level, 32 byte FIFO
+ *  > RX three level, 32 byte FIFO
+ */
+#define NRF24L01P_TX_FIFO_COUNT   3
+#define NRF24L01P_RX_FIFO_COUNT   3
+
+#define NRF24L01P_TX_FIFO_SIZE  32
+#define NRF24L01P_RX_FIFO_SIZE  32
+
+#define NRF24L01P_SPI_MAX_DATA_RATE_MBPS   10
+
+
+#define NRF24L01P_DR_250_KBPS   250
+#define NRF24L01P_DR_1_MBPS     1000
+#define NRF24L01P_DR_2_MBPS     2000
+
+#define NRF24L01P_MIN_CHAN_FREQ     2400
+#define NRF24L01P_MAX_CHAN_FREQ     2520
+
+
+#define NRF24L01P_MIN_PYLD_LEN   0
+#define NRF24L01P_MAX_PYLD_LEN   32
+
+#define NRF24L01P_SPI_CMD_RD_REG            0x00
+#define NRF24L01P_SPI_CMD_WR_REG            0x20
+#define NRF24L01P_SPI_CMD_RD_RX_PYLD        0x61   
+#define NRF24L01P_SPI_CMD_WR_TX_PYLD        0xa0
+#define NRF24L01P_SPI_CMD_FLUSH_TX          0xe1
+#define NRF24L01P_SPI_CMD_FLUSH_RX          0xe2
+#define NRF24L01P_SPI_CMD_REUSE_TX_PL       0xe3
+#define NRF24L01P_SPI_CMD_R_RX_PL_WID       0x60
+#define NRF24L01P_SPI_CMD_W_ACK_PYLD        0xa8
+#define NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK  0xb0
+#define NRF24L01P_SPI_CMD_NOP               0xff
+
+
+#define NRF24L01P_REG_CONFIG              0x00
+#define NRF24L01P_REG_EN_AA               0x01
+#define NRF24L01P_REG_EN_RX_ADDR          0x02
+#define NRF24L01P_REG_SETUP_AW            0x03
+#define NRF24L01P_REG_SETUP_RETR          0x04
+#define NRF24L01P_REG_RF_CH               0x05
+#define NRF24L01P_REG_RF_SETUP            0x06
+#define NRF24L01P_REG_STATUS              0x07
+#define NRF24L01P_REG_OBSERVE_TX          0x08
+#define NRF24L01P_REG_RPD                 0x09
+#define NRF24L01P_REG_RX_ADDR_P0          0x0a
+#define NRF24L01P_REG_RX_ADDR_P1          0x0b
+#define NRF24L01P_REG_RX_ADDR_P2          0x0c
+#define NRF24L01P_REG_RX_ADDR_P3          0x0d
+#define NRF24L01P_REG_RX_ADDR_P4          0x0e
+#define NRF24L01P_REG_RX_ADDR_P5          0x0f
+#define NRF24L01P_REG_TX_ADDR             0x10
+#define NRF24L01P_REG_RX_PW_P0            0x11
+#define NRF24L01P_REG_RX_PW_P1            0x12
+#define NRF24L01P_REG_RX_PW_P2            0x13
+#define NRF24L01P_REG_RX_PW_P3            0x14
+#define NRF24L01P_REG_RX_PW_P4            0x15
+#define NRF24L01P_REG_RX_PW_P5            0x16
+#define NRF24L01P_REG_FIFO_STATUS         0x17
+#define NRF24L01P_REG_DYNPD               0x1c
+#define NRF24L01P_REG_FEATURE             0x1d
+
+#define RF24L01P_RX_ADDR_REG_LEN     5
+#define RF24L01P_TX_ADDR_REG_LEN     5
+
+#define NRF24L01P_RF_SETUP_REG_DR_HIGH_BIT  (1 << 3)
+#define NRF24L01P_RF_SETUP_REG_DR_LOW_BIT   (1 << 5)
+
+#endif