rik te winkel / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_dmactrl.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
50:a417edff4437
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32gg_dmactrl.h
bogdanm 0:9b334a45a8ff 3 * @brief EFM32GG_DMACTRL register and bit field definitions
bogdanm 0:9b334a45a8ff 4 * @version 3.20.6
bogdanm 0:9b334a45a8ff 5 ******************************************************************************
bogdanm 0:9b334a45a8ff 6 * @section License
bogdanm 0:9b334a45a8ff 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 11 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 12 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 15 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 16 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 17 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 18 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 19 *
bogdanm 0:9b334a45a8ff 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 22 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 23 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 24 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 25 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 26 *
bogdanm 0:9b334a45a8ff 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 28 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 29 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 *****************************************************************************/
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 34 * @defgroup EFM32GG_DMACTRL_BitFields
bogdanm 0:9b334a45a8ff 35 * @{
bogdanm 0:9b334a45a8ff 36 *****************************************************************************/
bogdanm 0:9b334a45a8ff 37 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
bogdanm 0:9b334a45a8ff 38 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
bogdanm 0:9b334a45a8ff 39 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
bogdanm 0:9b334a45a8ff 40 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
bogdanm 0:9b334a45a8ff 41 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
bogdanm 0:9b334a45a8ff 42 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
bogdanm 0:9b334a45a8ff 43 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
bogdanm 0:9b334a45a8ff 44 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
bogdanm 0:9b334a45a8ff 45 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
bogdanm 0:9b334a45a8ff 46 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
bogdanm 0:9b334a45a8ff 47 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
bogdanm 0:9b334a45a8ff 48 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
bogdanm 0:9b334a45a8ff 49 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
bogdanm 0:9b334a45a8ff 50 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
bogdanm 0:9b334a45a8ff 51 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
bogdanm 0:9b334a45a8ff 52 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
bogdanm 0:9b334a45a8ff 53 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
bogdanm 0:9b334a45a8ff 54 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
bogdanm 0:9b334a45a8ff 55 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
bogdanm 0:9b334a45a8ff 56 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
bogdanm 0:9b334a45a8ff 57 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
bogdanm 0:9b334a45a8ff 58 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
bogdanm 0:9b334a45a8ff 59 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
bogdanm 0:9b334a45a8ff 60 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
bogdanm 0:9b334a45a8ff 61 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
bogdanm 0:9b334a45a8ff 62 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
bogdanm 0:9b334a45a8ff 63 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
bogdanm 0:9b334a45a8ff 64 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
bogdanm 0:9b334a45a8ff 65 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
bogdanm 0:9b334a45a8ff 66 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
bogdanm 0:9b334a45a8ff 67 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
bogdanm 0:9b334a45a8ff 68 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
bogdanm 0:9b334a45a8ff 69 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
bogdanm 0:9b334a45a8ff 70 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
bogdanm 0:9b334a45a8ff 71 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
bogdanm 0:9b334a45a8ff 72 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
bogdanm 0:9b334a45a8ff 73 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
bogdanm 0:9b334a45a8ff 74 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
bogdanm 0:9b334a45a8ff 75 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
bogdanm 0:9b334a45a8ff 76 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
bogdanm 0:9b334a45a8ff 77 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
bogdanm 0:9b334a45a8ff 78 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
bogdanm 0:9b334a45a8ff 79 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
bogdanm 0:9b334a45a8ff 80 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
bogdanm 0:9b334a45a8ff 81 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
bogdanm 0:9b334a45a8ff 82 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
bogdanm 0:9b334a45a8ff 83 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
bogdanm 0:9b334a45a8ff 84 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
bogdanm 0:9b334a45a8ff 85 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
bogdanm 0:9b334a45a8ff 86 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
bogdanm 0:9b334a45a8ff 87 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
bogdanm 0:9b334a45a8ff 88 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
bogdanm 0:9b334a45a8ff 89 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
bogdanm 0:9b334a45a8ff 90 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
bogdanm 0:9b334a45a8ff 91 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
bogdanm 0:9b334a45a8ff 92 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
bogdanm 0:9b334a45a8ff 93 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
bogdanm 0:9b334a45a8ff 94 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
bogdanm 0:9b334a45a8ff 95 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
bogdanm 0:9b334a45a8ff 96 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
bogdanm 0:9b334a45a8ff 97 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
bogdanm 0:9b334a45a8ff 98 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
bogdanm 0:9b334a45a8ff 99 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
bogdanm 0:9b334a45a8ff 100 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
bogdanm 0:9b334a45a8ff 101 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
bogdanm 0:9b334a45a8ff 102 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
bogdanm 0:9b334a45a8ff 103 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
bogdanm 0:9b334a45a8ff 104 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
bogdanm 0:9b334a45a8ff 105 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
bogdanm 0:9b334a45a8ff 106 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
bogdanm 0:9b334a45a8ff 107 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
bogdanm 0:9b334a45a8ff 108 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
bogdanm 0:9b334a45a8ff 109 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
bogdanm 0:9b334a45a8ff 110 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
bogdanm 0:9b334a45a8ff 111 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
bogdanm 0:9b334a45a8ff 112 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
bogdanm 0:9b334a45a8ff 113 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
bogdanm 0:9b334a45a8ff 114 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
bogdanm 0:9b334a45a8ff 115 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
bogdanm 0:9b334a45a8ff 116 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
bogdanm 0:9b334a45a8ff 117 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
bogdanm 0:9b334a45a8ff 118 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
bogdanm 0:9b334a45a8ff 119 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
bogdanm 0:9b334a45a8ff 120 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
bogdanm 0:9b334a45a8ff 121 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
bogdanm 0:9b334a45a8ff 122 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
bogdanm 0:9b334a45a8ff 123 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
bogdanm 0:9b334a45a8ff 124 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
bogdanm 0:9b334a45a8ff 125 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
bogdanm 0:9b334a45a8ff 126 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
bogdanm 0:9b334a45a8ff 127 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
bogdanm 0:9b334a45a8ff 128 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
bogdanm 0:9b334a45a8ff 129 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
bogdanm 0:9b334a45a8ff 130 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
bogdanm 0:9b334a45a8ff 131 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
bogdanm 0:9b334a45a8ff 132 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @} End of group EFM32GG_DMA */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136