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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/device/efm32wg_i2c.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_i2c.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32wg_i2c.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32WG_I2C register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32WG_I2C
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32WG_I2C Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t CMD; /**< Command Register */
<> 144:ef7eb2e8f9f7 45 __I uint32_t STATE; /**< State Register */
<> 144:ef7eb2e8f9f7 46 __I uint32_t STATUS; /**< Status Register */
<> 144:ef7eb2e8f9f7 47 __IO uint32_t CLKDIV; /**< Clock Division Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t SADDR; /**< Slave Address Register */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
<> 144:ef7eb2e8f9f7 50 __I uint32_t RXDATA; /**< Receive Buffer Data Register */
<> 144:ef7eb2e8f9f7 51 __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
<> 144:ef7eb2e8f9f7 53 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t ROUTE; /**< I/O Routing Register */
<> 144:ef7eb2e8f9f7 58 } I2C_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 61 * @defgroup EFM32WG_I2C_BitFields
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 *****************************************************************************/
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /* Bit fields for I2C CTRL */
<> 144:ef7eb2e8f9f7 66 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
<> 144:ef7eb2e8f9f7 67 #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
<> 144:ef7eb2e8f9f7 68 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
<> 144:ef7eb2e8f9f7 69 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
<> 144:ef7eb2e8f9f7 70 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
<> 144:ef7eb2e8f9f7 71 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 72 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 73 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
<> 144:ef7eb2e8f9f7 74 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
<> 144:ef7eb2e8f9f7 75 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
<> 144:ef7eb2e8f9f7 76 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 77 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 78 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
<> 144:ef7eb2e8f9f7 79 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
<> 144:ef7eb2e8f9f7 80 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
<> 144:ef7eb2e8f9f7 81 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 82 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 83 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
<> 144:ef7eb2e8f9f7 84 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
<> 144:ef7eb2e8f9f7 85 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
<> 144:ef7eb2e8f9f7 86 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 87 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 88 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
<> 144:ef7eb2e8f9f7 89 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
<> 144:ef7eb2e8f9f7 90 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
<> 144:ef7eb2e8f9f7 91 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 92 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 93 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
<> 144:ef7eb2e8f9f7 94 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
<> 144:ef7eb2e8f9f7 95 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
<> 144:ef7eb2e8f9f7 96 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 97 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 98 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
<> 144:ef7eb2e8f9f7 99 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
<> 144:ef7eb2e8f9f7 100 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
<> 144:ef7eb2e8f9f7 101 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 102 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 103 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
<> 144:ef7eb2e8f9f7 104 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
<> 144:ef7eb2e8f9f7 105 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 106 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
<> 144:ef7eb2e8f9f7 107 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 108 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
<> 144:ef7eb2e8f9f7 109 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 110 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
<> 144:ef7eb2e8f9f7 111 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 112 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
<> 144:ef7eb2e8f9f7 113 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
<> 144:ef7eb2e8f9f7 114 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
<> 144:ef7eb2e8f9f7 115 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 116 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 144:ef7eb2e8f9f7 117 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 118 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 119 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 120 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 121 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
<> 144:ef7eb2e8f9f7 122 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 123 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 124 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 125 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
<> 144:ef7eb2e8f9f7 126 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
<> 144:ef7eb2e8f9f7 127 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
<> 144:ef7eb2e8f9f7 128 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 129 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 130 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
<> 144:ef7eb2e8f9f7 131 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
<> 144:ef7eb2e8f9f7 132 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 133 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
<> 144:ef7eb2e8f9f7 134 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 135 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 136 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 137 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 138 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 139 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
<> 144:ef7eb2e8f9f7 140 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
<> 144:ef7eb2e8f9f7 141 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 142 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 143 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 144 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 145 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Bit fields for I2C CMD */
<> 144:ef7eb2e8f9f7 148 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
<> 144:ef7eb2e8f9f7 149 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
<> 144:ef7eb2e8f9f7 150 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
<> 144:ef7eb2e8f9f7 151 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
<> 144:ef7eb2e8f9f7 152 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 144:ef7eb2e8f9f7 153 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 154 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 155 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
<> 144:ef7eb2e8f9f7 156 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
<> 144:ef7eb2e8f9f7 157 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
<> 144:ef7eb2e8f9f7 158 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 159 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 160 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
<> 144:ef7eb2e8f9f7 161 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
<> 144:ef7eb2e8f9f7 162 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
<> 144:ef7eb2e8f9f7 163 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 164 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 165 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
<> 144:ef7eb2e8f9f7 166 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
<> 144:ef7eb2e8f9f7 167 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
<> 144:ef7eb2e8f9f7 168 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 169 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 170 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
<> 144:ef7eb2e8f9f7 171 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
<> 144:ef7eb2e8f9f7 172 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
<> 144:ef7eb2e8f9f7 173 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 174 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 175 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
<> 144:ef7eb2e8f9f7 176 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
<> 144:ef7eb2e8f9f7 177 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
<> 144:ef7eb2e8f9f7 178 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 179 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 180 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
<> 144:ef7eb2e8f9f7 181 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
<> 144:ef7eb2e8f9f7 182 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
<> 144:ef7eb2e8f9f7 183 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 184 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 185 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
<> 144:ef7eb2e8f9f7 186 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
<> 144:ef7eb2e8f9f7 187 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
<> 144:ef7eb2e8f9f7 188 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 189 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Bit fields for I2C STATE */
<> 144:ef7eb2e8f9f7 192 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
<> 144:ef7eb2e8f9f7 193 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
<> 144:ef7eb2e8f9f7 194 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
<> 144:ef7eb2e8f9f7 195 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
<> 144:ef7eb2e8f9f7 196 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
<> 144:ef7eb2e8f9f7 197 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 198 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 199 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
<> 144:ef7eb2e8f9f7 200 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
<> 144:ef7eb2e8f9f7 201 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
<> 144:ef7eb2e8f9f7 202 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 203 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 204 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
<> 144:ef7eb2e8f9f7 205 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
<> 144:ef7eb2e8f9f7 206 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
<> 144:ef7eb2e8f9f7 207 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 208 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 209 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
<> 144:ef7eb2e8f9f7 210 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
<> 144:ef7eb2e8f9f7 211 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
<> 144:ef7eb2e8f9f7 212 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 213 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 214 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
<> 144:ef7eb2e8f9f7 215 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 216 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 217 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 218 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 219 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
<> 144:ef7eb2e8f9f7 220 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
<> 144:ef7eb2e8f9f7 221 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 222 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
<> 144:ef7eb2e8f9f7 223 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
<> 144:ef7eb2e8f9f7 224 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
<> 144:ef7eb2e8f9f7 225 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
<> 144:ef7eb2e8f9f7 226 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
<> 144:ef7eb2e8f9f7 227 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
<> 144:ef7eb2e8f9f7 228 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
<> 144:ef7eb2e8f9f7 229 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
<> 144:ef7eb2e8f9f7 230 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
<> 144:ef7eb2e8f9f7 231 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
<> 144:ef7eb2e8f9f7 232 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
<> 144:ef7eb2e8f9f7 233 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
<> 144:ef7eb2e8f9f7 234 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
<> 144:ef7eb2e8f9f7 235 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
<> 144:ef7eb2e8f9f7 236 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Bit fields for I2C STATUS */
<> 144:ef7eb2e8f9f7 239 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
<> 144:ef7eb2e8f9f7 240 #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
<> 144:ef7eb2e8f9f7 241 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
<> 144:ef7eb2e8f9f7 242 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
<> 144:ef7eb2e8f9f7 243 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
<> 144:ef7eb2e8f9f7 244 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 245 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 246 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
<> 144:ef7eb2e8f9f7 247 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
<> 144:ef7eb2e8f9f7 248 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
<> 144:ef7eb2e8f9f7 249 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 250 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 251 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
<> 144:ef7eb2e8f9f7 252 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
<> 144:ef7eb2e8f9f7 253 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
<> 144:ef7eb2e8f9f7 254 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 255 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 256 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
<> 144:ef7eb2e8f9f7 257 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
<> 144:ef7eb2e8f9f7 258 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
<> 144:ef7eb2e8f9f7 259 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 260 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 261 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
<> 144:ef7eb2e8f9f7 262 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
<> 144:ef7eb2e8f9f7 263 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
<> 144:ef7eb2e8f9f7 264 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 265 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 266 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
<> 144:ef7eb2e8f9f7 267 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
<> 144:ef7eb2e8f9f7 268 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
<> 144:ef7eb2e8f9f7 269 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 270 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 271 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
<> 144:ef7eb2e8f9f7 272 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
<> 144:ef7eb2e8f9f7 273 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
<> 144:ef7eb2e8f9f7 274 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 275 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 276 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
<> 144:ef7eb2e8f9f7 277 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
<> 144:ef7eb2e8f9f7 278 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
<> 144:ef7eb2e8f9f7 279 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 280 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 281 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
<> 144:ef7eb2e8f9f7 282 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 283 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 284 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 285 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Bit fields for I2C CLKDIV */
<> 144:ef7eb2e8f9f7 288 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
<> 144:ef7eb2e8f9f7 289 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
<> 144:ef7eb2e8f9f7 290 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
<> 144:ef7eb2e8f9f7 291 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
<> 144:ef7eb2e8f9f7 292 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
<> 144:ef7eb2e8f9f7 293 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Bit fields for I2C SADDR */
<> 144:ef7eb2e8f9f7 296 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
<> 144:ef7eb2e8f9f7 297 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
<> 144:ef7eb2e8f9f7 298 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
<> 144:ef7eb2e8f9f7 299 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
<> 144:ef7eb2e8f9f7 300 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
<> 144:ef7eb2e8f9f7 301 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Bit fields for I2C SADDRMASK */
<> 144:ef7eb2e8f9f7 304 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
<> 144:ef7eb2e8f9f7 305 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
<> 144:ef7eb2e8f9f7 306 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
<> 144:ef7eb2e8f9f7 307 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
<> 144:ef7eb2e8f9f7 308 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
<> 144:ef7eb2e8f9f7 309 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Bit fields for I2C RXDATA */
<> 144:ef7eb2e8f9f7 312 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 313 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 314 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 315 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 316 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 317 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Bit fields for I2C RXDATAP */
<> 144:ef7eb2e8f9f7 320 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 321 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 322 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 323 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 324 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 325 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Bit fields for I2C TXDATA */
<> 144:ef7eb2e8f9f7 328 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 329 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 330 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 331 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 332 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 333 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Bit fields for I2C IF */
<> 144:ef7eb2e8f9f7 336 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
<> 144:ef7eb2e8f9f7 337 #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
<> 144:ef7eb2e8f9f7 338 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
<> 144:ef7eb2e8f9f7 339 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
<> 144:ef7eb2e8f9f7 340 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 144:ef7eb2e8f9f7 341 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 342 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 343 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
<> 144:ef7eb2e8f9f7 344 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 144:ef7eb2e8f9f7 345 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 144:ef7eb2e8f9f7 346 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 347 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 348 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
<> 144:ef7eb2e8f9f7 349 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 144:ef7eb2e8f9f7 350 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 144:ef7eb2e8f9f7 351 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 352 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 353 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
<> 144:ef7eb2e8f9f7 354 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 144:ef7eb2e8f9f7 355 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 144:ef7eb2e8f9f7 356 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 357 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 358 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
<> 144:ef7eb2e8f9f7 359 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 144:ef7eb2e8f9f7 360 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 144:ef7eb2e8f9f7 361 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 362 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 363 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
<> 144:ef7eb2e8f9f7 364 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 365 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 366 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 367 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 368 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 369 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 144:ef7eb2e8f9f7 370 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 144:ef7eb2e8f9f7 371 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 372 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 373 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 374 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 144:ef7eb2e8f9f7 375 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 144:ef7eb2e8f9f7 376 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 377 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 378 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
<> 144:ef7eb2e8f9f7 379 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 380 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 381 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 382 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 383 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
<> 144:ef7eb2e8f9f7 384 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 385 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 386 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 387 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 388 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 389 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 390 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 391 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 392 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 393 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
<> 144:ef7eb2e8f9f7 394 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 395 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 396 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 397 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 398 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 399 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 144:ef7eb2e8f9f7 400 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 144:ef7eb2e8f9f7 401 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 402 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 403 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 404 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 144:ef7eb2e8f9f7 405 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 144:ef7eb2e8f9f7 406 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 407 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 408 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
<> 144:ef7eb2e8f9f7 409 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 144:ef7eb2e8f9f7 410 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 144:ef7eb2e8f9f7 411 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 412 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 413 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
<> 144:ef7eb2e8f9f7 414 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 144:ef7eb2e8f9f7 415 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 144:ef7eb2e8f9f7 416 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 417 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 418 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
<> 144:ef7eb2e8f9f7 419 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 420 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 421 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 422 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Bit fields for I2C IFS */
<> 144:ef7eb2e8f9f7 425 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
<> 144:ef7eb2e8f9f7 426 #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
<> 144:ef7eb2e8f9f7 427 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
<> 144:ef7eb2e8f9f7 428 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
<> 144:ef7eb2e8f9f7 429 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 144:ef7eb2e8f9f7 430 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 431 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 432 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
<> 144:ef7eb2e8f9f7 433 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 144:ef7eb2e8f9f7 434 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 144:ef7eb2e8f9f7 435 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 436 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 437 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
<> 144:ef7eb2e8f9f7 438 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 144:ef7eb2e8f9f7 439 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 144:ef7eb2e8f9f7 440 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 441 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 442 #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
<> 144:ef7eb2e8f9f7 443 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 144:ef7eb2e8f9f7 444 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 144:ef7eb2e8f9f7 445 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 446 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 447 #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 448 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 144:ef7eb2e8f9f7 449 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 144:ef7eb2e8f9f7 450 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 451 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 452 #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 453 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 144:ef7eb2e8f9f7 454 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 144:ef7eb2e8f9f7 455 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 456 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 457 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
<> 144:ef7eb2e8f9f7 458 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 459 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 460 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 461 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 462 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
<> 144:ef7eb2e8f9f7 463 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 464 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 465 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 466 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 467 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 468 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 469 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 470 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 471 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 472 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
<> 144:ef7eb2e8f9f7 473 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 474 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 475 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 476 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 477 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 478 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 144:ef7eb2e8f9f7 479 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 144:ef7eb2e8f9f7 480 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 481 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 482 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 483 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 144:ef7eb2e8f9f7 484 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 144:ef7eb2e8f9f7 485 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 486 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 487 #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
<> 144:ef7eb2e8f9f7 488 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 144:ef7eb2e8f9f7 489 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 144:ef7eb2e8f9f7 490 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 491 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 492 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
<> 144:ef7eb2e8f9f7 493 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 144:ef7eb2e8f9f7 494 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 144:ef7eb2e8f9f7 495 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 496 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 497 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
<> 144:ef7eb2e8f9f7 498 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 499 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 500 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 501 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Bit fields for I2C IFC */
<> 144:ef7eb2e8f9f7 504 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
<> 144:ef7eb2e8f9f7 505 #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
<> 144:ef7eb2e8f9f7 506 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
<> 144:ef7eb2e8f9f7 507 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
<> 144:ef7eb2e8f9f7 508 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 144:ef7eb2e8f9f7 509 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 510 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 511 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
<> 144:ef7eb2e8f9f7 512 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 144:ef7eb2e8f9f7 513 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 144:ef7eb2e8f9f7 514 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 515 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 516 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
<> 144:ef7eb2e8f9f7 517 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 144:ef7eb2e8f9f7 518 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 144:ef7eb2e8f9f7 519 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 520 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 521 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
<> 144:ef7eb2e8f9f7 522 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 144:ef7eb2e8f9f7 523 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 144:ef7eb2e8f9f7 524 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 525 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 526 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 527 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 144:ef7eb2e8f9f7 528 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 144:ef7eb2e8f9f7 529 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 530 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 531 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
<> 144:ef7eb2e8f9f7 532 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 144:ef7eb2e8f9f7 533 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 144:ef7eb2e8f9f7 534 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 535 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 536 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
<> 144:ef7eb2e8f9f7 537 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 538 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 539 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 540 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 541 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
<> 144:ef7eb2e8f9f7 542 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 543 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 544 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 545 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 546 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 547 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 548 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 549 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 550 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 551 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
<> 144:ef7eb2e8f9f7 552 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 553 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 554 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 555 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 556 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 557 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 144:ef7eb2e8f9f7 558 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 144:ef7eb2e8f9f7 559 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 560 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 561 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 562 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 144:ef7eb2e8f9f7 563 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 144:ef7eb2e8f9f7 564 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 565 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 566 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
<> 144:ef7eb2e8f9f7 567 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 144:ef7eb2e8f9f7 568 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 144:ef7eb2e8f9f7 569 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 570 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 571 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
<> 144:ef7eb2e8f9f7 572 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 144:ef7eb2e8f9f7 573 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 144:ef7eb2e8f9f7 574 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 575 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 576 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
<> 144:ef7eb2e8f9f7 577 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 578 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 579 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 580 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /* Bit fields for I2C IEN */
<> 144:ef7eb2e8f9f7 583 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
<> 144:ef7eb2e8f9f7 584 #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
<> 144:ef7eb2e8f9f7 585 #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
<> 144:ef7eb2e8f9f7 586 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
<> 144:ef7eb2e8f9f7 587 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
<> 144:ef7eb2e8f9f7 588 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 589 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 590 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
<> 144:ef7eb2e8f9f7 591 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
<> 144:ef7eb2e8f9f7 592 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
<> 144:ef7eb2e8f9f7 593 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 594 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 595 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
<> 144:ef7eb2e8f9f7 596 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
<> 144:ef7eb2e8f9f7 597 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
<> 144:ef7eb2e8f9f7 598 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 599 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 600 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
<> 144:ef7eb2e8f9f7 601 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
<> 144:ef7eb2e8f9f7 602 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
<> 144:ef7eb2e8f9f7 603 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 604 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 605 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
<> 144:ef7eb2e8f9f7 606 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
<> 144:ef7eb2e8f9f7 607 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
<> 144:ef7eb2e8f9f7 608 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 609 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 610 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
<> 144:ef7eb2e8f9f7 611 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 612 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
<> 144:ef7eb2e8f9f7 613 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 614 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 615 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
<> 144:ef7eb2e8f9f7 616 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
<> 144:ef7eb2e8f9f7 617 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
<> 144:ef7eb2e8f9f7 618 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 619 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 620 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
<> 144:ef7eb2e8f9f7 621 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
<> 144:ef7eb2e8f9f7 622 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
<> 144:ef7eb2e8f9f7 623 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 624 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 625 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
<> 144:ef7eb2e8f9f7 626 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 627 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
<> 144:ef7eb2e8f9f7 628 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 629 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 630 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
<> 144:ef7eb2e8f9f7 631 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 632 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
<> 144:ef7eb2e8f9f7 633 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 634 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 635 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
<> 144:ef7eb2e8f9f7 636 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 637 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
<> 144:ef7eb2e8f9f7 638 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 639 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 640 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
<> 144:ef7eb2e8f9f7 641 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 642 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
<> 144:ef7eb2e8f9f7 643 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 644 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 645 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 646 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
<> 144:ef7eb2e8f9f7 647 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
<> 144:ef7eb2e8f9f7 648 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 649 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 650 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 651 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
<> 144:ef7eb2e8f9f7 652 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
<> 144:ef7eb2e8f9f7 653 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 654 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 655 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
<> 144:ef7eb2e8f9f7 656 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
<> 144:ef7eb2e8f9f7 657 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
<> 144:ef7eb2e8f9f7 658 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 659 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 660 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
<> 144:ef7eb2e8f9f7 661 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
<> 144:ef7eb2e8f9f7 662 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
<> 144:ef7eb2e8f9f7 663 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 664 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 665 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
<> 144:ef7eb2e8f9f7 666 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 667 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
<> 144:ef7eb2e8f9f7 668 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 669 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Bit fields for I2C ROUTE */
<> 144:ef7eb2e8f9f7 672 #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 673 #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 674 #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
<> 144:ef7eb2e8f9f7 675 #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
<> 144:ef7eb2e8f9f7 676 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
<> 144:ef7eb2e8f9f7 677 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 678 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 679 #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
<> 144:ef7eb2e8f9f7 680 #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
<> 144:ef7eb2e8f9f7 681 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
<> 144:ef7eb2e8f9f7 682 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 683 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 684 #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
<> 144:ef7eb2e8f9f7 685 #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */
<> 144:ef7eb2e8f9f7 686 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 687 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 688 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 689 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 690 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 691 #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 692 #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 693 #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 694 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 695 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 696 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 697 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 698 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 699 #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 700 #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 701 #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /** @} End of group EFM32WG_I2C */
<> 144:ef7eb2e8f9f7 704 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 705