rik te winkel / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG_STK3200/TOOLCHAIN_GCC_ARM/startup_efm32zg.S@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* @file startup_efm32zg.S
<> 144:ef7eb2e8f9f7 2 * @brief startup file for Silicon Labs EFM32ZG devices.
<> 144:ef7eb2e8f9f7 3 * For use with GCC for ARM Embedded Processors
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 * Date: 12 June 2014
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 */
<> 144:ef7eb2e8f9f7 8 /* Copyright (c) 2011 - 2014 ARM LIMITED
<> 144:ef7eb2e8f9f7 9
<> 144:ef7eb2e8f9f7 10 All rights reserved.
<> 144:ef7eb2e8f9f7 11 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 12 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 14 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 17 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 19 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 20 specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 32 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 .syntax unified
<> 144:ef7eb2e8f9f7 36 .arch armv6-m
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 .section .stack
<> 144:ef7eb2e8f9f7 39 .align 3
<> 144:ef7eb2e8f9f7 40 #ifdef __STACK_SIZE
<> 144:ef7eb2e8f9f7 41 .equ Stack_Size, __STACK_SIZE
<> 144:ef7eb2e8f9f7 42 #else
<> 144:ef7eb2e8f9f7 43 .equ Stack_Size, 0x00000400
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45 .globl __StackTop
<> 144:ef7eb2e8f9f7 46 .globl __StackLimit
<> 144:ef7eb2e8f9f7 47 __StackLimit:
<> 144:ef7eb2e8f9f7 48 .space Stack_Size
<> 144:ef7eb2e8f9f7 49 .size __StackLimit, . - __StackLimit
<> 144:ef7eb2e8f9f7 50 __StackTop:
<> 144:ef7eb2e8f9f7 51 .size __StackTop, . - __StackTop
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 .section .heap
<> 144:ef7eb2e8f9f7 54 .align 3
<> 144:ef7eb2e8f9f7 55 #ifdef __HEAP_SIZE
<> 144:ef7eb2e8f9f7 56 .equ Heap_Size, __HEAP_SIZE
<> 144:ef7eb2e8f9f7 57 #else
<> 144:ef7eb2e8f9f7 58 .equ Heap_Size, 0x00000000
<> 144:ef7eb2e8f9f7 59 #endif
<> 144:ef7eb2e8f9f7 60 .globl __HeapBase
<> 144:ef7eb2e8f9f7 61 .globl __HeapLimit
<> 144:ef7eb2e8f9f7 62 __HeapBase:
<> 144:ef7eb2e8f9f7 63 .if Heap_Size
<> 144:ef7eb2e8f9f7 64 .space Heap_Size
<> 144:ef7eb2e8f9f7 65 .endif
<> 144:ef7eb2e8f9f7 66 .size __HeapBase, . - __HeapBase
<> 144:ef7eb2e8f9f7 67 __HeapLimit:
<> 144:ef7eb2e8f9f7 68 .size __HeapLimit, . - __HeapLimit
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 .section .vectors
<> 144:ef7eb2e8f9f7 71 .align 2
<> 144:ef7eb2e8f9f7 72 .globl __Vectors
<> 144:ef7eb2e8f9f7 73 __Vectors:
<> 144:ef7eb2e8f9f7 74 .long __StackTop /* Top of Stack */
<> 144:ef7eb2e8f9f7 75 .long Reset_Handler /* Reset Handler */
<> 144:ef7eb2e8f9f7 76 .long NMI_Handler /* NMI Handler */
<> 144:ef7eb2e8f9f7 77 .long HardFault_Handler /* Hard Fault Handler */
<> 144:ef7eb2e8f9f7 78 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 79 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 80 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 81 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 82 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 83 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 84 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 85 .long SVC_Handler /* SVCall Handler */
<> 144:ef7eb2e8f9f7 86 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 87 .long Default_Handler /* Reserved */
<> 144:ef7eb2e8f9f7 88 .long PendSV_Handler /* PendSV Handler */
<> 144:ef7eb2e8f9f7 89 .long SysTick_Handler /* SysTick Handler */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* External interrupts */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 .long DMA_IRQHandler /* 0 - DMA */
<> 144:ef7eb2e8f9f7 94 .long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
<> 144:ef7eb2e8f9f7 95 .long TIMER0_IRQHandler /* 2 - TIMER0 */
<> 144:ef7eb2e8f9f7 96 .long ACMP0_IRQHandler /* 3 - ACMP0 */
<> 144:ef7eb2e8f9f7 97 .long ADC0_IRQHandler /* 4 - ADC0 */
<> 144:ef7eb2e8f9f7 98 .long I2C0_IRQHandler /* 5 - I2C0 */
<> 144:ef7eb2e8f9f7 99 .long GPIO_ODD_IRQHandler /* 6 - GPIO_ODD */
<> 144:ef7eb2e8f9f7 100 .long TIMER1_IRQHandler /* 7 - TIMER1 */
<> 144:ef7eb2e8f9f7 101 .long USART1_RX_IRQHandler /* 8 - USART1_RX */
<> 144:ef7eb2e8f9f7 102 .long USART1_TX_IRQHandler /* 9 - USART1_TX */
<> 144:ef7eb2e8f9f7 103 .long LEUART0_IRQHandler /* 10 - LEUART0 */
<> 144:ef7eb2e8f9f7 104 .long PCNT0_IRQHandler /* 11 - PCNT0 */
<> 144:ef7eb2e8f9f7 105 .long RTC_IRQHandler /* 12 - RTC */
<> 144:ef7eb2e8f9f7 106 .long CMU_IRQHandler /* 13 - CMU */
<> 144:ef7eb2e8f9f7 107 .long VCMP_IRQHandler /* 14 - VCMP */
<> 144:ef7eb2e8f9f7 108 .long MSC_IRQHandler /* 15 - MSC */
<> 144:ef7eb2e8f9f7 109 .long AES_IRQHandler /* 16 - AES */
<> 144:ef7eb2e8f9f7 110 .long Default_Handler /* 17 - Reserved */
<> 144:ef7eb2e8f9f7 111 .long Default_Handler /* 18 - Reserved */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 .size __Vectors, . - __Vectors
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 .text
<> 144:ef7eb2e8f9f7 117 .thumb
<> 144:ef7eb2e8f9f7 118 .thumb_func
<> 144:ef7eb2e8f9f7 119 .align 2
<> 144:ef7eb2e8f9f7 120 .globl Reset_Handler
<> 144:ef7eb2e8f9f7 121 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 122 Reset_Handler:
<> 144:ef7eb2e8f9f7 123 #ifndef __NO_SYSTEM_INIT
<> 144:ef7eb2e8f9f7 124 ldr r0, =SystemInit
<> 144:ef7eb2e8f9f7 125 blx r0
<> 144:ef7eb2e8f9f7 126 #endif
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Firstly it copies data from read only memory to RAM. There are two schemes
<> 144:ef7eb2e8f9f7 129 * to copy. One can copy more than one sections. Another can only copy
<> 144:ef7eb2e8f9f7 130 * one section. The former scheme needs more instructions and read-only
<> 144:ef7eb2e8f9f7 131 * data to implement than the latter.
<> 144:ef7eb2e8f9f7 132 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #ifdef __STARTUP_COPY_MULTIPLE
<> 144:ef7eb2e8f9f7 135 /* Multiple sections scheme.
<> 144:ef7eb2e8f9f7 136 *
<> 144:ef7eb2e8f9f7 137 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 144:ef7eb2e8f9f7 138 * there are array of triplets, each of which specify:
<> 144:ef7eb2e8f9f7 139 * offset 0: LMA of start of a section to copy from
<> 144:ef7eb2e8f9f7 140 * offset 4: VMA of start of a section to copy to
<> 144:ef7eb2e8f9f7 141 * offset 8: size of the section to copy. Must be multiply of 4
<> 144:ef7eb2e8f9f7 142 *
<> 144:ef7eb2e8f9f7 143 * All addresses must be aligned to 4 bytes boundary.
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145 ldr r4, =__copy_table_start__
<> 144:ef7eb2e8f9f7 146 ldr r5, =__copy_table_end__
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 .L_loop0:
<> 144:ef7eb2e8f9f7 149 cmp r4, r5
<> 144:ef7eb2e8f9f7 150 bge .L_loop0_done
<> 144:ef7eb2e8f9f7 151 ldr r1, [r4]
<> 144:ef7eb2e8f9f7 152 ldr r2, [r4, #4]
<> 144:ef7eb2e8f9f7 153 ldr r3, [r4, #8]
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 .L_loop0_0:
<> 144:ef7eb2e8f9f7 156 subs r3, #4
<> 144:ef7eb2e8f9f7 157 blt .L_loop0_0_done
<> 144:ef7eb2e8f9f7 158 ldr r0, [r1, r3]
<> 144:ef7eb2e8f9f7 159 str r0, [r2, r3]
<> 144:ef7eb2e8f9f7 160 b .L_loop0_0
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 .L_loop0_0_done:
<> 144:ef7eb2e8f9f7 163 adds r4, #12
<> 144:ef7eb2e8f9f7 164 b .L_loop0
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 .L_loop0_done:
<> 144:ef7eb2e8f9f7 167 #else
<> 144:ef7eb2e8f9f7 168 /* Single section scheme.
<> 144:ef7eb2e8f9f7 169 *
<> 144:ef7eb2e8f9f7 170 * The ranges of copy from/to are specified by following symbols
<> 144:ef7eb2e8f9f7 171 * __etext: LMA of start of the section to copy from. Usually end of text
<> 144:ef7eb2e8f9f7 172 * __data_start__: VMA of start of the section to copy to
<> 144:ef7eb2e8f9f7 173 * __data_end__: VMA of end of the section to copy to
<> 144:ef7eb2e8f9f7 174 *
<> 144:ef7eb2e8f9f7 175 * All addresses must be aligned to 4 bytes boundary.
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177 ldr r1, =__etext
<> 144:ef7eb2e8f9f7 178 ldr r2, =__data_start__
<> 144:ef7eb2e8f9f7 179 ldr r3, =__data_end__
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 subs r3, r2
<> 144:ef7eb2e8f9f7 182 ble .L_loop1_done
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 .L_loop1:
<> 144:ef7eb2e8f9f7 185 subs r3, #4
<> 144:ef7eb2e8f9f7 186 ldr r0, [r1,r3]
<> 144:ef7eb2e8f9f7 187 str r0, [r2,r3]
<> 144:ef7eb2e8f9f7 188 bgt .L_loop1
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 .L_loop1_done:
<> 144:ef7eb2e8f9f7 191 #endif /*__STARTUP_COPY_MULTIPLE */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* This part of work usually is done in C library startup code. Otherwise,
<> 144:ef7eb2e8f9f7 194 * define this macro to enable it in this startup.
<> 144:ef7eb2e8f9f7 195 *
<> 144:ef7eb2e8f9f7 196 * There are two schemes too. One can clear multiple BSS sections. Another
<> 144:ef7eb2e8f9f7 197 * can only clear one section. The former is more size expensive than the
<> 144:ef7eb2e8f9f7 198 * latter.
<> 144:ef7eb2e8f9f7 199 *
<> 144:ef7eb2e8f9f7 200 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
<> 144:ef7eb2e8f9f7 201 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
<> 144:ef7eb2e8f9f7 204 /* Multiple sections scheme.
<> 144:ef7eb2e8f9f7 205 *
<> 144:ef7eb2e8f9f7 206 * Between symbol address __copy_table_start__ and __copy_table_end__,
<> 144:ef7eb2e8f9f7 207 * there are array of tuples specifying:
<> 144:ef7eb2e8f9f7 208 * offset 0: Start of a BSS section
<> 144:ef7eb2e8f9f7 209 * offset 4: Size of this BSS section. Must be multiply of 4
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 ldr r3, =__zero_table_start__
<> 144:ef7eb2e8f9f7 212 ldr r4, =__zero_table_end__
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 .L_loop2:
<> 144:ef7eb2e8f9f7 215 cmp r3, r4
<> 144:ef7eb2e8f9f7 216 bge .L_loop2_done
<> 144:ef7eb2e8f9f7 217 ldr r1, [r3]
<> 144:ef7eb2e8f9f7 218 ldr r2, [r3, #4]
<> 144:ef7eb2e8f9f7 219 movs r0, 0
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 .L_loop2_0:
<> 144:ef7eb2e8f9f7 222 subs r2, #4
<> 144:ef7eb2e8f9f7 223 blt .L_loop2_0_done
<> 144:ef7eb2e8f9f7 224 str r0, [r1, r2]
<> 144:ef7eb2e8f9f7 225 b .L_loop2_0
<> 144:ef7eb2e8f9f7 226 .L_loop2_0_done:
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 adds r3, #8
<> 144:ef7eb2e8f9f7 229 b .L_loop2
<> 144:ef7eb2e8f9f7 230 .L_loop2_done:
<> 144:ef7eb2e8f9f7 231 #elif defined (__STARTUP_CLEAR_BSS)
<> 144:ef7eb2e8f9f7 232 /* Single BSS section scheme.
<> 144:ef7eb2e8f9f7 233 *
<> 144:ef7eb2e8f9f7 234 * The BSS section is specified by following symbols
<> 144:ef7eb2e8f9f7 235 * __bss_start__: start of the BSS section.
<> 144:ef7eb2e8f9f7 236 * __bss_end__: end of the BSS section.
<> 144:ef7eb2e8f9f7 237 *
<> 144:ef7eb2e8f9f7 238 * Both addresses must be aligned to 4 bytes boundary.
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 ldr r1, =__bss_start__
<> 144:ef7eb2e8f9f7 241 ldr r2, =__bss_end__
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 movs r0, 0
<> 144:ef7eb2e8f9f7 244 subs r2, r1
<> 144:ef7eb2e8f9f7 245 ble .L_loop3_done
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 .L_loop3:
<> 144:ef7eb2e8f9f7 248 subs r2, #4
<> 144:ef7eb2e8f9f7 249 str r0, [r1, r2]
<> 144:ef7eb2e8f9f7 250 bgt .L_loop3
<> 144:ef7eb2e8f9f7 251 .L_loop3_done:
<> 144:ef7eb2e8f9f7 252 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #ifndef __START
<> 144:ef7eb2e8f9f7 255 #define __START _start
<> 144:ef7eb2e8f9f7 256 #endif
<> 144:ef7eb2e8f9f7 257 bl __START
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 .pool
<> 144:ef7eb2e8f9f7 260 .size Reset_Handler, . - Reset_Handler
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 .align 1
<> 144:ef7eb2e8f9f7 263 .thumb_func
<> 144:ef7eb2e8f9f7 264 .weak Default_Handler
<> 144:ef7eb2e8f9f7 265 .type Default_Handler, %function
<> 144:ef7eb2e8f9f7 266 Default_Handler:
<> 144:ef7eb2e8f9f7 267 b .
<> 144:ef7eb2e8f9f7 268 .size Default_Handler, . - Default_Handler
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Macro to define default handlers. Default handler
<> 144:ef7eb2e8f9f7 271 * will be weak symbol and just dead loops. They can be
<> 144:ef7eb2e8f9f7 272 * overwritten by other handlers */
<> 144:ef7eb2e8f9f7 273 .macro def_irq_handler handler_name
<> 144:ef7eb2e8f9f7 274 .weak \handler_name
<> 144:ef7eb2e8f9f7 275 .set \handler_name, Default_Handler
<> 144:ef7eb2e8f9f7 276 .endm
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 def_irq_handler NMI_Handler
<> 144:ef7eb2e8f9f7 279 def_irq_handler HardFault_Handler
<> 144:ef7eb2e8f9f7 280 def_irq_handler SVC_Handler
<> 144:ef7eb2e8f9f7 281 def_irq_handler PendSV_Handler
<> 144:ef7eb2e8f9f7 282 def_irq_handler SysTick_Handler
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 def_irq_handler DMA_IRQHandler
<> 144:ef7eb2e8f9f7 285 def_irq_handler GPIO_EVEN_IRQHandler
<> 144:ef7eb2e8f9f7 286 def_irq_handler TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 287 def_irq_handler ACMP0_IRQHandler
<> 144:ef7eb2e8f9f7 288 def_irq_handler ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 289 def_irq_handler I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 290 def_irq_handler GPIO_ODD_IRQHandler
<> 144:ef7eb2e8f9f7 291 def_irq_handler TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 292 def_irq_handler USART1_RX_IRQHandler
<> 144:ef7eb2e8f9f7 293 def_irq_handler USART1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 294 def_irq_handler LEUART0_IRQHandler
<> 144:ef7eb2e8f9f7 295 def_irq_handler PCNT0_IRQHandler
<> 144:ef7eb2e8f9f7 296 def_irq_handler RTC_IRQHandler
<> 144:ef7eb2e8f9f7 297 def_irq_handler CMU_IRQHandler
<> 144:ef7eb2e8f9f7 298 def_irq_handler VCMP_IRQHandler
<> 144:ef7eb2e8f9f7 299 def_irq_handler MSC_IRQHandler
<> 144:ef7eb2e8f9f7 300 def_irq_handler AES_IRQHandler
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 .end