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mbed-dev
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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG_STK3800/efm32wg_rtc.h@50:a417edff4437, 2016-01-15 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jan 15 07:45:16 2016 +0000
- Revision:
- 50:a417edff4437
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9
Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/
Remove doubling of buffer size in realiseEndpoint()
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 2 | * @file efm32wg_rtc.h |
| bogdanm | 0:9b334a45a8ff | 3 | * @brief EFM32WG_RTC register and bit field definitions |
| mbed_official | 50:a417edff4437 | 4 | * @version 4.2.0 |
| bogdanm | 0:9b334a45a8ff | 5 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 6 | * @section License |
| mbed_official | 50:a417edff4437 | 7 | * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * |
| bogdanm | 0:9b334a45a8ff | 10 | * Permission is granted to anyone to use this software for any purpose, |
| bogdanm | 0:9b334a45a8ff | 11 | * including commercial applications, and to alter it and redistribute it |
| bogdanm | 0:9b334a45a8ff | 12 | * freely, subject to the following restrictions: |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| bogdanm | 0:9b334a45a8ff | 15 | * claim that you wrote the original software.@n |
| bogdanm | 0:9b334a45a8ff | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| bogdanm | 0:9b334a45a8ff | 17 | * misrepresented as being the original software.@n |
| bogdanm | 0:9b334a45a8ff | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| bogdanm | 0:9b334a45a8ff | 19 | * |
| bogdanm | 0:9b334a45a8ff | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| bogdanm | 0:9b334a45a8ff | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| bogdanm | 0:9b334a45a8ff | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| bogdanm | 0:9b334a45a8ff | 23 | * kind, including, but not limited to, any implied warranties of |
| bogdanm | 0:9b334a45a8ff | 24 | * merchantability or fitness for any particular purpose or warranties against |
| bogdanm | 0:9b334a45a8ff | 25 | * infringement of any proprietary rights of a third party. |
| bogdanm | 0:9b334a45a8ff | 26 | * |
| bogdanm | 0:9b334a45a8ff | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| bogdanm | 0:9b334a45a8ff | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| bogdanm | 0:9b334a45a8ff | 29 | * any third party, arising from your use of this Software. |
| bogdanm | 0:9b334a45a8ff | 30 | * |
| bogdanm | 0:9b334a45a8ff | 31 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 32 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 33 | * @addtogroup Parts |
| mbed_official | 50:a417edff4437 | 34 | * @{ |
| mbed_official | 50:a417edff4437 | 35 | ******************************************************************************/ |
| mbed_official | 50:a417edff4437 | 36 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 37 | * @defgroup EFM32WG_RTC |
| bogdanm | 0:9b334a45a8ff | 38 | * @{ |
| bogdanm | 0:9b334a45a8ff | 39 | * @brief EFM32WG_RTC Register Declaration |
| bogdanm | 0:9b334a45a8ff | 40 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 41 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 42 | { |
| bogdanm | 0:9b334a45a8ff | 43 | __IO uint32_t CTRL; /**< Control Register */ |
| bogdanm | 0:9b334a45a8ff | 44 | __IO uint32_t CNT; /**< Counter Value Register */ |
| bogdanm | 0:9b334a45a8ff | 45 | __IO uint32_t COMP0; /**< Compare Value Register 0 */ |
| bogdanm | 0:9b334a45a8ff | 46 | __IO uint32_t COMP1; /**< Compare Value Register 1 */ |
| bogdanm | 0:9b334a45a8ff | 47 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| bogdanm | 0:9b334a45a8ff | 48 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| bogdanm | 0:9b334a45a8ff | 49 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 50 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| bogdanm | 0:9b334a45a8ff | 51 | |
| bogdanm | 0:9b334a45a8ff | 52 | __IO uint32_t FREEZE; /**< Freeze Register */ |
| bogdanm | 0:9b334a45a8ff | 53 | __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| bogdanm | 0:9b334a45a8ff | 54 | } RTC_TypeDef; /** @} */ |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 57 | * @defgroup EFM32WG_RTC_BitFields |
| bogdanm | 0:9b334a45a8ff | 58 | * @{ |
| bogdanm | 0:9b334a45a8ff | 59 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 60 | |
| bogdanm | 0:9b334a45a8ff | 61 | /* Bit fields for RTC CTRL */ |
| bogdanm | 0:9b334a45a8ff | 62 | #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 63 | #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 64 | #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */ |
| bogdanm | 0:9b334a45a8ff | 65 | #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */ |
| bogdanm | 0:9b334a45a8ff | 66 | #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */ |
| bogdanm | 0:9b334a45a8ff | 67 | #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 68 | #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 69 | #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */ |
| bogdanm | 0:9b334a45a8ff | 70 | #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */ |
| bogdanm | 0:9b334a45a8ff | 71 | #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */ |
| bogdanm | 0:9b334a45a8ff | 72 | #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 73 | #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 74 | #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */ |
| bogdanm | 0:9b334a45a8ff | 75 | #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */ |
| bogdanm | 0:9b334a45a8ff | 76 | #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */ |
| bogdanm | 0:9b334a45a8ff | 77 | #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 78 | #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 79 | #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 80 | #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 81 | #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 82 | #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 83 | |
| bogdanm | 0:9b334a45a8ff | 84 | /* Bit fields for RTC CNT */ |
| bogdanm | 0:9b334a45a8ff | 85 | #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 86 | #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 87 | #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 88 | #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 89 | #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 90 | #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */ |
| bogdanm | 0:9b334a45a8ff | 91 | |
| bogdanm | 0:9b334a45a8ff | 92 | /* Bit fields for RTC COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 93 | #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 94 | #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 95 | #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 96 | #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 99 | |
| bogdanm | 0:9b334a45a8ff | 100 | /* Bit fields for RTC COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 101 | #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 102 | #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 103 | #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 104 | #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 105 | #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 106 | #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | /* Bit fields for RTC IF */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 119 | #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 120 | #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 123 | #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 124 | #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 125 | #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */ |
| bogdanm | 0:9b334a45a8ff | 126 | |
| bogdanm | 0:9b334a45a8ff | 127 | /* Bit fields for RTC IFS */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 136 | #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 139 | #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 140 | #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 142 | #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 143 | #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 144 | #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */ |
| bogdanm | 0:9b334a45a8ff | 145 | |
| bogdanm | 0:9b334a45a8ff | 146 | /* Bit fields for RTC IFC */ |
| bogdanm | 0:9b334a45a8ff | 147 | #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 148 | #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 149 | #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 150 | #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 152 | #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 153 | #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 154 | #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 155 | #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 156 | #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 157 | #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 158 | #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 159 | #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 161 | #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 162 | #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */ |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | /* Bit fields for RTC IEN */ |
| bogdanm | 0:9b334a45a8ff | 166 | #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 167 | #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 168 | #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 170 | #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 174 | #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 177 | #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 178 | #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 179 | #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 180 | #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 182 | #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */ |
| bogdanm | 0:9b334a45a8ff | 183 | |
| bogdanm | 0:9b334a45a8ff | 184 | /* Bit fields for RTC FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 185 | #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 186 | #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 187 | #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */ |
| bogdanm | 0:9b334a45a8ff | 189 | #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 191 | #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */ |
| bogdanm | 0:9b334a45a8ff | 196 | |
| bogdanm | 0:9b334a45a8ff | 197 | /* Bit fields for RTC SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 198 | #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 204 | #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */ |
| bogdanm | 0:9b334a45a8ff | 206 | #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 207 | #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 209 | #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 210 | #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 212 | #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */ |
| bogdanm | 0:9b334a45a8ff | 215 | |
| bogdanm | 0:9b334a45a8ff | 216 | /** @} End of group EFM32WG_RTC */ |
| mbed_official | 50:a417edff4437 | 217 | /** @} End of group Parts */ |
| bogdanm | 0:9b334a45a8ff | 218 |