rik te winkel / mbed-dev

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Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_crg.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 #include "W7500x_crg.h"
bogdanm 0:9b334a45a8ff 2
bogdanm 0:9b334a45a8ff 3 void CRG_DeInit(void)
bogdanm 0:9b334a45a8ff 4 {
bogdanm 0:9b334a45a8ff 5 //To Do
bogdanm 0:9b334a45a8ff 6 }
bogdanm 0:9b334a45a8ff 7
bogdanm 0:9b334a45a8ff 8 void CRG_OSC_PowerDownEnable(FunctionalState NewState)
bogdanm 0:9b334a45a8ff 9 {
bogdanm 0:9b334a45a8ff 10 if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD;
bogdanm 0:9b334a45a8ff 11 else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP;
bogdanm 0:9b334a45a8ff 12 }
bogdanm 0:9b334a45a8ff 13
bogdanm 0:9b334a45a8ff 14 void CRG_PLL_PowerDownEnable(FunctionalState NewState)
bogdanm 0:9b334a45a8ff 15 {
bogdanm 0:9b334a45a8ff 16 if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD;
bogdanm 0:9b334a45a8ff 17 else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP;
bogdanm 0:9b334a45a8ff 18 }
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 void CRG_PLL_OutputEnable(FunctionalState NewState)
bogdanm 0:9b334a45a8ff 21 {
bogdanm 0:9b334a45a8ff 22 if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN;
bogdanm 0:9b334a45a8ff 23 else CRG->PLL_OER = CRG_PLL_OER_DIS;
bogdanm 0:9b334a45a8ff 24 }
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 void CRG_PLL_BypassEnable(FunctionalState NewState)
bogdanm 0:9b334a45a8ff 27 {
bogdanm 0:9b334a45a8ff 28 if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN;
bogdanm 0:9b334a45a8ff 29 else CRG->PLL_BPR = CRG_PLL_BPR_DIS;
bogdanm 0:9b334a45a8ff 30 }
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 33 {
bogdanm 0:9b334a45a8ff 34 assert_param(IS_CRG_PLL_SRC(src));
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
bogdanm 0:9b334a45a8ff 37 else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
bogdanm 0:9b334a45a8ff 38 }
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 41 {
bogdanm 0:9b334a45a8ff 42 assert_param(IS_CRG_FCLK_SRC(src));
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK;
bogdanm 0:9b334a45a8ff 45 else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK;
bogdanm 0:9b334a45a8ff 46 else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;
bogdanm 0:9b334a45a8ff 47 }
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 void CRG_FCLK_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 50 {
bogdanm 0:9b334a45a8ff 51 assert_param(IS_CRG_FCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 54 else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 55 else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 56 else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 57 }
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 60 {
bogdanm 0:9b334a45a8ff 61 assert_param(IS_CRG_SSPCLK_SRC(src));
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;
bogdanm 0:9b334a45a8ff 64 else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK;
bogdanm 0:9b334a45a8ff 65 else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK;
bogdanm 0:9b334a45a8ff 66 else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK;
bogdanm 0:9b334a45a8ff 67 }
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 70 {
bogdanm 0:9b334a45a8ff 71 assert_param(IS_CRG_SSPCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 74 else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 75 else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 76 else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 77 }
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 80 {
bogdanm 0:9b334a45a8ff 81 assert_param(IS_CRG_ADCCLK_SRC(src));
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;
bogdanm 0:9b334a45a8ff 84 else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK;
bogdanm 0:9b334a45a8ff 85 else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK;
bogdanm 0:9b334a45a8ff 86 else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK;
bogdanm 0:9b334a45a8ff 87 }
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 90 {
bogdanm 0:9b334a45a8ff 91 assert_param(IS_CRG_ADCCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 94 else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 95 else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 96 else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 97 }
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 100 {
bogdanm 0:9b334a45a8ff 101 assert_param(IS_CRG_TIMERCLK_NUM(num));
bogdanm 0:9b334a45a8ff 102 assert_param(IS_CRG_TIMERCLK_SRC(src));
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS);
bogdanm 0:9b334a45a8ff 105 else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK);
bogdanm 0:9b334a45a8ff 106 else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK);
bogdanm 0:9b334a45a8ff 107 else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK);
bogdanm 0:9b334a45a8ff 108 }
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 111 {
bogdanm 0:9b334a45a8ff 112 assert_param(IS_CRG_TIMERCLK_NUM(num));
bogdanm 0:9b334a45a8ff 113 assert_param(IS_CRG_TIMERCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1);
bogdanm 0:9b334a45a8ff 116 else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2);
bogdanm 0:9b334a45a8ff 117 else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4);
bogdanm 0:9b334a45a8ff 118 else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8);
bogdanm 0:9b334a45a8ff 119 else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16);
bogdanm 0:9b334a45a8ff 120 else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32);
bogdanm 0:9b334a45a8ff 121 else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64);
bogdanm 0:9b334a45a8ff 122 else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128);
bogdanm 0:9b334a45a8ff 123 }
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 126 {
bogdanm 0:9b334a45a8ff 127 assert_param(IS_CRG_PWMCLK_NUM(num));
bogdanm 0:9b334a45a8ff 128 assert_param(IS_CRG_PWMCLK_SRC(src));
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS);
bogdanm 0:9b334a45a8ff 131 else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK);
bogdanm 0:9b334a45a8ff 132 else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK);
bogdanm 0:9b334a45a8ff 133 else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK);
bogdanm 0:9b334a45a8ff 134 }
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 137 {
bogdanm 0:9b334a45a8ff 138 assert_param(IS_CRG_PWMCLK_NUM(num));
bogdanm 0:9b334a45a8ff 139 assert_param(IS_CRG_PWMCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1);
bogdanm 0:9b334a45a8ff 142 else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2);
bogdanm 0:9b334a45a8ff 143 else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4);
bogdanm 0:9b334a45a8ff 144 else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8);
bogdanm 0:9b334a45a8ff 145 else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16);
bogdanm 0:9b334a45a8ff 146 else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32);
bogdanm 0:9b334a45a8ff 147 else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64);
bogdanm 0:9b334a45a8ff 148 else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128);
bogdanm 0:9b334a45a8ff 149 }
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 152 {
bogdanm 0:9b334a45a8ff 153 assert_param(IS_CRG_RTC_HS_SRC(src));
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS;
bogdanm 0:9b334a45a8ff 156 else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK;
bogdanm 0:9b334a45a8ff 157 else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK;
bogdanm 0:9b334a45a8ff 158 else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK;
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH);
bogdanm 0:9b334a45a8ff 161 }
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 164 {
bogdanm 0:9b334a45a8ff 165 assert_param(IS_CRG_RTC_HS_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167 if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 168 else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 169 else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 170 else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 171 else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16;
bogdanm 0:9b334a45a8ff 172 else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32;
bogdanm 0:9b334a45a8ff 173 else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64;
bogdanm 0:9b334a45a8ff 174 else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128;
bogdanm 0:9b334a45a8ff 175 }
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src)
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 assert_param(IS_CRG_RTC_LOW_SRC(src));
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 if (src == CRG_CLK_LOW)
bogdanm 0:9b334a45a8ff 182 {
bogdanm 0:9b334a45a8ff 183 CRG_RTC_HS_SourceSelect(CRG_CLK_DIS);
bogdanm 0:9b334a45a8ff 184 CRG->RTC_SSR = CRG_RTC_SSR_LW;
bogdanm 0:9b334a45a8ff 185 }
bogdanm 0:9b334a45a8ff 186 else
bogdanm 0:9b334a45a8ff 187 {
bogdanm 0:9b334a45a8ff 188 CRG->RTC_SSR = CRG_RTC_SSR_HS;
bogdanm 0:9b334a45a8ff 189 }
bogdanm 0:9b334a45a8ff 190 }
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 193 {
bogdanm 0:9b334a45a8ff 194 assert_param(IS_CRG_WDOGCLK_HS_SRC(src));
bogdanm 0:9b334a45a8ff 195
bogdanm 0:9b334a45a8ff 196 if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS;
bogdanm 0:9b334a45a8ff 197 else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK;
bogdanm 0:9b334a45a8ff 198 else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK;
bogdanm 0:9b334a45a8ff 199 else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK;
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH);
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 205 {
bogdanm 0:9b334a45a8ff 206 assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 209 else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 210 else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 211 else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 212 else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16;
bogdanm 0:9b334a45a8ff 213 else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32;
bogdanm 0:9b334a45a8ff 214 else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64;
bogdanm 0:9b334a45a8ff 215 else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128;
bogdanm 0:9b334a45a8ff 216 }
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 assert_param(IS_CRG_WDOGCLK_LOW_SRC(src));
bogdanm 0:9b334a45a8ff 221
bogdanm 0:9b334a45a8ff 222 if (src == CRG_CLK_LOW)
bogdanm 0:9b334a45a8ff 223 {
bogdanm 0:9b334a45a8ff 224 CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS);
bogdanm 0:9b334a45a8ff 225 CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW;
bogdanm 0:9b334a45a8ff 226 }
bogdanm 0:9b334a45a8ff 227 else
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS;
bogdanm 0:9b334a45a8ff 230 }
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src)
bogdanm 0:9b334a45a8ff 234 {
bogdanm 0:9b334a45a8ff 235 assert_param(IS_CRG_UARTCLK_SRC(src));
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS;
bogdanm 0:9b334a45a8ff 238 else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;
bogdanm 0:9b334a45a8ff 239 else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK;
bogdanm 0:9b334a45a8ff 240 else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK;
bogdanm 0:9b334a45a8ff 241 }
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv)
bogdanm 0:9b334a45a8ff 244 {
bogdanm 0:9b334a45a8ff 245 assert_param(IS_CRG_UARTCLK_PREDIV(prediv));
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1;
bogdanm 0:9b334a45a8ff 248 else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2;
bogdanm 0:9b334a45a8ff 249 else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4;
bogdanm 0:9b334a45a8ff 250 else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8;
bogdanm 0:9b334a45a8ff 251 }
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk)
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 assert_param(IS_FUNCTIONAL_STATE(rx_clk));
bogdanm 0:9b334a45a8ff 256 assert_param(IS_FUNCTIONAL_STATE(tx_clk));
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK;
bogdanm 0:9b334a45a8ff 259 else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK);
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK;
bogdanm 0:9b334a45a8ff 262 else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK);
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 void CRG_SetMonitoringClock(uint32_t value)
bogdanm 0:9b334a45a8ff 266 {
bogdanm 0:9b334a45a8ff 267 assert_param(IS_CRG_MONCLK_SSR(value));
bogdanm 0:9b334a45a8ff 268
bogdanm 0:9b334a45a8ff 269 CRG->MONCLK_SSR = value;
bogdanm 0:9b334a45a8ff 270 }
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 uint32_t CRG_GetMonitoringClock(void)
bogdanm 0:9b334a45a8ff 273 {
bogdanm 0:9b334a45a8ff 274 return (uint8_t)CRG->MONCLK_SSR;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276