rik te winkel / mbed-dev

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targets/TARGET_Maxim/TARGET_MAX32620/device/gpio_regs.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Maxim/TARGET_MAX32620/gpio_regs.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #ifndef _MXC_GPIO_REGS_H_
<> 144:ef7eb2e8f9f7 35 #define _MXC_GPIO_REGS_H_
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 38 extern "C" {
<> 144:ef7eb2e8f9f7 39 #endif
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #include <stdint.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*
<> 144:ef7eb2e8f9f7 44 If types are not defined elsewhere (CMSIS) define them here
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 #ifndef __IO
<> 144:ef7eb2e8f9f7 47 #define __IO volatile
<> 144:ef7eb2e8f9f7 48 #endif
<> 144:ef7eb2e8f9f7 49 #ifndef __I
<> 144:ef7eb2e8f9f7 50 #define __I volatile const
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52 #ifndef __O
<> 144:ef7eb2e8f9f7 53 #define __O volatile
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*
<> 144:ef7eb2e8f9f7 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 144:ef7eb2e8f9f7 59 access to each register in module.
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Offset Register Description
<> 144:ef7eb2e8f9f7 63 ============= ============================================================================ */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 __IO uint32_t rst_mode[7]; /* 0x0000-0x0018 Port P[0..6] Default (Power-On Reset) Output Drive Mode */
<> 144:ef7eb2e8f9f7 66 __I uint32_t rsv01C[9]; /* 0x001C-0x003C */
<> 144:ef7eb2e8f9f7 67 __IO uint32_t free[7]; /* 0x0040-0x0058 Port P[0..6] Free for GPIO Operation Flags */
<> 144:ef7eb2e8f9f7 68 __I uint32_t rsv05C[9]; /* 0x005C-0x007C */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t out_mode[7]; /* 0x0080-0x0098 Port P[0..6] Output Drive Mode */
<> 144:ef7eb2e8f9f7 70 __I uint32_t rsv09C[9]; /* 0x009C-0x00BC */
<> 144:ef7eb2e8f9f7 71 __IO uint32_t out_val[7]; /* 0x00C0-0x00D8 Port P[0..6] GPIO Output Value */
<> 144:ef7eb2e8f9f7 72 __I uint32_t rsv0DC[9]; /* 0x00DC-0x00FC */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t func_sel[7]; /* 0x0100-0x0118 Port P[0..6] GPIO Function Select */
<> 144:ef7eb2e8f9f7 74 __I uint32_t rsv11C[9]; /* 0x011C-0x013C */
<> 144:ef7eb2e8f9f7 75 __IO uint32_t in_mode[7]; /* 0x0140-0x0158 Port P[0..6] GPIO Input Monitoring Mode */
<> 144:ef7eb2e8f9f7 76 __I uint32_t rsv15C[9]; /* 0x015C-0x017C */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t in_val[7]; /* 0x0180-0x0198 Port P[0..6] GPIO Input Value */
<> 144:ef7eb2e8f9f7 78 __I uint32_t rsv19C[9]; /* 0x019C-0x01BC */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t int_mode[7]; /* 0x01C0-0x01D8 Port P[0..6] Interrupt Detection Mode */
<> 144:ef7eb2e8f9f7 80 __I uint32_t rsv1DC[9]; /* 0x01DC-0x01FC */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t intfl[7]; /* 0x0200-0x0218 Port P[0..6] Interrupt Flags */
<> 144:ef7eb2e8f9f7 82 __I uint32_t rsv21C[9]; /* 0x021C-0x023C */
<> 144:ef7eb2e8f9f7 83 __IO uint32_t inten[7]; /* 0x0240-0x0258 Port P[0..6] Interrupt Enables */
<> 144:ef7eb2e8f9f7 84 } mxc_gpio_regs_t;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /*
<> 144:ef7eb2e8f9f7 88 Register offsets for module GPIO.
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL)
<> 144:ef7eb2e8f9f7 92 #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL)
<> 144:ef7eb2e8f9f7 93 #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL)
<> 144:ef7eb2e8f9f7 94 #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL)
<> 144:ef7eb2e8f9f7 95 #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL)
<> 144:ef7eb2e8f9f7 96 #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL)
<> 144:ef7eb2e8f9f7 97 #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL)
<> 144:ef7eb2e8f9f7 98 #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL)
<> 144:ef7eb2e8f9f7 99 #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL)
<> 144:ef7eb2e8f9f7 100 #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL)
<> 144:ef7eb2e8f9f7 101 #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL)
<> 144:ef7eb2e8f9f7 102 #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL)
<> 144:ef7eb2e8f9f7 103 #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL)
<> 144:ef7eb2e8f9f7 104 #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL)
<> 144:ef7eb2e8f9f7 105 #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL)
<> 144:ef7eb2e8f9f7 106 #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL)
<> 144:ef7eb2e8f9f7 107 #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL)
<> 144:ef7eb2e8f9f7 108 #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL)
<> 144:ef7eb2e8f9f7 109 #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL)
<> 144:ef7eb2e8f9f7 110 #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL)
<> 144:ef7eb2e8f9f7 111 #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL)
<> 144:ef7eb2e8f9f7 112 #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL)
<> 144:ef7eb2e8f9f7 113 #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL)
<> 144:ef7eb2e8f9f7 114 #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL)
<> 144:ef7eb2e8f9f7 115 #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL)
<> 144:ef7eb2e8f9f7 116 #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL)
<> 144:ef7eb2e8f9f7 117 #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL)
<> 144:ef7eb2e8f9f7 118 #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL)
<> 144:ef7eb2e8f9f7 119 #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL)
<> 144:ef7eb2e8f9f7 120 #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL)
<> 144:ef7eb2e8f9f7 121 #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL)
<> 144:ef7eb2e8f9f7 122 #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL)
<> 144:ef7eb2e8f9f7 123 #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL)
<> 144:ef7eb2e8f9f7 124 #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL)
<> 144:ef7eb2e8f9f7 125 #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL)
<> 144:ef7eb2e8f9f7 126 #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL)
<> 144:ef7eb2e8f9f7 127 #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL)
<> 144:ef7eb2e8f9f7 128 #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL)
<> 144:ef7eb2e8f9f7 129 #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL)
<> 144:ef7eb2e8f9f7 130 #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL)
<> 144:ef7eb2e8f9f7 131 #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL)
<> 144:ef7eb2e8f9f7 132 #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL)
<> 144:ef7eb2e8f9f7 133 #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL)
<> 144:ef7eb2e8f9f7 134 #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL)
<> 144:ef7eb2e8f9f7 135 #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL)
<> 144:ef7eb2e8f9f7 136 #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL)
<> 144:ef7eb2e8f9f7 137 #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL)
<> 144:ef7eb2e8f9f7 138 #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL)
<> 144:ef7eb2e8f9f7 139 #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL)
<> 144:ef7eb2e8f9f7 140 #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL)
<> 144:ef7eb2e8f9f7 141 #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL)
<> 144:ef7eb2e8f9f7 142 #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL)
<> 144:ef7eb2e8f9f7 143 #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL)
<> 144:ef7eb2e8f9f7 144 #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL)
<> 144:ef7eb2e8f9f7 145 #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL)
<> 144:ef7eb2e8f9f7 146 #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL)
<> 144:ef7eb2e8f9f7 147 #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL)
<> 144:ef7eb2e8f9f7 148 #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL)
<> 144:ef7eb2e8f9f7 149 #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL)
<> 144:ef7eb2e8f9f7 150 #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL)
<> 144:ef7eb2e8f9f7 151 #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL)
<> 144:ef7eb2e8f9f7 152 #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL)
<> 144:ef7eb2e8f9f7 153 #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL)
<> 144:ef7eb2e8f9f7 154 #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL)
<> 144:ef7eb2e8f9f7 155 #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL)
<> 144:ef7eb2e8f9f7 156 #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL)
<> 144:ef7eb2e8f9f7 157 #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL)
<> 144:ef7eb2e8f9f7 158 #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL)
<> 144:ef7eb2e8f9f7 159 #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL)
<> 144:ef7eb2e8f9f7 160 #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL)
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /*
<> 144:ef7eb2e8f9f7 164 Field positions and masks for module GPIO.
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define MXC_F_GPIO_RST_MODE_PIN0_POS 0
<> 144:ef7eb2e8f9f7 168 #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 169 #define MXC_F_GPIO_RST_MODE_PIN1_POS 4
<> 144:ef7eb2e8f9f7 170 #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 171 #define MXC_F_GPIO_RST_MODE_PIN2_POS 8
<> 144:ef7eb2e8f9f7 172 #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 173 #define MXC_F_GPIO_RST_MODE_PIN3_POS 12
<> 144:ef7eb2e8f9f7 174 #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 175 #define MXC_F_GPIO_RST_MODE_PIN4_POS 16
<> 144:ef7eb2e8f9f7 176 #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 177 #define MXC_F_GPIO_RST_MODE_PIN5_POS 20
<> 144:ef7eb2e8f9f7 178 #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 179 #define MXC_F_GPIO_RST_MODE_PIN6_POS 24
<> 144:ef7eb2e8f9f7 180 #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 181 #define MXC_F_GPIO_RST_MODE_PIN7_POS 28
<> 144:ef7eb2e8f9f7 182 #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #define MXC_F_GPIO_FREE_PIN0_POS 0
<> 144:ef7eb2e8f9f7 185 #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
<> 144:ef7eb2e8f9f7 186 #define MXC_F_GPIO_FREE_PIN1_POS 1
<> 144:ef7eb2e8f9f7 187 #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
<> 144:ef7eb2e8f9f7 188 #define MXC_F_GPIO_FREE_PIN2_POS 2
<> 144:ef7eb2e8f9f7 189 #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
<> 144:ef7eb2e8f9f7 190 #define MXC_F_GPIO_FREE_PIN3_POS 3
<> 144:ef7eb2e8f9f7 191 #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
<> 144:ef7eb2e8f9f7 192 #define MXC_F_GPIO_FREE_PIN4_POS 4
<> 144:ef7eb2e8f9f7 193 #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
<> 144:ef7eb2e8f9f7 194 #define MXC_F_GPIO_FREE_PIN5_POS 5
<> 144:ef7eb2e8f9f7 195 #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
<> 144:ef7eb2e8f9f7 196 #define MXC_F_GPIO_FREE_PIN6_POS 6
<> 144:ef7eb2e8f9f7 197 #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
<> 144:ef7eb2e8f9f7 198 #define MXC_F_GPIO_FREE_PIN7_POS 7
<> 144:ef7eb2e8f9f7 199 #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0
<> 144:ef7eb2e8f9f7 202 #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 203 #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4
<> 144:ef7eb2e8f9f7 204 #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 205 #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8
<> 144:ef7eb2e8f9f7 206 #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 207 #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12
<> 144:ef7eb2e8f9f7 208 #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 209 #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16
<> 144:ef7eb2e8f9f7 210 #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 211 #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20
<> 144:ef7eb2e8f9f7 212 #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 213 #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24
<> 144:ef7eb2e8f9f7 214 #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 215 #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28
<> 144:ef7eb2e8f9f7 216 #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0
<> 144:ef7eb2e8f9f7 219 #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
<> 144:ef7eb2e8f9f7 220 #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1
<> 144:ef7eb2e8f9f7 221 #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
<> 144:ef7eb2e8f9f7 222 #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2
<> 144:ef7eb2e8f9f7 223 #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
<> 144:ef7eb2e8f9f7 224 #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3
<> 144:ef7eb2e8f9f7 225 #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
<> 144:ef7eb2e8f9f7 226 #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4
<> 144:ef7eb2e8f9f7 227 #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
<> 144:ef7eb2e8f9f7 228 #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5
<> 144:ef7eb2e8f9f7 229 #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
<> 144:ef7eb2e8f9f7 230 #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6
<> 144:ef7eb2e8f9f7 231 #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
<> 144:ef7eb2e8f9f7 232 #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7
<> 144:ef7eb2e8f9f7 233 #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #define MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS 0
<> 144:ef7eb2e8f9f7 236 #define MXC_F_GPIO_FUNC_SEL_P0_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN0_POS))
<> 144:ef7eb2e8f9f7 237 #define MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS 4
<> 144:ef7eb2e8f9f7 238 #define MXC_F_GPIO_FUNC_SEL_P0_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN1_POS))
<> 144:ef7eb2e8f9f7 239 #define MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS 8
<> 144:ef7eb2e8f9f7 240 #define MXC_F_GPIO_FUNC_SEL_P0_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN2_POS))
<> 144:ef7eb2e8f9f7 241 #define MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS 12
<> 144:ef7eb2e8f9f7 242 #define MXC_F_GPIO_FUNC_SEL_P0_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN3_POS))
<> 144:ef7eb2e8f9f7 243 #define MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS 16
<> 144:ef7eb2e8f9f7 244 #define MXC_F_GPIO_FUNC_SEL_P0_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN4_POS))
<> 144:ef7eb2e8f9f7 245 #define MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS 20
<> 144:ef7eb2e8f9f7 246 #define MXC_F_GPIO_FUNC_SEL_P0_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN5_POS))
<> 144:ef7eb2e8f9f7 247 #define MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS 24
<> 144:ef7eb2e8f9f7 248 #define MXC_F_GPIO_FUNC_SEL_P0_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN6_POS))
<> 144:ef7eb2e8f9f7 249 #define MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS 28
<> 144:ef7eb2e8f9f7 250 #define MXC_F_GPIO_FUNC_SEL_P0_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P0_PIN7_POS))
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 #define MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS 0
<> 144:ef7eb2e8f9f7 253 #define MXC_F_GPIO_FUNC_SEL_P1_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN0_POS))
<> 144:ef7eb2e8f9f7 254 #define MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS 4
<> 144:ef7eb2e8f9f7 255 #define MXC_F_GPIO_FUNC_SEL_P1_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN1_POS))
<> 144:ef7eb2e8f9f7 256 #define MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS 8
<> 144:ef7eb2e8f9f7 257 #define MXC_F_GPIO_FUNC_SEL_P1_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN2_POS))
<> 144:ef7eb2e8f9f7 258 #define MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS 12
<> 144:ef7eb2e8f9f7 259 #define MXC_F_GPIO_FUNC_SEL_P1_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN3_POS))
<> 144:ef7eb2e8f9f7 260 #define MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS 16
<> 144:ef7eb2e8f9f7 261 #define MXC_F_GPIO_FUNC_SEL_P1_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN4_POS))
<> 144:ef7eb2e8f9f7 262 #define MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS 20
<> 144:ef7eb2e8f9f7 263 #define MXC_F_GPIO_FUNC_SEL_P1_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN5_POS))
<> 144:ef7eb2e8f9f7 264 #define MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS 24
<> 144:ef7eb2e8f9f7 265 #define MXC_F_GPIO_FUNC_SEL_P1_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN6_POS))
<> 144:ef7eb2e8f9f7 266 #define MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS 28
<> 144:ef7eb2e8f9f7 267 #define MXC_F_GPIO_FUNC_SEL_P1_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P1_PIN7_POS))
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 #define MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS 0
<> 144:ef7eb2e8f9f7 270 #define MXC_F_GPIO_FUNC_SEL_P2_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN0_POS))
<> 144:ef7eb2e8f9f7 271 #define MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS 4
<> 144:ef7eb2e8f9f7 272 #define MXC_F_GPIO_FUNC_SEL_P2_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN1_POS))
<> 144:ef7eb2e8f9f7 273 #define MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS 8
<> 144:ef7eb2e8f9f7 274 #define MXC_F_GPIO_FUNC_SEL_P2_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN2_POS))
<> 144:ef7eb2e8f9f7 275 #define MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS 12
<> 144:ef7eb2e8f9f7 276 #define MXC_F_GPIO_FUNC_SEL_P2_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN3_POS))
<> 144:ef7eb2e8f9f7 277 #define MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS 16
<> 144:ef7eb2e8f9f7 278 #define MXC_F_GPIO_FUNC_SEL_P2_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN4_POS))
<> 144:ef7eb2e8f9f7 279 #define MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS 20
<> 144:ef7eb2e8f9f7 280 #define MXC_F_GPIO_FUNC_SEL_P2_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN5_POS))
<> 144:ef7eb2e8f9f7 281 #define MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS 24
<> 144:ef7eb2e8f9f7 282 #define MXC_F_GPIO_FUNC_SEL_P2_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN6_POS))
<> 144:ef7eb2e8f9f7 283 #define MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS 28
<> 144:ef7eb2e8f9f7 284 #define MXC_F_GPIO_FUNC_SEL_P2_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P2_PIN7_POS))
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 #define MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS 0
<> 144:ef7eb2e8f9f7 287 #define MXC_F_GPIO_FUNC_SEL_P3_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN0_POS))
<> 144:ef7eb2e8f9f7 288 #define MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS 4
<> 144:ef7eb2e8f9f7 289 #define MXC_F_GPIO_FUNC_SEL_P3_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN1_POS))
<> 144:ef7eb2e8f9f7 290 #define MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS 8
<> 144:ef7eb2e8f9f7 291 #define MXC_F_GPIO_FUNC_SEL_P3_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN2_POS))
<> 144:ef7eb2e8f9f7 292 #define MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS 12
<> 144:ef7eb2e8f9f7 293 #define MXC_F_GPIO_FUNC_SEL_P3_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN3_POS))
<> 144:ef7eb2e8f9f7 294 #define MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS 16
<> 144:ef7eb2e8f9f7 295 #define MXC_F_GPIO_FUNC_SEL_P3_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN4_POS))
<> 144:ef7eb2e8f9f7 296 #define MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS 20
<> 144:ef7eb2e8f9f7 297 #define MXC_F_GPIO_FUNC_SEL_P3_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN5_POS))
<> 144:ef7eb2e8f9f7 298 #define MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS 24
<> 144:ef7eb2e8f9f7 299 #define MXC_F_GPIO_FUNC_SEL_P3_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN6_POS))
<> 144:ef7eb2e8f9f7 300 #define MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS 28
<> 144:ef7eb2e8f9f7 301 #define MXC_F_GPIO_FUNC_SEL_P3_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P3_PIN7_POS))
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 #define MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS 0
<> 144:ef7eb2e8f9f7 304 #define MXC_F_GPIO_FUNC_SEL_P4_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN0_POS))
<> 144:ef7eb2e8f9f7 305 #define MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS 4
<> 144:ef7eb2e8f9f7 306 #define MXC_F_GPIO_FUNC_SEL_P4_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN1_POS))
<> 144:ef7eb2e8f9f7 307 #define MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS 8
<> 144:ef7eb2e8f9f7 308 #define MXC_F_GPIO_FUNC_SEL_P4_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN2_POS))
<> 144:ef7eb2e8f9f7 309 #define MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS 12
<> 144:ef7eb2e8f9f7 310 #define MXC_F_GPIO_FUNC_SEL_P4_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN3_POS))
<> 144:ef7eb2e8f9f7 311 #define MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS 16
<> 144:ef7eb2e8f9f7 312 #define MXC_F_GPIO_FUNC_SEL_P4_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN4_POS))
<> 144:ef7eb2e8f9f7 313 #define MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS 20
<> 144:ef7eb2e8f9f7 314 #define MXC_F_GPIO_FUNC_SEL_P4_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN5_POS))
<> 144:ef7eb2e8f9f7 315 #define MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS 24
<> 144:ef7eb2e8f9f7 316 #define MXC_F_GPIO_FUNC_SEL_P4_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN6_POS))
<> 144:ef7eb2e8f9f7 317 #define MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS 28
<> 144:ef7eb2e8f9f7 318 #define MXC_F_GPIO_FUNC_SEL_P4_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P4_PIN7_POS))
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #define MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS 0
<> 144:ef7eb2e8f9f7 321 #define MXC_F_GPIO_FUNC_SEL_P5_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN0_POS))
<> 144:ef7eb2e8f9f7 322 #define MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS 4
<> 144:ef7eb2e8f9f7 323 #define MXC_F_GPIO_FUNC_SEL_P5_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN1_POS))
<> 144:ef7eb2e8f9f7 324 #define MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS 8
<> 144:ef7eb2e8f9f7 325 #define MXC_F_GPIO_FUNC_SEL_P5_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN2_POS))
<> 144:ef7eb2e8f9f7 326 #define MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS 12
<> 144:ef7eb2e8f9f7 327 #define MXC_F_GPIO_FUNC_SEL_P5_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN3_POS))
<> 144:ef7eb2e8f9f7 328 #define MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS 16
<> 144:ef7eb2e8f9f7 329 #define MXC_F_GPIO_FUNC_SEL_P5_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN4_POS))
<> 144:ef7eb2e8f9f7 330 #define MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS 20
<> 144:ef7eb2e8f9f7 331 #define MXC_F_GPIO_FUNC_SEL_P5_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN5_POS))
<> 144:ef7eb2e8f9f7 332 #define MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS 24
<> 144:ef7eb2e8f9f7 333 #define MXC_F_GPIO_FUNC_SEL_P5_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN6_POS))
<> 144:ef7eb2e8f9f7 334 #define MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS 28
<> 144:ef7eb2e8f9f7 335 #define MXC_F_GPIO_FUNC_SEL_P5_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P5_PIN7_POS))
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 #define MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS 0
<> 144:ef7eb2e8f9f7 338 #define MXC_F_GPIO_FUNC_SEL_P6_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_P6_PIN0_POS))
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 #define MXC_F_GPIO_IN_MODE_PIN0_POS 0
<> 144:ef7eb2e8f9f7 341 #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 342 #define MXC_F_GPIO_IN_MODE_PIN1_POS 4
<> 144:ef7eb2e8f9f7 343 #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 344 #define MXC_F_GPIO_IN_MODE_PIN2_POS 8
<> 144:ef7eb2e8f9f7 345 #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 346 #define MXC_F_GPIO_IN_MODE_PIN3_POS 12
<> 144:ef7eb2e8f9f7 347 #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 348 #define MXC_F_GPIO_IN_MODE_PIN4_POS 16
<> 144:ef7eb2e8f9f7 349 #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 350 #define MXC_F_GPIO_IN_MODE_PIN5_POS 20
<> 144:ef7eb2e8f9f7 351 #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 352 #define MXC_F_GPIO_IN_MODE_PIN6_POS 24
<> 144:ef7eb2e8f9f7 353 #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 354 #define MXC_F_GPIO_IN_MODE_PIN7_POS 28
<> 144:ef7eb2e8f9f7 355 #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define MXC_F_GPIO_IN_VAL_PIN0_POS 0
<> 144:ef7eb2e8f9f7 358 #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
<> 144:ef7eb2e8f9f7 359 #define MXC_F_GPIO_IN_VAL_PIN1_POS 1
<> 144:ef7eb2e8f9f7 360 #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
<> 144:ef7eb2e8f9f7 361 #define MXC_F_GPIO_IN_VAL_PIN2_POS 2
<> 144:ef7eb2e8f9f7 362 #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
<> 144:ef7eb2e8f9f7 363 #define MXC_F_GPIO_IN_VAL_PIN3_POS 3
<> 144:ef7eb2e8f9f7 364 #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
<> 144:ef7eb2e8f9f7 365 #define MXC_F_GPIO_IN_VAL_PIN4_POS 4
<> 144:ef7eb2e8f9f7 366 #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
<> 144:ef7eb2e8f9f7 367 #define MXC_F_GPIO_IN_VAL_PIN5_POS 5
<> 144:ef7eb2e8f9f7 368 #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
<> 144:ef7eb2e8f9f7 369 #define MXC_F_GPIO_IN_VAL_PIN6_POS 6
<> 144:ef7eb2e8f9f7 370 #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
<> 144:ef7eb2e8f9f7 371 #define MXC_F_GPIO_IN_VAL_PIN7_POS 7
<> 144:ef7eb2e8f9f7 372 #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 #define MXC_F_GPIO_INT_MODE_PIN0_POS 0
<> 144:ef7eb2e8f9f7 375 #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 376 #define MXC_F_GPIO_INT_MODE_PIN1_POS 4
<> 144:ef7eb2e8f9f7 377 #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 378 #define MXC_F_GPIO_INT_MODE_PIN2_POS 8
<> 144:ef7eb2e8f9f7 379 #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 380 #define MXC_F_GPIO_INT_MODE_PIN3_POS 12
<> 144:ef7eb2e8f9f7 381 #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 382 #define MXC_F_GPIO_INT_MODE_PIN4_POS 16
<> 144:ef7eb2e8f9f7 383 #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 384 #define MXC_F_GPIO_INT_MODE_PIN5_POS 20
<> 144:ef7eb2e8f9f7 385 #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 386 #define MXC_F_GPIO_INT_MODE_PIN6_POS 24
<> 144:ef7eb2e8f9f7 387 #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 388 #define MXC_F_GPIO_INT_MODE_PIN7_POS 28
<> 144:ef7eb2e8f9f7 389 #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #define MXC_F_GPIO_INTFL_PIN0_POS 0
<> 144:ef7eb2e8f9f7 392 #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
<> 144:ef7eb2e8f9f7 393 #define MXC_F_GPIO_INTFL_PIN1_POS 1
<> 144:ef7eb2e8f9f7 394 #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
<> 144:ef7eb2e8f9f7 395 #define MXC_F_GPIO_INTFL_PIN2_POS 2
<> 144:ef7eb2e8f9f7 396 #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
<> 144:ef7eb2e8f9f7 397 #define MXC_F_GPIO_INTFL_PIN3_POS 3
<> 144:ef7eb2e8f9f7 398 #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
<> 144:ef7eb2e8f9f7 399 #define MXC_F_GPIO_INTFL_PIN4_POS 4
<> 144:ef7eb2e8f9f7 400 #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
<> 144:ef7eb2e8f9f7 401 #define MXC_F_GPIO_INTFL_PIN5_POS 5
<> 144:ef7eb2e8f9f7 402 #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
<> 144:ef7eb2e8f9f7 403 #define MXC_F_GPIO_INTFL_PIN6_POS 6
<> 144:ef7eb2e8f9f7 404 #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
<> 144:ef7eb2e8f9f7 405 #define MXC_F_GPIO_INTFL_PIN7_POS 7
<> 144:ef7eb2e8f9f7 406 #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define MXC_F_GPIO_INTEN_PIN0_POS 0
<> 144:ef7eb2e8f9f7 409 #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
<> 144:ef7eb2e8f9f7 410 #define MXC_F_GPIO_INTEN_PIN1_POS 1
<> 144:ef7eb2e8f9f7 411 #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
<> 144:ef7eb2e8f9f7 412 #define MXC_F_GPIO_INTEN_PIN2_POS 2
<> 144:ef7eb2e8f9f7 413 #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
<> 144:ef7eb2e8f9f7 414 #define MXC_F_GPIO_INTEN_PIN3_POS 3
<> 144:ef7eb2e8f9f7 415 #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
<> 144:ef7eb2e8f9f7 416 #define MXC_F_GPIO_INTEN_PIN4_POS 4
<> 144:ef7eb2e8f9f7 417 #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
<> 144:ef7eb2e8f9f7 418 #define MXC_F_GPIO_INTEN_PIN5_POS 5
<> 144:ef7eb2e8f9f7 419 #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
<> 144:ef7eb2e8f9f7 420 #define MXC_F_GPIO_INTEN_PIN6_POS 6
<> 144:ef7eb2e8f9f7 421 #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
<> 144:ef7eb2e8f9f7 422 #define MXC_F_GPIO_INTEN_PIN7_POS 7
<> 144:ef7eb2e8f9f7 423 #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /*
<> 144:ef7eb2e8f9f7 428 Field values and shifted values for module GPIO.
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 432 #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 433 #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 434 #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 435 #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 438 #define MXC_V_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 #define MXC_S_GPIO_FREE_PIN0_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE << MXC_F_GPIO_FREE_PIN0_POS))
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 #define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 443 #define MXC_V_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #define MXC_S_GPIO_FREE_PIN1_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE << MXC_F_GPIO_FREE_PIN1_POS))
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 448 #define MXC_V_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define MXC_S_GPIO_FREE_PIN2_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE << MXC_F_GPIO_FREE_PIN2_POS))
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 453 #define MXC_V_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 #define MXC_S_GPIO_FREE_PIN3_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE << MXC_F_GPIO_FREE_PIN3_POS))
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 #define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 458 #define MXC_V_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 #define MXC_S_GPIO_FREE_PIN4_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE << MXC_F_GPIO_FREE_PIN4_POS))
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 #define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 463 #define MXC_V_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 #define MXC_S_GPIO_FREE_PIN5_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE << MXC_F_GPIO_FREE_PIN5_POS))
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 468 #define MXC_V_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #define MXC_S_GPIO_FREE_PIN6_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE << MXC_F_GPIO_FREE_PIN6_POS))
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 #define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 473 #define MXC_V_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 #define MXC_S_GPIO_FREE_PIN7_AVAILABLE ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE << MXC_F_GPIO_FREE_PIN7_POS))
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 478 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 479 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 480 #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 481 #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 482 #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL))
<> 144:ef7eb2e8f9f7 483 #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL))
<> 144:ef7eb2e8f9f7 484 #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL))
<> 144:ef7eb2e8f9f7 485 #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL))
<> 144:ef7eb2e8f9f7 486 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL))
<> 144:ef7eb2e8f9f7 487 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL))
<> 144:ef7eb2e8f9f7 488 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL))
<> 144:ef7eb2e8f9f7 489 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL))
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 492 #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 493 #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 494 #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #define MXC_V_GPIO_IN_MODE_PIN0_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 497 #define MXC_V_GPIO_IN_MODE_PIN0_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 498 #define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 499 #define MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #define MXC_S_GPIO_IN_MODE_PIN0_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN0_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 #define MXC_V_GPIO_IN_MODE_PIN1_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 504 #define MXC_V_GPIO_IN_MODE_PIN1_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 505 #define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 506 #define MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 #define MXC_S_GPIO_IN_MODE_PIN1_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN1_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #define MXC_V_GPIO_IN_MODE_PIN2_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 511 #define MXC_V_GPIO_IN_MODE_PIN2_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 512 #define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 513 #define MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 #define MXC_S_GPIO_IN_MODE_PIN2_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN2_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #define MXC_V_GPIO_IN_MODE_PIN3_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 518 #define MXC_V_GPIO_IN_MODE_PIN3_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 519 #define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 520 #define MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 #define MXC_S_GPIO_IN_MODE_PIN3_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN3_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 #define MXC_V_GPIO_IN_MODE_PIN4_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 525 #define MXC_V_GPIO_IN_MODE_PIN4_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 526 #define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 527 #define MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #define MXC_S_GPIO_IN_MODE_PIN4_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN4_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 #define MXC_V_GPIO_IN_MODE_PIN5_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 532 #define MXC_V_GPIO_IN_MODE_PIN5_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 533 #define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 534 #define MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 #define MXC_S_GPIO_IN_MODE_PIN5_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN5_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 #define MXC_V_GPIO_IN_MODE_PIN6_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 539 #define MXC_V_GPIO_IN_MODE_PIN6_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 540 #define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 541 #define MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 #define MXC_S_GPIO_IN_MODE_PIN6_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN6_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define MXC_V_GPIO_IN_MODE_PIN7_NORMAL ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 546 #define MXC_V_GPIO_IN_MODE_PIN7_INVERTED ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 547 #define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ZERO ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 548 #define MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 #define MXC_S_GPIO_IN_MODE_PIN7_ALWAYS_ONE ((uint32_t)(MXC_V_GPIO_IN_MODE_PIN7_ALWAYS_ONE << MXC_F_GPIO_IN_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 553 #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 554 #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 555 #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 556 #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 557 #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 #define MXC_V_GPIO_INT_MODE_PIN0_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 560 #define MXC_V_GPIO_INT_MODE_PIN0_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 561 #define MXC_V_GPIO_INT_MODE_PIN0_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 562 #define MXC_V_GPIO_INT_MODE_PIN0_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 563 #define MXC_V_GPIO_INT_MODE_PIN0_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 564 #define MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 #define MXC_S_GPIO_INT_MODE_PIN0_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN0_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN0_POS))
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 #define MXC_V_GPIO_INT_MODE_PIN1_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 569 #define MXC_V_GPIO_INT_MODE_PIN1_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 570 #define MXC_V_GPIO_INT_MODE_PIN1_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 571 #define MXC_V_GPIO_INT_MODE_PIN1_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 572 #define MXC_V_GPIO_INT_MODE_PIN1_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 573 #define MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 #define MXC_S_GPIO_INT_MODE_PIN1_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN1_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN1_POS))
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 #define MXC_V_GPIO_INT_MODE_PIN2_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 578 #define MXC_V_GPIO_INT_MODE_PIN2_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 579 #define MXC_V_GPIO_INT_MODE_PIN2_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 580 #define MXC_V_GPIO_INT_MODE_PIN2_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 581 #define MXC_V_GPIO_INT_MODE_PIN2_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 582 #define MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 #define MXC_S_GPIO_INT_MODE_PIN2_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN2_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN2_POS))
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #define MXC_V_GPIO_INT_MODE_PIN3_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 587 #define MXC_V_GPIO_INT_MODE_PIN3_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 588 #define MXC_V_GPIO_INT_MODE_PIN3_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 589 #define MXC_V_GPIO_INT_MODE_PIN3_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 590 #define MXC_V_GPIO_INT_MODE_PIN3_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 591 #define MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 #define MXC_S_GPIO_INT_MODE_PIN3_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN3_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN3_POS))
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 #define MXC_V_GPIO_INT_MODE_PIN4_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 596 #define MXC_V_GPIO_INT_MODE_PIN4_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 597 #define MXC_V_GPIO_INT_MODE_PIN4_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 598 #define MXC_V_GPIO_INT_MODE_PIN4_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 599 #define MXC_V_GPIO_INT_MODE_PIN4_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 600 #define MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #define MXC_S_GPIO_INT_MODE_PIN4_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN4_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN4_POS))
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 #define MXC_V_GPIO_INT_MODE_PIN5_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 605 #define MXC_V_GPIO_INT_MODE_PIN5_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 606 #define MXC_V_GPIO_INT_MODE_PIN5_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 607 #define MXC_V_GPIO_INT_MODE_PIN5_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 608 #define MXC_V_GPIO_INT_MODE_PIN5_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 609 #define MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 #define MXC_S_GPIO_INT_MODE_PIN5_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN5_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN5_POS))
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 #define MXC_V_GPIO_INT_MODE_PIN6_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 614 #define MXC_V_GPIO_INT_MODE_PIN6_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 615 #define MXC_V_GPIO_INT_MODE_PIN6_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 616 #define MXC_V_GPIO_INT_MODE_PIN6_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 617 #define MXC_V_GPIO_INT_MODE_PIN6_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 618 #define MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 #define MXC_S_GPIO_INT_MODE_PIN6_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN6_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN6_POS))
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 #define MXC_V_GPIO_INT_MODE_PIN7_DISABLE ((uint32_t)(0x00000000UL))
<> 144:ef7eb2e8f9f7 623 #define MXC_V_GPIO_INT_MODE_PIN7_FALLING_EDGE ((uint32_t)(0x00000001UL))
<> 144:ef7eb2e8f9f7 624 #define MXC_V_GPIO_INT_MODE_PIN7_RISING_EDGE ((uint32_t)(0x00000002UL))
<> 144:ef7eb2e8f9f7 625 #define MXC_V_GPIO_INT_MODE_PIN7_ANY_EDGE ((uint32_t)(0x00000003UL))
<> 144:ef7eb2e8f9f7 626 #define MXC_V_GPIO_INT_MODE_PIN7_LOW_LVL ((uint32_t)(0x00000004UL))
<> 144:ef7eb2e8f9f7 627 #define MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(0x00000005UL))
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 #define MXC_S_GPIO_INT_MODE_PIN7_HIGH_LVL ((uint32_t)(MXC_V_GPIO_INT_MODE_PIN7_HIGH_LVL << MXC_F_GPIO_INT_MODE_PIN7_POS))
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635 #endif
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 #endif /* _MXC_GPIO_REGS_H_ */
<> 144:ef7eb2e8f9f7 638