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DMA_RAM_DAC
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stm32f30x_tim.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_tim.h 00004 * @author MCD Application Team 00005 * @version V1.1.1 00006 * @date 04-April-2014 00007 * @brief This file contains all the functions prototypes for the TIM firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00013 * 00014 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00015 * You may not use this file except in compliance with the License. 00016 * You may obtain a copy of the License at: 00017 * 00018 * http://www.st.com/software_license_agreement_liberty_v2 00019 * 00020 * Unless required by applicable law or agreed to in writing, software 00021 * distributed under the License is distributed on an "AS IS" BASIS, 00022 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00023 * See the License for the specific language governing permissions and 00024 * limitations under the License. 00025 * 00026 ****************************************************************************** 00027 */ 00028 00029 /* Define to prevent recursive inclusion -------------------------------------*/ 00030 #ifndef __STM32F30x_TIM_H 00031 #define __STM32F30x_TIM_H 00032 00033 #ifdef __cplusplus 00034 extern "C" { 00035 #endif 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f30x.h" 00039 00040 /** @addtogroup stm32f30x_StdPeriph_Driver 00041 * @{ 00042 */ 00043 00044 /** @addtogroup TIM 00045 * @{ 00046 */ 00047 00048 /* Exported types ------------------------------------------------------------*/ 00049 00050 /** 00051 * @brief TIM Time Base Init structure definition 00052 * @note This structure is used with all TIMx except for TIM6 and TIM7. 00053 */ 00054 00055 typedef struct 00056 { 00057 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00058 This parameter can be a number between 0x0000 and 0xFFFF */ 00059 00060 uint16_t TIM_CounterMode; /*!< Specifies the counter mode. 00061 This parameter can be a value of @ref TIM_Counter_Mode */ 00062 00063 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active 00064 Auto-Reload Register at the next update event. 00065 This parameter must be a number between 0x0000 and 0xFFFF. */ 00066 00067 uint16_t TIM_ClockDivision; /*!< Specifies the clock division. 00068 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 00069 00070 uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00071 reaches zero, an update event is generated and counting restarts 00072 from the RCR value (N). 00073 This means in PWM mode that (N+1) corresponds to: 00074 - the number of PWM periods in edge-aligned mode 00075 - the number of half PWM period in center-aligned mode 00076 This parameter must be a number between 0x00 and 0xFF. 00077 @note This parameter is valid only for TIM1 and TIM8. */ 00078 } TIM_TimeBaseInitTypeDef; 00079 00080 /** 00081 * @brief TIM Output Compare Init structure definition 00082 */ 00083 00084 typedef struct 00085 { 00086 uint32_t TIM_OCMode; /*!< Specifies the TIM mode. 00087 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00088 00089 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 00090 This parameter can be a value of @ref TIM_Output_Compare_State */ 00091 00092 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. 00093 This parameter can be a value of @ref TIM_Output_Compare_N_State 00094 @note This parameter is valid only for TIM1 and TIM8. */ 00095 00096 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00097 This parameter can be a number between 0x0000 and 0xFFFF */ 00098 00099 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. 00100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00101 00102 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. 00103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00104 @note This parameter is valid only for TIM1 and TIM8. */ 00105 00106 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00108 @note This parameter is valid only for TIM1 and TIM8. */ 00109 00110 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00112 @note This parameter is valid only for TIM1 and TIM8. */ 00113 } TIM_OCInitTypeDef; 00114 00115 /** 00116 * @brief TIM Input Capture Init structure definition 00117 */ 00118 00119 typedef struct 00120 { 00121 00122 uint16_t TIM_Channel; /*!< Specifies the TIM channel. 00123 This parameter can be a value of @ref TIM_Channel */ 00124 00125 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. 00126 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00127 00128 uint16_t TIM_ICSelection; /*!< Specifies the input. 00129 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00130 00131 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00132 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00133 00134 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. 00135 This parameter can be a number between 0x0 and 0xF */ 00136 } TIM_ICInitTypeDef; 00137 00138 /** 00139 * @brief BDTR structure definition 00140 * @note This structure is used only with TIM1 and TIM8. 00141 */ 00142 00143 typedef struct 00144 { 00145 00146 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00147 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 00148 00149 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. 00150 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 00151 00152 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. 00153 This parameter can be a value of @ref TIM_Lock_level */ 00154 00155 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the 00156 switching-on of the outputs. 00157 This parameter can be a number between 0x00 and 0xFF */ 00158 00159 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. 00160 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 00161 00162 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00163 This parameter can be a value of @ref TIM_Break_Polarity */ 00164 00165 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00166 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 00167 } TIM_BDTRInitTypeDef; 00168 00169 /* Exported constants --------------------------------------------------------*/ 00170 00171 /** @defgroup TIM_Exported_constants 00172 * @{ 00173 */ 00174 00175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00176 ((PERIPH) == TIM2) || \ 00177 ((PERIPH) == TIM3) || \ 00178 ((PERIPH) == TIM4) || \ 00179 ((PERIPH) == TIM6) || \ 00180 ((PERIPH) == TIM7) || \ 00181 ((PERIPH) == TIM8) || \ 00182 ((PERIPH) == TIM15) || \ 00183 ((PERIPH) == TIM16) || \ 00184 ((PERIPH) == TIM17)) 00185 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */ 00186 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00187 ((PERIPH) == TIM2) || \ 00188 ((PERIPH) == TIM3) || \ 00189 ((PERIPH) == TIM4) || \ 00190 ((PERIPH) == TIM8) || \ 00191 ((PERIPH) == TIM15) || \ 00192 ((PERIPH) == TIM16) || \ 00193 ((PERIPH) == TIM17)) 00194 00195 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */ 00196 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00197 ((PERIPH) == TIM2) || \ 00198 ((PERIPH) == TIM3) || \ 00199 ((PERIPH) == TIM4) || \ 00200 ((PERIPH) == TIM8) || \ 00201 ((PERIPH) == TIM15)) 00202 /* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */ 00203 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00204 ((PERIPH) == TIM2) || \ 00205 ((PERIPH) == TIM3) || \ 00206 ((PERIPH) == TIM4) || \ 00207 ((PERIPH) == TIM8)) 00208 /* LIST4: TIM1 and TIM8 */ 00209 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\ 00210 ((PERIPH) == TIM8)) 00211 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ 00212 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00213 ((PERIPH) == TIM2) || \ 00214 ((PERIPH) == TIM3) || \ 00215 ((PERIPH) == TIM4) || \ 00216 ((PERIPH) == TIM6) || \ 00217 ((PERIPH) == TIM7) || \ 00218 ((PERIPH) == TIM8)) 00219 /* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */ 00220 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00221 ((PERIPH) == TIM8) || \ 00222 ((PERIPH) == TIM15) || \ 00223 ((PERIPH) == TIM16) || \ 00224 ((PERIPH) == TIM17)) 00225 00226 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ 00227 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 00228 ((PERIPH) == TIM2) || \ 00229 ((PERIPH) == TIM3) || \ 00230 ((PERIPH) == TIM4) || \ 00231 ((PERIPH) == TIM6) || \ 00232 ((PERIPH) == TIM7) || \ 00233 ((PERIPH) == TIM8) || \ 00234 ((PERIPH) == TIM15)) 00235 /* LIST8: TIM16 (option register) */ 00236 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \ 00237 ((PERIPH) == TIM1)||\ 00238 ((PERIPH) == TIM8)) 00239 00240 /** @defgroup TIM_Output_Compare_and_PWM_modes 00241 * @{ 00242 */ 00243 00244 #define TIM_OCMode_Timing ((uint32_t)0x00000) 00245 #define TIM_OCMode_Active ((uint32_t)0x00010) 00246 #define TIM_OCMode_Inactive ((uint32_t)0x00020) 00247 #define TIM_OCMode_Toggle ((uint32_t)0x00030) 00248 #define TIM_OCMode_PWM1 ((uint32_t)0x00060) 00249 #define TIM_OCMode_PWM2 ((uint32_t)0x00070) 00250 00251 #define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000) 00252 #define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010) 00253 #define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040) 00254 #define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050) 00255 #define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060) 00256 #define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070) 00257 00258 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 00259 ((MODE) == TIM_OCMode_Active) || \ 00260 ((MODE) == TIM_OCMode_Inactive) || \ 00261 ((MODE) == TIM_OCMode_Toggle)|| \ 00262 ((MODE) == TIM_OCMode_PWM1) || \ 00263 ((MODE) == TIM_OCMode_PWM2) || \ 00264 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ 00265 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ 00266 ((MODE) == TIM_OCMode_Combined_PWM1) || \ 00267 ((MODE) == TIM_OCMode_Combined_PWM2) || \ 00268 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ 00269 ((MODE) == TIM_OCMode_Asymmetric_PWM2)) 00270 00271 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 00272 ((MODE) == TIM_OCMode_Active) || \ 00273 ((MODE) == TIM_OCMode_Inactive) || \ 00274 ((MODE) == TIM_OCMode_Toggle)|| \ 00275 ((MODE) == TIM_OCMode_PWM1) || \ 00276 ((MODE) == TIM_OCMode_PWM2) || \ 00277 ((MODE) == TIM_ForcedAction_Active) || \ 00278 ((MODE) == TIM_ForcedAction_InActive) || \ 00279 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ 00280 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ 00281 ((MODE) == TIM_OCMode_Combined_PWM1) || \ 00282 ((MODE) == TIM_OCMode_Combined_PWM2) || \ 00283 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ 00284 ((MODE) == TIM_OCMode_Asymmetric_PWM2)) 00285 /** 00286 * @} 00287 */ 00288 00289 /** @defgroup TIM_One_Pulse_Mode 00290 * @{ 00291 */ 00292 00293 #define TIM_OPMode_Single ((uint16_t)0x0008) 00294 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 00295 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 00296 ((MODE) == TIM_OPMode_Repetitive)) 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup TIM_Channel 00302 * @{ 00303 */ 00304 00305 #define TIM_Channel_1 ((uint16_t)0x0000) 00306 #define TIM_Channel_2 ((uint16_t)0x0004) 00307 #define TIM_Channel_3 ((uint16_t)0x0008) 00308 #define TIM_Channel_4 ((uint16_t)0x000C) 00309 #define TIM_Channel_5 ((uint16_t)0x0010) 00310 #define TIM_Channel_6 ((uint16_t)0x0014) 00311 00312 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00313 ((CHANNEL) == TIM_Channel_2) || \ 00314 ((CHANNEL) == TIM_Channel_3) || \ 00315 ((CHANNEL) == TIM_Channel_4)) 00316 00317 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00318 ((CHANNEL) == TIM_Channel_2)) 00319 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 00320 ((CHANNEL) == TIM_Channel_2) || \ 00321 ((CHANNEL) == TIM_Channel_3)) 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup TIM_Clock_Division_CKD 00327 * @{ 00328 */ 00329 00330 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 00331 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 00332 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 00333 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 00334 ((DIV) == TIM_CKD_DIV2) || \ 00335 ((DIV) == TIM_CKD_DIV4)) 00336 /** 00337 * @} 00338 */ 00339 00340 /** @defgroup TIM_Counter_Mode 00341 * @{ 00342 */ 00343 00344 #define TIM_CounterMode_Up ((uint16_t)0x0000) 00345 #define TIM_CounterMode_Down ((uint16_t)0x0010) 00346 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 00347 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 00348 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 00349 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 00350 ((MODE) == TIM_CounterMode_Down) || \ 00351 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 00352 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 00353 ((MODE) == TIM_CounterMode_CenterAligned3)) 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup TIM_Output_Compare_Polarity 00359 * @{ 00360 */ 00361 00362 #define TIM_OCPolarity_High ((uint16_t)0x0000) 00363 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 00364 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 00365 ((POLARITY) == TIM_OCPolarity_Low)) 00366 /** 00367 * @} 00368 */ 00369 00370 /** @defgroup TIM_Output_Compare_N_Polarity 00371 * @{ 00372 */ 00373 00374 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 00375 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 00376 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 00377 ((POLARITY) == TIM_OCNPolarity_Low)) 00378 /** 00379 * @} 00380 */ 00381 00382 /** @defgroup TIM_Output_Compare_State 00383 * @{ 00384 */ 00385 00386 #define TIM_OutputState_Disable ((uint16_t)0x0000) 00387 #define TIM_OutputState_Enable ((uint16_t)0x0001) 00388 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 00389 ((STATE) == TIM_OutputState_Enable)) 00390 /** 00391 * @} 00392 */ 00393 00394 /** @defgroup TIM_Output_Compare_N_State 00395 * @{ 00396 */ 00397 00398 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 00399 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 00400 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 00401 ((STATE) == TIM_OutputNState_Enable)) 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup TIM_Capture_Compare_State 00407 * @{ 00408 */ 00409 00410 #define TIM_CCx_Enable ((uint16_t)0x0001) 00411 #define TIM_CCx_Disable ((uint16_t)0x0000) 00412 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 00413 ((CCX) == TIM_CCx_Disable)) 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup TIM_Capture_Compare_N_State 00419 * @{ 00420 */ 00421 00422 #define TIM_CCxN_Enable ((uint16_t)0x0004) 00423 #define TIM_CCxN_Disable ((uint16_t)0x0000) 00424 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 00425 ((CCXN) == TIM_CCxN_Disable)) 00426 /** 00427 * @} 00428 */ 00429 00430 /** @defgroup TIM_Break_Input_enable_disable 00431 * @{ 00432 */ 00433 00434 #define TIM_Break_Enable ((uint16_t)0x1000) 00435 #define TIM_Break_Disable ((uint16_t)0x0000) 00436 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 00437 ((STATE) == TIM_Break_Disable)) 00438 /** 00439 * @} 00440 */ 00441 00442 /** @defgroup TIM_Break1_Input_enable_disable 00443 * @{ 00444 */ 00445 00446 #define TIM_Break1_Enable ((uint32_t)0x00001000) 00447 #define TIM_Break1_Disable ((uint32_t)0x00000000) 00448 #define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \ 00449 ((STATE) == TIM_Break1_Disable)) 00450 /** 00451 * @} 00452 */ 00453 00454 /** @defgroup TIM_Break2_Input_enable_disable 00455 * @{ 00456 */ 00457 00458 #define TIM_Break2_Enable ((uint32_t)0x01000000) 00459 #define TIM_Break2_Disable ((uint32_t)0x00000000) 00460 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \ 00461 ((STATE) == TIM_Break2_Disable)) 00462 /** 00463 * @} 00464 */ 00465 00466 /** @defgroup TIM_Break_Polarity 00467 * @{ 00468 */ 00469 00470 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 00471 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 00472 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 00473 ((POLARITY) == TIM_BreakPolarity_High)) 00474 /** 00475 * @} 00476 */ 00477 00478 /** @defgroup TIM_Break1_Polarity 00479 * @{ 00480 */ 00481 00482 #define TIM_Break1Polarity_Low ((uint32_t)0x00000000) 00483 #define TIM_Break1Polarity_High ((uint32_t)0x00002000) 00484 #define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \ 00485 ((POLARITY) == TIM_Break1Polarity_High)) 00486 /** 00487 * @} 00488 */ 00489 00490 /** @defgroup TIM_Break2_Polarity 00491 * @{ 00492 */ 00493 00494 #define TIM_Break2Polarity_Low ((uint32_t)0x00000000) 00495 #define TIM_Break2Polarity_High ((uint32_t)0x02000000) 00496 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \ 00497 ((POLARITY) == TIM_Break2Polarity_High)) 00498 /** 00499 * @} 00500 */ 00501 00502 /** @defgroup TIM_Break1_Filter 00503 * @{ 00504 */ 00505 00506 #define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF) 00507 /** 00508 * @} 00509 */ 00510 00511 /** @defgroup TIM_Break2_Filter 00512 * @{ 00513 */ 00514 00515 #define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF) 00516 /** 00517 * @} 00518 */ 00519 00520 /** @defgroup TIM_AOE_Bit_Set_Reset 00521 * @{ 00522 */ 00523 00524 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 00525 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 00526 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 00527 ((STATE) == TIM_AutomaticOutput_Disable)) 00528 /** 00529 * @} 00530 */ 00531 00532 /** @defgroup TIM_Lock_level 00533 * @{ 00534 */ 00535 00536 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 00537 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 00538 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 00539 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 00540 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 00541 ((LEVEL) == TIM_LOCKLevel_1) || \ 00542 ((LEVEL) == TIM_LOCKLevel_2) || \ 00543 ((LEVEL) == TIM_LOCKLevel_3)) 00544 /** 00545 * @} 00546 */ 00547 00548 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 00549 * @{ 00550 */ 00551 00552 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 00553 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 00554 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 00555 ((STATE) == TIM_OSSIState_Disable)) 00556 /** 00557 * @} 00558 */ 00559 00560 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 00561 * @{ 00562 */ 00563 00564 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 00565 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 00566 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 00567 ((STATE) == TIM_OSSRState_Disable)) 00568 /** 00569 * @} 00570 */ 00571 00572 /** @defgroup TIM_Output_Compare_Idle_State 00573 * @{ 00574 */ 00575 00576 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 00577 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 00578 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 00579 ((STATE) == TIM_OCIdleState_Reset)) 00580 /** 00581 * @} 00582 */ 00583 00584 /** @defgroup TIM_Output_Compare_N_Idle_State 00585 * @{ 00586 */ 00587 00588 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 00589 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 00590 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 00591 ((STATE) == TIM_OCNIdleState_Reset)) 00592 /** 00593 * @} 00594 */ 00595 00596 /** @defgroup TIM_Input_Capture_Polarity 00597 * @{ 00598 */ 00599 00600 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 00601 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 00602 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 00603 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 00604 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 00605 ((POLARITY) == TIM_ICPolarity_BothEdge)) 00606 /** 00607 * @} 00608 */ 00609 00610 /** @defgroup TIM_Input_Capture_Selection 00611 * @{ 00612 */ 00613 00614 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00615 connected to IC1, IC2, IC3 or IC4, respectively */ 00616 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00617 connected to IC2, IC1, IC4 or IC3, respectively. */ 00618 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 00619 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 00620 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 00621 ((SELECTION) == TIM_ICSelection_TRC)) 00622 /** 00623 * @} 00624 */ 00625 00626 /** @defgroup TIM_Input_Capture_Prescaler 00627 * @{ 00628 */ 00629 00630 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ 00631 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ 00632 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ 00633 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ 00634 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 00635 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 00636 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 00637 ((PRESCALER) == TIM_ICPSC_DIV8)) 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup TIM_interrupt_sources 00643 * @{ 00644 */ 00645 00646 #define TIM_IT_Update ((uint16_t)0x0001) 00647 #define TIM_IT_CC1 ((uint16_t)0x0002) 00648 #define TIM_IT_CC2 ((uint16_t)0x0004) 00649 #define TIM_IT_CC3 ((uint16_t)0x0008) 00650 #define TIM_IT_CC4 ((uint16_t)0x0010) 00651 #define TIM_IT_COM ((uint16_t)0x0020) 00652 #define TIM_IT_Trigger ((uint16_t)0x0040) 00653 #define TIM_IT_Break ((uint16_t)0x0080) 00654 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 00655 00656 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 00657 ((IT) == TIM_IT_CC1) || \ 00658 ((IT) == TIM_IT_CC2) || \ 00659 ((IT) == TIM_IT_CC3) || \ 00660 ((IT) == TIM_IT_CC4) || \ 00661 ((IT) == TIM_IT_COM) || \ 00662 ((IT) == TIM_IT_Trigger) || \ 00663 ((IT) == TIM_IT_Break)) 00664 /** 00665 * @} 00666 */ 00667 00668 /** @defgroup TIM_DMA_Base_address 00669 * @{ 00670 */ 00671 00672 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 00673 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 00674 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 00675 #define TIM_DMABase_DIER ((uint16_t)0x0003) 00676 #define TIM_DMABase_SR ((uint16_t)0x0004) 00677 #define TIM_DMABase_EGR ((uint16_t)0x0005) 00678 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 00679 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 00680 #define TIM_DMABase_CCER ((uint16_t)0x0008) 00681 #define TIM_DMABase_CNT ((uint16_t)0x0009) 00682 #define TIM_DMABase_PSC ((uint16_t)0x000A) 00683 #define TIM_DMABase_ARR ((uint16_t)0x000B) 00684 #define TIM_DMABase_RCR ((uint16_t)0x000C) 00685 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 00686 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 00687 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 00688 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 00689 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 00690 #define TIM_DMABase_DCR ((uint16_t)0x0012) 00691 #define TIM_DMABase_OR ((uint16_t)0x0013) 00692 #define TIM_DMABase_CCMR3 ((uint16_t)0x0014) 00693 #define TIM_DMABase_CCR5 ((uint16_t)0x0015) 00694 #define TIM_DMABase_CCR6 ((uint16_t)0x0016) 00695 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 00696 ((BASE) == TIM_DMABase_CR2) || \ 00697 ((BASE) == TIM_DMABase_SMCR) || \ 00698 ((BASE) == TIM_DMABase_DIER) || \ 00699 ((BASE) == TIM_DMABase_SR) || \ 00700 ((BASE) == TIM_DMABase_EGR) || \ 00701 ((BASE) == TIM_DMABase_CCMR1) || \ 00702 ((BASE) == TIM_DMABase_CCMR2) || \ 00703 ((BASE) == TIM_DMABase_CCER) || \ 00704 ((BASE) == TIM_DMABase_CNT) || \ 00705 ((BASE) == TIM_DMABase_PSC) || \ 00706 ((BASE) == TIM_DMABase_ARR) || \ 00707 ((BASE) == TIM_DMABase_RCR) || \ 00708 ((BASE) == TIM_DMABase_CCR1) || \ 00709 ((BASE) == TIM_DMABase_CCR2) || \ 00710 ((BASE) == TIM_DMABase_CCR3) || \ 00711 ((BASE) == TIM_DMABase_CCR4) || \ 00712 ((BASE) == TIM_DMABase_BDTR) || \ 00713 ((BASE) == TIM_DMABase_DCR) || \ 00714 ((BASE) == TIM_DMABase_OR) || \ 00715 ((BASE) == TIM_DMABase_CCMR3) || \ 00716 ((BASE) == TIM_DMABase_CCR5) || \ 00717 ((BASE) == TIM_DMABase_CCR6)) 00718 /** 00719 * @} 00720 */ 00721 00722 /** @defgroup TIM_DMA_Burst_Length 00723 * @{ 00724 */ 00725 00726 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 00727 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 00728 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 00729 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 00730 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 00731 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 00732 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 00733 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 00734 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 00735 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 00736 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 00737 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 00738 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 00739 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 00740 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 00741 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 00742 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 00743 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 00744 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ 00745 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ 00746 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ 00747 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ 00748 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ 00749 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ 00750 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ 00751 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ 00752 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ 00753 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ 00754 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 00755 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ 00756 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ 00757 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ 00758 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ 00759 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ 00760 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 00761 ((LENGTH) == TIM_DMABurstLength_18Transfers)) 00762 /** 00763 * @} 00764 */ 00765 00766 /** @defgroup TIM_DMA_sources 00767 * @{ 00768 */ 00769 00770 #define TIM_DMA_Update ((uint16_t)0x0100) 00771 #define TIM_DMA_CC1 ((uint16_t)0x0200) 00772 #define TIM_DMA_CC2 ((uint16_t)0x0400) 00773 #define TIM_DMA_CC3 ((uint16_t)0x0800) 00774 #define TIM_DMA_CC4 ((uint16_t)0x1000) 00775 #define TIM_DMA_COM ((uint16_t)0x2000) 00776 #define TIM_DMA_Trigger ((uint16_t)0x4000) 00777 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 00778 00779 /** 00780 * @} 00781 */ 00782 00783 /** @defgroup TIM_External_Trigger_Prescaler 00784 * @{ 00785 */ 00786 00787 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 00788 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 00789 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 00790 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 00791 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 00792 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 00793 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 00794 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 00795 /** 00796 * @} 00797 */ 00798 00799 /** @defgroup TIM_Internal_Trigger_Selection 00800 * @{ 00801 */ 00802 00803 #define TIM_TS_ITR0 ((uint16_t)0x0000) 00804 #define TIM_TS_ITR1 ((uint16_t)0x0010) 00805 #define TIM_TS_ITR2 ((uint16_t)0x0020) 00806 #define TIM_TS_ITR3 ((uint16_t)0x0030) 00807 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 00808 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 00809 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 00810 #define TIM_TS_ETRF ((uint16_t)0x0070) 00811 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 00812 ((SELECTION) == TIM_TS_ITR1) || \ 00813 ((SELECTION) == TIM_TS_ITR2) || \ 00814 ((SELECTION) == TIM_TS_ITR3) || \ 00815 ((SELECTION) == TIM_TS_TI1F_ED) || \ 00816 ((SELECTION) == TIM_TS_TI1FP1) || \ 00817 ((SELECTION) == TIM_TS_TI2FP2) || \ 00818 ((SELECTION) == TIM_TS_ETRF)) 00819 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 00820 ((SELECTION) == TIM_TS_ITR1) || \ 00821 ((SELECTION) == TIM_TS_ITR2) || \ 00822 ((SELECTION) == TIM_TS_ITR3)) 00823 /** 00824 * @} 00825 */ 00826 00827 /** @defgroup TIM_TIx_External_Clock_Source 00828 * @{ 00829 */ 00830 00831 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 00832 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 00833 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 00834 00835 /** 00836 * @} 00837 */ 00838 00839 /** @defgroup TIM_External_Trigger_Polarity 00840 * @{ 00841 */ 00842 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 00843 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 00844 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 00845 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 00846 /** 00847 * @} 00848 */ 00849 00850 /** @defgroup TIM_Prescaler_Reload_Mode 00851 * @{ 00852 */ 00853 00854 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 00855 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 00856 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 00857 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 00858 /** 00859 * @} 00860 */ 00861 00862 /** @defgroup TIM_Forced_Action 00863 * @{ 00864 */ 00865 00866 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 00867 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 00868 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 00869 ((ACTION) == TIM_ForcedAction_InActive)) 00870 /** 00871 * @} 00872 */ 00873 00874 /** @defgroup TIM_Encoder_Mode 00875 * @{ 00876 */ 00877 00878 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 00879 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 00880 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 00881 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 00882 ((MODE) == TIM_EncoderMode_TI2) || \ 00883 ((MODE) == TIM_EncoderMode_TI12)) 00884 /** 00885 * @} 00886 */ 00887 00888 00889 /** @defgroup TIM_Event_Source 00890 * @{ 00891 */ 00892 00893 #define TIM_EventSource_Update ((uint16_t)0x0001) 00894 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 00895 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 00896 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 00897 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 00898 #define TIM_EventSource_COM ((uint16_t)0x0020) 00899 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 00900 #define TIM_EventSource_Break ((uint16_t)0x0080) 00901 #define TIM_EventSource_Break2 ((uint16_t)0x0100) 00902 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000)) 00903 00904 /** 00905 * @} 00906 */ 00907 00908 /** @defgroup TIM_Update_Source 00909 * @{ 00910 */ 00911 00912 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow 00913 or the setting of UG bit, or an update generation 00914 through the slave mode controller. */ 00915 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ 00916 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 00917 ((SOURCE) == TIM_UpdateSource_Regular)) 00918 /** 00919 * @} 00920 */ 00921 00922 /** @defgroup TIM_Output_Compare_Preload_State 00923 * @{ 00924 */ 00925 00926 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 00927 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 00928 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 00929 ((STATE) == TIM_OCPreload_Disable)) 00930 /** 00931 * @} 00932 */ 00933 00934 /** @defgroup TIM_Output_Compare_Fast_State 00935 * @{ 00936 */ 00937 00938 #define TIM_OCFast_Enable ((uint16_t)0x0004) 00939 #define TIM_OCFast_Disable ((uint16_t)0x0000) 00940 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 00941 ((STATE) == TIM_OCFast_Disable)) 00942 00943 /** 00944 * @} 00945 */ 00946 00947 /** @defgroup TIM_Output_Compare_Clear_State 00948 * @{ 00949 */ 00950 00951 #define TIM_OCClear_Enable ((uint16_t)0x0080) 00952 #define TIM_OCClear_Disable ((uint16_t)0x0000) 00953 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 00954 ((STATE) == TIM_OCClear_Disable)) 00955 /** 00956 * @} 00957 */ 00958 00959 /** @defgroup TIM_Trigger_Output_Source 00960 * @{ 00961 */ 00962 00963 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 00964 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 00965 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 00966 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 00967 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 00968 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 00969 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 00970 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 00971 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 00972 ((SOURCE) == TIM_TRGOSource_Enable) || \ 00973 ((SOURCE) == TIM_TRGOSource_Update) || \ 00974 ((SOURCE) == TIM_TRGOSource_OC1) || \ 00975 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 00976 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 00977 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 00978 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 00979 00980 00981 #define TIM_TRGO2Source_Reset ((uint32_t)0x00000000) 00982 #define TIM_TRGO2Source_Enable ((uint32_t)0x00100000) 00983 #define TIM_TRGO2Source_Update ((uint32_t)0x00200000) 00984 #define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000) 00985 #define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000) 00986 #define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000) 00987 #define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000) 00988 #define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000) 00989 #define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000) 00990 #define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000) 00991 #define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000) 00992 #define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000) 00993 #define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000) 00994 #define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000) 00995 #define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000) 00996 #define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000) 00997 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \ 00998 ((SOURCE) == TIM_TRGO2Source_Enable) || \ 00999 ((SOURCE) == TIM_TRGO2Source_Update) || \ 01000 ((SOURCE) == TIM_TRGO2Source_OC1) || \ 01001 ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \ 01002 ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \ 01003 ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \ 01004 ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \ 01005 ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \ 01006 ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \ 01007 ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \ 01008 ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \ 01009 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \ 01010 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \ 01011 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \ 01012 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling)) 01013 /** 01014 * @} 01015 */ 01016 01017 /** @defgroup TIM_Slave_Mode 01018 * @{ 01019 */ 01020 01021 #define TIM_SlaveMode_Reset ((uint32_t)0x00004) 01022 #define TIM_SlaveMode_Gated ((uint32_t)0x00005) 01023 #define TIM_SlaveMode_Trigger ((uint32_t)0x00006) 01024 #define TIM_SlaveMode_External1 ((uint32_t)0x00007) 01025 #define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000) 01026 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 01027 ((MODE) == TIM_SlaveMode_Gated) || \ 01028 ((MODE) == TIM_SlaveMode_Trigger) || \ 01029 ((MODE) == TIM_SlaveMode_External1) || \ 01030 ((MODE) == TIM_SlaveMode_Combined_ResetTrigger)) 01031 /** 01032 * @} 01033 */ 01034 01035 /** @defgroup TIM_Master_Slave_Mode 01036 * @{ 01037 */ 01038 01039 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 01040 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 01041 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 01042 ((STATE) == TIM_MasterSlaveMode_Disable)) 01043 /** 01044 * @} 01045 */ 01046 /** @defgroup TIM_Remap 01047 * @{ 01048 */ 01049 #define TIM16_GPIO ((uint16_t)0x0000) 01050 #define TIM16_RTC_CLK ((uint16_t)0x0001) 01051 #define TIM16_HSEDiv32 ((uint16_t)0x0002) 01052 #define TIM16_MCO ((uint16_t)0x0003) 01053 01054 #define TIM1_ADC1_AWDG1 ((uint16_t)0x0001) 01055 #define TIM1_ADC1_AWDG2 ((uint16_t)0x0002) 01056 #define TIM1_ADC1_AWDG3 ((uint16_t)0x0003) 01057 #define TIM1_ADC4_AWDG1 ((uint16_t)0x0004) 01058 #define TIM1_ADC4_AWDG2 ((uint16_t)0x0008) 01059 #define TIM1_ADC4_AWDG3 ((uint16_t)0x000C) 01060 01061 #define TIM8_ADC2_AWDG1 ((uint16_t)0x0001) 01062 #define TIM8_ADC2_AWDG2 ((uint16_t)0x0002) 01063 #define TIM8_ADC2_AWDG3 ((uint16_t)0x0003) 01064 #define TIM8_ADC3_AWDG1 ((uint16_t)0x0004) 01065 #define TIM8_ADC3_AWDG2 ((uint16_t)0x0008) 01066 #define TIM8_ADC3_AWDG3 ((uint16_t)0x000C) 01067 01068 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \ 01069 ((TIM_REMAP) == TIM16_RTC_CLK) || \ 01070 ((TIM_REMAP) == TIM16_HSEDiv32) || \ 01071 ((TIM_REMAP) == TIM16_MCO) ||\ 01072 ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\ 01073 ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\ 01074 ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\ 01075 ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\ 01076 ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\ 01077 ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\ 01078 ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\ 01079 ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\ 01080 ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\ 01081 ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\ 01082 ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\ 01083 ((TIM_REMAP) == TIM8_ADC3_AWDG3)) 01084 01085 /** 01086 * @} 01087 */ 01088 /** @defgroup TIM_Flags 01089 * @{ 01090 */ 01091 01092 #define TIM_FLAG_Update ((uint32_t)0x00001) 01093 #define TIM_FLAG_CC1 ((uint32_t)0x00002) 01094 #define TIM_FLAG_CC2 ((uint32_t)0x00004) 01095 #define TIM_FLAG_CC3 ((uint32_t)0x00008) 01096 #define TIM_FLAG_CC4 ((uint32_t)0x00010) 01097 #define TIM_FLAG_COM ((uint32_t)0x00020) 01098 #define TIM_FLAG_Trigger ((uint32_t)0x00040) 01099 #define TIM_FLAG_Break ((uint32_t)0x00080) 01100 #define TIM_FLAG_Break2 ((uint32_t)0x00100) 01101 #define TIM_FLAG_CC1OF ((uint32_t)0x00200) 01102 #define TIM_FLAG_CC2OF ((uint32_t)0x00400) 01103 #define TIM_FLAG_CC3OF ((uint32_t)0x00800) 01104 #define TIM_FLAG_CC4OF ((uint32_t)0x01000) 01105 #define TIM_FLAG_CC5 ((uint32_t)0x10000) 01106 #define TIM_FLAG_CC6 ((uint32_t)0x20000) 01107 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 01108 ((FLAG) == TIM_FLAG_CC1) || \ 01109 ((FLAG) == TIM_FLAG_CC2) || \ 01110 ((FLAG) == TIM_FLAG_CC3) || \ 01111 ((FLAG) == TIM_FLAG_CC4) || \ 01112 ((FLAG) == TIM_FLAG_COM) || \ 01113 ((FLAG) == TIM_FLAG_Trigger) || \ 01114 ((FLAG) == TIM_FLAG_Break) || \ 01115 ((FLAG) == TIM_FLAG_Break2) || \ 01116 ((FLAG) == TIM_FLAG_CC1OF) || \ 01117 ((FLAG) == TIM_FLAG_CC2OF) || \ 01118 ((FLAG) == TIM_FLAG_CC3OF) || \ 01119 ((FLAG) == TIM_FLAG_CC4OF) ||\ 01120 ((FLAG) == TIM_FLAG_CC5) ||\ 01121 ((FLAG) == TIM_FLAG_CC6)) 01122 01123 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000)) 01124 /** 01125 * @} 01126 */ 01127 01128 /** @defgroup TIM_OCReferenceClear 01129 * @{ 01130 */ 01131 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) 01132 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) 01133 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ 01134 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 01135 01136 /** @defgroup TIM_Input_Capture_Filer_Value 01137 * @{ 01138 */ 01139 01140 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 01141 /** 01142 * @} 01143 */ 01144 01145 /** @defgroup TIM_External_Trigger_Filter 01146 * @{ 01147 */ 01148 01149 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 01150 /** 01151 * @} 01152 */ 01153 01154 /** @defgroup TIM_Legacy 01155 * @{ 01156 */ 01157 01158 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 01159 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 01160 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 01161 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 01162 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 01163 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 01164 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 01165 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 01166 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 01167 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 01168 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 01169 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 01170 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 01171 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 01172 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 01173 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 01174 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 01175 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 01176 /** 01177 * @} 01178 */ 01179 01180 /** 01181 * @} 01182 */ 01183 01184 /* Exported macro ------------------------------------------------------------*/ 01185 /* Exported functions --------------------------------------------------------*/ 01186 01187 /* TimeBase management ********************************************************/ 01188 void TIM_DeInit(TIM_TypeDef* TIMx); 01189 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 01190 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 01191 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 01192 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 01193 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); 01194 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); 01195 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); 01196 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 01197 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 01198 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 01199 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState); 01200 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 01201 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 01202 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 01203 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 01204 01205 /* Output Compare management **************************************************/ 01206 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01207 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01208 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01209 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01210 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01211 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 01212 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState); 01213 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState); 01214 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState); 01215 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 01216 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode); 01217 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); 01218 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); 01219 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); 01220 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); 01221 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5); 01222 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6); 01223 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01224 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01225 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01226 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01227 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01228 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 01229 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01230 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01231 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01232 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01233 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01234 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 01235 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01236 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01237 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01238 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 01239 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01240 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01241 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01242 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01243 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01244 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 01245 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); 01246 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01247 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01248 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01249 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01250 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01251 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 01252 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01253 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01254 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 01255 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 01256 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 01257 01258 /* Input Capture management ***************************************************/ 01259 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 01260 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 01261 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 01262 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); 01263 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); 01264 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); 01265 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); 01266 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01267 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01268 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01269 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 01270 01271 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/ 01272 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 01273 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter); 01274 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter); 01275 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 01276 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 01277 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 01278 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 01279 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 01280 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 01281 01282 /* Interrupts, DMA and flags management ***************************************/ 01283 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 01284 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 01285 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG); 01286 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 01287 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 01288 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 01289 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 01290 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 01291 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 01292 01293 /* Clocks management **********************************************************/ 01294 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 01295 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 01296 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 01297 uint16_t TIM_ICPolarity, uint16_t ICFilter); 01298 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01299 uint16_t ExtTRGFilter); 01300 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 01301 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 01302 01303 /* Synchronization management *************************************************/ 01304 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 01305 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 01306 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source); 01307 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); 01308 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 01309 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01310 uint16_t ExtTRGFilter); 01311 01312 /* Specific interface management **********************************************/ 01313 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 01314 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 01315 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 01316 01317 /* Specific remapping management **********************************************/ 01318 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); 01319 01320 #ifdef __cplusplus 01321 } 01322 #endif 01323 01324 #endif /*__STM32F30x_TIM_H */ 01325 01326 /** 01327 * @} 01328 */ 01329 01330 /** 01331 * @} 01332 */ 01333 01334 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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