Richard Vasquez
/
DMA_RAM_DAC
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
stm32f30x_tim.c
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_tim.c 00004 * @author MCD Application Team 00005 * @version V1.1.1 00006 * @date 04-April-2014 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the TIM peripheral: 00009 * + TimeBase management 00010 * + Output Compare management 00011 * + Input Capture management 00012 * + Advanced-control timers (TIM1 and TIM8) specific features 00013 * + Interrupts, DMA and flags management 00014 * + Clocks management 00015 * + Synchronization management 00016 * + Specific interface management 00017 * + Specific remapping management 00018 * 00019 @verbatim 00020 00021 ============================================================================== 00022 ##### How to use this driver ##### 00023 ============================================================================== 00024 [..] This driver provides functions to configure and program the TIM 00025 of all stm32f30x devices. 00026 These functions are split in 9 groups: 00027 00028 (#) TIM TimeBase management: this group includes all needed functions 00029 to configure the TM Timebase unit: 00030 (++) Set/Get Prescaler 00031 (++) Set/Get Autoreload 00032 (++) Counter modes configuration 00033 (++) Set Clock division 00034 (++) Select the One Pulse mode 00035 (++) Update Request Configuration 00036 (++) Update Disable Configuration 00037 (++) Auto-Preload Configuration 00038 (++) Enable/Disable the counter 00039 00040 (#) TIM Output Compare management: this group includes all needed 00041 functions to configure the Capture/Compare unit used in Output 00042 compare mode: 00043 (++) Configure each channel, independently, in Output Compare mode 00044 (++) Select the output compare modes 00045 (++) Select the Polarities of each channel 00046 (++) Set/Get the Capture/Compare register values 00047 (++) Select the Output Compare Fast mode 00048 (++) Select the Output Compare Forced mode 00049 (++) Output Compare-Preload Configuration 00050 (++) Clear Output Compare Reference 00051 (++) Select the OCREF Clear signal 00052 (++) Enable/Disable the Capture/Compare Channels 00053 00054 (#) TIM Input Capture management: this group includes all needed 00055 functions to configure the Capture/Compare unit used in 00056 Input Capture mode: 00057 (++) Configure each channel in input capture mode 00058 (++) Configure Channel1/2 in PWM Input mode 00059 (++) Set the Input Capture Prescaler 00060 (++) Get the Capture/Compare values 00061 00062 (#) Advanced-control timers (TIM1 and TIM8) specific features 00063 (++) Configures the Break input, dead time, Lock level, the OSSI, 00064 the OSSR State and the AOE(automatic output enable) 00065 (++) Enable/Disable the TIM peripheral Main Outputs 00066 (++) Select the Commutation event 00067 (++) Set/Reset the Capture Compare Preload Control bit 00068 00069 (#) TIM interrupts, DMA and flags management 00070 (++) Enable/Disable interrupt sources 00071 (++) Get flags status 00072 (++) Clear flags/ Pending bits 00073 (++) Enable/Disable DMA requests 00074 (++) Configure DMA burst mode 00075 (++) Select CaptureCompare DMA request 00076 00077 (#) TIM clocks management: this group includes all needed functions 00078 to configure the clock controller unit: 00079 (++) Select internal/External clock 00080 (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx 00081 00082 (#) TIM synchronization management: this group includes all needed 00083 functions to configure the Synchronization unit: 00084 (++) Select Input Trigger 00085 (++) Select Output Trigger 00086 (++) Select Master Slave Mode 00087 (++) ETR Configuration when used as external trigger 00088 00089 (#) TIM specific interface management, this group includes all 00090 needed functions to use the specific TIM interface: 00091 (++) Encoder Interface Configuration 00092 (++) Select Hall Sensor 00093 00094 (#) TIM specific remapping management includes the Remapping 00095 configuration of specific timers 00096 00097 @endverbatim 00098 00099 ****************************************************************************** 00100 * @attention 00101 * 00102 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00103 * 00104 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00105 * You may not use this file except in compliance with the License. 00106 * You may obtain a copy of the License at: 00107 * 00108 * http://www.st.com/software_license_agreement_liberty_v2 00109 * 00110 * Unless required by applicable law or agreed to in writing, software 00111 * distributed under the License is distributed on an "AS IS" BASIS, 00112 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00113 * See the License for the specific language governing permissions and 00114 * limitations under the License. 00115 * 00116 ****************************************************************************** 00117 */ 00118 00119 /* Includes ------------------------------------------------------------------*/ 00120 #include "stm32f30x_tim.h" 00121 #include "stm32f30x_rcc.h" 00122 00123 /** @addtogroup STM32F30x_StdPeriph_Driver 00124 * @{ 00125 */ 00126 00127 /** @defgroup TIM 00128 * @brief TIM driver modules 00129 * @{ 00130 */ 00131 00132 /* Private typedef -----------------------------------------------------------*/ 00133 /* Private define ------------------------------------------------------------*/ 00134 00135 /* ---------------------- TIM registers bit mask ------------------------ */ 00136 #define SMCR_ETR_MASK ((uint16_t)0x00FF) 00137 #define CCMR_OFFSET ((uint16_t)0x0018) 00138 #define CCER_CCE_SET ((uint16_t)0x0001) 00139 #define CCER_CCNE_SET ((uint16_t)0x0004) 00140 #define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F) 00141 #define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF) 00142 00143 /* Private macro -------------------------------------------------------------*/ 00144 /* Private variables ---------------------------------------------------------*/ 00145 /* Private function prototypes -----------------------------------------------*/ 00146 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00147 uint16_t TIM_ICFilter); 00148 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00149 uint16_t TIM_ICFilter); 00150 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00151 uint16_t TIM_ICFilter); 00152 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00153 uint16_t TIM_ICFilter); 00154 00155 /* Private functions ---------------------------------------------------------*/ 00156 00157 /** @defgroup TIM_Private_Functions 00158 * @{ 00159 */ 00160 00161 /** @defgroup TIM_Group1 TimeBase management functions 00162 * @brief TimeBase management functions 00163 * 00164 @verbatim 00165 =============================================================================== 00166 ##### TimeBase management functions ##### 00167 =============================================================================== 00168 00169 00170 *** TIM Driver: how to use it in Timing(Time base) Mode *** 00171 ============================================================ 00172 [..] 00173 To use the Timer in Timing(Time base) mode, the following steps are mandatory: 00174 00175 (#) Enable TIM clock using 00176 RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 00177 (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. 00178 (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure 00179 the Time Base unit 00180 with the corresponding configuration 00181 (#) Enable the NVIC if you need to generate the update interrupt. 00182 (#) Enable the corresponding interrupt using the function 00183 TIM_ITConfig(TIMx, TIM_IT_Update) 00184 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 00185 [..] 00186 (@) All other functions can be used separately to modify, if needed, 00187 a specific feature of the Timer. 00188 00189 @endverbatim 00190 * @{ 00191 */ 00192 00193 /** 00194 * @brief Deinitializes the TIMx peripheral registers to their default reset values. 00195 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00196 * @retval None 00197 00198 */ 00199 void TIM_DeInit(TIM_TypeDef* TIMx) 00200 { 00201 /* Check the parameters */ 00202 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00203 00204 if (TIMx == TIM1) 00205 { 00206 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); 00207 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); 00208 } 00209 else if (TIMx == TIM2) 00210 { 00211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); 00212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); 00213 } 00214 else if (TIMx == TIM3) 00215 { 00216 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); 00217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); 00218 } 00219 else if (TIMx == TIM4) 00220 { 00221 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); 00222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); 00223 } 00224 else if (TIMx == TIM6) 00225 { 00226 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); 00227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); 00228 } 00229 else if (TIMx == TIM7) 00230 { 00231 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); 00232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); 00233 } 00234 else if (TIMx == TIM8) 00235 { 00236 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); 00237 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); 00238 } 00239 else if (TIMx == TIM15) 00240 { 00241 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); 00242 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); 00243 } 00244 else if (TIMx == TIM16) 00245 { 00246 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); 00247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); 00248 } 00249 else 00250 { 00251 if (TIMx == TIM17) 00252 { 00253 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); 00254 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); 00255 } 00256 } 00257 } 00258 00259 /** 00260 * @brief Initializes the TIMx Time Base Unit peripheral according to 00261 * the specified parameters in the TIM_TimeBaseInitStruct. 00262 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00263 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure 00264 * that contains the configuration information for the specified TIM peripheral. 00265 * @retval None 00266 */ 00267 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) 00268 { 00269 uint16_t tmpcr1 = 0; 00270 00271 /* Check the parameters */ 00272 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00273 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); 00274 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); 00275 00276 tmpcr1 = TIMx->CR1; 00277 00278 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || 00279 (TIMx == TIM3)|| (TIMx == TIM4)) 00280 { 00281 /* Select the Counter Mode */ 00282 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); 00283 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 00284 } 00285 00286 if((TIMx != TIM6) && (TIMx != TIM7)) 00287 { 00288 /* Set the clock division */ 00289 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); 00290 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 00291 } 00292 00293 TIMx->CR1 = tmpcr1; 00294 00295 /* Set the Autoreload value */ 00296 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 00297 00298 /* Set the Prescaler value */ 00299 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 00300 00301 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) || 00302 (TIMx == TIM16) || (TIMx == TIM17)) 00303 { 00304 /* Set the Repetition Counter value */ 00305 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 00306 } 00307 00308 /* Generate an update event to reload the Prescaler 00309 and the repetition counter(only for TIM1 and TIM8) value immediatly */ 00310 TIMx->EGR = TIM_PSCReloadMode_Immediate; 00311 } 00312 00313 /** 00314 * @brief Fills each TIM_TimeBaseInitStruct member with its default value. 00315 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef 00316 * structure which will be initialized. 00317 * @retval None 00318 */ 00319 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) 00320 { 00321 /* Set the default configuration */ 00322 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; 00323 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; 00324 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; 00325 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; 00326 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; 00327 } 00328 00329 /** 00330 * @brief Configures the TIMx Prescaler. 00331 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 00332 * @param Prescaler: specifies the Prescaler Register value 00333 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode 00334 * This parameter can be one of the following values: 00335 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. 00336 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. 00337 * @retval None 00338 */ 00339 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) 00340 { 00341 /* Check the parameters */ 00342 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00343 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); 00344 /* Set the Prescaler value */ 00345 TIMx->PSC = Prescaler; 00346 /* Set or reset the UG Bit */ 00347 TIMx->EGR = TIM_PSCReloadMode; 00348 } 00349 00350 /** 00351 * @brief Specifies the TIMx Counter Mode to be used. 00352 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 00353 * @param TIM_CounterMode: specifies the Counter Mode to be used 00354 * This parameter can be one of the following values: 00355 * @arg TIM_CounterMode_Up: TIM Up Counting Mode 00356 * @arg TIM_CounterMode_Down: TIM Down Counting Mode 00357 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 00358 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 00359 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 00360 * @retval None 00361 */ 00362 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) 00363 { 00364 uint16_t tmpcr1 = 0; 00365 00366 /* Check the parameters */ 00367 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00368 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); 00369 00370 tmpcr1 = TIMx->CR1; 00371 00372 /* Reset the CMS and DIR Bits */ 00373 tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); 00374 00375 /* Set the Counter Mode */ 00376 tmpcr1 |= TIM_CounterMode; 00377 00378 /* Write to TIMx CR1 register */ 00379 TIMx->CR1 = tmpcr1; 00380 } 00381 00382 /** 00383 * @brief Sets the TIMx Counter Register value 00384 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00385 * @param Counter: specifies the Counter register new value. 00386 * @retval None 00387 */ 00388 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) 00389 { 00390 /* Check the parameters */ 00391 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00392 00393 /* Set the Counter Register value */ 00394 TIMx->CNT = Counter; 00395 } 00396 00397 /** 00398 * @brief Sets the TIMx Autoreload Register value 00399 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00400 * @param Autoreload: specifies the Autoreload register new value. 00401 * @retval None 00402 */ 00403 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) 00404 { 00405 /* Check the parameters */ 00406 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00407 00408 /* Set the Autoreload Register value */ 00409 TIMx->ARR = Autoreload; 00410 } 00411 00412 /** 00413 * @brief Gets the TIMx Counter value. 00414 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00415 * @retval Counter Register value 00416 */ 00417 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) 00418 { 00419 /* Check the parameters */ 00420 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00421 00422 /* Get the Counter Register value */ 00423 return TIMx->CNT; 00424 } 00425 00426 /** 00427 * @brief Gets the TIMx Prescaler value. 00428 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00429 * @retval Prescaler Register value. 00430 */ 00431 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) 00432 { 00433 /* Check the parameters */ 00434 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00435 00436 /* Get the Prescaler Register value */ 00437 return TIMx->PSC; 00438 } 00439 00440 /** 00441 * @brief Enables or Disables the TIMx Update event. 00442 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00443 * @param NewState: new state of the TIMx UDIS bit 00444 * This parameter can be: ENABLE or DISABLE. 00445 * @retval None 00446 */ 00447 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) 00448 { 00449 /* Check the parameters */ 00450 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00451 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00452 00453 if (NewState != DISABLE) 00454 { 00455 /* Set the Update Disable Bit */ 00456 TIMx->CR1 |= TIM_CR1_UDIS; 00457 } 00458 else 00459 { 00460 /* Reset the Update Disable Bit */ 00461 TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; 00462 } 00463 } 00464 00465 /** 00466 * @brief Configures the TIMx Update Request Interrupt source. 00467 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00468 * @param TIM_UpdateSource: specifies the Update source. 00469 * This parameter can be one of the following values: 00470 * @arg TIM_UpdateSource_Regular: Source of update is the counter 00471 * overflow/underflow or the setting of UG bit, or an update 00472 * generation through the slave mode controller. 00473 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. 00474 * @retval None 00475 */ 00476 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) 00477 { 00478 /* Check the parameters */ 00479 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00480 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); 00481 00482 if (TIM_UpdateSource != TIM_UpdateSource_Global) 00483 { 00484 /* Set the URS Bit */ 00485 TIMx->CR1 |= TIM_CR1_URS; 00486 } 00487 else 00488 { 00489 /* Reset the URS Bit */ 00490 TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; 00491 } 00492 } 00493 00494 /** 00495 * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping. 00496 * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31] 00497 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00498 * @param NewState: new state of the UIFREMAP bit. 00499 * This parameter can be: ENABLE or DISABLE. 00500 * @retval None 00501 */ 00502 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState) 00503 { 00504 /* Check the parameters */ 00505 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00506 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00507 00508 if (NewState != DISABLE) 00509 { 00510 /* Enable the TIM Counter */ 00511 TIMx->CR1 |= TIM_CR1_UIFREMAP; 00512 } 00513 else 00514 { 00515 /* Disable the TIM Counter */ 00516 TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP; 00517 } 00518 } 00519 00520 /** 00521 * @brief Enables or disables TIMx peripheral Preload register on ARR. 00522 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00523 * @param NewState: new state of the TIMx peripheral Preload register 00524 * This parameter can be: ENABLE or DISABLE. 00525 * @retval None 00526 */ 00527 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) 00528 { 00529 /* Check the parameters */ 00530 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00531 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00532 00533 if (NewState != DISABLE) 00534 { 00535 /* Set the ARR Preload Bit */ 00536 TIMx->CR1 |= TIM_CR1_ARPE; 00537 } 00538 else 00539 { 00540 /* Reset the ARR Preload Bit */ 00541 TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; 00542 } 00543 } 00544 00545 /** 00546 * @brief Selects the TIMx's One Pulse Mode. 00547 * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. 00548 * @param TIM_OPMode: specifies the OPM Mode to be used. 00549 * This parameter can be one of the following values: 00550 * @arg TIM_OPMode_Single 00551 * @arg TIM_OPMode_Repetitive 00552 * @retval None 00553 */ 00554 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) 00555 { 00556 /* Check the parameters */ 00557 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00558 assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); 00559 00560 /* Reset the OPM Bit */ 00561 TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; 00562 00563 /* Configure the OPM Mode */ 00564 TIMx->CR1 |= TIM_OPMode; 00565 } 00566 00567 /** 00568 * @brief Sets the TIMx Clock Division value. 00569 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. 00570 * @param TIM_CKD: specifies the clock division value. 00571 * This parameter can be one of the following value: 00572 * @arg TIM_CKD_DIV1: TDTS = Tck_tim 00573 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim 00574 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim 00575 * @retval None 00576 */ 00577 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) 00578 { 00579 /* Check the parameters */ 00580 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 00581 assert_param(IS_TIM_CKD_DIV(TIM_CKD)); 00582 00583 /* Reset the CKD Bits */ 00584 TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); 00585 00586 /* Set the CKD value */ 00587 TIMx->CR1 |= TIM_CKD; 00588 } 00589 00590 /** 00591 * @brief Enables or disables the specified TIM peripheral. 00592 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select 00593 * the TIMx peripheral. 00594 * @param NewState: new state of the TIMx peripheral. 00595 * This parameter can be: ENABLE or DISABLE. 00596 * @retval None 00597 */ 00598 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) 00599 { 00600 /* Check the parameters */ 00601 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00602 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00603 00604 if (NewState != DISABLE) 00605 { 00606 /* Enable the TIM Counter */ 00607 TIMx->CR1 |= TIM_CR1_CEN; 00608 } 00609 else 00610 { 00611 /* Disable the TIM Counter */ 00612 TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; 00613 } 00614 } 00615 /** 00616 * @} 00617 */ 00618 00619 /** @defgroup TIM_Group2 Output Compare management functions 00620 * @brief Output Compare management functions 00621 * 00622 @verbatim 00623 =============================================================================== 00624 ##### Output Compare management functions ##### 00625 =============================================================================== 00626 00627 *** TIM Driver: how to use it in Output Compare Mode *** 00628 ======================================================== 00629 [..] 00630 To use the Timer in Output Compare mode, the following steps are mandatory: 00631 00632 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 00633 00634 (#) Configure the TIM pins by configuring the corresponding GPIO pins 00635 00636 (#) Configure the Time base unit as described in the first part of this driver, 00637 if needed, else the Timer will run with the default configuration: 00638 (++) Autoreload value = 0xFFFF 00639 (++) Prescaler value = 0x0000 00640 (++) Counter mode = Up counting 00641 (++) Clock Division = TIM_CKD_DIV1 00642 (#) Fill the TIM_OCInitStruct with the desired parameters including: 00643 (++) The TIM Output Compare mode: TIM_OCMode 00644 (++) TIM Output State: TIM_OutputState 00645 (++) TIM Pulse value: TIM_Pulse 00646 (++) TIM Output Compare Polarity : TIM_OCPolarity 00647 00648 (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the 00649 corresponding configuration 00650 00651 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 00652 [..] 00653 (@) All other functions can be used separately to modify, if needed, 00654 a specific feature of the Timer. 00655 00656 (@) In case of PWM mode, this function is mandatory: 00657 TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 00658 00659 (@) If the corresponding interrupt or DMA request are needed, the user should: 00660 (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 00661 (#@) Enable the corresponding interrupt (or DMA request) using the function 00662 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 00663 00664 @endverbatim 00665 * @{ 00666 */ 00667 00668 /** 00669 * @brief Initializes the TIMx Channel1 according to the specified parameters in 00670 * the TIM_OCInitStruct. 00671 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. 00672 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 00673 * the configuration information for the specified TIM peripheral. 00674 * @retval None 00675 */ 00676 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00677 { 00678 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00679 00680 /* Check the parameters */ 00681 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 00682 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00683 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00684 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00685 00686 /* Disable the Channel 1: Reset the CC1E Bit */ 00687 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; 00688 00689 /* Get the TIMx CCER register value */ 00690 tmpccer = TIMx->CCER; 00691 /* Get the TIMx CR2 register value */ 00692 tmpcr2 = TIMx->CR2; 00693 00694 /* Get the TIMx CCMR1 register value */ 00695 tmpccmrx = TIMx->CCMR1; 00696 00697 /* Reset the Output Compare Mode Bits */ 00698 tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M; 00699 tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S; 00700 /* Select the Output Compare Mode */ 00701 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00702 00703 /* Reset the Output Polarity level */ 00704 tmpccer &= (uint32_t)~TIM_CCER_CC1P; 00705 /* Set the Output Compare Polarity */ 00706 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; 00707 00708 /* Set the Output State */ 00709 tmpccer |= TIM_OCInitStruct->TIM_OutputState; 00710 00711 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) 00712 { 00713 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00714 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00715 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00716 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00717 00718 /* Reset the Output N Polarity level */ 00719 tmpccer &= (uint32_t)~TIM_CCER_CC1NP; 00720 /* Set the Output N Polarity */ 00721 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; 00722 /* Reset the Output N State */ 00723 tmpccer &= (uint32_t)~TIM_CCER_CC1NE; 00724 00725 /* Set the Output N State */ 00726 tmpccer |= TIM_OCInitStruct->TIM_OutputNState; 00727 /* Reset the Output Compare and Output Compare N IDLE State */ 00728 tmpcr2 &= (uint32_t)~TIM_CR2_OIS1; 00729 tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N; 00730 /* Set the Output Idle state */ 00731 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; 00732 /* Set the Output N Idle state */ 00733 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; 00734 } 00735 /* Write to TIMx CR2 */ 00736 TIMx->CR2 = tmpcr2; 00737 00738 /* Write to TIMx CCMR1 */ 00739 TIMx->CCMR1 = tmpccmrx; 00740 00741 /* Set the Capture Compare Register value */ 00742 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 00743 00744 /* Write to TIMx CCER */ 00745 TIMx->CCER = tmpccer; 00746 } 00747 00748 /** 00749 * @brief Initializes the TIMx Channel2 according to the specified parameters 00750 * in the TIM_OCInitStruct. 00751 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. 00752 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 00753 * the configuration information for the specified TIM peripheral. 00754 * @retval None 00755 */ 00756 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00757 { 00758 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00759 00760 /* Check the parameters */ 00761 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 00762 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00763 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00764 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00765 00766 /* Disable the Channel 2: Reset the CC2E Bit */ 00767 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; 00768 00769 /* Get the TIMx CCER register value */ 00770 tmpccer = TIMx->CCER; 00771 /* Get the TIMx CR2 register value */ 00772 tmpcr2 = TIMx->CR2; 00773 00774 /* Get the TIMx CCMR1 register value */ 00775 tmpccmrx = TIMx->CCMR1; 00776 00777 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00778 tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M; 00779 tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S; 00780 00781 /* Select the Output Compare Mode */ 00782 tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00783 00784 /* Reset the Output Polarity level */ 00785 tmpccer &= (uint32_t)~TIM_CCER_CC2P; 00786 /* Set the Output Compare Polarity */ 00787 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4); 00788 00789 /* Set the Output State */ 00790 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4); 00791 00792 if((TIMx == TIM1) || (TIMx == TIM8)) 00793 { 00794 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00795 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00796 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00797 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00798 00799 /* Reset the Output N Polarity level */ 00800 tmpccer &= (uint32_t)~TIM_CCER_CC2NP; 00801 /* Set the Output N Polarity */ 00802 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4); 00803 /* Reset the Output N State */ 00804 tmpccer &= (uint32_t)~TIM_CCER_CC2NE; 00805 00806 /* Set the Output N State */ 00807 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4); 00808 /* Reset the Output Compare and Output Compare N IDLE State */ 00809 tmpcr2 &= (uint32_t)~TIM_CR2_OIS2; 00810 tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N; 00811 /* Set the Output Idle state */ 00812 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2); 00813 /* Set the Output N Idle state */ 00814 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2); 00815 } 00816 /* Write to TIMx CR2 */ 00817 TIMx->CR2 = tmpcr2; 00818 00819 /* Write to TIMx CCMR1 */ 00820 TIMx->CCMR1 = tmpccmrx; 00821 00822 /* Set the Capture Compare Register value */ 00823 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; 00824 00825 /* Write to TIMx CCER */ 00826 TIMx->CCER = tmpccer; 00827 } 00828 00829 /** 00830 * @brief Initializes the TIMx Channel3 according to the specified parameters 00831 * in the TIM_OCInitStruct. 00832 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 00833 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 00834 * the configuration information for the specified TIM peripheral. 00835 * @retval None 00836 */ 00837 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00838 { 00839 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00840 00841 /* Check the parameters */ 00842 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00843 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00844 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00845 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00846 00847 /* Disable the Channel 3: Reset the CC2E Bit */ 00848 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; 00849 00850 /* Get the TIMx CCER register value */ 00851 tmpccer = TIMx->CCER; 00852 /* Get the TIMx CR2 register value */ 00853 tmpcr2 = TIMx->CR2; 00854 00855 /* Get the TIMx CCMR2 register value */ 00856 tmpccmrx = TIMx->CCMR2; 00857 00858 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00859 tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M; 00860 tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S; 00861 /* Select the Output Compare Mode */ 00862 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00863 00864 /* Reset the Output Polarity level */ 00865 tmpccer &= (uint32_t)~TIM_CCER_CC3P; 00866 /* Set the Output Compare Polarity */ 00867 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8); 00868 00869 /* Set the Output State */ 00870 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8); 00871 00872 if((TIMx == TIM1) || (TIMx == TIM8)) 00873 { 00874 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00875 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00876 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00877 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00878 00879 /* Reset the Output N Polarity level */ 00880 tmpccer &= (uint32_t)~TIM_CCER_CC3NP; 00881 /* Set the Output N Polarity */ 00882 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8); 00883 /* Reset the Output N State */ 00884 tmpccer &= (uint32_t)~TIM_CCER_CC3NE; 00885 00886 /* Set the Output N State */ 00887 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8); 00888 /* Reset the Output Compare and Output Compare N IDLE State */ 00889 tmpcr2 &= (uint32_t)~TIM_CR2_OIS3; 00890 tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N; 00891 /* Set the Output Idle state */ 00892 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4); 00893 /* Set the Output N Idle state */ 00894 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4); 00895 } 00896 /* Write to TIMx CR2 */ 00897 TIMx->CR2 = tmpcr2; 00898 00899 /* Write to TIMx CCMR2 */ 00900 TIMx->CCMR2 = tmpccmrx; 00901 00902 /* Set the Capture Compare Register value */ 00903 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; 00904 00905 /* Write to TIMx CCER */ 00906 TIMx->CCER = tmpccer; 00907 } 00908 00909 /** 00910 * @brief Initializes the TIMx Channel4 according to the specified parameters 00911 * in the TIM_OCInitStruct. 00912 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 00913 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 00914 * the configuration information for the specified TIM peripheral. 00915 * @retval None 00916 */ 00917 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00918 { 00919 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00920 00921 /* Check the parameters */ 00922 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00923 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00924 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00925 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00926 00927 /* Disable the Channel 4: Reset the CC4E Bit */ 00928 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; 00929 00930 /* Get the TIMx CCER register value */ 00931 tmpccer = TIMx->CCER; 00932 /* Get the TIMx CR2 register value */ 00933 tmpcr2 = TIMx->CR2; 00934 00935 /* Get the TIMx CCMR2 register value */ 00936 tmpccmrx = TIMx->CCMR2; 00937 00938 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00939 tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M; 00940 tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S; 00941 00942 /* Select the Output Compare Mode */ 00943 tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00944 00945 /* Reset the Output Polarity level */ 00946 tmpccer &= (uint32_t)~TIM_CCER_CC4P; 00947 /* Set the Output Compare Polarity */ 00948 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12); 00949 00950 /* Set the Output State */ 00951 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12); 00952 00953 if((TIMx == TIM1) || (TIMx == TIM8)) 00954 { 00955 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00956 /* Reset the Output Compare IDLE State */ 00957 tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4; 00958 /* Set the Output Idle state */ 00959 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6); 00960 } 00961 /* Write to TIMx CR2 */ 00962 TIMx->CR2 = tmpcr2; 00963 00964 /* Write to TIMx CCMR2 */ 00965 TIMx->CCMR2 = tmpccmrx; 00966 00967 /* Set the Capture Compare Register value */ 00968 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; 00969 00970 /* Write to TIMx CCER */ 00971 TIMx->CCER = tmpccer; 00972 } 00973 00974 /** 00975 * @brief Initializes the TIMx Channel5 according to the specified parameters 00976 * in the TIM_OCInitStruct. 00977 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 00978 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 00979 * the configuration information for the specified TIM peripheral. 00980 * @retval None 00981 */ 00982 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00983 { 00984 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00985 00986 /* Check the parameters */ 00987 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 00988 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00989 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00990 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00991 00992 /* Disable the Channel 5: Reset the CC5E Bit */ 00993 TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/ 00994 00995 /* Get the TIMx CCER register value */ 00996 tmpccer = TIMx->CCER; 00997 /* Get the TIMx CR2 register value */ 00998 tmpcr2 = TIMx->CR2; 00999 01000 /* Get the TIMx CCMR3 register value */ 01001 tmpccmrx = TIMx->CCMR3; 01002 01003 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 01004 tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M; 01005 01006 /* Select the Output Compare Mode */ 01007 tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode); 01008 01009 /* Reset the Output Polarity level */ 01010 tmpccer &= (uint32_t)~TIM_CCER_CC5P; 01011 /* Set the Output Compare Polarity */ 01012 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16); 01013 01014 /* Set the Output State */ 01015 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16); 01016 01017 if((TIMx == TIM1) || (TIMx == TIM8)) 01018 { 01019 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 01020 /* Reset the Output Compare IDLE State */ 01021 tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5; 01022 /* Set the Output Idle state */ 01023 tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16); 01024 } 01025 /* Write to TIMx CR2 */ 01026 TIMx->CR2 = tmpcr2; 01027 01028 /* Write to TIMx CCMR2 */ 01029 TIMx->CCMR3 = tmpccmrx; 01030 01031 /* Set the Capture Compare Register value */ 01032 TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse; 01033 01034 /* Write to TIMx CCER */ 01035 TIMx->CCER = tmpccer; 01036 } 01037 01038 /** 01039 * @brief Initializes the TIMx Channel6 according to the specified parameters 01040 * in the TIM_OCInitStruct. 01041 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01042 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains 01043 * the configuration information for the specified TIM peripheral. 01044 * @retval None 01045 */ 01046 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 01047 { 01048 uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 01049 01050 /* Check the parameters */ 01051 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01052 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 01053 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 01054 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 01055 01056 /* Disable the Channel 5: Reset the CC5E Bit */ 01057 TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/ 01058 01059 /* Get the TIMx CCER register value */ 01060 tmpccer = TIMx->CCER; 01061 /* Get the TIMx CR2 register value */ 01062 tmpcr2 = TIMx->CR2; 01063 01064 /* Get the TIMx CCMR3 register value */ 01065 tmpccmrx = TIMx->CCMR3; 01066 01067 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 01068 tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M; 01069 01070 /* Select the Output Compare Mode */ 01071 tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); 01072 01073 /* Reset the Output Polarity level */ 01074 tmpccer &= (uint32_t)~TIM_CCER_CC6P; 01075 /* Set the Output Compare Polarity */ 01076 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20); 01077 01078 /* Set the Output State */ 01079 tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20); 01080 01081 if((TIMx == TIM1) || (TIMx == TIM8)) 01082 { 01083 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 01084 /* Reset the Output Compare IDLE State */ 01085 tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6; 01086 /* Set the Output Idle state */ 01087 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18); 01088 } 01089 /* Write to TIMx CR2 */ 01090 TIMx->CR2 = tmpcr2; 01091 01092 /* Write to TIMx CCMR2 */ 01093 TIMx->CCMR3 = tmpccmrx; 01094 01095 /* Set the Capture Compare Register value */ 01096 TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse; 01097 01098 /* Write to TIMx CCER */ 01099 TIMx->CCER = tmpccer; 01100 } 01101 01102 /** 01103 * @brief Selects the TIM Group Channel 5 and Channel 1, 01104 OC1REFC is the logical AND of OC1REFC and OC5REF. 01105 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 01106 * @param NewState: new state of the Commutation event. 01107 * This parameter can be: ENABLE or DISABLE. 01108 * @retval None 01109 */ 01110 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState) 01111 { 01112 /* Check the parameters */ 01113 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01114 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01115 01116 if (NewState != DISABLE) 01117 { 01118 /* Set the GC5C1 Bit */ 01119 TIMx->CCR5 |= TIM_CCR5_GC5C1; 01120 } 01121 else 01122 { 01123 /* Reset the GC5C1 Bit */ 01124 TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1; 01125 } 01126 } 01127 01128 /** 01129 * @brief Selects the TIM Group Channel 5 and Channel 2, 01130 OC2REFC is the logical AND of OC2REFC and OC5REF. 01131 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 01132 * @param NewState: new state of the Commutation event. 01133 * This parameter can be: ENABLE or DISABLE. 01134 * @retval None 01135 */ 01136 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState) 01137 { 01138 /* Check the parameters */ 01139 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01140 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01141 01142 if (NewState != DISABLE) 01143 { 01144 /* Set the GC5C2 Bit */ 01145 TIMx->CCR5 |= TIM_CCR5_GC5C2; 01146 } 01147 else 01148 { 01149 /* Reset the GC5C2 Bit */ 01150 TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2; 01151 } 01152 } 01153 01154 01155 /** 01156 * @brief Selects the TIM Group Channel 5 and Channel 3, 01157 OC3REFC is the logical AND of OC3REFC and OC5REF. 01158 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 01159 * @param NewState: new state of the Commutation event. 01160 * This parameter can be: ENABLE or DISABLE. 01161 * @retval None 01162 */ 01163 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState) 01164 { 01165 /* Check the parameters */ 01166 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01167 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01168 01169 if (NewState != DISABLE) 01170 { 01171 /* Set the GC5C3 Bit */ 01172 TIMx->CCR5 |= TIM_CCR5_GC5C3; 01173 } 01174 else 01175 { 01176 /* Reset the GC5C3 Bit */ 01177 TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3; 01178 } 01179 } 01180 01181 /** 01182 * @brief Fills each TIM_OCInitStruct member with its default value. 01183 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will 01184 * be initialized. 01185 * @retval None 01186 */ 01187 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) 01188 { 01189 /* Set the default configuration */ 01190 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; 01191 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; 01192 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; 01193 TIM_OCInitStruct->TIM_Pulse = 0x00000000; 01194 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; 01195 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; 01196 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; 01197 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; 01198 } 01199 01200 /** 01201 * @brief Selects the TIM Output Compare Mode. 01202 * @note This function disables the selected channel before changing the Output 01203 * Compare Mode. If needed, user has to enable this channel using 01204 * TIM_CCxCmd() and TIM_CCxNCmd() functions. 01205 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01206 * @param TIM_Channel: specifies the TIM Channel 01207 * This parameter can be one of the following values: 01208 * @arg TIM_Channel_1: TIM Channel 1 01209 * @arg TIM_Channel_2: TIM Channel 2 01210 * @arg TIM_Channel_3: TIM Channel 3 01211 * @arg TIM_Channel_4: TIM Channel 4 01212 * @param TIM_OCMode: specifies the TIM Output Compare Mode. 01213 * This parameter can be one of the following values: 01214 * @arg TIM_OCMode_Timing 01215 * @arg TIM_OCMode_Active 01216 * @arg TIM_OCMode_Toggle 01217 * @arg TIM_OCMode_PWM1 01218 * @arg TIM_OCMode_PWM2 01219 * @arg TIM_ForcedAction_Active 01220 * @arg TIM_ForcedAction_InActive 01221 * @arg TIM_OCMode_Retrigerrable_OPM1 01222 * @arg TIM_OCMode_Retrigerrable_OPM2 01223 * @arg TIM_OCMode_Combined_PWM1 01224 * @arg TIM_OCMode_Combined_PWM2 01225 * @arg TIM_OCMode_Asymmetric_PWM1 01226 * @arg TIM_OCMode_Asymmetric_PWM2 01227 * @retval None 01228 */ 01229 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode) 01230 { 01231 uint32_t tmp = 0; 01232 uint16_t tmp1 = 0; 01233 01234 /* Check the parameters */ 01235 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01236 assert_param(IS_TIM_CHANNEL(TIM_Channel)); 01237 assert_param(IS_TIM_OCM(TIM_OCMode)); 01238 01239 tmp = (uint32_t) TIMx; 01240 tmp += CCMR_OFFSET; 01241 01242 tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; 01243 01244 /* Disable the Channel: Reset the CCxE Bit */ 01245 TIMx->CCER &= (uint16_t) ~tmp1; 01246 01247 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) 01248 { 01249 tmp += (TIM_Channel>>1); 01250 01251 /* Reset the OCxM bits in the CCMRx register */ 01252 *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; 01253 01254 /* Configure the OCxM bits in the CCMRx register */ 01255 *(__IO uint32_t *) tmp |= TIM_OCMode; 01256 } 01257 else 01258 { 01259 tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1; 01260 01261 /* Reset the OCxM bits in the CCMRx register */ 01262 *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; 01263 01264 /* Configure the OCxM bits in the CCMRx register */ 01265 *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8); 01266 } 01267 } 01268 01269 /** 01270 * @brief Sets the TIMx Capture Compare1 Register value 01271 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01272 * @param Compare1: specifies the Capture Compare1 register new value. 01273 * @retval None 01274 */ 01275 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) 01276 { 01277 /* Check the parameters */ 01278 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01279 01280 /* Set the Capture Compare1 Register value */ 01281 TIMx->CCR1 = Compare1; 01282 } 01283 01284 /** 01285 * @brief Sets the TIMx Capture Compare2 Register value 01286 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 01287 * peripheral. 01288 * @param Compare2: specifies the Capture Compare2 register new value. 01289 * @retval None 01290 */ 01291 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) 01292 { 01293 /* Check the parameters */ 01294 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01295 01296 /* Set the Capture Compare2 Register value */ 01297 TIMx->CCR2 = Compare2; 01298 } 01299 01300 /** 01301 * @brief Sets the TIMx Capture Compare3 Register value 01302 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01303 * @param Compare3: specifies the Capture Compare3 register new value. 01304 * @retval None 01305 */ 01306 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) 01307 { 01308 /* Check the parameters */ 01309 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01310 01311 /* Set the Capture Compare3 Register value */ 01312 TIMx->CCR3 = Compare3; 01313 } 01314 01315 /** 01316 * @brief Sets the TIMx Capture Compare4 Register value 01317 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01318 * @param Compare4: specifies the Capture Compare4 register new value. 01319 * @retval None 01320 */ 01321 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) 01322 { 01323 /* Check the parameters */ 01324 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01325 01326 /* Set the Capture Compare4 Register value */ 01327 TIMx->CCR4 = Compare4; 01328 } 01329 01330 /** 01331 * @brief Sets the TIMx Capture Compare5 Register value 01332 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01333 * @param Compare5: specifies the Capture Compare5 register new value. 01334 * @retval None 01335 */ 01336 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5) 01337 { 01338 /* Check the parameters */ 01339 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01340 01341 /* Set the Capture Compare5 Register value */ 01342 TIMx->CCR5 = Compare5; 01343 } 01344 01345 /** 01346 * @brief Sets the TIMx Capture Compare6 Register value 01347 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01348 * @param Compare6: specifies the Capture Compare5 register new value. 01349 * @retval None 01350 */ 01351 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6) 01352 { 01353 /* Check the parameters */ 01354 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01355 01356 /* Set the Capture Compare6 Register value */ 01357 TIMx->CCR6 = Compare6; 01358 } 01359 01360 /** 01361 * @brief Forces the TIMx output 1 waveform to active or inactive level. 01362 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01363 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01364 * This parameter can be one of the following values: 01365 * @arg TIM_ForcedAction_Active: Force active level on OC1REF 01366 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. 01367 * @retval None 01368 */ 01369 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01370 { 01371 uint32_t tmpccmr1 = 0; 01372 01373 /* Check the parameters */ 01374 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01375 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01376 tmpccmr1 = TIMx->CCMR1; 01377 01378 /* Reset the OC1M Bits */ 01379 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M; 01380 01381 /* Configure The Forced output Mode */ 01382 tmpccmr1 |= TIM_ForcedAction; 01383 01384 /* Write to TIMx CCMR1 register */ 01385 TIMx->CCMR1 = tmpccmr1; 01386 } 01387 01388 /** 01389 * @brief Forces the TIMx output 2 waveform to active or inactive level. 01390 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 01391 * peripheral. 01392 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01393 * This parameter can be one of the following values: 01394 * @arg TIM_ForcedAction_Active: Force active level on OC2REF 01395 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. 01396 * @retval None 01397 */ 01398 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01399 { 01400 uint32_t tmpccmr1 = 0; 01401 01402 /* Check the parameters */ 01403 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01404 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01405 tmpccmr1 = TIMx->CCMR1; 01406 01407 /* Reset the OC2M Bits */ 01408 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M; 01409 01410 /* Configure The Forced output Mode */ 01411 tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8); 01412 01413 /* Write to TIMx CCMR1 register */ 01414 TIMx->CCMR1 = tmpccmr1; 01415 } 01416 01417 /** 01418 * @brief Forces the TIMx output 3 waveform to active or inactive level. 01419 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01420 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01421 * This parameter can be one of the following values: 01422 * @arg TIM_ForcedAction_Active: Force active level on OC3REF 01423 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. 01424 * @retval None 01425 */ 01426 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01427 { 01428 uint32_t tmpccmr2 = 0; 01429 01430 /* Check the parameters */ 01431 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01432 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01433 01434 tmpccmr2 = TIMx->CCMR2; 01435 01436 /* Reset the OC1M Bits */ 01437 tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M; 01438 01439 /* Configure The Forced output Mode */ 01440 tmpccmr2 |= TIM_ForcedAction; 01441 01442 /* Write to TIMx CCMR2 register */ 01443 TIMx->CCMR2 = tmpccmr2; 01444 } 01445 01446 /** 01447 * @brief Forces the TIMx output 4 waveform to active or inactive level. 01448 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01449 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01450 * This parameter can be one of the following values: 01451 * @arg TIM_ForcedAction_Active: Force active level on OC4REF 01452 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. 01453 * @retval None 01454 */ 01455 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01456 { 01457 uint32_t tmpccmr2 = 0; 01458 01459 /* Check the parameters */ 01460 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01461 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01462 tmpccmr2 = TIMx->CCMR2; 01463 01464 /* Reset the OC2M Bits */ 01465 tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M; 01466 01467 /* Configure The Forced output Mode */ 01468 tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8); 01469 01470 /* Write to TIMx CCMR2 register */ 01471 TIMx->CCMR2 = tmpccmr2; 01472 } 01473 01474 /** 01475 * @brief Forces the TIMx output 5 waveform to active or inactive level. 01476 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01477 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01478 * This parameter can be one of the following values: 01479 * @arg TIM_ForcedAction_Active: Force active level on OC5REF 01480 * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. 01481 * @retval None 01482 */ 01483 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01484 { 01485 uint32_t tmpccmr3 = 0; 01486 01487 /* Check the parameters */ 01488 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01489 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01490 tmpccmr3 = TIMx->CCMR3; 01491 01492 /* Reset the OC5M Bits */ 01493 tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M; 01494 01495 /* Configure The Forced output Mode */ 01496 tmpccmr3 |= (uint32_t)(TIM_ForcedAction); 01497 01498 /* Write to TIMx CCMR3 register */ 01499 TIMx->CCMR3 = tmpccmr3; 01500 } 01501 01502 /** 01503 * @brief Forces the TIMx output 6 waveform to active or inactive level. 01504 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01505 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01506 * This parameter can be one of the following values: 01507 * @arg TIM_ForcedAction_Active: Force active level on OC5REF 01508 * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. 01509 * @retval None 01510 */ 01511 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01512 { 01513 uint32_t tmpccmr3 = 0; 01514 01515 /* Check the parameters */ 01516 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01517 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01518 tmpccmr3 = TIMx->CCMR3; 01519 01520 /* Reset the OC6M Bits */ 01521 tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M; 01522 01523 /* Configure The Forced output Mode */ 01524 tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8); 01525 01526 /* Write to TIMx CCMR3 register */ 01527 TIMx->CCMR3 = tmpccmr3; 01528 } 01529 01530 /** 01531 * @brief Enables or disables the TIMx peripheral Preload register on CCR1. 01532 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01533 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01534 * This parameter can be one of the following values: 01535 * @arg TIM_OCPreload_Enable 01536 * @arg TIM_OCPreload_Disable 01537 * @retval None 01538 */ 01539 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01540 { 01541 uint32_t tmpccmr1 = 0; 01542 01543 /* Check the parameters */ 01544 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01545 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01546 01547 tmpccmr1 = TIMx->CCMR1; 01548 01549 /* Reset the OC1PE Bit */ 01550 tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE); 01551 01552 /* Enable or Disable the Output Compare Preload feature */ 01553 tmpccmr1 |= TIM_OCPreload; 01554 01555 /* Write to TIMx CCMR1 register */ 01556 TIMx->CCMR1 = tmpccmr1; 01557 } 01558 01559 /** 01560 * @brief Enables or disables the TIMx peripheral Preload register on CCR2. 01561 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 01562 * peripheral. 01563 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01564 * This parameter can be one of the following values: 01565 * @arg TIM_OCPreload_Enable 01566 * @arg TIM_OCPreload_Disable 01567 * @retval None 01568 */ 01569 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01570 { 01571 uint32_t tmpccmr1 = 0; 01572 01573 /* Check the parameters */ 01574 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01575 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01576 01577 tmpccmr1 = TIMx->CCMR1; 01578 01579 /* Reset the OC2PE Bit */ 01580 tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE); 01581 01582 /* Enable or Disable the Output Compare Preload feature */ 01583 tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8); 01584 01585 /* Write to TIMx CCMR1 register */ 01586 TIMx->CCMR1 = tmpccmr1; 01587 } 01588 01589 /** 01590 * @brief Enables or disables the TIMx peripheral Preload register on CCR3. 01591 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01592 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01593 * This parameter can be one of the following values: 01594 * @arg TIM_OCPreload_Enable 01595 * @arg TIM_OCPreload_Disable 01596 * @retval None 01597 */ 01598 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01599 { 01600 uint32_t tmpccmr2 = 0; 01601 01602 /* Check the parameters */ 01603 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01604 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01605 01606 tmpccmr2 = TIMx->CCMR2; 01607 01608 /* Reset the OC3PE Bit */ 01609 tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE); 01610 01611 /* Enable or Disable the Output Compare Preload feature */ 01612 tmpccmr2 |= TIM_OCPreload; 01613 01614 /* Write to TIMx CCMR2 register */ 01615 TIMx->CCMR2 = tmpccmr2; 01616 } 01617 01618 /** 01619 * @brief Enables or disables the TIMx peripheral Preload register on CCR4. 01620 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01621 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01622 * This parameter can be one of the following values: 01623 * @arg TIM_OCPreload_Enable 01624 * @arg TIM_OCPreload_Disable 01625 * @retval None 01626 */ 01627 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01628 { 01629 uint32_t tmpccmr2 = 0; 01630 01631 /* Check the parameters */ 01632 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01633 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01634 01635 tmpccmr2 = TIMx->CCMR2; 01636 01637 /* Reset the OC4PE Bit */ 01638 tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE); 01639 01640 /* Enable or Disable the Output Compare Preload feature */ 01641 tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8); 01642 01643 /* Write to TIMx CCMR2 register */ 01644 TIMx->CCMR2 = tmpccmr2; 01645 } 01646 01647 /** 01648 * @brief Enables or disables the TIMx peripheral Preload register on CCR5. 01649 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01650 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01651 * This parameter can be one of the following values: 01652 * @arg TIM_OCPreload_Enable 01653 * @arg TIM_OCPreload_Disable 01654 * @retval None 01655 */ 01656 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01657 { 01658 uint32_t tmpccmr3 = 0; 01659 01660 /* Check the parameters */ 01661 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01662 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01663 01664 tmpccmr3 = TIMx->CCMR3; 01665 01666 /* Reset the OC5PE Bit */ 01667 tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE); 01668 01669 /* Enable or Disable the Output Compare Preload feature */ 01670 tmpccmr3 |= (uint32_t)(TIM_OCPreload); 01671 01672 /* Write to TIMx CCMR3 register */ 01673 TIMx->CCMR3 = tmpccmr3; 01674 } 01675 01676 /** 01677 * @brief Enables or disables the TIMx peripheral Preload register on CCR6. 01678 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01679 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01680 * This parameter can be one of the following values: 01681 * @arg TIM_OCPreload_Enable 01682 * @arg TIM_OCPreload_Disable 01683 * @retval None 01684 */ 01685 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01686 { 01687 uint32_t tmpccmr3 = 0; 01688 01689 /* Check the parameters */ 01690 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01691 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01692 01693 tmpccmr3 = TIMx->CCMR3; 01694 01695 /* Reset the OC5PE Bit */ 01696 tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE); 01697 01698 /* Enable or Disable the Output Compare Preload feature */ 01699 tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8); 01700 01701 /* Write to TIMx CCMR3 register */ 01702 TIMx->CCMR3 = tmpccmr3; 01703 } 01704 01705 /** 01706 * @brief Configures the TIMx Output Compare 1 Fast feature. 01707 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01708 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01709 * This parameter can be one of the following values: 01710 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01711 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01712 * @retval None 01713 */ 01714 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01715 { 01716 uint32_t tmpccmr1 = 0; 01717 01718 /* Check the parameters */ 01719 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01720 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01721 01722 /* Get the TIMx CCMR1 register value */ 01723 tmpccmr1 = TIMx->CCMR1; 01724 01725 /* Reset the OC1FE Bit */ 01726 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE; 01727 01728 /* Enable or Disable the Output Compare Fast Bit */ 01729 tmpccmr1 |= TIM_OCFast; 01730 01731 /* Write to TIMx CCMR1 */ 01732 TIMx->CCMR1 = tmpccmr1; 01733 } 01734 01735 /** 01736 * @brief Configures the TIMx Output Compare 2 Fast feature. 01737 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 01738 * peripheral. 01739 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01740 * This parameter can be one of the following values: 01741 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01742 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01743 * @retval None 01744 */ 01745 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01746 { 01747 uint32_t tmpccmr1 = 0; 01748 01749 /* Check the parameters */ 01750 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01751 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01752 01753 /* Get the TIMx CCMR1 register value */ 01754 tmpccmr1 = TIMx->CCMR1; 01755 01756 /* Reset the OC2FE Bit */ 01757 tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE); 01758 01759 /* Enable or Disable the Output Compare Fast Bit */ 01760 tmpccmr1 |= ((uint32_t)TIM_OCFast << 8); 01761 01762 /* Write to TIMx CCMR1 */ 01763 TIMx->CCMR1 = tmpccmr1; 01764 } 01765 01766 /** 01767 * @brief Configures the TIMx Output Compare 3 Fast feature. 01768 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01769 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01770 * This parameter can be one of the following values: 01771 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01772 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01773 * @retval None 01774 */ 01775 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01776 { 01777 uint32_t tmpccmr2 = 0; 01778 01779 /* Check the parameters */ 01780 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01781 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01782 01783 /* Get the TIMx CCMR2 register value */ 01784 tmpccmr2 = TIMx->CCMR2; 01785 01786 /* Reset the OC3FE Bit */ 01787 tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE; 01788 01789 /* Enable or Disable the Output Compare Fast Bit */ 01790 tmpccmr2 |= TIM_OCFast; 01791 01792 /* Write to TIMx CCMR2 */ 01793 TIMx->CCMR2 = tmpccmr2; 01794 } 01795 01796 /** 01797 * @brief Configures the TIMx Output Compare 4 Fast feature. 01798 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01799 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01800 * This parameter can be one of the following values: 01801 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01802 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01803 * @retval None 01804 */ 01805 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01806 { 01807 uint32_t tmpccmr2 = 0; 01808 01809 /* Check the parameters */ 01810 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01811 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01812 01813 /* Get the TIMx CCMR2 register value */ 01814 tmpccmr2 = TIMx->CCMR2; 01815 01816 /* Reset the OC4FE Bit */ 01817 tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE); 01818 01819 /* Enable or Disable the Output Compare Fast Bit */ 01820 tmpccmr2 |= ((uint32_t)TIM_OCFast << 8); 01821 01822 /* Write to TIMx CCMR2 */ 01823 TIMx->CCMR2 = tmpccmr2; 01824 } 01825 01826 /** 01827 * @brief Clears or safeguards the OCREF1 signal on an external event 01828 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 01829 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01830 * This parameter can be one of the following values: 01831 * @arg TIM_OCClear_Enable: TIM Output clear enable 01832 * @arg TIM_OCClear_Disable: TIM Output clear disable 01833 * @retval None 01834 */ 01835 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01836 { 01837 uint32_t tmpccmr1 = 0; 01838 01839 /* Check the parameters */ 01840 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01841 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01842 01843 tmpccmr1 = TIMx->CCMR1; 01844 01845 /* Reset the OC1CE Bit */ 01846 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE; 01847 01848 /* Enable or Disable the Output Compare Clear Bit */ 01849 tmpccmr1 |= TIM_OCClear; 01850 01851 /* Write to TIMx CCMR1 register */ 01852 TIMx->CCMR1 = tmpccmr1; 01853 } 01854 01855 /** 01856 * @brief Clears or safeguards the OCREF2 signal on an external event 01857 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 01858 * peripheral. 01859 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01860 * This parameter can be one of the following values: 01861 * @arg TIM_OCClear_Enable: TIM Output clear enable 01862 * @arg TIM_OCClear_Disable: TIM Output clear disable 01863 * @retval None 01864 */ 01865 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01866 { 01867 uint32_t tmpccmr1 = 0; 01868 01869 /* Check the parameters */ 01870 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01871 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01872 01873 tmpccmr1 = TIMx->CCMR1; 01874 01875 /* Reset the OC2CE Bit */ 01876 tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE; 01877 01878 /* Enable or Disable the Output Compare Clear Bit */ 01879 tmpccmr1 |= ((uint32_t)TIM_OCClear << 8); 01880 01881 /* Write to TIMx CCMR1 register */ 01882 TIMx->CCMR1 = tmpccmr1; 01883 } 01884 01885 /** 01886 * @brief Clears or safeguards the OCREF3 signal on an external event 01887 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01888 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01889 * This parameter can be one of the following values: 01890 * @arg TIM_OCClear_Enable: TIM Output clear enable 01891 * @arg TIM_OCClear_Disable: TIM Output clear disable 01892 * @retval None 01893 */ 01894 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01895 { 01896 uint32_t tmpccmr2 = 0; 01897 01898 /* Check the parameters */ 01899 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01900 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01901 01902 tmpccmr2 = TIMx->CCMR2; 01903 01904 /* Reset the OC3CE Bit */ 01905 tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE; 01906 01907 /* Enable or Disable the Output Compare Clear Bit */ 01908 tmpccmr2 |= TIM_OCClear; 01909 01910 /* Write to TIMx CCMR2 register */ 01911 TIMx->CCMR2 = tmpccmr2; 01912 } 01913 01914 /** 01915 * @brief Clears or safeguards the OCREF4 signal on an external event 01916 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 01917 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01918 * This parameter can be one of the following values: 01919 * @arg TIM_OCClear_Enable: TIM Output clear enable 01920 * @arg TIM_OCClear_Disable: TIM Output clear disable 01921 * @retval None 01922 */ 01923 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01924 { 01925 uint32_t tmpccmr2 = 0; 01926 01927 /* Check the parameters */ 01928 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01929 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01930 01931 tmpccmr2 = TIMx->CCMR2; 01932 01933 /* Reset the OC4CE Bit */ 01934 tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE; 01935 01936 /* Enable or Disable the Output Compare Clear Bit */ 01937 tmpccmr2 |= ((uint32_t)TIM_OCClear << 8); 01938 01939 /* Write to TIMx CCMR2 register */ 01940 TIMx->CCMR2 = tmpccmr2; 01941 } 01942 01943 /** 01944 * @brief Clears or safeguards the OCREF5 signal on an external event 01945 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01946 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01947 * This parameter can be one of the following values: 01948 * @arg TIM_OCClear_Enable: TIM Output clear enable 01949 * @arg TIM_OCClear_Disable: TIM Output clear disable 01950 * @retval None 01951 */ 01952 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01953 { 01954 uint32_t tmpccmr3 = 0; 01955 01956 /* Check the parameters */ 01957 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01958 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01959 01960 tmpccmr3 = TIMx->CCMR3; 01961 01962 /* Reset the OC5CE Bit */ 01963 tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE; 01964 01965 /* Enable or Disable the Output Compare Clear Bit */ 01966 tmpccmr3 |= (uint32_t)(TIM_OCClear); 01967 01968 /* Write to TIMx CCMR3 register */ 01969 TIMx->CCMR3 = tmpccmr3; 01970 } 01971 01972 /** 01973 * @brief Clears or safeguards the OCREF6 signal on an external event 01974 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01975 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01976 * This parameter can be one of the following values: 01977 * @arg TIM_OCClear_Enable: TIM Output clear enable 01978 * @arg TIM_OCClear_Disable: TIM Output clear disable 01979 * @retval None 01980 */ 01981 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01982 { 01983 uint32_t tmpccmr3 = 0; 01984 01985 /* Check the parameters */ 01986 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01987 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01988 01989 tmpccmr3 = TIMx->CCMR3; 01990 01991 /* Reset the OC5CE Bit */ 01992 tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE; 01993 01994 /* Enable or Disable the Output Compare Clear Bit */ 01995 tmpccmr3 |= ((uint32_t)TIM_OCClear << 8); 01996 01997 /* Write to TIMx CCMR3 register */ 01998 TIMx->CCMR3 = tmpccmr3; 01999 } 02000 02001 /** 02002 * @brief Selects the OCReference Clear source. 02003 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02004 * @param TIM_OCReferenceClear: specifies the OCReference Clear source. 02005 * This parameter can be one of the following values: 02006 * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. 02007 * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. 02008 * @retval None 02009 */ 02010 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) 02011 { 02012 /* Check the parameters */ 02013 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02014 assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); 02015 02016 /* Set the TIM_OCReferenceClear source */ 02017 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); 02018 TIMx->SMCR |= TIM_OCReferenceClear; 02019 } 02020 02021 /** 02022 * @brief Configures the TIMx channel 1 polarity. 02023 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02024 * @param TIM_OCPolarity: specifies the OC1 Polarity 02025 * This parameter can be one of the following values: 02026 * @arg TIM_OCPolarity_High: Output Compare active high 02027 * @arg TIM_OCPolarity_Low: Output Compare active low 02028 * @retval None 02029 */ 02030 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02031 { 02032 uint32_t tmpccer = 0; 02033 02034 /* Check the parameters */ 02035 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 02036 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02037 02038 tmpccer = TIMx->CCER; 02039 02040 /* Set or Reset the CC1P Bit */ 02041 tmpccer &= (uint32_t)(~TIM_CCER_CC1P); 02042 tmpccer |= TIM_OCPolarity; 02043 02044 /* Write to TIMx CCER register */ 02045 TIMx->CCER = tmpccer; 02046 } 02047 02048 /** 02049 * @brief Configures the TIMx Channel 1N polarity. 02050 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. 02051 * @param TIM_OCNPolarity: specifies the OC1N Polarity 02052 * This parameter can be one of the following values: 02053 * @arg TIM_OCNPolarity_High: Output Compare active high 02054 * @arg TIM_OCNPolarity_Low: Output Compare active low 02055 * @retval None 02056 */ 02057 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 02058 { 02059 uint32_t tmpccer = 0; 02060 /* Check the parameters */ 02061 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02062 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 02063 02064 tmpccer = TIMx->CCER; 02065 02066 /* Set or Reset the CC1NP Bit */ 02067 tmpccer &= (uint32_t)~TIM_CCER_CC1NP; 02068 tmpccer |= TIM_OCNPolarity; 02069 02070 /* Write to TIMx CCER register */ 02071 TIMx->CCER = tmpccer; 02072 } 02073 02074 /** 02075 * @brief Configures the TIMx channel 2 polarity. 02076 * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM 02077 * peripheral. 02078 * @param TIM_OCPolarity: specifies the OC2 Polarity 02079 * This parameter can be one of the following values: 02080 * @arg TIM_OCPolarity_High: Output Compare active high 02081 * @arg TIM_OCPolarity_Low: Output Compare active low 02082 * @retval None 02083 */ 02084 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02085 { 02086 uint32_t tmpccer = 0; 02087 02088 /* Check the parameters */ 02089 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02090 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02091 02092 tmpccer = TIMx->CCER; 02093 02094 /* Set or Reset the CC2P Bit */ 02095 tmpccer &= (uint32_t)(~TIM_CCER_CC2P); 02096 tmpccer |= ((uint32_t)TIM_OCPolarity << 4); 02097 02098 /* Write to TIMx CCER register */ 02099 TIMx->CCER = tmpccer; 02100 } 02101 02102 /** 02103 * @brief Configures the TIMx Channel 2N polarity. 02104 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 02105 * @param TIM_OCNPolarity: specifies the OC2N Polarity 02106 * This parameter can be one of the following values: 02107 * @arg TIM_OCNPolarity_High: Output Compare active high 02108 * @arg TIM_OCNPolarity_Low: Output Compare active low 02109 * @retval None 02110 */ 02111 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 02112 { 02113 uint32_t tmpccer = 0; 02114 02115 /* Check the parameters */ 02116 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02117 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 02118 02119 tmpccer = TIMx->CCER; 02120 02121 /* Set or Reset the CC2NP Bit */ 02122 tmpccer &= (uint32_t)~TIM_CCER_CC2NP; 02123 tmpccer |= ((uint32_t)TIM_OCNPolarity << 4); 02124 02125 /* Write to TIMx CCER register */ 02126 TIMx->CCER = tmpccer; 02127 } 02128 02129 /** 02130 * @brief Configures the TIMx channel 3 polarity. 02131 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02132 * @param TIM_OCPolarity: specifies the OC3 Polarity 02133 * This parameter can be one of the following values: 02134 * @arg TIM_OCPolarity_High: Output Compare active high 02135 * @arg TIM_OCPolarity_Low: Output Compare active low 02136 * @retval None 02137 */ 02138 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02139 { 02140 uint32_t tmpccer = 0; 02141 02142 /* Check the parameters */ 02143 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02144 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02145 02146 tmpccer = TIMx->CCER; 02147 02148 /* Set or Reset the CC3P Bit */ 02149 tmpccer &= (uint32_t)~TIM_CCER_CC3P; 02150 tmpccer |= ((uint32_t)TIM_OCPolarity << 8); 02151 02152 /* Write to TIMx CCER register */ 02153 TIMx->CCER = tmpccer; 02154 } 02155 02156 /** 02157 * @brief Configures the TIMx Channel 3N polarity. 02158 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 02159 * @param TIM_OCNPolarity: specifies the OC3N Polarity 02160 * This parameter can be one of the following values: 02161 * @arg TIM_OCNPolarity_High: Output Compare active high 02162 * @arg TIM_OCNPolarity_Low: Output Compare active low 02163 * @retval None 02164 */ 02165 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 02166 { 02167 uint32_t tmpccer = 0; 02168 02169 /* Check the parameters */ 02170 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02171 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 02172 02173 tmpccer = TIMx->CCER; 02174 02175 /* Set or Reset the CC3NP Bit */ 02176 tmpccer &= (uint32_t)~TIM_CCER_CC3NP; 02177 tmpccer |= ((uint32_t)TIM_OCNPolarity << 8); 02178 02179 /* Write to TIMx CCER register */ 02180 TIMx->CCER = tmpccer; 02181 } 02182 02183 /** 02184 * @brief Configures the TIMx channel 4 polarity. 02185 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02186 * @param TIM_OCPolarity: specifies the OC4 Polarity 02187 * This parameter can be one of the following values: 02188 * @arg TIM_OCPolarity_High: Output Compare active high 02189 * @arg TIM_OCPolarity_Low: Output Compare active low 02190 * @retval None 02191 */ 02192 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02193 { 02194 uint32_t tmpccer = 0; 02195 02196 /* Check the parameters */ 02197 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02198 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02199 02200 tmpccer = TIMx->CCER; 02201 02202 /* Set or Reset the CC4P Bit */ 02203 tmpccer &= (uint32_t)~TIM_CCER_CC4P; 02204 tmpccer |= ((uint32_t)TIM_OCPolarity << 12); 02205 02206 /* Write to TIMx CCER register */ 02207 TIMx->CCER = tmpccer; 02208 } 02209 02210 /** 02211 * @brief Configures the TIMx channel 5 polarity. 02212 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 02213 * @param TIM_OCPolarity: specifies the OC5 Polarity 02214 * This parameter can be one of the following values: 02215 * @arg TIM_OCPolarity_High: Output Compare active high 02216 * @arg TIM_OCPolarity_Low: Output Compare active low 02217 * @retval None 02218 */ 02219 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02220 { 02221 uint32_t tmpccer = 0; 02222 02223 /* Check the parameters */ 02224 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02225 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02226 02227 tmpccer = TIMx->CCER; 02228 02229 /* Set or Reset the CC5P Bit */ 02230 tmpccer &= (uint32_t)~TIM_CCER_CC5P; 02231 tmpccer |= ((uint32_t)TIM_OCPolarity << 16); 02232 02233 /* Write to TIMx CCER register */ 02234 TIMx->CCER = tmpccer; 02235 } 02236 02237 /** 02238 * @brief Configures the TIMx channel 6 polarity. 02239 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 02240 * @param TIM_OCPolarity: specifies the OC6 Polarity 02241 * This parameter can be one of the following values: 02242 * @arg TIM_OCPolarity_High: Output Compare active high 02243 * @arg TIM_OCPolarity_Low: Output Compare active low 02244 * @retval None 02245 */ 02246 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 02247 { 02248 uint32_t tmpccer = 0; 02249 02250 /* Check the parameters */ 02251 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02252 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 02253 02254 tmpccer = TIMx->CCER; 02255 02256 /* Set or Reset the CC6P Bit */ 02257 tmpccer &= (uint32_t)~TIM_CCER_CC6P; 02258 tmpccer |= ((uint32_t)TIM_OCPolarity << 20); 02259 02260 /* Write to TIMx CCER register */ 02261 TIMx->CCER = tmpccer; 02262 } 02263 02264 /** 02265 * @brief Enables or disables the TIM Capture Compare Channel x. 02266 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02267 * @param TIM_Channel: specifies the TIM Channel 02268 * This parameter can be one of the following values: 02269 * @arg TIM_Channel_1: TIM Channel 1 02270 * @arg TIM_Channel_2: TIM Channel 2 02271 * @arg TIM_Channel_3: TIM Channel 3 02272 * @arg TIM_Channel_4: TIM Channel 4 02273 * @arg TIM_Channel_5: TIM Channel 5 02274 * @arg TIM_Channel_6: TIM Channel 6 02275 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. 02276 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 02277 * @retval None 02278 */ 02279 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) 02280 { 02281 uint32_t tmp = 0; 02282 02283 /* Check the parameters */ 02284 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 02285 assert_param(IS_TIM_CHANNEL(TIM_Channel)); 02286 assert_param(IS_TIM_CCX(TIM_CCx)); 02287 02288 tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel; 02289 02290 /* Reset the CCxE Bit */ 02291 TIMx->CCER &= (uint32_t)(~tmp); 02292 02293 /* Set or reset the CCxE Bit */ 02294 TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel); 02295 } 02296 02297 /** 02298 * @brief Enables or disables the TIM Capture Compare Channel xN. 02299 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. 02300 * @param TIM_Channel: specifies the TIM Channel 02301 * This parameter can be one of the following values: 02302 * @arg TIM_Channel_1: TIM Channel 1 02303 * @arg TIM_Channel_2: TIM Channel 2 02304 * @arg TIM_Channel_3: TIM Channel 3 02305 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. 02306 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 02307 * @retval None 02308 */ 02309 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) 02310 { 02311 uint32_t tmp = 0; 02312 02313 /* Check the parameters */ 02314 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02315 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); 02316 assert_param(IS_TIM_CCXN(TIM_CCxN)); 02317 02318 tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel; 02319 02320 /* Reset the CCxNE Bit */ 02321 TIMx->CCER &= (uint32_t) ~tmp; 02322 02323 /* Set or reset the CCxNE Bit */ 02324 TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel); 02325 } 02326 /** 02327 * @} 02328 */ 02329 02330 /** @defgroup TIM_Group3 Input Capture management functions 02331 * @brief Input Capture management functions 02332 * 02333 @verbatim 02334 =============================================================================== 02335 ##### Input Capture management functions ##### 02336 =============================================================================== 02337 02338 *** TIM Driver: how to use it in Input Capture Mode *** 02339 ======================================================= 02340 [..] 02341 To use the Timer in Input Capture mode, the following steps are mandatory: 02342 02343 (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function 02344 02345 (#) Configure the TIM pins by configuring the corresponding GPIO pins 02346 02347 (#) Configure the Time base unit as described in the first part of this driver, 02348 if needed, else the Timer will run with the default configuration: 02349 (++) Autoreload value = 0xFFFF 02350 (++) Prescaler value = 0x0000 02351 (++) Counter mode = Up counting 02352 (++) Clock Division = TIM_CKD_DIV1 02353 02354 (#) Fill the TIM_ICInitStruct with the desired parameters including: 02355 (++) TIM Channel: TIM_Channel 02356 (++) TIM Input Capture polarity: TIM_ICPolarity 02357 (++) TIM Input Capture selection: TIM_ICSelection 02358 (++) TIM Input Capture Prescaler: TIM_ICPrescaler 02359 (++) TIM Input CApture filter value: TIM_ICFilter 02360 02361 (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the 02362 corresponding configuration and to measure only frequency or duty cycle of the input signal, 02363 or, 02364 Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the 02365 corresponding configuration and to measure the frequency and the duty cycle of the input signal 02366 02367 (#) Enable the NVIC or the DMA to read the measured frequency. 02368 02369 (#) Enable the corresponding interrupt (or DMA request) to read the Captured value, 02370 using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 02371 02372 (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. 02373 02374 (#) Use TIM_GetCapturex(TIMx); to read the captured value. 02375 [..] 02376 (@) All other functions can be used separately to modify, if needed, 02377 a specific feature of the Timer. 02378 02379 @endverbatim 02380 * @{ 02381 */ 02382 02383 /** 02384 * @brief Initializes the TIM peripheral according to the specified parameters 02385 * in the TIM_ICInitStruct. 02386 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02387 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains 02388 * the configuration information for the specified TIM peripheral. 02389 * @retval None 02390 */ 02391 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) 02392 { 02393 /* Check the parameters */ 02394 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 02395 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); 02396 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); 02397 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); 02398 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); 02399 02400 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 02401 { 02402 /* TI1 Configuration */ 02403 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 02404 TIM_ICInitStruct->TIM_ICSelection, 02405 TIM_ICInitStruct->TIM_ICFilter); 02406 /* Set the Input Capture Prescaler value */ 02407 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02408 } 02409 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) 02410 { 02411 /* TI2 Configuration */ 02412 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 02413 TIM_ICInitStruct->TIM_ICSelection, 02414 TIM_ICInitStruct->TIM_ICFilter); 02415 /* Set the Input Capture Prescaler value */ 02416 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02417 } 02418 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) 02419 { 02420 /* TI3 Configuration */ 02421 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 02422 TIM_ICInitStruct->TIM_ICSelection, 02423 TIM_ICInitStruct->TIM_ICFilter); 02424 /* Set the Input Capture Prescaler value */ 02425 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02426 } 02427 else 02428 { 02429 /* TI4 Configuration */ 02430 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 02431 TIM_ICInitStruct->TIM_ICSelection, 02432 TIM_ICInitStruct->TIM_ICFilter); 02433 /* Set the Input Capture Prescaler value */ 02434 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02435 } 02436 } 02437 02438 /** 02439 * @brief Fills each TIM_ICInitStruct member with its default value. 02440 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will 02441 * be initialized. 02442 * @retval None 02443 */ 02444 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) 02445 { 02446 /* Set the default configuration */ 02447 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; 02448 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; 02449 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; 02450 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; 02451 TIM_ICInitStruct->TIM_ICFilter = 0x00; 02452 } 02453 02454 /** 02455 * @brief Configures the TIM peripheral according to the specified parameters 02456 * in the TIM_ICInitStruct to measure an external PWM signal. 02457 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 02458 * peripheral. 02459 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains 02460 * the configuration information for the specified TIM peripheral. 02461 * @retval None 02462 */ 02463 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) 02464 { 02465 uint16_t icoppositepolarity = TIM_ICPolarity_Rising; 02466 uint16_t icoppositeselection = TIM_ICSelection_DirectTI; 02467 02468 /* Check the parameters */ 02469 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02470 02471 /* Select the Opposite Input Polarity */ 02472 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) 02473 { 02474 icoppositepolarity = TIM_ICPolarity_Falling; 02475 } 02476 else 02477 { 02478 icoppositepolarity = TIM_ICPolarity_Rising; 02479 } 02480 /* Select the Opposite Input */ 02481 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) 02482 { 02483 icoppositeselection = TIM_ICSelection_IndirectTI; 02484 } 02485 else 02486 { 02487 icoppositeselection = TIM_ICSelection_DirectTI; 02488 } 02489 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 02490 { 02491 /* TI1 Configuration */ 02492 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 02493 TIM_ICInitStruct->TIM_ICFilter); 02494 /* Set the Input Capture Prescaler value */ 02495 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02496 /* TI2 Configuration */ 02497 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 02498 /* Set the Input Capture Prescaler value */ 02499 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02500 } 02501 else 02502 { 02503 /* TI2 Configuration */ 02504 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 02505 TIM_ICInitStruct->TIM_ICFilter); 02506 /* Set the Input Capture Prescaler value */ 02507 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02508 /* TI1 Configuration */ 02509 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 02510 /* Set the Input Capture Prescaler value */ 02511 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 02512 } 02513 } 02514 02515 /** 02516 * @brief Gets the TIMx Input Capture 1 value. 02517 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02518 * @retval Capture Compare 1 Register value. 02519 */ 02520 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) 02521 { 02522 /* Check the parameters */ 02523 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 02524 02525 /* Get the Capture 1 Register value */ 02526 return TIMx->CCR1; 02527 } 02528 02529 /** 02530 * @brief Gets the TIMx Input Capture 2 value. 02531 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 02532 * peripheral. 02533 * @retval Capture Compare 2 Register value. 02534 */ 02535 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) 02536 { 02537 /* Check the parameters */ 02538 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02539 02540 /* Get the Capture 2 Register value */ 02541 return TIMx->CCR2; 02542 } 02543 02544 /** 02545 * @brief Gets the TIMx Input Capture 3 value. 02546 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02547 * @retval Capture Compare 3 Register value. 02548 */ 02549 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) 02550 { 02551 /* Check the parameters */ 02552 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02553 02554 /* Get the Capture 3 Register value */ 02555 return TIMx->CCR3; 02556 } 02557 02558 /** 02559 * @brief Gets the TIMx Input Capture 4 value. 02560 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02561 * @retval Capture Compare 4 Register value. 02562 */ 02563 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) 02564 { 02565 /* Check the parameters */ 02566 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02567 02568 /* Get the Capture 4 Register value */ 02569 return TIMx->CCR4; 02570 } 02571 02572 /** 02573 * @brief Sets the TIMx Input Capture 1 prescaler. 02574 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 02575 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. 02576 * This parameter can be one of the following values: 02577 * @arg TIM_ICPSC_DIV1: no prescaler 02578 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02579 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02580 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02581 * @retval None 02582 */ 02583 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02584 { 02585 /* Check the parameters */ 02586 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 02587 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02588 02589 /* Reset the IC1PSC Bits */ 02590 TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC; 02591 02592 /* Set the IC1PSC value */ 02593 TIMx->CCMR1 |= TIM_ICPSC; 02594 } 02595 02596 /** 02597 * @brief Sets the TIMx Input Capture 2 prescaler. 02598 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 02599 * peripheral. 02600 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. 02601 * This parameter can be one of the following values: 02602 * @arg TIM_ICPSC_DIV1: no prescaler 02603 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02604 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02605 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02606 * @retval None 02607 */ 02608 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02609 { 02610 /* Check the parameters */ 02611 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02612 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02613 02614 /* Reset the IC2PSC Bits */ 02615 TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC; 02616 02617 /* Set the IC2PSC value */ 02618 TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8); 02619 } 02620 02621 /** 02622 * @brief Sets the TIMx Input Capture 3 prescaler. 02623 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02624 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. 02625 * This parameter can be one of the following values: 02626 * @arg TIM_ICPSC_DIV1: no prescaler 02627 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02628 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02629 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02630 * @retval None 02631 */ 02632 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02633 { 02634 /* Check the parameters */ 02635 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02636 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02637 02638 /* Reset the IC3PSC Bits */ 02639 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; 02640 02641 /* Set the IC3PSC value */ 02642 TIMx->CCMR2 |= TIM_ICPSC; 02643 } 02644 02645 /** 02646 * @brief Sets the TIMx Input Capture 4 prescaler. 02647 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 02648 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. 02649 * This parameter can be one of the following values: 02650 * @arg TIM_ICPSC_DIV1: no prescaler 02651 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02652 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02653 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02654 * @retval None 02655 */ 02656 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02657 { 02658 /* Check the parameters */ 02659 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02660 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02661 02662 /* Reset the IC4PSC Bits */ 02663 TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; 02664 02665 /* Set the IC4PSC value */ 02666 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); 02667 } 02668 /** 02669 * @} 02670 */ 02671 02672 /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features 02673 * @brief Advanced-control timers (TIM1 and TIM8) specific features 02674 * 02675 @verbatim 02676 =============================================================================== 02677 ##### Advanced-control timers (TIM1 and TIM8) specific features ##### 02678 =============================================================================== 02679 02680 *** TIM Driver: how to use the Break feature *** 02681 ================================================ 02682 [..] 02683 After configuring the Timer channel(s) in the appropriate Output Compare mode: 02684 02685 (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer 02686 Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 02687 AOE(automatic output enable). 02688 02689 (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer 02690 02691 (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 02692 02693 (#) Once the break even occurs, the Timer's output signals are put in reset 02694 state or in a known state (according to the configuration made in 02695 TIM_BDTRConfig() function). 02696 02697 @endverbatim 02698 * @{ 02699 */ 02700 02701 /** 02702 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State 02703 * and the AOE(automatic output enable). 02704 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM 02705 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that 02706 * contains the BDTR Register configuration information for the TIM peripheral. 02707 * @retval None 02708 */ 02709 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) 02710 { 02711 /* Check the parameters */ 02712 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02713 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); 02714 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); 02715 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); 02716 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); 02717 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); 02718 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); 02719 02720 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, 02721 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 02722 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 02723 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | 02724 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | 02725 TIM_BDTRInitStruct->TIM_AutomaticOutput; 02726 } 02727 02728 /** 02729 * @brief Configures the Break1 feature. 02730 * @param TIMx: where x can be 1 or 8 to select the TIM 02731 * @param TIM_Break1Polarity: specifies the Break1 polarity. 02732 * This parameter can be one of the following values: 02733 * @arg TIM_Break1Polarity_Low: Break1 input is active low 02734 * @arg TIM_Break1Polarity_High: Break1 input is active high 02735 * @param TIM_Break1Filter: specifies the Break1 filter value. 02736 * This parameter must be a value between 0x00 and 0x0F 02737 * @retval None 02738 */ 02739 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter) 02740 { /* Check the parameters */ 02741 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02742 assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter)); 02743 02744 /* Reset the BKP and BKF Bits */ 02745 TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF); 02746 /* Configure the Break1 polarity and filter */ 02747 TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16); 02748 } 02749 02750 /** 02751 * @brief Configures the Break2 feature. 02752 * @param TIMx: where x can be 1 or 8 to select the TIM 02753 * @param TIM_Break2Polarity: specifies the Break2 polarity. 02754 * This parameter can be one of the following values: 02755 * @arg TIM_Break2Polarity_Low: Break2 input is active low 02756 * @arg TIM_Break2Polarity_High: Break2 input is active high 02757 * @param TIM_Break2Filter: specifies the Break2 filter value. 02758 * This parameter must be a value between 0x00 and 0x0F 02759 * @retval None 02760 */ 02761 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter) 02762 { 02763 /* Check the parameters */ 02764 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02765 assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter)); 02766 02767 /* Reset the BKP and BKF Bits */ 02768 TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F); 02769 02770 /* Configure the Break1 polarity and filter */ 02771 TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20); 02772 } 02773 02774 /** 02775 * @brief Enables or disables the TIM Break1 input. 02776 * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral. 02777 * @param NewState: new state of the TIM Break1 input. 02778 * This parameter can be: ENABLE or DISABLE. 02779 * @retval None 02780 */ 02781 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) 02782 { 02783 /* Check the parameters */ 02784 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02785 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02786 02787 if (NewState != DISABLE) 02788 { 02789 /* Enable the Break1 */ 02790 TIMx->BDTR |= TIM_BDTR_BKE; 02791 } 02792 else 02793 { 02794 /* Disable the Break1 */ 02795 TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE; 02796 } 02797 } 02798 02799 /** 02800 * @brief Enables or disables the TIM Break2 input. 02801 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. 02802 * @param NewState: new state of the TIM Break2 input. 02803 * This parameter can be: ENABLE or DISABLE. 02804 * @retval None 02805 */ 02806 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) 02807 { 02808 /* Check the parameters */ 02809 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 02810 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02811 02812 if (NewState != DISABLE) 02813 { 02814 /* Enable the Break1 */ 02815 TIMx->BDTR |= TIM_BDTR_BK2E; 02816 } 02817 else 02818 { 02819 /* Disable the Break1 */ 02820 TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E; 02821 } 02822 } 02823 02824 /** 02825 * @brief Fills each TIM_BDTRInitStruct member with its default value. 02826 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which 02827 * will be initialized. 02828 * @retval None 02829 */ 02830 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) 02831 { 02832 /* Set the default configuration */ 02833 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; 02834 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; 02835 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; 02836 TIM_BDTRInitStruct->TIM_DeadTime = 0x00; 02837 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; 02838 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; 02839 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; 02840 } 02841 02842 /** 02843 * @brief Enables or disables the TIM peripheral Main Outputs. 02844 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. 02845 * @param NewState: new state of the TIM peripheral Main Outputs. 02846 * This parameter can be: ENABLE or DISABLE. 02847 * @retval None 02848 */ 02849 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) 02850 { 02851 /* Check the parameters */ 02852 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02853 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02854 02855 if (NewState != DISABLE) 02856 { 02857 /* Enable the TIM Main Output */ 02858 TIMx->BDTR |= TIM_BDTR_MOE; 02859 } 02860 else 02861 { 02862 /* Disable the TIM Main Output */ 02863 TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; 02864 } 02865 } 02866 02867 /** 02868 * @brief Selects the TIM peripheral Commutation event. 02869 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral 02870 * @param NewState: new state of the Commutation event. 02871 * This parameter can be: ENABLE or DISABLE. 02872 * @retval None 02873 */ 02874 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) 02875 { 02876 /* Check the parameters */ 02877 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02878 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02879 02880 if (NewState != DISABLE) 02881 { 02882 /* Set the COM Bit */ 02883 TIMx->CR2 |= TIM_CR2_CCUS; 02884 } 02885 else 02886 { 02887 /* Reset the COM Bit */ 02888 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; 02889 } 02890 } 02891 02892 /** 02893 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. 02894 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral 02895 * @param NewState: new state of the Capture Compare Preload Control bit 02896 * This parameter can be: ENABLE or DISABLE. 02897 * @retval None 02898 */ 02899 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) 02900 { 02901 /* Check the parameters */ 02902 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02903 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02904 if (NewState != DISABLE) 02905 { 02906 /* Set the CCPC Bit */ 02907 TIMx->CR2 |= TIM_CR2_CCPC; 02908 } 02909 else 02910 { 02911 /* Reset the CCPC Bit */ 02912 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; 02913 } 02914 } 02915 /** 02916 * @} 02917 */ 02918 02919 /** @defgroup TIM_Group5 Interrupts DMA and flags management functions 02920 * @brief Interrupts, DMA and flags management functions 02921 * 02922 @verbatim 02923 =============================================================================== 02924 ##### Interrupts, DMA and flags management functions ##### 02925 =============================================================================== 02926 02927 @endverbatim 02928 * @{ 02929 */ 02930 02931 /** 02932 * @brief Enables or disables the specified TIM interrupts. 02933 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral. 02934 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. 02935 * This parameter can be any combination of the following values: 02936 * @arg TIM_IT_Update: TIM update Interrupt source 02937 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 02938 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 02939 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 02940 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 02941 * @arg TIM_IT_COM: TIM Commutation Interrupt source 02942 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 02943 * @arg TIM_IT_Break: TIM Break Interrupt source 02944 * 02945 * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used 02946 * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, 02947 * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 02948 * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can 02949 * be used: TIM_IT_Update or TIM_IT_CC1 02950 * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 02951 * 02952 * @param NewState: new state of the TIM interrupts. 02953 * This parameter can be: ENABLE or DISABLE. 02954 * @retval None 02955 */ 02956 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) 02957 { 02958 /* Check the parameters */ 02959 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02960 assert_param(IS_TIM_IT(TIM_IT)); 02961 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02962 02963 if (NewState != DISABLE) 02964 { 02965 /* Enable the Interrupt sources */ 02966 TIMx->DIER |= TIM_IT; 02967 } 02968 else 02969 { 02970 /* Disable the Interrupt sources */ 02971 TIMx->DIER &= (uint16_t)~TIM_IT; 02972 } 02973 } 02974 02975 /** 02976 * @brief Configures the TIMx event to be generate by software. 02977 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 02978 * @param TIM_EventSource: specifies the event source. 02979 * This parameter can be one or more of the following values: 02980 * @arg TIM_EventSource_Update: Timer update Event source 02981 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source 02982 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source 02983 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source 02984 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source 02985 * @arg TIM_EventSource_COM: Timer COM event source 02986 * @arg TIM_EventSource_Trigger: Timer Trigger Event source 02987 * @arg TIM_EventSource_Break: Timer Break event source 02988 * 02989 * @note TIM6 and TIM7 can only generate an update event. 02990 * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. 02991 * 02992 * @retval None 02993 */ 02994 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) 02995 { 02996 /* Check the parameters */ 02997 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02998 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); 02999 03000 /* Set the event sources */ 03001 TIMx->EGR = TIM_EventSource; 03002 } 03003 03004 /** 03005 * @brief Checks whether the specified TIM flag is set or not. 03006 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 03007 * @param TIM_FLAG: specifies the flag to check. 03008 * This parameter can be one of the following values: 03009 * @arg TIM_FLAG_Update: TIM update Flag 03010 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag 03011 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag 03012 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag 03013 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag 03014 * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag 03015 * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag 03016 * @arg TIM_FLAG_COM: TIM Commutation Flag 03017 * @arg TIM_FLAG_Trigger: TIM Trigger Flag 03018 * @arg TIM_FLAG_Break: TIM Break Flag 03019 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag 03020 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag 03021 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag 03022 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag 03023 * 03024 * @note TIM6 and TIM7 can have only one update flag. 03025 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. 03026 * 03027 * @retval The new state of TIM_FLAG (SET or RESET). 03028 */ 03029 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG) 03030 { 03031 ITStatus bitstatus = RESET; 03032 /* Check the parameters */ 03033 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 03034 assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); 03035 03036 03037 if ((TIMx->SR & TIM_FLAG) != RESET) 03038 { 03039 bitstatus = SET; 03040 } 03041 else 03042 { 03043 bitstatus = RESET; 03044 } 03045 return bitstatus; 03046 } 03047 03048 /** 03049 * @brief Clears the TIMx's pending flags. 03050 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 03051 * @param TIM_FLAG: specifies the flag bit to clear. 03052 * This parameter can be any combination of the following values: 03053 * @arg TIM_FLAG_Update: TIM update Flag 03054 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag 03055 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag 03056 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag 03057 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag 03058 * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag 03059 * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag 03060 * @arg TIM_FLAG_COM: TIM Commutation Flag 03061 * @arg TIM_FLAG_Trigger: TIM Trigger Flag 03062 * @arg TIM_FLAG_Break: TIM Break Flag 03063 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag 03064 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag 03065 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag 03066 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag 03067 * 03068 * @note TIM6 and TIM7 can have only one update flag. 03069 * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. 03070 * 03071 * @retval None 03072 */ 03073 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) 03074 { 03075 /* Check the parameters */ 03076 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 03077 03078 /* Clear the flags */ 03079 TIMx->SR = (uint16_t)~TIM_FLAG; 03080 } 03081 03082 /** 03083 * @brief Checks whether the TIM interrupt has occurred or not. 03084 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 03085 * @param TIM_IT: specifies the TIM interrupt source to check. 03086 * This parameter can be one of the following values: 03087 * @arg TIM_IT_Update: TIM update Interrupt source 03088 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 03089 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 03090 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 03091 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 03092 * @arg TIM_IT_COM: TIM Commutation Interrupt source 03093 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 03094 * @arg TIM_IT_Break: TIM Break Interrupt source 03095 * 03096 * @note TIM6 and TIM7 can generate only an update interrupt. 03097 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. 03098 * 03099 * @retval The new state of the TIM_IT(SET or RESET). 03100 */ 03101 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) 03102 { 03103 ITStatus bitstatus = RESET; 03104 uint16_t itstatus = 0x0, itenable = 0x0; 03105 /* Check the parameters */ 03106 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 03107 assert_param(IS_TIM_GET_IT(TIM_IT)); 03108 03109 itstatus = TIMx->SR & TIM_IT; 03110 03111 itenable = TIMx->DIER & TIM_IT; 03112 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 03113 { 03114 bitstatus = SET; 03115 } 03116 else 03117 { 03118 bitstatus = RESET; 03119 } 03120 return bitstatus; 03121 } 03122 03123 /** 03124 * @brief Clears the TIMx's interrupt pending bits. 03125 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 03126 * @param TIM_IT: specifies the pending bit to clear. 03127 * This parameter can be any combination of the following values: 03128 * @arg TIM_IT_Update: TIM1 update Interrupt source 03129 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 03130 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 03131 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 03132 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 03133 * @arg TIM_IT_COM: TIM Commutation Interrupt source 03134 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 03135 * @arg TIM_IT_Break: TIM Break Interrupt source 03136 * 03137 * @note TIM6 and TIM7 can generate only an update interrupt. 03138 * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. 03139 * 03140 * @retval None 03141 */ 03142 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) 03143 { 03144 /* Check the parameters */ 03145 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 03146 03147 /* Clear the IT pending Bit */ 03148 TIMx->SR = (uint16_t)~TIM_IT; 03149 } 03150 03151 /** 03152 * @brief Configures the TIMx's DMA interface. 03153 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 03154 * @param TIM_DMABase: DMA Base address. 03155 * This parameter can be one of the following values: 03156 * @arg TIM_DMABase_CR1 03157 * @arg TIM_DMABase_CR2 03158 * @arg TIM_DMABase_SMCR 03159 * @arg TIM_DMABase_DIER 03160 * @arg TIM1_DMABase_SR 03161 * @arg TIM_DMABase_EGR 03162 * @arg TIM_DMABase_CCMR1 03163 * @arg TIM_DMABase_CCMR2 03164 * @arg TIM_DMABase_CCER 03165 * @arg TIM_DMABase_CNT 03166 * @arg TIM_DMABase_PSC 03167 * @arg TIM_DMABase_ARR 03168 * @arg TIM_DMABase_RCR 03169 * @arg TIM_DMABase_CCR1 03170 * @arg TIM_DMABase_CCR2 03171 * @arg TIM_DMABase_CCR3 03172 * @arg TIM_DMABase_CCR4 03173 * @arg TIM_DMABase_BDTR 03174 * @arg TIM_DMABase_DCR 03175 * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value 03176 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. 03177 * @retval None 03178 */ 03179 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) 03180 { 03181 /* Check the parameters */ 03182 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 03183 assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 03184 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); 03185 03186 /* Set the DMA Base and the DMA Burst Length */ 03187 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; 03188 } 03189 03190 /** 03191 * @brief Enables or disables the TIMx's DMA Requests. 03192 * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. 03193 * @param TIM_DMASource: specifies the DMA Request sources. 03194 * This parameter can be any combination of the following values: 03195 * @arg TIM_DMA_Update: TIM update Interrupt source 03196 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03197 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03198 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03199 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03200 * @arg TIM_DMA_COM: TIM Commutation DMA source 03201 * @arg TIM_DMA_Trigger: TIM Trigger DMA source 03202 * @param NewState: new state of the DMA Request sources. 03203 * This parameter can be: ENABLE or DISABLE. 03204 * @retval None 03205 */ 03206 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) 03207 { 03208 /* Check the parameters */ 03209 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 03210 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); 03211 assert_param(IS_FUNCTIONAL_STATE(NewState)); 03212 03213 if (NewState != DISABLE) 03214 { 03215 /* Enable the DMA sources */ 03216 TIMx->DIER |= TIM_DMASource; 03217 } 03218 else 03219 { 03220 /* Disable the DMA sources */ 03221 TIMx->DIER &= (uint16_t)~TIM_DMASource; 03222 } 03223 } 03224 03225 /** 03226 * @brief Selects the TIMx peripheral Capture Compare DMA source. 03227 * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. 03228 * @param NewState: new state of the Capture Compare DMA source 03229 * This parameter can be: ENABLE or DISABLE. 03230 * @retval None 03231 */ 03232 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) 03233 { 03234 /* Check the parameters */ 03235 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 03236 assert_param(IS_FUNCTIONAL_STATE(NewState)); 03237 03238 if (NewState != DISABLE) 03239 { 03240 /* Set the CCDS Bit */ 03241 TIMx->CR2 |= TIM_CR2_CCDS; 03242 } 03243 else 03244 { 03245 /* Reset the CCDS Bit */ 03246 TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; 03247 } 03248 } 03249 /** 03250 * @} 03251 */ 03252 03253 /** @defgroup TIM_Group6 Clocks management functions 03254 * @brief Clocks management functions 03255 * 03256 @verbatim 03257 =============================================================================== 03258 ##### Clocks management functions ##### 03259 =============================================================================== 03260 03261 @endverbatim 03262 * @{ 03263 */ 03264 03265 /** 03266 * @brief Configures the TIMx internal Clock 03267 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 03268 * peripheral. 03269 * @retval None 03270 */ 03271 void TIM_InternalClockConfig(TIM_TypeDef* TIMx) 03272 { 03273 /* Check the parameters */ 03274 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03275 03276 /* Disable slave mode to clock the prescaler directly with the internal clock */ 03277 TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; 03278 } 03279 03280 /** 03281 * @brief Configures the TIMx Internal Trigger as External Clock 03282 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 03283 * peripheral. 03284 * @param TIM_InputTriggerSource: Trigger source. 03285 * This parameter can be one of the following values: 03286 * @arg TIM_TS_ITR0: Internal Trigger 0 03287 * @arg TIM_TS_ITR1: Internal Trigger 1 03288 * @arg TIM_TS_ITR2: Internal Trigger 2 03289 * @arg TIM_TS_ITR3: Internal Trigger 3 03290 * @retval None 03291 */ 03292 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) 03293 { 03294 /* Check the parameters */ 03295 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03296 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); 03297 03298 /* Select the Internal Trigger */ 03299 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); 03300 03301 /* Select the External clock mode1 */ 03302 TIMx->SMCR |= TIM_SlaveMode_External1; 03303 } 03304 03305 /** 03306 * @brief Configures the TIMx Trigger as External Clock 03307 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 03308 * to select the TIM peripheral. 03309 * @param TIM_TIxExternalCLKSource: Trigger source. 03310 * This parameter can be one of the following values: 03311 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector 03312 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 03313 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 03314 * @param TIM_ICPolarity: specifies the TIx Polarity. 03315 * This parameter can be one of the following values: 03316 * @arg TIM_ICPolarity_Rising 03317 * @arg TIM_ICPolarity_Falling 03318 * @param ICFilter: specifies the filter value. 03319 * This parameter must be a value between 0x0 and 0xF. 03320 * @retval None 03321 */ 03322 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 03323 uint16_t TIM_ICPolarity, uint16_t ICFilter) 03324 { 03325 /* Check the parameters */ 03326 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03327 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); 03328 assert_param(IS_TIM_IC_FILTER(ICFilter)); 03329 03330 /* Configure the Timer Input Clock Source */ 03331 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) 03332 { 03333 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 03334 } 03335 else 03336 { 03337 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 03338 } 03339 /* Select the Trigger source */ 03340 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); 03341 /* Select the External clock mode1 */ 03342 TIMx->SMCR |= TIM_SlaveMode_External1; 03343 } 03344 03345 /** 03346 * @brief Configures the External clock Mode1 03347 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 03348 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 03349 * This parameter can be one of the following values: 03350 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 03351 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 03352 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 03353 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 03354 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 03355 * This parameter can be one of the following values: 03356 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 03357 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 03358 * @param ExtTRGFilter: External Trigger Filter. 03359 * This parameter must be a value between 0x00 and 0x0F 03360 * @retval None 03361 */ 03362 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 03363 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 03364 { 03365 uint16_t tmpsmcr = 0; 03366 03367 /* Check the parameters */ 03368 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 03369 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 03370 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 03371 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 03372 /* Configure the ETR Clock source */ 03373 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 03374 03375 /* Get the TIMx SMCR register value */ 03376 tmpsmcr = TIMx->SMCR; 03377 03378 /* Reset the SMS Bits */ 03379 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; 03380 03381 /* Select the External clock mode1 */ 03382 tmpsmcr |= TIM_SlaveMode_External1; 03383 03384 /* Select the Trigger selection : ETRF */ 03385 tmpsmcr &= (uint16_t)~TIM_SMCR_TS; 03386 tmpsmcr |= TIM_TS_ETRF; 03387 03388 /* Write to TIMx SMCR */ 03389 TIMx->SMCR = tmpsmcr; 03390 } 03391 03392 /** 03393 * @brief Configures the External clock Mode2 03394 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 03395 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 03396 * This parameter can be one of the following values: 03397 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 03398 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 03399 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 03400 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 03401 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 03402 * This parameter can be one of the following values: 03403 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 03404 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 03405 * @param ExtTRGFilter: External Trigger Filter. 03406 * This parameter must be a value between 0x00 and 0x0F 03407 * @retval None 03408 */ 03409 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 03410 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 03411 { 03412 /* Check the parameters */ 03413 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 03414 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 03415 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 03416 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 03417 03418 /* Configure the ETR Clock source */ 03419 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 03420 03421 /* Enable the External clock mode2 */ 03422 TIMx->SMCR |= TIM_SMCR_ECE; 03423 } 03424 /** 03425 * @} 03426 */ 03427 03428 /** @defgroup TIM_Group7 Synchronization management functions 03429 * @brief Synchronization management functions 03430 * 03431 @verbatim 03432 =============================================================================== 03433 ##### Synchronization management functions ##### 03434 =============================================================================== 03435 03436 *** TIM Driver: how to use it in synchronization Mode *** 03437 ========================================================= 03438 [..] Case of two/several Timers 03439 03440 (#) Configure the Master Timers using the following functions: 03441 (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 03442 (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 03443 (#) Configure the Slave Timers using the following functions: 03444 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 03445 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 03446 03447 [..] Case of Timers and external trigger(ETR pin) 03448 03449 (#) Configure the External trigger using this function: 03450 (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 03451 uint16_t ExtTRGFilter); 03452 (#) Configure the Slave Timers using the following functions: 03453 (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 03454 (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 03455 03456 @endverbatim 03457 * @{ 03458 */ 03459 03460 /** 03461 * @brief Selects the Input Trigger source 03462 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 03463 * to select the TIM peripheral. 03464 * @param TIM_InputTriggerSource: The Input Trigger source. 03465 * This parameter can be one of the following values: 03466 * @arg TIM_TS_ITR0: Internal Trigger 0 03467 * @arg TIM_TS_ITR1: Internal Trigger 1 03468 * @arg TIM_TS_ITR2: Internal Trigger 2 03469 * @arg TIM_TS_ITR3: Internal Trigger 3 03470 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector 03471 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 03472 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 03473 * @arg TIM_TS_ETRF: External Trigger input 03474 * @retval None 03475 */ 03476 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) 03477 { 03478 uint16_t tmpsmcr = 0; 03479 03480 /* Check the parameters */ 03481 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03482 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); 03483 03484 /* Get the TIMx SMCR register value */ 03485 tmpsmcr = TIMx->SMCR; 03486 03487 /* Reset the TS Bits */ 03488 tmpsmcr &= (uint16_t)~TIM_SMCR_TS; 03489 03490 /* Set the Input Trigger source */ 03491 tmpsmcr |= TIM_InputTriggerSource; 03492 03493 /* Write to TIMx SMCR */ 03494 TIMx->SMCR = tmpsmcr; 03495 } 03496 03497 /** 03498 * @brief Selects the TIMx Trigger Output Mode. 03499 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral. 03500 * 03501 * @param TIM_TRGOSource: specifies the Trigger Output source. 03502 * This parameter can be one of the following values: 03503 * 03504 * - For all TIMx 03505 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) 03506 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) 03507 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) 03508 * 03509 * - For all TIMx except TIM6 and TIM7 03510 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag 03511 * is to be set, as soon as a capture or compare match occurs(TRGO) 03512 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) 03513 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) 03514 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) 03515 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) 03516 * 03517 * @retval None 03518 */ 03519 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) 03520 { 03521 /* Check the parameters */ 03522 assert_param(IS_TIM_LIST7_PERIPH(TIMx)); 03523 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); 03524 03525 /* Reset the MMS Bits */ 03526 TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; 03527 /* Select the TRGO source */ 03528 TIMx->CR2 |= TIM_TRGOSource; 03529 } 03530 03531 /** 03532 * @brief Selects the TIMx Trigger Output Mode2 (TRGO2). 03533 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 03534 * 03535 * @param TIM_TRGO2Source: specifies the Trigger Output source. 03536 * This parameter can be one of the following values: 03537 * 03538 * - For all TIMx 03539 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2) 03540 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2) 03541 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2) 03542 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag 03543 * is to be set, as soon as a capture or compare match occurs(TRGO2) 03544 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2) 03545 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2) 03546 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2) 03547 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2) 03548 * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2) 03549 * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2) 03550 * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) 03551 * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) 03552 * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) 03553 * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) 03554 * 03555 * @retval None 03556 */ 03557 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source) 03558 { 03559 /* Check the parameters */ 03560 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 03561 assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source)); 03562 03563 /* Reset the MMS Bits */ 03564 TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2; 03565 /* Select the TRGO source */ 03566 TIMx->CR2 |= TIM_TRGO2Source; 03567 } 03568 03569 /** 03570 * @brief Selects the TIMx Slave Mode. 03571 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. 03572 * @param TIM_SlaveMode: specifies the Timer Slave Mode. 03573 * This parameter can be one of the following values: 03574 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize 03575 * the counter and triggers an update of the registers 03576 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high 03577 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI 03578 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter 03579 * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI) 03580 * reinitializes the counter, generates an update 03581 * of the registers and starts the counter. 03582 * @retval None 03583 */ 03584 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode) 03585 { 03586 /* Check the parameters */ 03587 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03588 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); 03589 03590 /* Reset the SMS Bits */ 03591 TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS; 03592 03593 /* Select the Slave Mode */ 03594 TIMx->SMCR |= (uint32_t)TIM_SlaveMode; 03595 } 03596 03597 /** 03598 * @brief Sets or Resets the TIMx Master/Slave Mode. 03599 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. 03600 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. 03601 * This parameter can be one of the following values: 03602 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer 03603 * and its slaves (through TRGO) 03604 * @arg TIM_MasterSlaveMode_Disable: No action 03605 * @retval None 03606 */ 03607 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) 03608 { 03609 /* Check the parameters */ 03610 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03611 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); 03612 03613 /* Reset the MSM Bit */ 03614 TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; 03615 03616 /* Set or Reset the MSM Bit */ 03617 TIMx->SMCR |= TIM_MasterSlaveMode; 03618 } 03619 03620 /** 03621 * @brief Configures the TIMx External Trigger (ETR). 03622 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. 03623 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 03624 * This parameter can be one of the following values: 03625 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 03626 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 03627 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 03628 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 03629 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 03630 * This parameter can be one of the following values: 03631 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 03632 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 03633 * @param ExtTRGFilter: External Trigger Filter. 03634 * This parameter must be a value between 0x00 and 0x0F 03635 * @retval None 03636 */ 03637 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 03638 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 03639 { 03640 uint16_t tmpsmcr = 0; 03641 03642 /* Check the parameters */ 03643 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 03644 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 03645 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 03646 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 03647 03648 tmpsmcr = TIMx->SMCR; 03649 03650 /* Reset the ETR Bits */ 03651 tmpsmcr &= SMCR_ETR_MASK; 03652 03653 /* Set the Prescaler, the Filter value and the Polarity */ 03654 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); 03655 03656 /* Write to TIMx SMCR */ 03657 TIMx->SMCR = tmpsmcr; 03658 } 03659 /** 03660 * @} 03661 */ 03662 03663 /** @defgroup TIM_Group8 Specific interface management functions 03664 * @brief Specific interface management functions 03665 * 03666 @verbatim 03667 =============================================================================== 03668 ##### Specific interface management functions ##### 03669 =============================================================================== 03670 03671 @endverbatim 03672 * @{ 03673 */ 03674 03675 /** 03676 * @brief Configures the TIMx Encoder Interface. 03677 * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM 03678 * peripheral. 03679 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. 03680 * This parameter can be one of the following values: 03681 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. 03682 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. 03683 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending 03684 * on the level of the other input. 03685 * @param TIM_IC1Polarity: specifies the IC1 Polarity 03686 * This parameter can be one of the following values: 03687 * @arg TIM_ICPolarity_Falling: IC Falling edge. 03688 * @arg TIM_ICPolarity_Rising: IC Rising edge. 03689 * @param TIM_IC2Polarity: specifies the IC2 Polarity 03690 * This parameter can be one of the following values: 03691 * @arg TIM_ICPolarity_Falling: IC Falling edge. 03692 * @arg TIM_ICPolarity_Rising: IC Rising edge. 03693 * @retval None 03694 */ 03695 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 03696 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) 03697 { 03698 uint16_t tmpsmcr = 0; 03699 uint16_t tmpccmr1 = 0; 03700 uint16_t tmpccer = 0; 03701 03702 /* Check the parameters */ 03703 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 03704 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); 03705 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); 03706 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); 03707 03708 /* Get the TIMx SMCR register value */ 03709 tmpsmcr = TIMx->SMCR; 03710 03711 /* Get the TIMx CCMR1 register value */ 03712 tmpccmr1 = TIMx->CCMR1; 03713 03714 /* Get the TIMx CCER register value */ 03715 tmpccer = TIMx->CCER; 03716 03717 /* Set the encoder Mode */ 03718 tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; 03719 tmpsmcr |= TIM_EncoderMode; 03720 03721 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 03722 tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); 03723 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; 03724 03725 /* Set the TI1 and the TI2 Polarities */ 03726 tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); 03727 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); 03728 03729 /* Write to TIMx SMCR */ 03730 TIMx->SMCR = tmpsmcr; 03731 03732 /* Write to TIMx CCMR1 */ 03733 TIMx->CCMR1 = tmpccmr1; 03734 03735 /* Write to TIMx CCER */ 03736 TIMx->CCER = tmpccer; 03737 } 03738 03739 /** 03740 * @brief Enables or disables the TIMx's Hall sensor interface. 03741 * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM 03742 * peripheral. 03743 * @param NewState: new state of the TIMx Hall sensor interface. 03744 * This parameter can be: ENABLE or DISABLE. 03745 * @retval None 03746 */ 03747 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) 03748 { 03749 /* Check the parameters */ 03750 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 03751 assert_param(IS_FUNCTIONAL_STATE(NewState)); 03752 03753 if (NewState != DISABLE) 03754 { 03755 /* Set the TI1S Bit */ 03756 TIMx->CR2 |= TIM_CR2_TI1S; 03757 } 03758 else 03759 { 03760 /* Reset the TI1S Bit */ 03761 TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; 03762 } 03763 } 03764 /** 03765 * @} 03766 */ 03767 03768 /** @defgroup TIM_Group9 Specific remapping management function 03769 * @brief Specific remapping management function 03770 * 03771 @verbatim 03772 =============================================================================== 03773 ##### Specific remapping management function ##### 03774 =============================================================================== 03775 03776 @endverbatim 03777 * @{ 03778 */ 03779 03780 /** 03781 * @brief Configures the TIM16 Remapping input Capabilities. 03782 * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral. 03783 * @param TIM_Remap: specifies the TIM input reampping source. 03784 * This parameter can be one of the following values: 03785 * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO. 03786 * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock. 03787 * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock. 03788 * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock. 03789 * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1. 03790 * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2. 03791 * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3. 03792 * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1. 03793 * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2. 03794 * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3. 03795 * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1. 03796 * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2. 03797 * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3. 03798 * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1. 03799 * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2. 03800 * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3. 03801 * @retval : None 03802 */ 03803 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) 03804 { 03805 /* Check the parameters */ 03806 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 03807 assert_param(IS_TIM_REMAP(TIM_Remap)); 03808 03809 /* Set the Timer remapping configuration */ 03810 TIMx->OR = TIM_Remap; 03811 } 03812 /** 03813 * @} 03814 */ 03815 03816 /** 03817 * @brief Configure the TI1 as Input. 03818 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 03819 * to select the TIM peripheral. 03820 * @param TIM_ICPolarity : The Input Polarity. 03821 * This parameter can be one of the following values: 03822 * @arg TIM_ICPolarity_Rising 03823 * @arg TIM_ICPolarity_Falling 03824 * @arg TIM_ICPolarity_BothEdge 03825 * @param TIM_ICSelection: specifies the input to be used. 03826 * This parameter can be one of the following values: 03827 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. 03828 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. 03829 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. 03830 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03831 * This parameter must be a value between 0x00 and 0x0F. 03832 * @retval None 03833 */ 03834 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03835 uint16_t TIM_ICFilter) 03836 { 03837 uint32_t tmpccmr1 = 0, tmpccer = 0; 03838 03839 /* Disable the Channel 1: Reset the CC1E Bit */ 03840 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; 03841 tmpccmr1 = TIMx->CCMR1; 03842 tmpccer = TIMx->CCER; 03843 03844 /* Select the Input and set the filter */ 03845 tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F); 03846 tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4)); 03847 03848 /* Select the Polarity and set the CC1E Bit */ 03849 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 03850 tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E); 03851 03852 /* Write to TIMx CCMR1 and CCER registers */ 03853 TIMx->CCMR1 = tmpccmr1; 03854 TIMx->CCER = tmpccer; 03855 } 03856 03857 /** 03858 * @brief Configure the TI2 as Input. 03859 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 03860 * peripheral. 03861 * @param TIM_ICPolarity : The Input Polarity. 03862 * This parameter can be one of the following values: 03863 * @arg TIM_ICPolarity_Rising 03864 * @arg TIM_ICPolarity_Falling 03865 * @arg TIM_ICPolarity_BothEdge 03866 * @param TIM_ICSelection: specifies the input to be used. 03867 * This parameter can be one of the following values: 03868 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. 03869 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. 03870 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. 03871 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03872 * This parameter must be a value between 0x00 and 0x0F. 03873 * @retval None 03874 */ 03875 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03876 uint16_t TIM_ICFilter) 03877 { 03878 uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; 03879 03880 /* Disable the Channel 2: Reset the CC2E Bit */ 03881 TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; 03882 tmpccmr1 = TIMx->CCMR1; 03883 tmpccer = TIMx->CCER; 03884 tmp = (uint16_t)(TIM_ICPolarity << 4); 03885 03886 /* Select the Input and set the filter */ 03887 tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F); 03888 tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12); 03889 tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8); 03890 03891 /* Select the Polarity and set the CC2E Bit */ 03892 tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 03893 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); 03894 03895 /* Write to TIMx CCMR1 and CCER registers */ 03896 TIMx->CCMR1 = tmpccmr1 ; 03897 TIMx->CCER = tmpccer; 03898 } 03899 03900 /** 03901 * @brief Configure the TI3 as Input. 03902 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 03903 * @param TIM_ICPolarity : The Input Polarity. 03904 * This parameter can be one of the following values: 03905 * @arg TIM_ICPolarity_Rising 03906 * @arg TIM_ICPolarity_Falling 03907 * @arg TIM_ICPolarity_BothEdge 03908 * @param TIM_ICSelection: specifies the input to be used. 03909 * This parameter can be one of the following values: 03910 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. 03911 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. 03912 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. 03913 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03914 * This parameter must be a value between 0x00 and 0x0F. 03915 * @retval None 03916 */ 03917 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03918 uint16_t TIM_ICFilter) 03919 { 03920 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 03921 03922 /* Disable the Channel 3: Reset the CC3E Bit */ 03923 TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; 03924 tmpccmr2 = TIMx->CCMR2; 03925 tmpccer = TIMx->CCER; 03926 tmp = (uint16_t)(TIM_ICPolarity << 8); 03927 03928 /* Select the Input and set the filter */ 03929 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); 03930 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 03931 03932 /* Select the Polarity and set the CC3E Bit */ 03933 tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 03934 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); 03935 03936 /* Write to TIMx CCMR2 and CCER registers */ 03937 TIMx->CCMR2 = tmpccmr2; 03938 TIMx->CCER = tmpccer; 03939 } 03940 03941 /** 03942 * @brief Configure the TI4 as Input. 03943 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 03944 * @param TIM_ICPolarity : The Input Polarity. 03945 * This parameter can be one of the following values: 03946 * @arg TIM_ICPolarity_Rising 03947 * @arg TIM_ICPolarity_Falling 03948 * @arg TIM_ICPolarity_BothEdge 03949 * @param TIM_ICSelection: specifies the input to be used. 03950 * This parameter can be one of the following values: 03951 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. 03952 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. 03953 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. 03954 * @param TIM_ICFilter: Specifies the Input Capture Filter. 03955 * This parameter must be a value between 0x00 and 0x0F. 03956 * @retval None 03957 */ 03958 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 03959 uint16_t TIM_ICFilter) 03960 { 03961 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 03962 03963 /* Disable the Channel 4: Reset the CC4E Bit */ 03964 TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; 03965 tmpccmr2 = TIMx->CCMR2; 03966 tmpccer = TIMx->CCER; 03967 tmp = (uint16_t)(TIM_ICPolarity << 12); 03968 03969 /* Select the Input and set the filter */ 03970 tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); 03971 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); 03972 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); 03973 03974 /* Select the Polarity and set the CC4E Bit */ 03975 tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 03976 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); 03977 03978 /* Write to TIMx CCMR2 and CCER registers */ 03979 TIMx->CCMR2 = tmpccmr2; 03980 TIMx->CCER = tmpccer ; 03981 } 03982 03983 /** 03984 * @} 03985 */ 03986 03987 /** 03988 * @} 03989 */ 03990 03991 /** 03992 * @} 03993 */ 03994 03995 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Wed Jul 13 2022 03:44:51 by
1.7.2