Ricardo Benitez
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mbed official
Revision 66:9c8f0e3462fb, committed 2013-08-19
- Comitter:
- bogdanm
- Date:
- Mon Aug 19 13:34:54 2013 +0300
- Parent:
- 65:5798e58a58b1
- Child:
- 67:a9913a65894f
- Commit message:
- New mbed library build with support for LPC1114.
Built from github tag 'mbed_lib_rev66'
Changed in this revision
--- a/CAN.h Mon Aug 12 13:17:46 2013 +0300
+++ b/CAN.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,229 +1,229 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** CANMessage class
- */
-class CANMessage : public CAN_Message {
-
-public:
- /** Creates empty CAN message.
- */
- CANMessage() {
- len = 8;
- type = CANData;
- format = CANStandard;
- id = 0;
- memset(data, 0, 8);
- }
-
- /** Creates CAN message with specific content.
- */
- CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
- len = _len & 0xF;
- type = _type;
- format = _format;
- id = _id;
- memcpy(data, _data, _len);
- }
-
- /** Creates CAN remote message.
- */
- CANMessage(int _id, CANFormat _format = CANStandard) {
- len = 0;
- type = CANRemote;
- format = _format;
- id = _id;
- memset(data, 0, 8);
- }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
- /** Creates an CAN interface connected to specific pins.
- *
- * @param rd read from transmitter
- * @param td transmit to transmitter
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * Ticker ticker;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- * CAN can1(p9, p10);
- * CAN can2(p30, p29);
- *
- * char counter = 0;
- *
- * void send() {
- * if(can1.write(CANMessage(1337, &counter, 1))) {
- * printf("Message sent: %d\n", counter);
- * counter++;
- * }
- * led1 = !led1;
- * }
- *
- * int main() {
- * ticker.attach(&send, 1);
- * CANMessage msg;
- * while(1) {
- * if(can2.read(msg)) {
- * printf("Message received: %d\n\n", msg.data[0]);
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- * @endcode
- */
- CAN(PinName rd, PinName td);
- virtual ~CAN();
-
- /** Set the frequency of the CAN interface
- *
- * @param hz The bus frequency in hertz
- *
- * @returns
- * 1 if successful,
- * 0 otherwise
- */
- int frequency(int hz);
-
- /** Write a CANMessage to the bus.
- *
- * @param msg The CANMessage to write.
- *
- * @returns
- * 0 if write failed,
- * 1 if write was successful
- */
- int write(CANMessage msg);
-
- /** Read a CANMessage from the bus.
- *
- * @param msg A CANMessage to read to.
- *
- * @returns
- * 0 if no message arrived,
- * 1 if message arrived
- */
- int read(CANMessage &msg);
-
- /** Reset CAN interface.
- *
- * To use after error overflow.
- */
- void reset();
-
- /** Puts or removes the CAN interface into silent monitoring mode
- *
- * @param silent boolean indicating whether to go into silent mode or not
- */
- void monitor(bool silent);
-
- enum Mode {
- Reset = 0,
- Normal,
- Silent,
- LocalTest,
- GlobalTest,
- SilentTest
- };
-
- /** Change CAN operation to the specified mode
- *
- * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
- *
- * @returns
- * 0 if mode change failed or unsupported,
- * 1 if mode change was successful
- */
- int mode(Mode mode);
-
- /** Returns number of read errors to detect read overflow errors.
- */
- unsigned char rderror();
-
- /** Returns number of write errors to detect write overflow errors.
- */
- unsigned char tderror();
-
- enum IrqType {
- RxIrq = 0,
- TxIrq,
- EwIrq,
- DoIrq,
- WuIrq,
- EpIrq,
- AlIrq,
- BeIrq,
- IdIrq
- };
-
- /** Attach a function to call whenever a CAN frame received interrupt is
- * generated.
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
- */
- void attach(void (*fptr)(void), IrqType type=RxIrq);
-
- /** Attach a member function to call whenever a CAN frame received interrupt
- * is generated.
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
- */
- template<typename T>
- void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- if((mptr != NULL) && (tptr != NULL)) {
- _irq[type].attach(tptr, mptr);
- can_irq_set(&_can, (CanIrqType)type, 1);
- }
- else {
- can_irq_set(&_can, (CanIrqType)type, 0);
- }
- }
-
- static void _irq_handler(uint32_t id, CanIrqType type);
-
-protected:
- can_t _can;
- FunctionPointer _irq[9];
-};
-
-} // namespace mbed
-
-#endif
-
-#endif // MBED_CAN_H
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard) {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Returns number of read errors to detect read overflow errors.
+ */
+ unsigned char rderror();
+
+ /** Returns number of write errors to detect write overflow errors.
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ }
+ else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ can_t _can;
+ FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
--- a/CallChain.h Mon Aug 12 13:17:46 2013 +0300
+++ b/CallChain.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,176 +1,176 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLCHAIN_H
-#define MBED_CALLCHAIN_H
-
-#include "FunctionPointer.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Group one or more functions in an instance of a CallChain, then call them in
- * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
- * but can be used for other purposes.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * CallChain chain;
- *
- * void first(void) {
- * printf("'first' function.\n");
- * }
- *
- * void second(void) {
- * printf("'second' function.\n");
- * }
- *
- * class Test {
- * public:
- * void f(void) {
- * printf("A::f (class member).\n");
- * }
- * };
- *
- * int main() {
- * Test test;
- *
- * chain.add(second);
- * chain.add_front(first);
- * chain.add(&test, &Test::f);
- * chain.call();
- * }
- * @endcode
- */
-
-typedef FunctionPointer* pFunctionPointer_t;
-
-class CallChain {
-public:
- /** Create an empty chain
- *
- * @param size (optional) Initial size of the chain
- */
- CallChain(int size = 4);
- virtual ~CallChain();
-
- /** Add a function at the end of the chain
- *
- * @param function A pointer to a void function
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add(void (*function)(void));
-
- /** Add a function at the end of the chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
- return common_add(new FunctionPointer(tptr, mptr));
- }
-
- /** Add a function at the beginning of the chain
- *
- * @param function A pointer to a void function
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_front(void (*function)(void));
-
- /** Add a function at the beginning of the chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
- return common_add_front(new FunctionPointer(tptr, mptr));
- }
-
- /** Get the number of functions in the chain
- */
- int size() const;
-
- /** Get a function object from the chain
- *
- * @param i function object index
- *
- * @returns
- * The function object at position 'i' in the chain
- */
- pFunctionPointer_t get(int i) const;
-
- /** Look for a function object in the call chain
- *
- * @param f the function object to search
- *
- * @returns
- * The index of the function object if found, -1 otherwise.
- */
- int find(pFunctionPointer_t f) const;
-
- /** Clear the call chain (remove all functions in the chain).
- */
- void clear();
-
- /** Remove a function object from the chain
- *
- * @arg f the function object to remove
- *
- * @returns
- * true if the function object was found and removed, false otherwise.
- */
- bool remove(pFunctionPointer_t f);
-
- /** Call all the functions in the chain in sequence
- */
- void call();
-
-#ifdef MBED_OPERATORS
- void operator ()(void) {
- call();
- }
- pFunctionPointer_t operator [](int i) const {
- return get(i);
- }
-#endif
-
-private:
- void _check_size();
- pFunctionPointer_t common_add(pFunctionPointer_t pf);
- pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
-
- pFunctionPointer_t* _chain;
- int _size;
- int _elements;
-};
-
-} // namespace mbed
-
-#endif
-
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+ /** Create an empty chain
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ CallChain(int size = 4);
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add(void (*function)(void));
+
+ /** Add a function at the end of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+ return common_add(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_front(void (*function)(void));
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+ return common_add_front(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Get the number of functions in the chain
+ */
+ int size() const;
+
+ /** Get a function object from the chain
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ */
+ void clear();
+
+ /** Remove a function object from the chain
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ */
+ void call();
+
+#ifdef MBED_OPERATORS
+ void operator ()(void) {
+ call();
+ }
+ pFunctionPointer_t operator [](int i) const {
+ return get(i);
+ }
+#endif
+
+private:
+ void _check_size();
+ pFunctionPointer_t common_add(pFunctionPointer_t pf);
+ pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+ pFunctionPointer_t* _chain;
+ int _size;
+ int _elements;
+};
+
+} // namespace mbed
+
+#endif
+
--- a/InterruptManager.h Mon Aug 12 13:17:46 2013 +0300
+++ b/InterruptManager.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,143 +1,143 @@
-#ifndef MBED_INTERRUPTMANAGER_H
-#define MBED_INTERRUPTMANAGER_H
-
-#include "cmsis.h"
-#include "CallChain.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Use this singleton if you need to chain interrupt handlers.
- *
- * Example (for LPC1768):
- * @code
- * #include "InterruptManager.h"
- * #include "mbed.h"
- *
- * Ticker flipper;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * void flip(void) {
- * led1 = !led1;
- * }
- *
- * void handler(void) {
- * led2 = !led1;
- * }
- *
- * int main() {
- * led1 = led2 = 0;
- * flipper.attach(&flip, 1.0);
- * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
- * }
- * @endcode
- */
-class InterruptManager {
-public:
- /** Return the only instance of this class
- */
- static InterruptManager* get();
-
- /** Destroy the current instance of the interrupt manager
- */
- static void destroy();
-
- /** Add a handler for an interrupt at the end of the handler list
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
- return add_common(function, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
- return add_common(function, irq, true);
- }
-
- /** Add a handler for an interrupt at the end of the handler list
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
- return add_common(tptr, mptr, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
- return add_common(tptr, mptr, irq, true);
- }
-
- /** Remove a handler from an interrupt
- *
- * @param handler the function object for the handler to remove
- * @param irq the interrupt number
- *
- * @returns
- * true if the handler was found and removed, false otherwise
- */
- bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
-
-private:
- InterruptManager();
- ~InterruptManager();
-
- // We declare the copy contructor and the assignment operator, but we don't
- // implement them. This way, if someone tries to copy/assign our instance,
- // he will get an error at compile time.
- InterruptManager(const InterruptManager&);
- InterruptManager& operator =(const InterruptManager&);
-
- template<typename T>
- pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
- int irq_pos = get_irq_index(irq);
- bool change = must_replace_vector(irq);
-
- pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
- if (change)
- NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
- return pf;
- }
-
- pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
- bool must_replace_vector(IRQn_Type irq);
- int get_irq_index(IRQn_Type irq);
- void irq_helper();
- void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
- static void static_irq_helper();
-
- CallChain* _chains[NVIC_NUM_VECTORS];
- static InterruptManager* _instance;
-};
-
-} // namespace mbed
-
-#endif
-
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+ /** Return the only instance of this class
+ */
+ static InterruptManager* get();
+
+ /** Destroy the current instance of the interrupt manager
+ */
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ // We declare the copy contructor and the assignment operator, but we don't
+ // implement them. This way, if someone tries to copy/assign our instance,
+ // he will get an error at compile time.
+ InterruptManager(const InterruptManager&);
+ InterruptManager& operator =(const InterruptManager&);
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+ static void static_irq_helper();
+
+ CallChain* _chains[NVIC_NUM_VECTORS];
+ static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+
--- a/Serial.h Mon Aug 12 13:17:46 2013 +0300
+++ b/Serial.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,228 +1,228 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "FunctionPointer.h"
-#include "serial_api.h"
-#include "CallChain.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- * pc.printf("Hello World\n");
- * }
- * @endcode
- */
-class Serial : public Stream {
-
-public:
- /** Create a Serial port, connected to the specified transmit and receive pins
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- *
- * @note
- * Either tx or rx may be specified as NC if unused
- */
- Serial(PinName tx, PinName rx, const char *name=NULL);
-
- /** Set the baud rate of the serial port
- *
- * @param baudrate The baudrate of the serial port (default = 9600).
- */
- void baud(int baudrate);
-
- enum Parity {
- None = 0,
- Odd,
- Even,
- Forced1,
- Forced0
- };
-
- enum IrqType {
- RxIrq = 0,
- TxIrq
- };
-
- /** Set the transmission format used by the Serial port
- *
- * @param bits The number of bits in a word (5-8; default = 8)
- * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
- * @param stop The number of stop bits (1 or 2; default = 1)
- */
- void format(int bits=8, Parity parity=Serial::None, int stop_bits=1);
-
- /** Determine if there is a character available to read
- *
- * @returns
- * 1 if there is a character available to read,
- * 0 otherwise
- */
- int readable();
-
- /** Determine if there is space available to write a character
- *
- * @returns
- * 1 if there is space to write a character,
- * 0 otherwise
- */
- int writeable();
-
- /** Attach a function to call whenever a serial interrupt is generated
- *
- * @param fptr A pointer to a void function, or 0 to set as none
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * The function object created for 'fptr'
- */
- pFunctionPointer_t attach(void (*fptr)(void), IrqType type=RxIrq);
-
- /** Add a function to be called when a serial interrupt is generated at the end of the call chain
- *
- * @param fptr the function to add
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * The function object created for 'fptr'
- */
- pFunctionPointer_t add_handler(void (*fptr)(void), IrqType type=RxIrq) {
- return add_handler_helper(fptr, type);
- }
-
- /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
- *
- * @param fptr the function to add
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * The function object created for 'fptr'
- */
- pFunctionPointer_t add_handler_front(void (*fptr)(void), IrqType type=RxIrq) {
- return add_handler_helper(fptr, type, true);
- }
-
- /** Attach a member function to call whenever a serial interrupt is generated
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @param
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- pFunctionPointer_t attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- if((mptr != NULL) && (tptr != NULL)) {
- _irq[type].clear();
- pFunctionPointer_t pf = _irq[type].add(tptr, mptr);
- serial_irq_set(&_serial, (SerialIrq)type, 1);
- return pf;
- }
- else
- return NULL;
- }
-
- /** Add a function to be called when a serial interrupt is generated at the end of the call chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * The function object created for 'fptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- return add_handler_helper(tptr, mptr, type);
- }
-
- /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
- *
- * @param tptr pointer to the object to call the member function on
- * @param mptr pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * The function object created for 'fptr'
- */
- template<typename T>
- pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
- return add_handler_helper(tptr, mptr, type, true);
- }
-
- /** Remove a function from the list of functions to be called when a serial interrupt is generated
- *
- * @param pf the function object to remove
- * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
- *
- * @returns
- * true if the function was found and removed, false otherwise
- */
- bool remove_handler(pFunctionPointer_t pf, IrqType type=RxIrq);
-
- /** Generate a break condition on the serial line
- */
- void send_break();
-
- static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-protected:
- virtual int _getc();
- virtual int _putc(int c);
- pFunctionPointer_t add_handler_helper(void (*function)(void), IrqType type, bool front=false);
-
- template<typename T>
- pFunctionPointer_t add_handler_helper(T* tptr, void (T::*mptr)(void), IrqType type, bool front=false) {
- if ((mptr != NULL) && (tptr != NULL)) {
- pFunctionPointer_t pf = front ? _irq[type].add_front(tptr, mptr) : _irq[type].add(tptr, mptr);
- serial_irq_set(&_serial, (SerialIrq)type, 1);
- return pf;
- }
- else
- return NULL;
- }
-
- serial_t _serial;
- CallChain _irq[2];
- int _baud;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+#include "CallChain.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public Stream {
+
+public:
+ /** Create a Serial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, const char *name=NULL);
+
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate);
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Forced1,
+ Forced0
+ };
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq
+ };
+
+ /** Set the transmission format used by the Serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (Serial::None, Serial::Odd, Serial::Even, Serial::Forced1, Serial::Forced0; default = Serial::None)
+ * @param stop The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits=8, Parity parity=Serial::None, int stop_bits=1);
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable();
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable();
+
+ /** Attach a function to call whenever a serial interrupt is generated
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Add a function to be called when a serial interrupt is generated at the end of the call chain
+ *
+ * @param fptr the function to add
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_handler(void (*fptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(fptr, type);
+ }
+
+ /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
+ *
+ * @param fptr the function to add
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ pFunctionPointer_t add_handler_front(void (*fptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(fptr, type, true);
+ }
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @param
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].clear();
+ pFunctionPointer_t pf = _irq[type].add(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ return pf;
+ }
+ else
+ return NULL;
+ }
+
+ /** Add a function to be called when a serial interrupt is generated at the end of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(tptr, mptr, type);
+ }
+
+ /** Add a function to be called when a serial interrupt is generated at the beginning of the call chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * The function object created for 'fptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ return add_handler_helper(tptr, mptr, type, true);
+ }
+
+ /** Remove a function from the list of functions to be called when a serial interrupt is generated
+ *
+ * @param pf the function object to remove
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ *
+ * @returns
+ * true if the function was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t pf, IrqType type=RxIrq);
+
+ /** Generate a break condition on the serial line
+ */
+ void send_break();
+
+ static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+ pFunctionPointer_t add_handler_helper(void (*function)(void), IrqType type, bool front=false);
+
+ template<typename T>
+ pFunctionPointer_t add_handler_helper(T* tptr, void (T::*mptr)(void), IrqType type, bool front=false) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ pFunctionPointer_t pf = front ? _irq[type].add_front(tptr, mptr) : _irq[type].add(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ return pf;
+ }
+ else
+ return NULL;
+ }
+
+ serial_t _serial;
+ CallChain _irq[2];
+ int _baud;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
--- a/TARGET_KL25Z/MKL25Z4.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/MKL25Z4.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,4155 +1,4155 @@
-/*
-** ###################################################################
-** Processor: MKL25Z128VLK4
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: KL25RM, Rev.1, Jun 2012
-** Version: rev. 1.1, 2012-06-21
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for MKL25Z4
-**
-** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2012-06-13)
-** Initial version.
-** - rev. 1.1 (2012-06-21)
-** Update according to reference manual rev. 1.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL25Z4.h
- * @version 1.1
- * @date 2012-06-21
- * @brief CMSIS Peripheral Access Layer for MKL25Z4
- *
- * CMSIS Peripheral Access Layer for MKL25Z4
- */
-
-#if !defined(MKL25Z4_H_)
-#define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100u
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
-
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-typedef enum IRQn {
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
-
- /* Device specific interrupts */
- DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
- DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
- DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
- DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
- Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
- FTFA_IRQn = 5, /**< FTFA interrupt */
- LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
- LLW_IRQn = 7, /**< Low Leakage Wakeup */
- I2C0_IRQn = 8, /**< I2C0 interrupt */
- I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
- SPI0_IRQn = 10, /**< SPI0 interrupt */
- SPI1_IRQn = 11, /**< SPI1 interrupt */
- UART0_IRQn = 12, /**< UART0 status/error interrupt */
- UART1_IRQn = 13, /**< UART1 status/error interrupt */
- UART2_IRQn = 14, /**< UART2 status/error interrupt */
- ADC0_IRQn = 15, /**< ADC0 interrupt */
- CMP0_IRQn = 16, /**< CMP0 interrupt */
- TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
- TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
- TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
- RTC_IRQn = 20, /**< RTC interrupt */
- RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
- PIT_IRQn = 22, /**< PIT timer interrupt */
- Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
- USB0_IRQn = 24, /**< USB0 interrupt */
- DAC0_IRQn = 25, /**< DAC interrupt */
- TSI0_IRQn = 26, /**< TSI0 interrupt */
- MCG_IRQn = 27, /**< MCG interrupt */
- LPTimer_IRQn = 28, /**< LPTimer interrupt */
- Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
- PORTA_IRQn = 30, /**< Port A interrupt */
- PORTD_IRQn = 31 /**< Port D interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M0 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
- * @{
- */
-
-#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
-#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
-#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-
-#include "core_cm0plus.h" /* Core Peripheral Access Layer */
-#include "system_MKL25Z4.h" /* Device specific configuration file */
-
-/**
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__CWCC__)
- #pragma push
- #pragma cpp_extensions on
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
- __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
- __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
- __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
- __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
- __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
- __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
- __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
- __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
- __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
- __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
- __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
- __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
- __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
- __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
- __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
- __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
- __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
- __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
- __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
- __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
- __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
- __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
- __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/* SC1 Bit Fields */
-#define ADC_SC1_ADCH_MASK 0x1Fu
-#define ADC_SC1_ADCH_SHIFT 0
-#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK 0x20u
-#define ADC_SC1_DIFF_SHIFT 5
-#define ADC_SC1_AIEN_MASK 0x40u
-#define ADC_SC1_AIEN_SHIFT 6
-#define ADC_SC1_COCO_MASK 0x80u
-#define ADC_SC1_COCO_SHIFT 7
-/* CFG1 Bit Fields */
-#define ADC_CFG1_ADICLK_MASK 0x3u
-#define ADC_CFG1_ADICLK_SHIFT 0
-#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK 0xCu
-#define ADC_CFG1_MODE_SHIFT 2
-#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK 0x10u
-#define ADC_CFG1_ADLSMP_SHIFT 4
-#define ADC_CFG1_ADIV_MASK 0x60u
-#define ADC_CFG1_ADIV_SHIFT 5
-#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK 0x80u
-#define ADC_CFG1_ADLPC_SHIFT 7
-/* CFG2 Bit Fields */
-#define ADC_CFG2_ADLSTS_MASK 0x3u
-#define ADC_CFG2_ADLSTS_SHIFT 0
-#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK 0x4u
-#define ADC_CFG2_ADHSC_SHIFT 2
-#define ADC_CFG2_ADACKEN_MASK 0x8u
-#define ADC_CFG2_ADACKEN_SHIFT 3
-#define ADC_CFG2_MUXSEL_MASK 0x10u
-#define ADC_CFG2_MUXSEL_SHIFT 4
-/* R Bit Fields */
-#define ADC_R_D_MASK 0xFFFFu
-#define ADC_R_D_SHIFT 0
-#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
-/* CV1 Bit Fields */
-#define ADC_CV1_CV_MASK 0xFFFFu
-#define ADC_CV1_CV_SHIFT 0
-#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
-/* CV2 Bit Fields */
-#define ADC_CV2_CV_MASK 0xFFFFu
-#define ADC_CV2_CV_SHIFT 0
-#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
-/* SC2 Bit Fields */
-#define ADC_SC2_REFSEL_MASK 0x3u
-#define ADC_SC2_REFSEL_SHIFT 0
-#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK 0x4u
-#define ADC_SC2_DMAEN_SHIFT 2
-#define ADC_SC2_ACREN_MASK 0x8u
-#define ADC_SC2_ACREN_SHIFT 3
-#define ADC_SC2_ACFGT_MASK 0x10u
-#define ADC_SC2_ACFGT_SHIFT 4
-#define ADC_SC2_ACFE_MASK 0x20u
-#define ADC_SC2_ACFE_SHIFT 5
-#define ADC_SC2_ADTRG_MASK 0x40u
-#define ADC_SC2_ADTRG_SHIFT 6
-#define ADC_SC2_ADACT_MASK 0x80u
-#define ADC_SC2_ADACT_SHIFT 7
-/* SC3 Bit Fields */
-#define ADC_SC3_AVGS_MASK 0x3u
-#define ADC_SC3_AVGS_SHIFT 0
-#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK 0x4u
-#define ADC_SC3_AVGE_SHIFT 2
-#define ADC_SC3_ADCO_MASK 0x8u
-#define ADC_SC3_ADCO_SHIFT 3
-#define ADC_SC3_CALF_MASK 0x40u
-#define ADC_SC3_CALF_SHIFT 6
-#define ADC_SC3_CAL_MASK 0x80u
-#define ADC_SC3_CAL_SHIFT 7
-/* OFS Bit Fields */
-#define ADC_OFS_OFS_MASK 0xFFFFu
-#define ADC_OFS_OFS_SHIFT 0
-#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
-/* PG Bit Fields */
-#define ADC_PG_PG_MASK 0xFFFFu
-#define ADC_PG_PG_SHIFT 0
-#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
-/* MG Bit Fields */
-#define ADC_MG_MG_MASK 0xFFFFu
-#define ADC_MG_MG_SHIFT 0
-#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
-/* CLPD Bit Fields */
-#define ADC_CLPD_CLPD_MASK 0x3Fu
-#define ADC_CLPD_CLPD_SHIFT 0
-#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
-/* CLPS Bit Fields */
-#define ADC_CLPS_CLPS_MASK 0x3Fu
-#define ADC_CLPS_CLPS_SHIFT 0
-#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
-/* CLP4 Bit Fields */
-#define ADC_CLP4_CLP4_MASK 0x3FFu
-#define ADC_CLP4_CLP4_SHIFT 0
-#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
-/* CLP3 Bit Fields */
-#define ADC_CLP3_CLP3_MASK 0x1FFu
-#define ADC_CLP3_CLP3_SHIFT 0
-#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
-/* CLP2 Bit Fields */
-#define ADC_CLP2_CLP2_MASK 0xFFu
-#define ADC_CLP2_CLP2_SHIFT 0
-#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
-/* CLP1 Bit Fields */
-#define ADC_CLP1_CLP1_MASK 0x7Fu
-#define ADC_CLP1_CLP1_SHIFT 0
-#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
-/* CLP0 Bit Fields */
-#define ADC_CLP0_CLP0_MASK 0x3Fu
-#define ADC_CLP0_CLP0_SHIFT 0
-#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
-/* CLMD Bit Fields */
-#define ADC_CLMD_CLMD_MASK 0x3Fu
-#define ADC_CLMD_CLMD_SHIFT 0
-#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
-/* CLMS Bit Fields */
-#define ADC_CLMS_CLMS_MASK 0x3Fu
-#define ADC_CLMS_CLMS_SHIFT 0
-#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
-/* CLM4 Bit Fields */
-#define ADC_CLM4_CLM4_MASK 0x3FFu
-#define ADC_CLM4_CLM4_SHIFT 0
-#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
-/* CLM3 Bit Fields */
-#define ADC_CLM3_CLM3_MASK 0x1FFu
-#define ADC_CLM3_CLM3_SHIFT 0
-#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
-/* CLM2 Bit Fields */
-#define ADC_CLM2_CLM2_MASK 0xFFu
-#define ADC_CLM2_CLM2_SHIFT 0
-#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
-/* CLM1 Bit Fields */
-#define ADC_CLM1_CLM1_MASK 0x7Fu
-#define ADC_CLM1_CLM1_SHIFT 0
-#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
-/* CLM0 Bit Fields */
-#define ADC_CLM0_CLM0_MASK 0x3Fu
-#define ADC_CLM0_CLM0_SHIFT 0
-#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
-
-/**
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x4003B000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASES { ADC0 }
-
-/**
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CMP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
- * @{
- */
-
-/** CMP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
- __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
- __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
- __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
- __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
- __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
-
-/* ----------------------------------------------------------------------------
- -- CMP Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup CMP_Register_Masks CMP Register Masks
- * @{
- */
-
-/* CR0 Bit Fields */
-#define CMP_CR0_HYSTCTR_MASK 0x3u
-#define CMP_CR0_HYSTCTR_SHIFT 0
-#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
-#define CMP_CR0_FILTER_CNT_MASK 0x70u
-#define CMP_CR0_FILTER_CNT_SHIFT 4
-#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
-/* CR1 Bit Fields */
-#define CMP_CR1_EN_MASK 0x1u
-#define CMP_CR1_EN_SHIFT 0
-#define CMP_CR1_OPE_MASK 0x2u
-#define CMP_CR1_OPE_SHIFT 1
-#define CMP_CR1_COS_MASK 0x4u
-#define CMP_CR1_COS_SHIFT 2
-#define CMP_CR1_INV_MASK 0x8u
-#define CMP_CR1_INV_SHIFT 3
-#define CMP_CR1_PMODE_MASK 0x10u
-#define CMP_CR1_PMODE_SHIFT 4
-#define CMP_CR1_TRIGM_MASK 0x20u
-#define CMP_CR1_TRIGM_SHIFT 5
-#define CMP_CR1_WE_MASK 0x40u
-#define CMP_CR1_WE_SHIFT 6
-#define CMP_CR1_SE_MASK 0x80u
-#define CMP_CR1_SE_SHIFT 7
-/* FPR Bit Fields */
-#define CMP_FPR_FILT_PER_MASK 0xFFu
-#define CMP_FPR_FILT_PER_SHIFT 0
-#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
-/* SCR Bit Fields */
-#define CMP_SCR_COUT_MASK 0x1u
-#define CMP_SCR_COUT_SHIFT 0
-#define CMP_SCR_CFF_MASK 0x2u
-#define CMP_SCR_CFF_SHIFT 1
-#define CMP_SCR_CFR_MASK 0x4u
-#define CMP_SCR_CFR_SHIFT 2
-#define CMP_SCR_IEF_MASK 0x8u
-#define CMP_SCR_IEF_SHIFT 3
-#define CMP_SCR_IER_MASK 0x10u
-#define CMP_SCR_IER_SHIFT 4
-#define CMP_SCR_DMAEN_MASK 0x40u
-#define CMP_SCR_DMAEN_SHIFT 6
-/* DACCR Bit Fields */
-#define CMP_DACCR_VOSEL_MASK 0x3Fu
-#define CMP_DACCR_VOSEL_SHIFT 0
-#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
-#define CMP_DACCR_VRSEL_MASK 0x40u
-#define CMP_DACCR_VRSEL_SHIFT 6
-#define CMP_DACCR_DACEN_MASK 0x80u
-#define CMP_DACCR_DACEN_SHIFT 7
-/* MUXCR Bit Fields */
-#define CMP_MUXCR_MSEL_MASK 0x7u
-#define CMP_MUXCR_MSEL_SHIFT 0
-#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
-#define CMP_MUXCR_PSEL_MASK 0x38u
-#define CMP_MUXCR_PSEL_SHIFT 3
-#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
-#define CMP_MUXCR_PSTM_MASK 0x40u
-#define CMP_MUXCR_PSTM_SHIFT 6
-
-/**
- * @}
- */ /* end of group CMP_Register_Masks */
-
-
-/* CMP - Peripheral instance base addresses */
-/** Peripheral CMP0 base address */
-#define CMP0_BASE (0x40073000u)
-/** Peripheral CMP0 base pointer */
-#define CMP0 ((CMP_Type *)CMP0_BASE)
-/** Array initializer of CMP peripheral base pointers */
-#define CMP_BASES { CMP0 }
-
-/**
- * @}
- */ /* end of group CMP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DAC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
- * @{
- */
-
-/** DAC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x2 */
- __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
- __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
- } DAT[2];
- uint8_t RESERVED_0[28];
- __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
- __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
- __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
- __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type;
-
-/* ----------------------------------------------------------------------------
- -- DAC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DAC_Register_Masks DAC Register Masks
- * @{
- */
-
-/* DATL Bit Fields */
-#define DAC_DATL_DATA0_MASK 0xFFu
-#define DAC_DATL_DATA0_SHIFT 0
-#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
-/* DATH Bit Fields */
-#define DAC_DATH_DATA1_MASK 0xFu
-#define DAC_DATH_DATA1_SHIFT 0
-#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
-/* SR Bit Fields */
-#define DAC_SR_DACBFRPBF_MASK 0x1u
-#define DAC_SR_DACBFRPBF_SHIFT 0
-#define DAC_SR_DACBFRPTF_MASK 0x2u
-#define DAC_SR_DACBFRPTF_SHIFT 1
-/* C0 Bit Fields */
-#define DAC_C0_DACBBIEN_MASK 0x1u
-#define DAC_C0_DACBBIEN_SHIFT 0
-#define DAC_C0_DACBTIEN_MASK 0x2u
-#define DAC_C0_DACBTIEN_SHIFT 1
-#define DAC_C0_LPEN_MASK 0x8u
-#define DAC_C0_LPEN_SHIFT 3
-#define DAC_C0_DACSWTRG_MASK 0x10u
-#define DAC_C0_DACSWTRG_SHIFT 4
-#define DAC_C0_DACTRGSEL_MASK 0x20u
-#define DAC_C0_DACTRGSEL_SHIFT 5
-#define DAC_C0_DACRFS_MASK 0x40u
-#define DAC_C0_DACRFS_SHIFT 6
-#define DAC_C0_DACEN_MASK 0x80u
-#define DAC_C0_DACEN_SHIFT 7
-/* C1 Bit Fields */
-#define DAC_C1_DACBFEN_MASK 0x1u
-#define DAC_C1_DACBFEN_SHIFT 0
-#define DAC_C1_DACBFMD_MASK 0x4u
-#define DAC_C1_DACBFMD_SHIFT 2
-#define DAC_C1_DMAEN_MASK 0x80u
-#define DAC_C1_DMAEN_SHIFT 7
-/* C2 Bit Fields */
-#define DAC_C2_DACBFUP_MASK 0x1u
-#define DAC_C2_DACBFUP_SHIFT 0
-#define DAC_C2_DACBFRP_MASK 0x10u
-#define DAC_C2_DACBFRP_SHIFT 4
-
-/**
- * @}
- */ /* end of group DAC_Register_Masks */
-
-
-/* DAC - Peripheral instance base addresses */
-/** Peripheral DAC0 base address */
-#define DAC0_BASE (0x4003F000u)
-/** Peripheral DAC0 base pointer */
-#define DAC0 ((DAC_Type *)DAC0_BASE)
-/** Array initializer of DAC peripheral base pointers */
-#define DAC_BASES { DAC0 }
-
-/**
- * @}
- */ /* end of group DAC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
- };
- uint8_t RESERVED_0[252];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
- __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
- union { /* offset: 0x108, array step: 0x10 */
- __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
- struct { /* offset: 0x108, array step: 0x10 */
- uint8_t RESERVED_0[3];
- __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
- } DMA_DSR_ACCESS8BIT;
- };
- __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
- } DMA[4];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/* REQC_ARR Bit Fields */
-#define DMA_REQC_ARR_DMAC_MASK 0xFu
-#define DMA_REQC_ARR_DMAC_SHIFT 0
-#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
-#define DMA_REQC_ARR_CFSM_MASK 0x80u
-#define DMA_REQC_ARR_CFSM_SHIFT 7
-/* SAR Bit Fields */
-#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
-#define DMA_SAR_SAR_SHIFT 0
-#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
-/* DAR Bit Fields */
-#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
-#define DMA_DAR_DAR_SHIFT 0
-#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
-/* DSR_BCR Bit Fields */
-#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
-#define DMA_DSR_BCR_BCR_SHIFT 0
-#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
-#define DMA_DSR_BCR_DONE_MASK 0x1000000u
-#define DMA_DSR_BCR_DONE_SHIFT 24
-#define DMA_DSR_BCR_BSY_MASK 0x2000000u
-#define DMA_DSR_BCR_BSY_SHIFT 25
-#define DMA_DSR_BCR_REQ_MASK 0x4000000u
-#define DMA_DSR_BCR_REQ_SHIFT 26
-#define DMA_DSR_BCR_BED_MASK 0x10000000u
-#define DMA_DSR_BCR_BED_SHIFT 28
-#define DMA_DSR_BCR_BES_MASK 0x20000000u
-#define DMA_DSR_BCR_BES_SHIFT 29
-#define DMA_DSR_BCR_CE_MASK 0x40000000u
-#define DMA_DSR_BCR_CE_SHIFT 30
-/* DCR Bit Fields */
-#define DMA_DCR_LCH2_MASK 0x3u
-#define DMA_DCR_LCH2_SHIFT 0
-#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
-#define DMA_DCR_LCH1_MASK 0xCu
-#define DMA_DCR_LCH1_SHIFT 2
-#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
-#define DMA_DCR_LINKCC_MASK 0x30u
-#define DMA_DCR_LINKCC_SHIFT 4
-#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
-#define DMA_DCR_D_REQ_MASK 0x80u
-#define DMA_DCR_D_REQ_SHIFT 7
-#define DMA_DCR_DMOD_MASK 0xF00u
-#define DMA_DCR_DMOD_SHIFT 8
-#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
-#define DMA_DCR_SMOD_MASK 0xF000u
-#define DMA_DCR_SMOD_SHIFT 12
-#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
-#define DMA_DCR_START_MASK 0x10000u
-#define DMA_DCR_START_SHIFT 16
-#define DMA_DCR_DSIZE_MASK 0x60000u
-#define DMA_DCR_DSIZE_SHIFT 17
-#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
-#define DMA_DCR_DINC_MASK 0x80000u
-#define DMA_DCR_DINC_SHIFT 19
-#define DMA_DCR_SSIZE_MASK 0x300000u
-#define DMA_DCR_SSIZE_SHIFT 20
-#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
-#define DMA_DCR_SINC_MASK 0x400000u
-#define DMA_DCR_SINC_SHIFT 22
-#define DMA_DCR_EADREQ_MASK 0x800000u
-#define DMA_DCR_EADREQ_SHIFT 23
-#define DMA_DCR_AA_MASK 0x10000000u
-#define DMA_DCR_AA_SHIFT 28
-#define DMA_DCR_CS_MASK 0x20000000u
-#define DMA_DCR_CS_SHIFT 29
-#define DMA_DCR_ERQ_MASK 0x40000000u
-#define DMA_DCR_ERQ_SHIFT 30
-#define DMA_DCR_EINT_MASK 0x80000000u
-#define DMA_DCR_EINT_SHIFT 31
-
-/**
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA base address */
-#define DMA_BASE (0x40008000u)
-/** Peripheral DMA base pointer */
-#define DMA0 ((DMA_Type *)DMA_BASE)
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASES { DMA0 }
-
-/**
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
- * @{
- */
-
-/** DMAMUX - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMAMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
- * @{
- */
-
-/* CHCFG Bit Fields */
-#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
-#define DMAMUX_CHCFG_SOURCE_SHIFT 0
-#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK 0x40u
-#define DMAMUX_CHCFG_TRIG_SHIFT 6
-#define DMAMUX_CHCFG_ENBL_MASK 0x80u
-#define DMAMUX_CHCFG_ENBL_SHIFT 7
-
-/**
- * @}
- */ /* end of group DMAMUX_Register_Masks */
-
-
-/* DMAMUX - Peripheral instance base addresses */
-/** Peripheral DMAMUX0 base address */
-#define DMAMUX0_BASE (0x40021000u)
-/** Peripheral DMAMUX0 base pointer */
-#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
-/** Array initializer of DMAMUX peripheral base pointers */
-#define DMAMUX_BASES { DMAMUX0 }
-
-/**
- * @}
- */ /* end of group DMAMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FGPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
- * @{
- */
-
-/** FGPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} FGPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- FGPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define FGPIO_PDOR_PDO_SHIFT 0
-#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define FGPIO_PSOR_PTSO_SHIFT 0
-#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define FGPIO_PCOR_PTCO_SHIFT 0
-#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define FGPIO_PTOR_PTTO_SHIFT 0
-#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define FGPIO_PDIR_PDI_SHIFT 0
-#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define FGPIO_PDDR_PDD_SHIFT 0
-#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group FGPIO_Register_Masks */
-
-
-/* FGPIO - Peripheral instance base addresses */
-/** Peripheral FPTA base address */
-#define FPTA_BASE (0xF80FF000u)
-/** Peripheral FPTA base pointer */
-#define FPTA ((FGPIO_Type *)FPTA_BASE)
-/** Peripheral FPTB base address */
-#define FPTB_BASE (0xF80FF040u)
-/** Peripheral FPTB base pointer */
-#define FPTB ((FGPIO_Type *)FPTB_BASE)
-/** Peripheral FPTC base address */
-#define FPTC_BASE (0xF80FF080u)
-/** Peripheral FPTC base pointer */
-#define FPTC ((FGPIO_Type *)FPTC_BASE)
-/** Peripheral FPTD base address */
-#define FPTD_BASE (0xF80FF0C0u)
-/** Peripheral FPTD base pointer */
-#define FPTD ((FGPIO_Type *)FPTD_BASE)
-/** Peripheral FPTE base address */
-#define FPTE_BASE (0xF80FF100u)
-/** Peripheral FPTE base pointer */
-#define FPTE ((FGPIO_Type *)FPTE_BASE)
-/** Array initializer of FGPIO peripheral base pointers */
-#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
-
-/**
- * @}
- */ /* end of group FGPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FTFA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
- * @{
- */
-
-/** FTFA - Register Layout Typedef */
-typedef struct {
- __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
- __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
- __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
- __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
- __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
- __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
- __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
- __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
- __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
- __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
- __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
- __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
- __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
- __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
- __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
- __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
- __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
- __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
- __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
- __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
-} FTFA_Type;
-
-/* ----------------------------------------------------------------------------
- -- FTFA Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup FTFA_Register_Masks FTFA Register Masks
- * @{
- */
-
-/* FSTAT Bit Fields */
-#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
-#define FTFA_FSTAT_MGSTAT0_SHIFT 0
-#define FTFA_FSTAT_FPVIOL_MASK 0x10u
-#define FTFA_FSTAT_FPVIOL_SHIFT 4
-#define FTFA_FSTAT_ACCERR_MASK 0x20u
-#define FTFA_FSTAT_ACCERR_SHIFT 5
-#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
-#define FTFA_FSTAT_RDCOLERR_SHIFT 6
-#define FTFA_FSTAT_CCIF_MASK 0x80u
-#define FTFA_FSTAT_CCIF_SHIFT 7
-/* FCNFG Bit Fields */
-#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
-#define FTFA_FCNFG_ERSSUSP_SHIFT 4
-#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
-#define FTFA_FCNFG_ERSAREQ_SHIFT 5
-#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
-#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
-#define FTFA_FCNFG_CCIE_MASK 0x80u
-#define FTFA_FCNFG_CCIE_SHIFT 7
-/* FSEC Bit Fields */
-#define FTFA_FSEC_SEC_MASK 0x3u
-#define FTFA_FSEC_SEC_SHIFT 0
-#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
-#define FTFA_FSEC_FSLACC_MASK 0xCu
-#define FTFA_FSEC_FSLACC_SHIFT 2
-#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
-#define FTFA_FSEC_MEEN_MASK 0x30u
-#define FTFA_FSEC_MEEN_SHIFT 4
-#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
-#define FTFA_FSEC_KEYEN_MASK 0xC0u
-#define FTFA_FSEC_KEYEN_SHIFT 6
-#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define FTFA_FOPT_OPT_MASK 0xFFu
-#define FTFA_FOPT_OPT_SHIFT 0
-#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
-/* FCCOB3 Bit Fields */
-#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB3_CCOBn_SHIFT 0
-#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
-/* FCCOB2 Bit Fields */
-#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB2_CCOBn_SHIFT 0
-#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
-/* FCCOB1 Bit Fields */
-#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB1_CCOBn_SHIFT 0
-#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
-/* FCCOB0 Bit Fields */
-#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB0_CCOBn_SHIFT 0
-#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
-/* FCCOB7 Bit Fields */
-#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB7_CCOBn_SHIFT 0
-#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
-/* FCCOB6 Bit Fields */
-#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB6_CCOBn_SHIFT 0
-#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
-/* FCCOB5 Bit Fields */
-#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB5_CCOBn_SHIFT 0
-#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
-/* FCCOB4 Bit Fields */
-#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB4_CCOBn_SHIFT 0
-#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
-/* FCCOBB Bit Fields */
-#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBB_CCOBn_SHIFT 0
-#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
-/* FCCOBA Bit Fields */
-#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
-#define FTFA_FCCOBA_CCOBn_SHIFT 0
-#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
-/* FCCOB9 Bit Fields */
-#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB9_CCOBn_SHIFT 0
-#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
-/* FCCOB8 Bit Fields */
-#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
-#define FTFA_FCCOB8_CCOBn_SHIFT 0
-#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
-/* FPROT3 Bit Fields */
-#define FTFA_FPROT3_PROT_MASK 0xFFu
-#define FTFA_FPROT3_PROT_SHIFT 0
-#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define FTFA_FPROT2_PROT_MASK 0xFFu
-#define FTFA_FPROT2_PROT_SHIFT 0
-#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define FTFA_FPROT1_PROT_MASK 0xFFu
-#define FTFA_FPROT1_PROT_SHIFT 0
-#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define FTFA_FPROT0_PROT_MASK 0xFFu
-#define FTFA_FPROT0_PROT_SHIFT 0
-#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
-
-/**
- * @}
- */ /* end of group FTFA_Register_Masks */
-
-
-/* FTFA - Peripheral instance base addresses */
-/** Peripheral FTFA base address */
-#define FTFA_BASE (0x40020000u)
-/** Peripheral FTFA base pointer */
-#define FTFA ((FTFA_Type *)FTFA_BASE)
-/** Array initializer of FTFA peripheral base pointers */
-#define FTFA_BASES { FTFA }
-
-/**
- * @}
- */ /* end of group FTFA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
- __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
- __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
- __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
- __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
- __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/* PDOR Bit Fields */
-#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
-#define GPIO_PDOR_PDO_SHIFT 0
-#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
-/* PSOR Bit Fields */
-#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
-#define GPIO_PSOR_PTSO_SHIFT 0
-#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
-/* PCOR Bit Fields */
-#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
-#define GPIO_PCOR_PTCO_SHIFT 0
-#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
-/* PTOR Bit Fields */
-#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
-#define GPIO_PTOR_PTTO_SHIFT 0
-#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
-/* PDIR Bit Fields */
-#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
-#define GPIO_PDIR_PDI_SHIFT 0
-#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
-/* PDDR Bit Fields */
-#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
-#define GPIO_PDDR_PDD_SHIFT 0
-#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
-
-/**
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE ((GPIO_Type *)PTE_BASE)
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
-
-/**
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
- __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
- __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
- __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
- __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
- __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
- __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
- __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
- __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
- __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
- __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
- __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/* A1 Bit Fields */
-#define I2C_A1_AD_MASK 0xFEu
-#define I2C_A1_AD_SHIFT 1
-#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
-/* F Bit Fields */
-#define I2C_F_ICR_MASK 0x3Fu
-#define I2C_F_ICR_SHIFT 0
-#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK 0xC0u
-#define I2C_F_MULT_SHIFT 6
-#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
-/* C1 Bit Fields */
-#define I2C_C1_DMAEN_MASK 0x1u
-#define I2C_C1_DMAEN_SHIFT 0
-#define I2C_C1_WUEN_MASK 0x2u
-#define I2C_C1_WUEN_SHIFT 1
-#define I2C_C1_RSTA_MASK 0x4u
-#define I2C_C1_RSTA_SHIFT 2
-#define I2C_C1_TXAK_MASK 0x8u
-#define I2C_C1_TXAK_SHIFT 3
-#define I2C_C1_TX_MASK 0x10u
-#define I2C_C1_TX_SHIFT 4
-#define I2C_C1_MST_MASK 0x20u
-#define I2C_C1_MST_SHIFT 5
-#define I2C_C1_IICIE_MASK 0x40u
-#define I2C_C1_IICIE_SHIFT 6
-#define I2C_C1_IICEN_MASK 0x80u
-#define I2C_C1_IICEN_SHIFT 7
-/* S Bit Fields */
-#define I2C_S_RXAK_MASK 0x1u
-#define I2C_S_RXAK_SHIFT 0
-#define I2C_S_IICIF_MASK 0x2u
-#define I2C_S_IICIF_SHIFT 1
-#define I2C_S_SRW_MASK 0x4u
-#define I2C_S_SRW_SHIFT 2
-#define I2C_S_RAM_MASK 0x8u
-#define I2C_S_RAM_SHIFT 3
-#define I2C_S_ARBL_MASK 0x10u
-#define I2C_S_ARBL_SHIFT 4
-#define I2C_S_BUSY_MASK 0x20u
-#define I2C_S_BUSY_SHIFT 5
-#define I2C_S_IAAS_MASK 0x40u
-#define I2C_S_IAAS_SHIFT 6
-#define I2C_S_TCF_MASK 0x80u
-#define I2C_S_TCF_SHIFT 7
-/* D Bit Fields */
-#define I2C_D_DATA_MASK 0xFFu
-#define I2C_D_DATA_SHIFT 0
-#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
-/* C2 Bit Fields */
-#define I2C_C2_AD_MASK 0x7u
-#define I2C_C2_AD_SHIFT 0
-#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK 0x8u
-#define I2C_C2_RMEN_SHIFT 3
-#define I2C_C2_SBRC_MASK 0x10u
-#define I2C_C2_SBRC_SHIFT 4
-#define I2C_C2_HDRS_MASK 0x20u
-#define I2C_C2_HDRS_SHIFT 5
-#define I2C_C2_ADEXT_MASK 0x40u
-#define I2C_C2_ADEXT_SHIFT 6
-#define I2C_C2_GCAEN_MASK 0x80u
-#define I2C_C2_GCAEN_SHIFT 7
-/* FLT Bit Fields */
-#define I2C_FLT_FLT_MASK 0x1Fu
-#define I2C_FLT_FLT_SHIFT 0
-#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
-#define I2C_FLT_STOPIE_MASK 0x20u
-#define I2C_FLT_STOPIE_SHIFT 5
-#define I2C_FLT_STOPF_MASK 0x40u
-#define I2C_FLT_STOPF_SHIFT 6
-#define I2C_FLT_SHEN_MASK 0x80u
-#define I2C_FLT_SHEN_SHIFT 7
-/* RA Bit Fields */
-#define I2C_RA_RAD_MASK 0xFEu
-#define I2C_RA_RAD_SHIFT 1
-#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
-/* SMB Bit Fields */
-#define I2C_SMB_SHTF2IE_MASK 0x1u
-#define I2C_SMB_SHTF2IE_SHIFT 0
-#define I2C_SMB_SHTF2_MASK 0x2u
-#define I2C_SMB_SHTF2_SHIFT 1
-#define I2C_SMB_SHTF1_MASK 0x4u
-#define I2C_SMB_SHTF1_SHIFT 2
-#define I2C_SMB_SLTF_MASK 0x8u
-#define I2C_SMB_SLTF_SHIFT 3
-#define I2C_SMB_TCKSEL_MASK 0x10u
-#define I2C_SMB_TCKSEL_SHIFT 4
-#define I2C_SMB_SIICAEN_MASK 0x20u
-#define I2C_SMB_SIICAEN_SHIFT 5
-#define I2C_SMB_ALERTEN_MASK 0x40u
-#define I2C_SMB_ALERTEN_SHIFT 6
-#define I2C_SMB_FACK_MASK 0x80u
-#define I2C_SMB_FACK_SHIFT 7
-/* A2 Bit Fields */
-#define I2C_A2_SAD_MASK 0xFEu
-#define I2C_A2_SAD_SHIFT 1
-#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
-/* SLTH Bit Fields */
-#define I2C_SLTH_SSLT_MASK 0xFFu
-#define I2C_SLTH_SSLT_SHIFT 0
-#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
-/* SLTL Bit Fields */
-#define I2C_SLTL_SSLT_MASK 0xFFu
-#define I2C_SLTL_SSLT_SHIFT 0
-#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
-
-/**
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40066000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x40067000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASES { I2C0, I2C1 }
-
-/**
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LLWU Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
- * @{
- */
-
-/** LLWU - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
- __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
- __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
- __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
- __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
- __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
- __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
- __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
- __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
- __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
-} LLWU_Type;
-
-/* ----------------------------------------------------------------------------
- -- LLWU Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LLWU_Register_Masks LLWU Register Masks
- * @{
- */
-
-/* PE1 Bit Fields */
-#define LLWU_PE1_WUPE0_MASK 0x3u
-#define LLWU_PE1_WUPE0_SHIFT 0
-#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
-#define LLWU_PE1_WUPE1_MASK 0xCu
-#define LLWU_PE1_WUPE1_SHIFT 2
-#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
-#define LLWU_PE1_WUPE2_MASK 0x30u
-#define LLWU_PE1_WUPE2_SHIFT 4
-#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
-#define LLWU_PE1_WUPE3_MASK 0xC0u
-#define LLWU_PE1_WUPE3_SHIFT 6
-#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
-/* PE2 Bit Fields */
-#define LLWU_PE2_WUPE4_MASK 0x3u
-#define LLWU_PE2_WUPE4_SHIFT 0
-#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
-#define LLWU_PE2_WUPE5_MASK 0xCu
-#define LLWU_PE2_WUPE5_SHIFT 2
-#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
-#define LLWU_PE2_WUPE6_MASK 0x30u
-#define LLWU_PE2_WUPE6_SHIFT 4
-#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
-#define LLWU_PE2_WUPE7_MASK 0xC0u
-#define LLWU_PE2_WUPE7_SHIFT 6
-#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
-/* PE3 Bit Fields */
-#define LLWU_PE3_WUPE8_MASK 0x3u
-#define LLWU_PE3_WUPE8_SHIFT 0
-#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
-#define LLWU_PE3_WUPE9_MASK 0xCu
-#define LLWU_PE3_WUPE9_SHIFT 2
-#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
-#define LLWU_PE3_WUPE10_MASK 0x30u
-#define LLWU_PE3_WUPE10_SHIFT 4
-#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
-#define LLWU_PE3_WUPE11_MASK 0xC0u
-#define LLWU_PE3_WUPE11_SHIFT 6
-#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
-/* PE4 Bit Fields */
-#define LLWU_PE4_WUPE12_MASK 0x3u
-#define LLWU_PE4_WUPE12_SHIFT 0
-#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
-#define LLWU_PE4_WUPE13_MASK 0xCu
-#define LLWU_PE4_WUPE13_SHIFT 2
-#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
-#define LLWU_PE4_WUPE14_MASK 0x30u
-#define LLWU_PE4_WUPE14_SHIFT 4
-#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
-#define LLWU_PE4_WUPE15_MASK 0xC0u
-#define LLWU_PE4_WUPE15_SHIFT 6
-#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
-/* ME Bit Fields */
-#define LLWU_ME_WUME0_MASK 0x1u
-#define LLWU_ME_WUME0_SHIFT 0
-#define LLWU_ME_WUME1_MASK 0x2u
-#define LLWU_ME_WUME1_SHIFT 1
-#define LLWU_ME_WUME2_MASK 0x4u
-#define LLWU_ME_WUME2_SHIFT 2
-#define LLWU_ME_WUME3_MASK 0x8u
-#define LLWU_ME_WUME3_SHIFT 3
-#define LLWU_ME_WUME4_MASK 0x10u
-#define LLWU_ME_WUME4_SHIFT 4
-#define LLWU_ME_WUME5_MASK 0x20u
-#define LLWU_ME_WUME5_SHIFT 5
-#define LLWU_ME_WUME6_MASK 0x40u
-#define LLWU_ME_WUME6_SHIFT 6
-#define LLWU_ME_WUME7_MASK 0x80u
-#define LLWU_ME_WUME7_SHIFT 7
-/* F1 Bit Fields */
-#define LLWU_F1_WUF0_MASK 0x1u
-#define LLWU_F1_WUF0_SHIFT 0
-#define LLWU_F1_WUF1_MASK 0x2u
-#define LLWU_F1_WUF1_SHIFT 1
-#define LLWU_F1_WUF2_MASK 0x4u
-#define LLWU_F1_WUF2_SHIFT 2
-#define LLWU_F1_WUF3_MASK 0x8u
-#define LLWU_F1_WUF3_SHIFT 3
-#define LLWU_F1_WUF4_MASK 0x10u
-#define LLWU_F1_WUF4_SHIFT 4
-#define LLWU_F1_WUF5_MASK 0x20u
-#define LLWU_F1_WUF5_SHIFT 5
-#define LLWU_F1_WUF6_MASK 0x40u
-#define LLWU_F1_WUF6_SHIFT 6
-#define LLWU_F1_WUF7_MASK 0x80u
-#define LLWU_F1_WUF7_SHIFT 7
-/* F2 Bit Fields */
-#define LLWU_F2_WUF8_MASK 0x1u
-#define LLWU_F2_WUF8_SHIFT 0
-#define LLWU_F2_WUF9_MASK 0x2u
-#define LLWU_F2_WUF9_SHIFT 1
-#define LLWU_F2_WUF10_MASK 0x4u
-#define LLWU_F2_WUF10_SHIFT 2
-#define LLWU_F2_WUF11_MASK 0x8u
-#define LLWU_F2_WUF11_SHIFT 3
-#define LLWU_F2_WUF12_MASK 0x10u
-#define LLWU_F2_WUF12_SHIFT 4
-#define LLWU_F2_WUF13_MASK 0x20u
-#define LLWU_F2_WUF13_SHIFT 5
-#define LLWU_F2_WUF14_MASK 0x40u
-#define LLWU_F2_WUF14_SHIFT 6
-#define LLWU_F2_WUF15_MASK 0x80u
-#define LLWU_F2_WUF15_SHIFT 7
-/* F3 Bit Fields */
-#define LLWU_F3_MWUF0_MASK 0x1u
-#define LLWU_F3_MWUF0_SHIFT 0
-#define LLWU_F3_MWUF1_MASK 0x2u
-#define LLWU_F3_MWUF1_SHIFT 1
-#define LLWU_F3_MWUF2_MASK 0x4u
-#define LLWU_F3_MWUF2_SHIFT 2
-#define LLWU_F3_MWUF3_MASK 0x8u
-#define LLWU_F3_MWUF3_SHIFT 3
-#define LLWU_F3_MWUF4_MASK 0x10u
-#define LLWU_F3_MWUF4_SHIFT 4
-#define LLWU_F3_MWUF5_MASK 0x20u
-#define LLWU_F3_MWUF5_SHIFT 5
-#define LLWU_F3_MWUF6_MASK 0x40u
-#define LLWU_F3_MWUF6_SHIFT 6
-#define LLWU_F3_MWUF7_MASK 0x80u
-#define LLWU_F3_MWUF7_SHIFT 7
-/* FILT1 Bit Fields */
-#define LLWU_FILT1_FILTSEL_MASK 0xFu
-#define LLWU_FILT1_FILTSEL_SHIFT 0
-#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
-#define LLWU_FILT1_FILTE_MASK 0x60u
-#define LLWU_FILT1_FILTE_SHIFT 5
-#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
-#define LLWU_FILT1_FILTF_MASK 0x80u
-#define LLWU_FILT1_FILTF_SHIFT 7
-/* FILT2 Bit Fields */
-#define LLWU_FILT2_FILTSEL_MASK 0xFu
-#define LLWU_FILT2_FILTSEL_SHIFT 0
-#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
-#define LLWU_FILT2_FILTE_MASK 0x60u
-#define LLWU_FILT2_FILTE_SHIFT 5
-#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
-#define LLWU_FILT2_FILTF_MASK 0x80u
-#define LLWU_FILT2_FILTF_SHIFT 7
-
-/**
- * @}
- */ /* end of group LLWU_Register_Masks */
-
-
-/* LLWU - Peripheral instance base addresses */
-/** Peripheral LLWU base address */
-#define LLWU_BASE (0x4007C000u)
-/** Peripheral LLWU base pointer */
-#define LLWU ((LLWU_Type *)LLWU_BASE)
-/** Array initializer of LLWU peripheral base pointers */
-#define LLWU_BASES { LLWU }
-
-/**
- * @}
- */ /* end of group LLWU_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
- * @{
- */
-
-/** LPTMR - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
- __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
- __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
- __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
-
-/* ----------------------------------------------------------------------------
- -- LPTMR Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
- * @{
- */
-
-/* CSR Bit Fields */
-#define LPTMR_CSR_TEN_MASK 0x1u
-#define LPTMR_CSR_TEN_SHIFT 0
-#define LPTMR_CSR_TMS_MASK 0x2u
-#define LPTMR_CSR_TMS_SHIFT 1
-#define LPTMR_CSR_TFC_MASK 0x4u
-#define LPTMR_CSR_TFC_SHIFT 2
-#define LPTMR_CSR_TPP_MASK 0x8u
-#define LPTMR_CSR_TPP_SHIFT 3
-#define LPTMR_CSR_TPS_MASK 0x30u
-#define LPTMR_CSR_TPS_SHIFT 4
-#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK 0x40u
-#define LPTMR_CSR_TIE_SHIFT 6
-#define LPTMR_CSR_TCF_MASK 0x80u
-#define LPTMR_CSR_TCF_SHIFT 7
-/* PSR Bit Fields */
-#define LPTMR_PSR_PCS_MASK 0x3u
-#define LPTMR_PSR_PCS_SHIFT 0
-#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK 0x4u
-#define LPTMR_PSR_PBYP_SHIFT 2
-#define LPTMR_PSR_PRESCALE_MASK 0x78u
-#define LPTMR_PSR_PRESCALE_SHIFT 3
-#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
-/* CMR Bit Fields */
-#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
-#define LPTMR_CMR_COMPARE_SHIFT 0
-#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
-/* CNR Bit Fields */
-#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
-#define LPTMR_CNR_COUNTER_SHIFT 0
-#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
-
-/**
- * @}
- */ /* end of group LPTMR_Register_Masks */
-
-
-/* LPTMR - Peripheral instance base addresses */
-/** Peripheral LPTMR0 base address */
-#define LPTMR0_BASE (0x40040000u)
-/** Peripheral LPTMR0 base pointer */
-#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
-/** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASES { LPTMR0 }
-
-/**
- * @}
- */ /* end of group LPTMR_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCG Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
- * @{
- */
-
-/** MCG - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
- __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
- __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
- __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
- __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
- __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
- __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
- uint8_t RESERVED_0[1];
- __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
- uint8_t RESERVED_1[1];
- __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
- __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
- __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
- __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
- __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
- __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
-} MCG_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCG Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCG_Register_Masks MCG Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define MCG_C1_IREFSTEN_MASK 0x1u
-#define MCG_C1_IREFSTEN_SHIFT 0
-#define MCG_C1_IRCLKEN_MASK 0x2u
-#define MCG_C1_IRCLKEN_SHIFT 1
-#define MCG_C1_IREFS_MASK 0x4u
-#define MCG_C1_IREFS_SHIFT 2
-#define MCG_C1_FRDIV_MASK 0x38u
-#define MCG_C1_FRDIV_SHIFT 3
-#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
-#define MCG_C1_CLKS_MASK 0xC0u
-#define MCG_C1_CLKS_SHIFT 6
-#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
-/* C2 Bit Fields */
-#define MCG_C2_IRCS_MASK 0x1u
-#define MCG_C2_IRCS_SHIFT 0
-#define MCG_C2_LP_MASK 0x2u
-#define MCG_C2_LP_SHIFT 1
-#define MCG_C2_EREFS0_MASK 0x4u
-#define MCG_C2_EREFS0_SHIFT 2
-#define MCG_C2_HGO0_MASK 0x8u
-#define MCG_C2_HGO0_SHIFT 3
-#define MCG_C2_RANGE0_MASK 0x30u
-#define MCG_C2_RANGE0_SHIFT 4
-#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
-#define MCG_C2_LOCRE0_MASK 0x80u
-#define MCG_C2_LOCRE0_SHIFT 7
-/* C3 Bit Fields */
-#define MCG_C3_SCTRIM_MASK 0xFFu
-#define MCG_C3_SCTRIM_SHIFT 0
-#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
-/* C4 Bit Fields */
-#define MCG_C4_SCFTRIM_MASK 0x1u
-#define MCG_C4_SCFTRIM_SHIFT 0
-#define MCG_C4_FCTRIM_MASK 0x1Eu
-#define MCG_C4_FCTRIM_SHIFT 1
-#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
-#define MCG_C4_DRST_DRS_MASK 0x60u
-#define MCG_C4_DRST_DRS_SHIFT 5
-#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
-#define MCG_C4_DMX32_MASK 0x80u
-#define MCG_C4_DMX32_SHIFT 7
-/* C5 Bit Fields */
-#define MCG_C5_PRDIV0_MASK 0x1Fu
-#define MCG_C5_PRDIV0_SHIFT 0
-#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
-#define MCG_C5_PLLSTEN0_MASK 0x20u
-#define MCG_C5_PLLSTEN0_SHIFT 5
-#define MCG_C5_PLLCLKEN0_MASK 0x40u
-#define MCG_C5_PLLCLKEN0_SHIFT 6
-/* C6 Bit Fields */
-#define MCG_C6_VDIV0_MASK 0x1Fu
-#define MCG_C6_VDIV0_SHIFT 0
-#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
-#define MCG_C6_CME0_MASK 0x20u
-#define MCG_C6_CME0_SHIFT 5
-#define MCG_C6_PLLS_MASK 0x40u
-#define MCG_C6_PLLS_SHIFT 6
-#define MCG_C6_LOLIE0_MASK 0x80u
-#define MCG_C6_LOLIE0_SHIFT 7
-/* S Bit Fields */
-#define MCG_S_IRCST_MASK 0x1u
-#define MCG_S_IRCST_SHIFT 0
-#define MCG_S_OSCINIT0_MASK 0x2u
-#define MCG_S_OSCINIT0_SHIFT 1
-#define MCG_S_CLKST_MASK 0xCu
-#define MCG_S_CLKST_SHIFT 2
-#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
-#define MCG_S_IREFST_MASK 0x10u
-#define MCG_S_IREFST_SHIFT 4
-#define MCG_S_PLLST_MASK 0x20u
-#define MCG_S_PLLST_SHIFT 5
-#define MCG_S_LOCK0_MASK 0x40u
-#define MCG_S_LOCK0_SHIFT 6
-#define MCG_S_LOLS_MASK 0x80u
-#define MCG_S_LOLS_SHIFT 7
-/* SC Bit Fields */
-#define MCG_SC_LOCS0_MASK 0x1u
-#define MCG_SC_LOCS0_SHIFT 0
-#define MCG_SC_FCRDIV_MASK 0xEu
-#define MCG_SC_FCRDIV_SHIFT 1
-#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
-#define MCG_SC_FLTPRSRV_MASK 0x10u
-#define MCG_SC_FLTPRSRV_SHIFT 4
-#define MCG_SC_ATMF_MASK 0x20u
-#define MCG_SC_ATMF_SHIFT 5
-#define MCG_SC_ATMS_MASK 0x40u
-#define MCG_SC_ATMS_SHIFT 6
-#define MCG_SC_ATME_MASK 0x80u
-#define MCG_SC_ATME_SHIFT 7
-/* ATCVH Bit Fields */
-#define MCG_ATCVH_ATCVH_MASK 0xFFu
-#define MCG_ATCVH_ATCVH_SHIFT 0
-#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
-/* ATCVL Bit Fields */
-#define MCG_ATCVL_ATCVL_MASK 0xFFu
-#define MCG_ATCVL_ATCVL_SHIFT 0
-#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
-/* C8 Bit Fields */
-#define MCG_C8_LOLRE_MASK 0x40u
-#define MCG_C8_LOLRE_SHIFT 6
-
-/**
- * @}
- */ /* end of group MCG_Register_Masks */
-
-
-/* MCG - Peripheral instance base addresses */
-/** Peripheral MCG base address */
-#define MCG_BASE (0x40064000u)
-/** Peripheral MCG base pointer */
-#define MCG ((MCG_Type *)MCG_BASE)
-/** Array initializer of MCG peripheral base pointers */
-#define MCG_BASES { MCG }
-
-/**
- * @}
- */ /* end of group MCG_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
- * @{
- */
-
-/** MCM - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[8];
- __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
- __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
- __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
- uint8_t RESERVED_1[48];
- __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- MCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MCM_Register_Masks MCM Register Masks
- * @{
- */
-
-/* PLASC Bit Fields */
-#define MCM_PLASC_ASC_MASK 0xFFu
-#define MCM_PLASC_ASC_SHIFT 0
-#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
-/* PLAMC Bit Fields */
-#define MCM_PLAMC_AMC_MASK 0xFFu
-#define MCM_PLAMC_AMC_SHIFT 0
-#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
-/* PLACR Bit Fields */
-#define MCM_PLACR_ARB_MASK 0x200u
-#define MCM_PLACR_ARB_SHIFT 9
-#define MCM_PLACR_CFCC_MASK 0x400u
-#define MCM_PLACR_CFCC_SHIFT 10
-#define MCM_PLACR_DFCDA_MASK 0x800u
-#define MCM_PLACR_DFCDA_SHIFT 11
-#define MCM_PLACR_DFCIC_MASK 0x1000u
-#define MCM_PLACR_DFCIC_SHIFT 12
-#define MCM_PLACR_DFCC_MASK 0x2000u
-#define MCM_PLACR_DFCC_SHIFT 13
-#define MCM_PLACR_EFDS_MASK 0x4000u
-#define MCM_PLACR_EFDS_SHIFT 14
-#define MCM_PLACR_DFCS_MASK 0x8000u
-#define MCM_PLACR_DFCS_SHIFT 15
-#define MCM_PLACR_ESFC_MASK 0x10000u
-#define MCM_PLACR_ESFC_SHIFT 16
-/* CPO Bit Fields */
-#define MCM_CPO_CPOREQ_MASK 0x1u
-#define MCM_CPO_CPOREQ_SHIFT 0
-#define MCM_CPO_CPOACK_MASK 0x2u
-#define MCM_CPO_CPOACK_SHIFT 1
-#define MCM_CPO_CPOWOI_MASK 0x4u
-#define MCM_CPO_CPOWOI_SHIFT 2
-
-/**
- * @}
- */ /* end of group MCM_Register_Masks */
-
-
-/* MCM - Peripheral instance base addresses */
-/** Peripheral MCM base address */
-#define MCM_BASE (0xF0003000u)
-/** Peripheral MCM base pointer */
-#define MCM ((MCM_Type *)MCM_BASE)
-/** Array initializer of MCM peripheral base pointers */
-#define MCM_BASES { MCM }
-
-/**
- * @}
- */ /* end of group MCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MTB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
- * @{
- */
-
-/** MTB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
- __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
- __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
- __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
- uint8_t RESERVED_0[3824];
- __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
- uint8_t RESERVED_1[156];
- __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
- __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
- uint8_t RESERVED_2[8];
- __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
- __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
- __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
- __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
- uint8_t RESERVED_3[8];
- __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
- __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
- __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTB_Type;
-
-/* ----------------------------------------------------------------------------
- -- MTB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTB_Register_Masks MTB Register Masks
- * @{
- */
-
-/* POSITION Bit Fields */
-#define MTB_POSITION_WRAP_MASK 0x4u
-#define MTB_POSITION_WRAP_SHIFT 2
-#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
-#define MTB_POSITION_POINTER_SHIFT 3
-#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
-/* MASTER Bit Fields */
-#define MTB_MASTER_MASK_MASK 0x1Fu
-#define MTB_MASTER_MASK_SHIFT 0
-#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
-#define MTB_MASTER_TSTARTEN_MASK 0x20u
-#define MTB_MASTER_TSTARTEN_SHIFT 5
-#define MTB_MASTER_TSTOPEN_MASK 0x40u
-#define MTB_MASTER_TSTOPEN_SHIFT 6
-#define MTB_MASTER_SFRWPRIV_MASK 0x80u
-#define MTB_MASTER_SFRWPRIV_SHIFT 7
-#define MTB_MASTER_RAMPRIV_MASK 0x100u
-#define MTB_MASTER_RAMPRIV_SHIFT 8
-#define MTB_MASTER_HALTREQ_MASK 0x200u
-#define MTB_MASTER_HALTREQ_SHIFT 9
-#define MTB_MASTER_EN_MASK 0x80000000u
-#define MTB_MASTER_EN_SHIFT 31
-/* FLOW Bit Fields */
-#define MTB_FLOW_AUTOSTOP_MASK 0x1u
-#define MTB_FLOW_AUTOSTOP_SHIFT 0
-#define MTB_FLOW_AUTOHALT_MASK 0x2u
-#define MTB_FLOW_AUTOHALT_SHIFT 1
-#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
-#define MTB_FLOW_WATERMARK_SHIFT 3
-#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
-/* BASE Bit Fields */
-#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
-#define MTB_BASE_BASEADDR_SHIFT 0
-#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
-/* MODECTRL Bit Fields */
-#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
-#define MTB_MODECTRL_MODECTRL_SHIFT 0
-#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
-/* TAGSET Bit Fields */
-#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
-#define MTB_TAGSET_TAGSET_SHIFT 0
-#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
-/* TAGCLEAR Bit Fields */
-#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
-#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
-#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
-/* LOCKACCESS Bit Fields */
-#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
-#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
-#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
-/* LOCKSTAT Bit Fields */
-#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
-#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
-#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
-/* AUTHSTAT Bit Fields */
-#define MTB_AUTHSTAT_BIT0_MASK 0x1u
-#define MTB_AUTHSTAT_BIT0_SHIFT 0
-#define MTB_AUTHSTAT_BIT1_MASK 0x2u
-#define MTB_AUTHSTAT_BIT1_SHIFT 1
-#define MTB_AUTHSTAT_BIT2_MASK 0x4u
-#define MTB_AUTHSTAT_BIT2_SHIFT 2
-#define MTB_AUTHSTAT_BIT3_MASK 0x8u
-#define MTB_AUTHSTAT_BIT3_SHIFT 3
-/* DEVICEARCH Bit Fields */
-#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
-#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
-#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
-/* DEVICECFG Bit Fields */
-#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
-#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
-#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
-#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
-#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
-#define MTB_PERIPHID_PERIPHID_SHIFT 0
-#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define MTB_COMPID_COMPID_SHIFT 0
-#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTB_Register_Masks */
-
-
-/* MTB - Peripheral instance base addresses */
-/** Peripheral MTB base address */
-#define MTB_BASE (0xF0000000u)
-/** Peripheral MTB base pointer */
-#define MTB ((MTB_Type *)MTB_BASE)
-/** Array initializer of MTB peripheral base pointers */
-#define MTB_BASES { MTB }
-
-/**
- * @}
- */ /* end of group MTB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MTBDWT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
- * @{
- */
-
-/** MTBDWT - Register Layout Typedef */
-typedef struct {
- __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
- uint8_t RESERVED_0[28];
- struct { /* offset: 0x20, array step: 0x10 */
- __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
- __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
- __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
- uint8_t RESERVED_0[4];
- } COMPARATOR[2];
- uint8_t RESERVED_1[448];
- __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
- uint8_t RESERVED_2[3524];
- __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
- __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
- __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} MTBDWT_Type;
-
-/* ----------------------------------------------------------------------------
- -- MTBDWT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
- * @{
- */
-
-/* CTRL Bit Fields */
-#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
-#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
-#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
-#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
-#define MTBDWT_CTRL_NUMCMP_SHIFT 28
-#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
-/* COMP Bit Fields */
-#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
-#define MTBDWT_COMP_COMP_SHIFT 0
-#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
-/* MASK Bit Fields */
-#define MTBDWT_MASK_MASK_MASK 0x1Fu
-#define MTBDWT_MASK_MASK_SHIFT 0
-#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
-/* FCT Bit Fields */
-#define MTBDWT_FCT_FUNCTION_MASK 0xFu
-#define MTBDWT_FCT_FUNCTION_SHIFT 0
-#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
-#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
-#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
-#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
-#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
-#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
-#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
-#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
-#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
-#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
-#define MTBDWT_FCT_MATCHED_SHIFT 24
-/* TBCTRL Bit Fields */
-#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
-#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
-#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
-#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
-#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
-#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
-#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
-/* DEVICECFG Bit Fields */
-#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
-#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
-#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
-/* DEVICETYPID Bit Fields */
-#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
-#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
-#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
-/* PERIPHID Bit Fields */
-#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
-#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
-#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define MTBDWT_COMPID_COMPID_SHIFT 0
-#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group MTBDWT_Register_Masks */
-
-
-/* MTBDWT - Peripheral instance base addresses */
-/** Peripheral MTBDWT base address */
-#define MTBDWT_BASE (0xF0001000u)
-/** Peripheral MTBDWT base pointer */
-#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
-/** Array initializer of MTBDWT peripheral base pointers */
-#define MTBDWT_BASES { MTBDWT }
-
-/**
- * @}
- */ /* end of group MTBDWT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- NV Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
- * @{
- */
-
-/** NV - Register Layout Typedef */
-typedef struct {
- __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
- __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
- __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
- __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
- __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
- __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
- __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
- __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
- __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
- __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
- __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
- __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
- __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
- __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
-} NV_Type;
-
-/* ----------------------------------------------------------------------------
- -- NV Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup NV_Register_Masks NV Register Masks
- * @{
- */
-
-/* BACKKEY3 Bit Fields */
-#define NV_BACKKEY3_KEY_MASK 0xFFu
-#define NV_BACKKEY3_KEY_SHIFT 0
-#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
-/* BACKKEY2 Bit Fields */
-#define NV_BACKKEY2_KEY_MASK 0xFFu
-#define NV_BACKKEY2_KEY_SHIFT 0
-#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
-/* BACKKEY1 Bit Fields */
-#define NV_BACKKEY1_KEY_MASK 0xFFu
-#define NV_BACKKEY1_KEY_SHIFT 0
-#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
-/* BACKKEY0 Bit Fields */
-#define NV_BACKKEY0_KEY_MASK 0xFFu
-#define NV_BACKKEY0_KEY_SHIFT 0
-#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
-/* BACKKEY7 Bit Fields */
-#define NV_BACKKEY7_KEY_MASK 0xFFu
-#define NV_BACKKEY7_KEY_SHIFT 0
-#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
-/* BACKKEY6 Bit Fields */
-#define NV_BACKKEY6_KEY_MASK 0xFFu
-#define NV_BACKKEY6_KEY_SHIFT 0
-#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
-/* BACKKEY5 Bit Fields */
-#define NV_BACKKEY5_KEY_MASK 0xFFu
-#define NV_BACKKEY5_KEY_SHIFT 0
-#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
-/* BACKKEY4 Bit Fields */
-#define NV_BACKKEY4_KEY_MASK 0xFFu
-#define NV_BACKKEY4_KEY_SHIFT 0
-#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
-/* FPROT3 Bit Fields */
-#define NV_FPROT3_PROT_MASK 0xFFu
-#define NV_FPROT3_PROT_SHIFT 0
-#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
-/* FPROT2 Bit Fields */
-#define NV_FPROT2_PROT_MASK 0xFFu
-#define NV_FPROT2_PROT_SHIFT 0
-#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
-/* FPROT1 Bit Fields */
-#define NV_FPROT1_PROT_MASK 0xFFu
-#define NV_FPROT1_PROT_SHIFT 0
-#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
-/* FPROT0 Bit Fields */
-#define NV_FPROT0_PROT_MASK 0xFFu
-#define NV_FPROT0_PROT_SHIFT 0
-#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
-/* FSEC Bit Fields */
-#define NV_FSEC_SEC_MASK 0x3u
-#define NV_FSEC_SEC_SHIFT 0
-#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
-#define NV_FSEC_FSLACC_MASK 0xCu
-#define NV_FSEC_FSLACC_SHIFT 2
-#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
-#define NV_FSEC_MEEN_MASK 0x30u
-#define NV_FSEC_MEEN_SHIFT 4
-#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
-#define NV_FSEC_KEYEN_MASK 0xC0u
-#define NV_FSEC_KEYEN_SHIFT 6
-#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
-/* FOPT Bit Fields */
-#define NV_FOPT_LPBOOT0_MASK 0x1u
-#define NV_FOPT_LPBOOT0_SHIFT 0
-#define NV_FOPT_NMI_DIS_MASK 0x4u
-#define NV_FOPT_NMI_DIS_SHIFT 2
-#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
-#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
-#define NV_FOPT_LPBOOT1_MASK 0x10u
-#define NV_FOPT_LPBOOT1_SHIFT 4
-#define NV_FOPT_FAST_INIT_MASK 0x20u
-#define NV_FOPT_FAST_INIT_SHIFT 5
-
-/**
- * @}
- */ /* end of group NV_Register_Masks */
-
-
-/* NV - Peripheral instance base addresses */
-/** Peripheral FTFA_FlashConfig base address */
-#define FTFA_FlashConfig_BASE (0x400u)
-/** Peripheral FTFA_FlashConfig base pointer */
-#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
-/** Array initializer of NV peripheral base pointers */
-#define NV_BASES { FTFA_FlashConfig }
-
-/**
- * @}
- */ /* end of group NV_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OSC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
- * @{
- */
-
-/** OSC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
-} OSC_Type;
-
-/* ----------------------------------------------------------------------------
- -- OSC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup OSC_Register_Masks OSC Register Masks
- * @{
- */
-
-/* CR Bit Fields */
-#define OSC_CR_SC16P_MASK 0x1u
-#define OSC_CR_SC16P_SHIFT 0
-#define OSC_CR_SC8P_MASK 0x2u
-#define OSC_CR_SC8P_SHIFT 1
-#define OSC_CR_SC4P_MASK 0x4u
-#define OSC_CR_SC4P_SHIFT 2
-#define OSC_CR_SC2P_MASK 0x8u
-#define OSC_CR_SC2P_SHIFT 3
-#define OSC_CR_EREFSTEN_MASK 0x20u
-#define OSC_CR_EREFSTEN_SHIFT 5
-#define OSC_CR_ERCLKEN_MASK 0x80u
-#define OSC_CR_ERCLKEN_SHIFT 7
-
-/**
- * @}
- */ /* end of group OSC_Register_Masks */
-
-
-/* OSC - Peripheral instance base addresses */
-/** Peripheral OSC0 base address */
-#define OSC0_BASE (0x40065000u)
-/** Peripheral OSC0 base pointer */
-#define OSC0 ((OSC_Type *)OSC0_BASE)
-/** Array initializer of OSC peripheral base pointers */
-#define OSC_BASES { OSC0 }
-
-/**
- * @}
- */ /* end of group OSC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
- * @{
- */
-
-/** PIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
- uint8_t RESERVED_0[220];
- __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
- __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
- uint8_t RESERVED_1[24];
- struct { /* offset: 0x100, array step: 0x10 */
- __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
- __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
- __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
- __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
- } CHANNEL[2];
-} PIT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PIT_Register_Masks PIT Register Masks
- * @{
- */
-
-/* MCR Bit Fields */
-#define PIT_MCR_FRZ_MASK 0x1u
-#define PIT_MCR_FRZ_SHIFT 0
-#define PIT_MCR_MDIS_MASK 0x2u
-#define PIT_MCR_MDIS_SHIFT 1
-/* LTMR64H Bit Fields */
-#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
-#define PIT_LTMR64H_LTH_SHIFT 0
-#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
-/* LTMR64L Bit Fields */
-#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
-#define PIT_LTMR64L_LTL_SHIFT 0
-#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
-/* LDVAL Bit Fields */
-#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
-#define PIT_LDVAL_TSV_SHIFT 0
-#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
-/* CVAL Bit Fields */
-#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
-#define PIT_CVAL_TVL_SHIFT 0
-#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
-/* TCTRL Bit Fields */
-#define PIT_TCTRL_TEN_MASK 0x1u
-#define PIT_TCTRL_TEN_SHIFT 0
-#define PIT_TCTRL_TIE_MASK 0x2u
-#define PIT_TCTRL_TIE_SHIFT 1
-#define PIT_TCTRL_CHN_MASK 0x4u
-#define PIT_TCTRL_CHN_SHIFT 2
-/* TFLG Bit Fields */
-#define PIT_TFLG_TIF_MASK 0x1u
-#define PIT_TFLG_TIF_SHIFT 0
-
-/**
- * @}
- */ /* end of group PIT_Register_Masks */
-
-
-/* PIT - Peripheral instance base addresses */
-/** Peripheral PIT base address */
-#define PIT_BASE (0x40037000u)
-/** Peripheral PIT base pointer */
-#define PIT ((PIT_Type *)PIT_BASE)
-/** Array initializer of PIT peripheral base pointers */
-#define PIT_BASES { PIT }
-
-/**
- * @}
- */ /* end of group PIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
- * @{
- */
-
-/** PMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
- __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
- __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- PMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PMC_Register_Masks PMC Register Masks
- * @{
- */
-
-/* LVDSC1 Bit Fields */
-#define PMC_LVDSC1_LVDV_MASK 0x3u
-#define PMC_LVDSC1_LVDV_SHIFT 0
-#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
-#define PMC_LVDSC1_LVDRE_MASK 0x10u
-#define PMC_LVDSC1_LVDRE_SHIFT 4
-#define PMC_LVDSC1_LVDIE_MASK 0x20u
-#define PMC_LVDSC1_LVDIE_SHIFT 5
-#define PMC_LVDSC1_LVDACK_MASK 0x40u
-#define PMC_LVDSC1_LVDACK_SHIFT 6
-#define PMC_LVDSC1_LVDF_MASK 0x80u
-#define PMC_LVDSC1_LVDF_SHIFT 7
-/* LVDSC2 Bit Fields */
-#define PMC_LVDSC2_LVWV_MASK 0x3u
-#define PMC_LVDSC2_LVWV_SHIFT 0
-#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
-#define PMC_LVDSC2_LVWIE_MASK 0x20u
-#define PMC_LVDSC2_LVWIE_SHIFT 5
-#define PMC_LVDSC2_LVWACK_MASK 0x40u
-#define PMC_LVDSC2_LVWACK_SHIFT 6
-#define PMC_LVDSC2_LVWF_MASK 0x80u
-#define PMC_LVDSC2_LVWF_SHIFT 7
-/* REGSC Bit Fields */
-#define PMC_REGSC_BGBE_MASK 0x1u
-#define PMC_REGSC_BGBE_SHIFT 0
-#define PMC_REGSC_REGONS_MASK 0x4u
-#define PMC_REGSC_REGONS_SHIFT 2
-#define PMC_REGSC_ACKISO_MASK 0x8u
-#define PMC_REGSC_ACKISO_SHIFT 3
-#define PMC_REGSC_BGEN_MASK 0x10u
-#define PMC_REGSC_BGEN_SHIFT 4
-
-/**
- * @}
- */ /* end of group PMC_Register_Masks */
-
-
-/* PMC - Peripheral instance base addresses */
-/** Peripheral PMC base address */
-#define PMC_BASE (0x4007D000u)
-/** Peripheral PMC base pointer */
-#define PMC ((PMC_Type *)PMC_BASE)
-/** Array initializer of PMC peripheral base pointers */
-#define PMC_BASES { PMC }
-
-/**
- * @}
- */ /* end of group PMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PORT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
- * @{
- */
-
-/** PORT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
- __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
- __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
- uint8_t RESERVED_0[24];
- __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
-} PORT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PORT Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup PORT_Register_Masks PORT Register Masks
- * @{
- */
-
-/* PCR Bit Fields */
-#define PORT_PCR_PS_MASK 0x1u
-#define PORT_PCR_PS_SHIFT 0
-#define PORT_PCR_PE_MASK 0x2u
-#define PORT_PCR_PE_SHIFT 1
-#define PORT_PCR_SRE_MASK 0x4u
-#define PORT_PCR_SRE_SHIFT 2
-#define PORT_PCR_PFE_MASK 0x10u
-#define PORT_PCR_PFE_SHIFT 4
-#define PORT_PCR_DSE_MASK 0x40u
-#define PORT_PCR_DSE_SHIFT 6
-#define PORT_PCR_MUX_MASK 0x700u
-#define PORT_PCR_MUX_SHIFT 8
-#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
-#define PORT_PCR_IRQC_MASK 0xF0000u
-#define PORT_PCR_IRQC_SHIFT 16
-#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
-#define PORT_PCR_ISF_MASK 0x1000000u
-#define PORT_PCR_ISF_SHIFT 24
-/* GPCLR Bit Fields */
-#define PORT_GPCLR_GPWD_MASK 0xFFFFu
-#define PORT_GPCLR_GPWD_SHIFT 0
-#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
-#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCLR_GPWE_SHIFT 16
-#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
-/* GPCHR Bit Fields */
-#define PORT_GPCHR_GPWD_MASK 0xFFFFu
-#define PORT_GPCHR_GPWD_SHIFT 0
-#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
-#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
-#define PORT_GPCHR_GPWE_SHIFT 16
-#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
-/* ISFR Bit Fields */
-#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
-#define PORT_ISFR_ISF_SHIFT 0
-#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
-
-/**
- * @}
- */ /* end of group PORT_Register_Masks */
-
-
-/* PORT - Peripheral instance base addresses */
-/** Peripheral PORTA base address */
-#define PORTA_BASE (0x40049000u)
-/** Peripheral PORTA base pointer */
-#define PORTA ((PORT_Type *)PORTA_BASE)
-/** Peripheral PORTB base address */
-#define PORTB_BASE (0x4004A000u)
-/** Peripheral PORTB base pointer */
-#define PORTB ((PORT_Type *)PORTB_BASE)
-/** Peripheral PORTC base address */
-#define PORTC_BASE (0x4004B000u)
-/** Peripheral PORTC base pointer */
-#define PORTC ((PORT_Type *)PORTC_BASE)
-/** Peripheral PORTD base address */
-#define PORTD_BASE (0x4004C000u)
-/** Peripheral PORTD base pointer */
-#define PORTD ((PORT_Type *)PORTD_BASE)
-/** Peripheral PORTE base address */
-#define PORTE_BASE (0x4004D000u)
-/** Peripheral PORTE base pointer */
-#define PORTE ((PORT_Type *)PORTE_BASE)
-/** Array initializer of PORT peripheral base pointers */
-#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
-
-/**
- * @}
- */ /* end of group PORT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RCM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
- * @{
- */
-
-/** RCM - Register Layout Typedef */
-typedef struct {
- __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
- __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
- uint8_t RESERVED_0[2];
- __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
- __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
-} RCM_Type;
-
-/* ----------------------------------------------------------------------------
- -- RCM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RCM_Register_Masks RCM Register Masks
- * @{
- */
-
-/* SRS0 Bit Fields */
-#define RCM_SRS0_WAKEUP_MASK 0x1u
-#define RCM_SRS0_WAKEUP_SHIFT 0
-#define RCM_SRS0_LVD_MASK 0x2u
-#define RCM_SRS0_LVD_SHIFT 1
-#define RCM_SRS0_LOC_MASK 0x4u
-#define RCM_SRS0_LOC_SHIFT 2
-#define RCM_SRS0_LOL_MASK 0x8u
-#define RCM_SRS0_LOL_SHIFT 3
-#define RCM_SRS0_WDOG_MASK 0x20u
-#define RCM_SRS0_WDOG_SHIFT 5
-#define RCM_SRS0_PIN_MASK 0x40u
-#define RCM_SRS0_PIN_SHIFT 6
-#define RCM_SRS0_POR_MASK 0x80u
-#define RCM_SRS0_POR_SHIFT 7
-/* SRS1 Bit Fields */
-#define RCM_SRS1_LOCKUP_MASK 0x2u
-#define RCM_SRS1_LOCKUP_SHIFT 1
-#define RCM_SRS1_SW_MASK 0x4u
-#define RCM_SRS1_SW_SHIFT 2
-#define RCM_SRS1_MDM_AP_MASK 0x8u
-#define RCM_SRS1_MDM_AP_SHIFT 3
-#define RCM_SRS1_SACKERR_MASK 0x20u
-#define RCM_SRS1_SACKERR_SHIFT 5
-/* RPFC Bit Fields */
-#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
-#define RCM_RPFC_RSTFLTSRW_SHIFT 0
-#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
-#define RCM_RPFC_RSTFLTSS_MASK 0x4u
-#define RCM_RPFC_RSTFLTSS_SHIFT 2
-/* RPFW Bit Fields */
-#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
-#define RCM_RPFW_RSTFLTSEL_SHIFT 0
-#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
-
-/**
- * @}
- */ /* end of group RCM_Register_Masks */
-
-
-/* RCM - Peripheral instance base addresses */
-/** Peripheral RCM base address */
-#define RCM_BASE (0x4007F000u)
-/** Peripheral RCM base pointer */
-#define RCM ((RCM_Type *)RCM_BASE)
-/** Array initializer of RCM peripheral base pointers */
-#define RCM_BASES { RCM }
-
-/**
- * @}
- */ /* end of group RCM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- ROM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
- * @{
- */
-
-/** ROM - Register Layout Typedef */
-typedef struct {
- __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
- __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
- uint8_t RESERVED_0[4028];
- __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
- __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
- __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
- __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
- __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
- __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
- __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
- __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
- __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
- __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
-} ROM_Type;
-
-/* ----------------------------------------------------------------------------
- -- ROM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup ROM_Register_Masks ROM Register Masks
- * @{
- */
-
-/* ENTRY Bit Fields */
-#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
-#define ROM_ENTRY_ENTRY_SHIFT 0
-#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
-/* TABLEMARK Bit Fields */
-#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
-#define ROM_TABLEMARK_MARK_SHIFT 0
-#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
-/* SYSACCESS Bit Fields */
-#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
-#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
-#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
-/* PERIPHID4 Bit Fields */
-#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID4_PERIPHID_SHIFT 0
-#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
-/* PERIPHID5 Bit Fields */
-#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID5_PERIPHID_SHIFT 0
-#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
-/* PERIPHID6 Bit Fields */
-#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID6_PERIPHID_SHIFT 0
-#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
-/* PERIPHID7 Bit Fields */
-#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID7_PERIPHID_SHIFT 0
-#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
-/* PERIPHID0 Bit Fields */
-#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID0_PERIPHID_SHIFT 0
-#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
-/* PERIPHID1 Bit Fields */
-#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID1_PERIPHID_SHIFT 0
-#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
-/* PERIPHID2 Bit Fields */
-#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID2_PERIPHID_SHIFT 0
-#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
-/* PERIPHID3 Bit Fields */
-#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
-#define ROM_PERIPHID3_PERIPHID_SHIFT 0
-#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
-/* COMPID Bit Fields */
-#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
-#define ROM_COMPID_COMPID_SHIFT 0
-#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
-
-/**
- * @}
- */ /* end of group ROM_Register_Masks */
-
-
-/* ROM - Peripheral instance base addresses */
-/** Peripheral ROM base address */
-#define ROM_BASE (0xF0002000u)
-/** Peripheral ROM base pointer */
-#define ROM ((ROM_Type *)ROM_BASE)
-/** Array initializer of ROM peripheral base pointers */
-#define ROM_BASES { ROM }
-
-/**
- * @}
- */ /* end of group ROM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
- __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
- __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
- __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
- __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
- __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
- __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
- __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/* TSR Bit Fields */
-#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
-#define RTC_TSR_TSR_SHIFT 0
-#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
-/* TPR Bit Fields */
-#define RTC_TPR_TPR_MASK 0xFFFFu
-#define RTC_TPR_TPR_SHIFT 0
-#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
-/* TAR Bit Fields */
-#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
-#define RTC_TAR_TAR_SHIFT 0
-#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
-/* TCR Bit Fields */
-#define RTC_TCR_TCR_MASK 0xFFu
-#define RTC_TCR_TCR_SHIFT 0
-#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
-#define RTC_TCR_CIR_MASK 0xFF00u
-#define RTC_TCR_CIR_SHIFT 8
-#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
-#define RTC_TCR_TCV_MASK 0xFF0000u
-#define RTC_TCR_TCV_SHIFT 16
-#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
-#define RTC_TCR_CIC_MASK 0xFF000000u
-#define RTC_TCR_CIC_SHIFT 24
-#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
-/* CR Bit Fields */
-#define RTC_CR_SWR_MASK 0x1u
-#define RTC_CR_SWR_SHIFT 0
-#define RTC_CR_WPE_MASK 0x2u
-#define RTC_CR_WPE_SHIFT 1
-#define RTC_CR_SUP_MASK 0x4u
-#define RTC_CR_SUP_SHIFT 2
-#define RTC_CR_UM_MASK 0x8u
-#define RTC_CR_UM_SHIFT 3
-#define RTC_CR_OSCE_MASK 0x100u
-#define RTC_CR_OSCE_SHIFT 8
-#define RTC_CR_CLKO_MASK 0x200u
-#define RTC_CR_CLKO_SHIFT 9
-#define RTC_CR_SC16P_MASK 0x400u
-#define RTC_CR_SC16P_SHIFT 10
-#define RTC_CR_SC8P_MASK 0x800u
-#define RTC_CR_SC8P_SHIFT 11
-#define RTC_CR_SC4P_MASK 0x1000u
-#define RTC_CR_SC4P_SHIFT 12
-#define RTC_CR_SC2P_MASK 0x2000u
-#define RTC_CR_SC2P_SHIFT 13
-/* SR Bit Fields */
-#define RTC_SR_TIF_MASK 0x1u
-#define RTC_SR_TIF_SHIFT 0
-#define RTC_SR_TOF_MASK 0x2u
-#define RTC_SR_TOF_SHIFT 1
-#define RTC_SR_TAF_MASK 0x4u
-#define RTC_SR_TAF_SHIFT 2
-#define RTC_SR_TCE_MASK 0x10u
-#define RTC_SR_TCE_SHIFT 4
-/* LR Bit Fields */
-#define RTC_LR_TCL_MASK 0x8u
-#define RTC_LR_TCL_SHIFT 3
-#define RTC_LR_CRL_MASK 0x10u
-#define RTC_LR_CRL_SHIFT 4
-#define RTC_LR_SRL_MASK 0x20u
-#define RTC_LR_SRL_SHIFT 5
-#define RTC_LR_LRL_MASK 0x40u
-#define RTC_LR_LRL_SHIFT 6
-/* IER Bit Fields */
-#define RTC_IER_TIIE_MASK 0x1u
-#define RTC_IER_TIIE_SHIFT 0
-#define RTC_IER_TOIE_MASK 0x2u
-#define RTC_IER_TOIE_SHIFT 1
-#define RTC_IER_TAIE_MASK 0x4u
-#define RTC_IER_TAIE_SHIFT 2
-#define RTC_IER_TSIE_MASK 0x10u
-#define RTC_IER_TSIE_SHIFT 4
-#define RTC_IER_WPON_MASK 0x80u
-#define RTC_IER_WPON_SHIFT 7
-
-/**
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4003D000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASES { RTC }
-
-/**
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SIM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
- * @{
- */
-
-/** SIM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
- __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
- uint8_t RESERVED_0[4092];
- __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
- __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
- uint8_t RESERVED_2[4];
- __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
- uint8_t RESERVED_3[8];
- __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
- uint8_t RESERVED_4[12];
- __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
- __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
- __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
- __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
- __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
- uint8_t RESERVED_5[4];
- __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
- __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
- uint8_t RESERVED_6[4];
- __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
- __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
- __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
- uint8_t RESERVED_7[156];
- __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
- __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
-} SIM_Type;
-
-/* ----------------------------------------------------------------------------
- -- SIM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SIM_Register_Masks SIM Register Masks
- * @{
- */
-
-/* SOPT1 Bit Fields */
-#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
-#define SIM_SOPT1_OSC32KSEL_SHIFT 18
-#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
-#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
-#define SIM_SOPT1_USBVSTBY_SHIFT 29
-#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
-#define SIM_SOPT1_USBSSTBY_SHIFT 30
-#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
-#define SIM_SOPT1_USBREGEN_SHIFT 31
-/* SOPT1CFG Bit Fields */
-#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
-#define SIM_SOPT1CFG_URWE_SHIFT 24
-#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
-#define SIM_SOPT1CFG_UVSWE_SHIFT 25
-#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
-#define SIM_SOPT1CFG_USSWE_SHIFT 26
-/* SOPT2 Bit Fields */
-#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
-#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
-#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
-#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
-#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
-#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
-#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
-#define SIM_SOPT2_USBSRC_MASK 0x40000u
-#define SIM_SOPT2_USBSRC_SHIFT 18
-#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
-#define SIM_SOPT2_TPMSRC_SHIFT 24
-#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
-#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
-#define SIM_SOPT2_UART0SRC_SHIFT 26
-#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
-/* SOPT4 Bit Fields */
-#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
-#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
-#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
-#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
-#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
-#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
-#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
-#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
-#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
-#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
-/* SOPT5 Bit Fields */
-#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
-#define SIM_SOPT5_UART0TXSRC_SHIFT 0
-#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
-#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
-#define SIM_SOPT5_UART0RXSRC_SHIFT 2
-#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
-#define SIM_SOPT5_UART1TXSRC_SHIFT 4
-#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
-#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
-#define SIM_SOPT5_UART1RXSRC_SHIFT 6
-#define SIM_SOPT5_UART0ODE_MASK 0x10000u
-#define SIM_SOPT5_UART0ODE_SHIFT 16
-#define SIM_SOPT5_UART1ODE_MASK 0x20000u
-#define SIM_SOPT5_UART1ODE_SHIFT 17
-#define SIM_SOPT5_UART2ODE_MASK 0x40000u
-#define SIM_SOPT5_UART2ODE_SHIFT 18
-/* SOPT7 Bit Fields */
-#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
-#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
-#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
-#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
-#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
-#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
-#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
-/* SDID Bit Fields */
-#define SIM_SDID_PINID_MASK 0xFu
-#define SIM_SDID_PINID_SHIFT 0
-#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
-#define SIM_SDID_DIEID_MASK 0xF80u
-#define SIM_SDID_DIEID_SHIFT 7
-#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
-#define SIM_SDID_REVID_MASK 0xF000u
-#define SIM_SDID_REVID_SHIFT 12
-#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
-#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
-#define SIM_SDID_SRAMSIZE_SHIFT 16
-#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
-#define SIM_SDID_SERIESID_MASK 0xF00000u
-#define SIM_SDID_SERIESID_SHIFT 20
-#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
-#define SIM_SDID_SUBFAMID_MASK 0xF000000u
-#define SIM_SDID_SUBFAMID_SHIFT 24
-#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
-#define SIM_SDID_FAMID_MASK 0xF0000000u
-#define SIM_SDID_FAMID_SHIFT 28
-#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
-/* SCGC4 Bit Fields */
-#define SIM_SCGC4_I2C0_MASK 0x40u
-#define SIM_SCGC4_I2C0_SHIFT 6
-#define SIM_SCGC4_I2C1_MASK 0x80u
-#define SIM_SCGC4_I2C1_SHIFT 7
-#define SIM_SCGC4_UART0_MASK 0x400u
-#define SIM_SCGC4_UART0_SHIFT 10
-#define SIM_SCGC4_UART1_MASK 0x800u
-#define SIM_SCGC4_UART1_SHIFT 11
-#define SIM_SCGC4_UART2_MASK 0x1000u
-#define SIM_SCGC4_UART2_SHIFT 12
-#define SIM_SCGC4_USBOTG_MASK 0x40000u
-#define SIM_SCGC4_USBOTG_SHIFT 18
-#define SIM_SCGC4_CMP_MASK 0x80000u
-#define SIM_SCGC4_CMP_SHIFT 19
-#define SIM_SCGC4_SPI0_MASK 0x400000u
-#define SIM_SCGC4_SPI0_SHIFT 22
-#define SIM_SCGC4_SPI1_MASK 0x800000u
-#define SIM_SCGC4_SPI1_SHIFT 23
-/* SCGC5 Bit Fields */
-#define SIM_SCGC5_LPTMR_MASK 0x1u
-#define SIM_SCGC5_LPTMR_SHIFT 0
-#define SIM_SCGC5_TSI_MASK 0x20u
-#define SIM_SCGC5_TSI_SHIFT 5
-#define SIM_SCGC5_PORTA_MASK 0x200u
-#define SIM_SCGC5_PORTA_SHIFT 9
-#define SIM_SCGC5_PORTB_MASK 0x400u
-#define SIM_SCGC5_PORTB_SHIFT 10
-#define SIM_SCGC5_PORTC_MASK 0x800u
-#define SIM_SCGC5_PORTC_SHIFT 11
-#define SIM_SCGC5_PORTD_MASK 0x1000u
-#define SIM_SCGC5_PORTD_SHIFT 12
-#define SIM_SCGC5_PORTE_MASK 0x2000u
-#define SIM_SCGC5_PORTE_SHIFT 13
-/* SCGC6 Bit Fields */
-#define SIM_SCGC6_FTF_MASK 0x1u
-#define SIM_SCGC6_FTF_SHIFT 0
-#define SIM_SCGC6_DMAMUX_MASK 0x2u
-#define SIM_SCGC6_DMAMUX_SHIFT 1
-#define SIM_SCGC6_PIT_MASK 0x800000u
-#define SIM_SCGC6_PIT_SHIFT 23
-#define SIM_SCGC6_TPM0_MASK 0x1000000u
-#define SIM_SCGC6_TPM0_SHIFT 24
-#define SIM_SCGC6_TPM1_MASK 0x2000000u
-#define SIM_SCGC6_TPM1_SHIFT 25
-#define SIM_SCGC6_TPM2_MASK 0x4000000u
-#define SIM_SCGC6_TPM2_SHIFT 26
-#define SIM_SCGC6_ADC0_MASK 0x8000000u
-#define SIM_SCGC6_ADC0_SHIFT 27
-#define SIM_SCGC6_RTC_MASK 0x20000000u
-#define SIM_SCGC6_RTC_SHIFT 29
-#define SIM_SCGC6_DAC0_MASK 0x80000000u
-#define SIM_SCGC6_DAC0_SHIFT 31
-/* SCGC7 Bit Fields */
-#define SIM_SCGC7_DMA_MASK 0x100u
-#define SIM_SCGC7_DMA_SHIFT 8
-/* CLKDIV1 Bit Fields */
-#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
-#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
-#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
-#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
-#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
-#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
-/* FCFG1 Bit Fields */
-#define SIM_FCFG1_FLASHDIS_MASK 0x1u
-#define SIM_FCFG1_FLASHDIS_SHIFT 0
-#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
-#define SIM_FCFG1_FLASHDOZE_SHIFT 1
-#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
-#define SIM_FCFG1_PFSIZE_SHIFT 24
-#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
-/* FCFG2 Bit Fields */
-#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
-#define SIM_FCFG2_MAXADDR_SHIFT 24
-#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
-/* UIDMH Bit Fields */
-#define SIM_UIDMH_UID_MASK 0xFFFFu
-#define SIM_UIDMH_UID_SHIFT 0
-#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
-/* UIDML Bit Fields */
-#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDML_UID_SHIFT 0
-#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
-/* UIDL Bit Fields */
-#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
-#define SIM_UIDL_UID_SHIFT 0
-#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
-/* COPC Bit Fields */
-#define SIM_COPC_COPW_MASK 0x1u
-#define SIM_COPC_COPW_SHIFT 0
-#define SIM_COPC_COPCLKS_MASK 0x2u
-#define SIM_COPC_COPCLKS_SHIFT 1
-#define SIM_COPC_COPT_MASK 0xCu
-#define SIM_COPC_COPT_SHIFT 2
-#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
-/* SRVCOP Bit Fields */
-#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
-#define SIM_SRVCOP_SRVCOP_SHIFT 0
-#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
-
-/**
- * @}
- */ /* end of group SIM_Register_Masks */
-
-
-/* SIM - Peripheral instance base addresses */
-/** Peripheral SIM base address */
-#define SIM_BASE (0x40047000u)
-/** Peripheral SIM base pointer */
-#define SIM ((SIM_Type *)SIM_BASE)
-/** Array initializer of SIM peripheral base pointers */
-#define SIM_BASES { SIM }
-
-/**
- * @}
- */ /* end of group SIM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
- * @{
- */
-
-/** SMC - Register Layout Typedef */
-typedef struct {
- __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
- __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
- __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
- __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- SMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SMC_Register_Masks SMC Register Masks
- * @{
- */
-
-/* PMPROT Bit Fields */
-#define SMC_PMPROT_AVLLS_MASK 0x2u
-#define SMC_PMPROT_AVLLS_SHIFT 1
-#define SMC_PMPROT_ALLS_MASK 0x8u
-#define SMC_PMPROT_ALLS_SHIFT 3
-#define SMC_PMPROT_AVLP_MASK 0x20u
-#define SMC_PMPROT_AVLP_SHIFT 5
-/* PMCTRL Bit Fields */
-#define SMC_PMCTRL_STOPM_MASK 0x7u
-#define SMC_PMCTRL_STOPM_SHIFT 0
-#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
-#define SMC_PMCTRL_STOPA_MASK 0x8u
-#define SMC_PMCTRL_STOPA_SHIFT 3
-#define SMC_PMCTRL_RUNM_MASK 0x60u
-#define SMC_PMCTRL_RUNM_SHIFT 5
-#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
-/* STOPCTRL Bit Fields */
-#define SMC_STOPCTRL_VLLSM_MASK 0x7u
-#define SMC_STOPCTRL_VLLSM_SHIFT 0
-#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
-#define SMC_STOPCTRL_PORPO_MASK 0x20u
-#define SMC_STOPCTRL_PORPO_SHIFT 5
-#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
-#define SMC_STOPCTRL_PSTOPO_SHIFT 6
-#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
-/* PMSTAT Bit Fields */
-#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
-#define SMC_PMSTAT_PMSTAT_SHIFT 0
-#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
-
-/**
- * @}
- */ /* end of group SMC_Register_Masks */
-
-
-/* SMC - Peripheral instance base addresses */
-/** Peripheral SMC base address */
-#define SMC_BASE (0x4007E000u)
-/** Peripheral SMC base pointer */
-#define SMC ((SMC_Type *)SMC_BASE)
-/** Array initializer of SMC peripheral base pointers */
-#define SMC_BASES { SMC }
-
-/**
- * @}
- */ /* end of group SMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
- __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
- __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
- __I uint8_t S; /**< SPI status register, offset: 0x3 */
- uint8_t RESERVED_0[1];
- __IO uint8_t D; /**< SPI data register, offset: 0x5 */
- uint8_t RESERVED_1[1];
- __IO uint8_t M; /**< SPI match register, offset: 0x7 */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/* C1 Bit Fields */
-#define SPI_C1_LSBFE_MASK 0x1u
-#define SPI_C1_LSBFE_SHIFT 0
-#define SPI_C1_SSOE_MASK 0x2u
-#define SPI_C1_SSOE_SHIFT 1
-#define SPI_C1_CPHA_MASK 0x4u
-#define SPI_C1_CPHA_SHIFT 2
-#define SPI_C1_CPOL_MASK 0x8u
-#define SPI_C1_CPOL_SHIFT 3
-#define SPI_C1_MSTR_MASK 0x10u
-#define SPI_C1_MSTR_SHIFT 4
-#define SPI_C1_SPTIE_MASK 0x20u
-#define SPI_C1_SPTIE_SHIFT 5
-#define SPI_C1_SPE_MASK 0x40u
-#define SPI_C1_SPE_SHIFT 6
-#define SPI_C1_SPIE_MASK 0x80u
-#define SPI_C1_SPIE_SHIFT 7
-/* C2 Bit Fields */
-#define SPI_C2_SPC0_MASK 0x1u
-#define SPI_C2_SPC0_SHIFT 0
-#define SPI_C2_SPISWAI_MASK 0x2u
-#define SPI_C2_SPISWAI_SHIFT 1
-#define SPI_C2_RXDMAE_MASK 0x4u
-#define SPI_C2_RXDMAE_SHIFT 2
-#define SPI_C2_BIDIROE_MASK 0x8u
-#define SPI_C2_BIDIROE_SHIFT 3
-#define SPI_C2_MODFEN_MASK 0x10u
-#define SPI_C2_MODFEN_SHIFT 4
-#define SPI_C2_TXDMAE_MASK 0x20u
-#define SPI_C2_TXDMAE_SHIFT 5
-#define SPI_C2_SPLPIE_MASK 0x40u
-#define SPI_C2_SPLPIE_SHIFT 6
-#define SPI_C2_SPMIE_MASK 0x80u
-#define SPI_C2_SPMIE_SHIFT 7
-/* BR Bit Fields */
-#define SPI_BR_SPR_MASK 0xFu
-#define SPI_BR_SPR_SHIFT 0
-#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
-#define SPI_BR_SPPR_MASK 0x70u
-#define SPI_BR_SPPR_SHIFT 4
-#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
-/* S Bit Fields */
-#define SPI_S_MODF_MASK 0x10u
-#define SPI_S_MODF_SHIFT 4
-#define SPI_S_SPTEF_MASK 0x20u
-#define SPI_S_SPTEF_SHIFT 5
-#define SPI_S_SPMF_MASK 0x40u
-#define SPI_S_SPMF_SHIFT 6
-#define SPI_S_SPRF_MASK 0x80u
-#define SPI_S_SPRF_SHIFT 7
-/* D Bit Fields */
-#define SPI_D_Bits_MASK 0xFFu
-#define SPI_D_Bits_SHIFT 0
-#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
-/* M Bit Fields */
-#define SPI_M_Bits_MASK 0xFFu
-#define SPI_M_Bits_SHIFT 0
-#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
-
-/**
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x40076000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x40077000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASES { SPI0, SPI1 }
-
-/**
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- TPM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
- * @{
- */
-
-/** TPM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
- __IO uint32_t CNT; /**< Counter, offset: 0x4 */
- __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
- struct { /* offset: 0xC, array step: 0x8 */
- __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
- __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
- } CONTROLS[6];
- uint8_t RESERVED_0[20];
- __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
- uint8_t RESERVED_1[48];
- __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
-} TPM_Type;
-
-/* ----------------------------------------------------------------------------
- -- TPM Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TPM_Register_Masks TPM Register Masks
- * @{
- */
-
-/* SC Bit Fields */
-#define TPM_SC_PS_MASK 0x7u
-#define TPM_SC_PS_SHIFT 0
-#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
-#define TPM_SC_CMOD_MASK 0x18u
-#define TPM_SC_CMOD_SHIFT 3
-#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
-#define TPM_SC_CPWMS_MASK 0x20u
-#define TPM_SC_CPWMS_SHIFT 5
-#define TPM_SC_TOIE_MASK 0x40u
-#define TPM_SC_TOIE_SHIFT 6
-#define TPM_SC_TOF_MASK 0x80u
-#define TPM_SC_TOF_SHIFT 7
-#define TPM_SC_DMA_MASK 0x100u
-#define TPM_SC_DMA_SHIFT 8
-/* CNT Bit Fields */
-#define TPM_CNT_COUNT_MASK 0xFFFFu
-#define TPM_CNT_COUNT_SHIFT 0
-#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
-/* MOD Bit Fields */
-#define TPM_MOD_MOD_MASK 0xFFFFu
-#define TPM_MOD_MOD_SHIFT 0
-#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
-/* CnSC Bit Fields */
-#define TPM_CnSC_DMA_MASK 0x1u
-#define TPM_CnSC_DMA_SHIFT 0
-#define TPM_CnSC_ELSA_MASK 0x4u
-#define TPM_CnSC_ELSA_SHIFT 2
-#define TPM_CnSC_ELSB_MASK 0x8u
-#define TPM_CnSC_ELSB_SHIFT 3
-#define TPM_CnSC_MSA_MASK 0x10u
-#define TPM_CnSC_MSA_SHIFT 4
-#define TPM_CnSC_MSB_MASK 0x20u
-#define TPM_CnSC_MSB_SHIFT 5
-#define TPM_CnSC_CHIE_MASK 0x40u
-#define TPM_CnSC_CHIE_SHIFT 6
-#define TPM_CnSC_CHF_MASK 0x80u
-#define TPM_CnSC_CHF_SHIFT 7
-/* CnV Bit Fields */
-#define TPM_CnV_VAL_MASK 0xFFFFu
-#define TPM_CnV_VAL_SHIFT 0
-#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
-/* STATUS Bit Fields */
-#define TPM_STATUS_CH0F_MASK 0x1u
-#define TPM_STATUS_CH0F_SHIFT 0
-#define TPM_STATUS_CH1F_MASK 0x2u
-#define TPM_STATUS_CH1F_SHIFT 1
-#define TPM_STATUS_CH2F_MASK 0x4u
-#define TPM_STATUS_CH2F_SHIFT 2
-#define TPM_STATUS_CH3F_MASK 0x8u
-#define TPM_STATUS_CH3F_SHIFT 3
-#define TPM_STATUS_CH4F_MASK 0x10u
-#define TPM_STATUS_CH4F_SHIFT 4
-#define TPM_STATUS_CH5F_MASK 0x20u
-#define TPM_STATUS_CH5F_SHIFT 5
-#define TPM_STATUS_TOF_MASK 0x100u
-#define TPM_STATUS_TOF_SHIFT 8
-/* CONF Bit Fields */
-#define TPM_CONF_DOZEEN_MASK 0x20u
-#define TPM_CONF_DOZEEN_SHIFT 5
-#define TPM_CONF_DBGMODE_MASK 0xC0u
-#define TPM_CONF_DBGMODE_SHIFT 6
-#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
-#define TPM_CONF_GTBEEN_MASK 0x200u
-#define TPM_CONF_GTBEEN_SHIFT 9
-#define TPM_CONF_CSOT_MASK 0x10000u
-#define TPM_CONF_CSOT_SHIFT 16
-#define TPM_CONF_CSOO_MASK 0x20000u
-#define TPM_CONF_CSOO_SHIFT 17
-#define TPM_CONF_CROT_MASK 0x40000u
-#define TPM_CONF_CROT_SHIFT 18
-#define TPM_CONF_TRGSEL_MASK 0xF000000u
-#define TPM_CONF_TRGSEL_SHIFT 24
-#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
-
-/**
- * @}
- */ /* end of group TPM_Register_Masks */
-
-
-/* TPM - Peripheral instance base addresses */
-/** Peripheral TPM0 base address */
-#define TPM0_BASE (0x40038000u)
-/** Peripheral TPM0 base pointer */
-#define TPM0 ((TPM_Type *)TPM0_BASE)
-/** Peripheral TPM1 base address */
-#define TPM1_BASE (0x40039000u)
-/** Peripheral TPM1 base pointer */
-#define TPM1 ((TPM_Type *)TPM1_BASE)
-/** Peripheral TPM2 base address */
-#define TPM2_BASE (0x4003A000u)
-/** Peripheral TPM2 base pointer */
-#define TPM2 ((TPM_Type *)TPM2_BASE)
-/** Array initializer of TPM peripheral base pointers */
-#define TPM_BASES { TPM0, TPM1, TPM2 }
-
-/**
- * @}
- */ /* end of group TPM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- TSI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
- * @{
- */
-
-/** TSI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
- __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
- __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
-} TSI_Type;
-
-/* ----------------------------------------------------------------------------
- -- TSI Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup TSI_Register_Masks TSI Register Masks
- * @{
- */
-
-/* GENCS Bit Fields */
-#define TSI_GENCS_CURSW_MASK 0x2u
-#define TSI_GENCS_CURSW_SHIFT 1
-#define TSI_GENCS_EOSF_MASK 0x4u
-#define TSI_GENCS_EOSF_SHIFT 2
-#define TSI_GENCS_SCNIP_MASK 0x8u
-#define TSI_GENCS_SCNIP_SHIFT 3
-#define TSI_GENCS_STM_MASK 0x10u
-#define TSI_GENCS_STM_SHIFT 4
-#define TSI_GENCS_STPE_MASK 0x20u
-#define TSI_GENCS_STPE_SHIFT 5
-#define TSI_GENCS_TSIIEN_MASK 0x40u
-#define TSI_GENCS_TSIIEN_SHIFT 6
-#define TSI_GENCS_TSIEN_MASK 0x80u
-#define TSI_GENCS_TSIEN_SHIFT 7
-#define TSI_GENCS_NSCN_MASK 0x1F00u
-#define TSI_GENCS_NSCN_SHIFT 8
-#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
-#define TSI_GENCS_PS_MASK 0xE000u
-#define TSI_GENCS_PS_SHIFT 13
-#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
-#define TSI_GENCS_EXTCHRG_MASK 0x70000u
-#define TSI_GENCS_EXTCHRG_SHIFT 16
-#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
-#define TSI_GENCS_DVOLT_MASK 0x180000u
-#define TSI_GENCS_DVOLT_SHIFT 19
-#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
-#define TSI_GENCS_REFCHRG_MASK 0xE00000u
-#define TSI_GENCS_REFCHRG_SHIFT 21
-#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
-#define TSI_GENCS_MODE_MASK 0xF000000u
-#define TSI_GENCS_MODE_SHIFT 24
-#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
-#define TSI_GENCS_ESOR_MASK 0x10000000u
-#define TSI_GENCS_ESOR_SHIFT 28
-#define TSI_GENCS_OUTRGF_MASK 0x80000000u
-#define TSI_GENCS_OUTRGF_SHIFT 31
-/* DATA Bit Fields */
-#define TSI_DATA_TSICNT_MASK 0xFFFFu
-#define TSI_DATA_TSICNT_SHIFT 0
-#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
-#define TSI_DATA_SWTS_MASK 0x400000u
-#define TSI_DATA_SWTS_SHIFT 22
-#define TSI_DATA_DMAEN_MASK 0x800000u
-#define TSI_DATA_DMAEN_SHIFT 23
-#define TSI_DATA_TSICH_MASK 0xF0000000u
-#define TSI_DATA_TSICH_SHIFT 28
-#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
-/* TSHD Bit Fields */
-#define TSI_TSHD_THRESL_MASK 0xFFFFu
-#define TSI_TSHD_THRESL_SHIFT 0
-#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
-#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
-#define TSI_TSHD_THRESH_SHIFT 16
-#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
-
-/**
- * @}
- */ /* end of group TSI_Register_Masks */
-
-
-/* TSI - Peripheral instance base addresses */
-/** Peripheral TSI0 base address */
-#define TSI0_BASE (0x40045000u)
-/** Peripheral TSI0 base pointer */
-#define TSI0 ((TSI_Type *)TSI0_BASE)
-/** Array initializer of TSI peripheral base pointers */
-#define TSI_BASES { TSI0 }
-
-/**
- * @}
- */ /* end of group TSI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
- * @{
- */
-
-/** UART - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
-} UART_Type;
-
-/* ----------------------------------------------------------------------------
- -- UART Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UART_Register_Masks UART Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UART_BDH_SBR_MASK 0x1Fu
-#define UART_BDH_SBR_SHIFT 0
-#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
-#define UART_BDH_SBNS_MASK 0x20u
-#define UART_BDH_SBNS_SHIFT 5
-#define UART_BDH_RXEDGIE_MASK 0x40u
-#define UART_BDH_RXEDGIE_SHIFT 6
-#define UART_BDH_LBKDIE_MASK 0x80u
-#define UART_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UART_BDL_SBR_MASK 0xFFu
-#define UART_BDL_SBR_SHIFT 0
-#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UART_C1_PT_MASK 0x1u
-#define UART_C1_PT_SHIFT 0
-#define UART_C1_PE_MASK 0x2u
-#define UART_C1_PE_SHIFT 1
-#define UART_C1_ILT_MASK 0x4u
-#define UART_C1_ILT_SHIFT 2
-#define UART_C1_WAKE_MASK 0x8u
-#define UART_C1_WAKE_SHIFT 3
-#define UART_C1_M_MASK 0x10u
-#define UART_C1_M_SHIFT 4
-#define UART_C1_RSRC_MASK 0x20u
-#define UART_C1_RSRC_SHIFT 5
-#define UART_C1_UARTSWAI_MASK 0x40u
-#define UART_C1_UARTSWAI_SHIFT 6
-#define UART_C1_LOOPS_MASK 0x80u
-#define UART_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UART_C2_SBK_MASK 0x1u
-#define UART_C2_SBK_SHIFT 0
-#define UART_C2_RWU_MASK 0x2u
-#define UART_C2_RWU_SHIFT 1
-#define UART_C2_RE_MASK 0x4u
-#define UART_C2_RE_SHIFT 2
-#define UART_C2_TE_MASK 0x8u
-#define UART_C2_TE_SHIFT 3
-#define UART_C2_ILIE_MASK 0x10u
-#define UART_C2_ILIE_SHIFT 4
-#define UART_C2_RIE_MASK 0x20u
-#define UART_C2_RIE_SHIFT 5
-#define UART_C2_TCIE_MASK 0x40u
-#define UART_C2_TCIE_SHIFT 6
-#define UART_C2_TIE_MASK 0x80u
-#define UART_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UART_S1_PF_MASK 0x1u
-#define UART_S1_PF_SHIFT 0
-#define UART_S1_FE_MASK 0x2u
-#define UART_S1_FE_SHIFT 1
-#define UART_S1_NF_MASK 0x4u
-#define UART_S1_NF_SHIFT 2
-#define UART_S1_OR_MASK 0x8u
-#define UART_S1_OR_SHIFT 3
-#define UART_S1_IDLE_MASK 0x10u
-#define UART_S1_IDLE_SHIFT 4
-#define UART_S1_RDRF_MASK 0x20u
-#define UART_S1_RDRF_SHIFT 5
-#define UART_S1_TC_MASK 0x40u
-#define UART_S1_TC_SHIFT 6
-#define UART_S1_TDRE_MASK 0x80u
-#define UART_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UART_S2_RAF_MASK 0x1u
-#define UART_S2_RAF_SHIFT 0
-#define UART_S2_LBKDE_MASK 0x2u
-#define UART_S2_LBKDE_SHIFT 1
-#define UART_S2_BRK13_MASK 0x4u
-#define UART_S2_BRK13_SHIFT 2
-#define UART_S2_RWUID_MASK 0x8u
-#define UART_S2_RWUID_SHIFT 3
-#define UART_S2_RXINV_MASK 0x10u
-#define UART_S2_RXINV_SHIFT 4
-#define UART_S2_RXEDGIF_MASK 0x40u
-#define UART_S2_RXEDGIF_SHIFT 6
-#define UART_S2_LBKDIF_MASK 0x80u
-#define UART_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UART_C3_PEIE_MASK 0x1u
-#define UART_C3_PEIE_SHIFT 0
-#define UART_C3_FEIE_MASK 0x2u
-#define UART_C3_FEIE_SHIFT 1
-#define UART_C3_NEIE_MASK 0x4u
-#define UART_C3_NEIE_SHIFT 2
-#define UART_C3_ORIE_MASK 0x8u
-#define UART_C3_ORIE_SHIFT 3
-#define UART_C3_TXINV_MASK 0x10u
-#define UART_C3_TXINV_SHIFT 4
-#define UART_C3_TXDIR_MASK 0x20u
-#define UART_C3_TXDIR_SHIFT 5
-#define UART_C3_T8_MASK 0x40u
-#define UART_C3_T8_SHIFT 6
-#define UART_C3_R8_MASK 0x80u
-#define UART_C3_R8_SHIFT 7
-/* D Bit Fields */
-#define UART_D_R0T0_MASK 0x1u
-#define UART_D_R0T0_SHIFT 0
-#define UART_D_R1T1_MASK 0x2u
-#define UART_D_R1T1_SHIFT 1
-#define UART_D_R2T2_MASK 0x4u
-#define UART_D_R2T2_SHIFT 2
-#define UART_D_R3T3_MASK 0x8u
-#define UART_D_R3T3_SHIFT 3
-#define UART_D_R4T4_MASK 0x10u
-#define UART_D_R4T4_SHIFT 4
-#define UART_D_R5T5_MASK 0x20u
-#define UART_D_R5T5_SHIFT 5
-#define UART_D_R6T6_MASK 0x40u
-#define UART_D_R6T6_SHIFT 6
-#define UART_D_R7T7_MASK 0x80u
-#define UART_D_R7T7_SHIFT 7
-/* C4 Bit Fields */
-#define UART_C4_LBKDDMAS_MASK 0x8u
-#define UART_C4_LBKDDMAS_SHIFT 3
-#define UART_C4_ILDMAS_MASK 0x10u
-#define UART_C4_ILDMAS_SHIFT 4
-#define UART_C4_RDMAS_MASK 0x20u
-#define UART_C4_RDMAS_SHIFT 5
-#define UART_C4_TCDMAS_MASK 0x40u
-#define UART_C4_TCDMAS_SHIFT 6
-#define UART_C4_TDMAS_MASK 0x80u
-#define UART_C4_TDMAS_SHIFT 7
-
-/**
- * @}
- */ /* end of group UART_Register_Masks */
-
-
-/* UART - Peripheral instance base addresses */
-/** Peripheral UART1 base address */
-#define UART1_BASE (0x4006B000u)
-/** Peripheral UART1 base pointer */
-#define UART1 ((UART_Type *)UART1_BASE)
-/** Peripheral UART2 base address */
-#define UART2_BASE (0x4006C000u)
-/** Peripheral UART2 base pointer */
-#define UART2 ((UART_Type *)UART2_BASE)
-/** Array initializer of UART peripheral base pointers */
-#define UART_BASES { UART1, UART2 }
-
-/**
- * @}
- */ /* end of group UART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UARTLP Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
- * @{
- */
-
-/** UARTLP - Register Layout Typedef */
-typedef struct {
- __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
- __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
- __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
- __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
- __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
- __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
- __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
- __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
- __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
- __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
- __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
- __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
-} UARTLP_Type;
-
-/* ----------------------------------------------------------------------------
- -- UARTLP Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
- * @{
- */
-
-/* BDH Bit Fields */
-#define UARTLP_BDH_SBR_MASK 0x1Fu
-#define UARTLP_BDH_SBR_SHIFT 0
-#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
-#define UARTLP_BDH_SBNS_MASK 0x20u
-#define UARTLP_BDH_SBNS_SHIFT 5
-#define UARTLP_BDH_RXEDGIE_MASK 0x40u
-#define UARTLP_BDH_RXEDGIE_SHIFT 6
-#define UARTLP_BDH_LBKDIE_MASK 0x80u
-#define UARTLP_BDH_LBKDIE_SHIFT 7
-/* BDL Bit Fields */
-#define UARTLP_BDL_SBR_MASK 0xFFu
-#define UARTLP_BDL_SBR_SHIFT 0
-#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
-/* C1 Bit Fields */
-#define UARTLP_C1_PT_MASK 0x1u
-#define UARTLP_C1_PT_SHIFT 0
-#define UARTLP_C1_PE_MASK 0x2u
-#define UARTLP_C1_PE_SHIFT 1
-#define UARTLP_C1_ILT_MASK 0x4u
-#define UARTLP_C1_ILT_SHIFT 2
-#define UARTLP_C1_WAKE_MASK 0x8u
-#define UARTLP_C1_WAKE_SHIFT 3
-#define UARTLP_C1_M_MASK 0x10u
-#define UARTLP_C1_M_SHIFT 4
-#define UARTLP_C1_RSRC_MASK 0x20u
-#define UARTLP_C1_RSRC_SHIFT 5
-#define UARTLP_C1_DOZEEN_MASK 0x40u
-#define UARTLP_C1_DOZEEN_SHIFT 6
-#define UARTLP_C1_LOOPS_MASK 0x80u
-#define UARTLP_C1_LOOPS_SHIFT 7
-/* C2 Bit Fields */
-#define UARTLP_C2_SBK_MASK 0x1u
-#define UARTLP_C2_SBK_SHIFT 0
-#define UARTLP_C2_RWU_MASK 0x2u
-#define UARTLP_C2_RWU_SHIFT 1
-#define UARTLP_C2_RE_MASK 0x4u
-#define UARTLP_C2_RE_SHIFT 2
-#define UARTLP_C2_TE_MASK 0x8u
-#define UARTLP_C2_TE_SHIFT 3
-#define UARTLP_C2_ILIE_MASK 0x10u
-#define UARTLP_C2_ILIE_SHIFT 4
-#define UARTLP_C2_RIE_MASK 0x20u
-#define UARTLP_C2_RIE_SHIFT 5
-#define UARTLP_C2_TCIE_MASK 0x40u
-#define UARTLP_C2_TCIE_SHIFT 6
-#define UARTLP_C2_TIE_MASK 0x80u
-#define UARTLP_C2_TIE_SHIFT 7
-/* S1 Bit Fields */
-#define UARTLP_S1_PF_MASK 0x1u
-#define UARTLP_S1_PF_SHIFT 0
-#define UARTLP_S1_FE_MASK 0x2u
-#define UARTLP_S1_FE_SHIFT 1
-#define UARTLP_S1_NF_MASK 0x4u
-#define UARTLP_S1_NF_SHIFT 2
-#define UARTLP_S1_OR_MASK 0x8u
-#define UARTLP_S1_OR_SHIFT 3
-#define UARTLP_S1_IDLE_MASK 0x10u
-#define UARTLP_S1_IDLE_SHIFT 4
-#define UARTLP_S1_RDRF_MASK 0x20u
-#define UARTLP_S1_RDRF_SHIFT 5
-#define UARTLP_S1_TC_MASK 0x40u
-#define UARTLP_S1_TC_SHIFT 6
-#define UARTLP_S1_TDRE_MASK 0x80u
-#define UARTLP_S1_TDRE_SHIFT 7
-/* S2 Bit Fields */
-#define UARTLP_S2_RAF_MASK 0x1u
-#define UARTLP_S2_RAF_SHIFT 0
-#define UARTLP_S2_LBKDE_MASK 0x2u
-#define UARTLP_S2_LBKDE_SHIFT 1
-#define UARTLP_S2_BRK13_MASK 0x4u
-#define UARTLP_S2_BRK13_SHIFT 2
-#define UARTLP_S2_RWUID_MASK 0x8u
-#define UARTLP_S2_RWUID_SHIFT 3
-#define UARTLP_S2_RXINV_MASK 0x10u
-#define UARTLP_S2_RXINV_SHIFT 4
-#define UARTLP_S2_MSBF_MASK 0x20u
-#define UARTLP_S2_MSBF_SHIFT 5
-#define UARTLP_S2_RXEDGIF_MASK 0x40u
-#define UARTLP_S2_RXEDGIF_SHIFT 6
-#define UARTLP_S2_LBKDIF_MASK 0x80u
-#define UARTLP_S2_LBKDIF_SHIFT 7
-/* C3 Bit Fields */
-#define UARTLP_C3_PEIE_MASK 0x1u
-#define UARTLP_C3_PEIE_SHIFT 0
-#define UARTLP_C3_FEIE_MASK 0x2u
-#define UARTLP_C3_FEIE_SHIFT 1
-#define UARTLP_C3_NEIE_MASK 0x4u
-#define UARTLP_C3_NEIE_SHIFT 2
-#define UARTLP_C3_ORIE_MASK 0x8u
-#define UARTLP_C3_ORIE_SHIFT 3
-#define UARTLP_C3_TXINV_MASK 0x10u
-#define UARTLP_C3_TXINV_SHIFT 4
-#define UARTLP_C3_TXDIR_MASK 0x20u
-#define UARTLP_C3_TXDIR_SHIFT 5
-#define UARTLP_C3_R9T8_MASK 0x40u
-#define UARTLP_C3_R9T8_SHIFT 6
-#define UARTLP_C3_R8T9_MASK 0x80u
-#define UARTLP_C3_R8T9_SHIFT 7
-/* D Bit Fields */
-#define UARTLP_D_R0T0_MASK 0x1u
-#define UARTLP_D_R0T0_SHIFT 0
-#define UARTLP_D_R1T1_MASK 0x2u
-#define UARTLP_D_R1T1_SHIFT 1
-#define UARTLP_D_R2T2_MASK 0x4u
-#define UARTLP_D_R2T2_SHIFT 2
-#define UARTLP_D_R3T3_MASK 0x8u
-#define UARTLP_D_R3T3_SHIFT 3
-#define UARTLP_D_R4T4_MASK 0x10u
-#define UARTLP_D_R4T4_SHIFT 4
-#define UARTLP_D_R5T5_MASK 0x20u
-#define UARTLP_D_R5T5_SHIFT 5
-#define UARTLP_D_R6T6_MASK 0x40u
-#define UARTLP_D_R6T6_SHIFT 6
-#define UARTLP_D_R7T7_MASK 0x80u
-#define UARTLP_D_R7T7_SHIFT 7
-/* MA1 Bit Fields */
-#define UARTLP_MA1_MA_MASK 0xFFu
-#define UARTLP_MA1_MA_SHIFT 0
-#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
-/* MA2 Bit Fields */
-#define UARTLP_MA2_MA_MASK 0xFFu
-#define UARTLP_MA2_MA_SHIFT 0
-#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
-/* C4 Bit Fields */
-#define UARTLP_C4_OSR_MASK 0x1Fu
-#define UARTLP_C4_OSR_SHIFT 0
-#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
-#define UARTLP_C4_M10_MASK 0x20u
-#define UARTLP_C4_M10_SHIFT 5
-#define UARTLP_C4_MAEN2_MASK 0x40u
-#define UARTLP_C4_MAEN2_SHIFT 6
-#define UARTLP_C4_MAEN1_MASK 0x80u
-#define UARTLP_C4_MAEN1_SHIFT 7
-/* C5 Bit Fields */
-#define UARTLP_C5_RESYNCDIS_MASK 0x1u
-#define UARTLP_C5_RESYNCDIS_SHIFT 0
-#define UARTLP_C5_BOTHEDGE_MASK 0x2u
-#define UARTLP_C5_BOTHEDGE_SHIFT 1
-#define UARTLP_C5_RDMAE_MASK 0x20u
-#define UARTLP_C5_RDMAE_SHIFT 5
-#define UARTLP_C5_TDMAE_MASK 0x80u
-#define UARTLP_C5_TDMAE_SHIFT 7
-
-/**
- * @}
- */ /* end of group UARTLP_Register_Masks */
-
-
-/* UARTLP - Peripheral instance base addresses */
-/** Peripheral UART0 base address */
-#define UART0_BASE (0x4006A000u)
-/** Peripheral UART0 base pointer */
-#define UART0 ((UARTLP_Type *)UART0_BASE)
-/** Array initializer of UARTLP peripheral base pointers */
-#define UARTLP_BASES { UART0 }
-
-/**
- * @}
- */ /* end of group UARTLP_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
- uint8_t RESERVED_0[3];
- __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
- uint8_t RESERVED_1[3];
- __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
- uint8_t RESERVED_2[3];
- __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
- uint8_t RESERVED_3[3];
- __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
- uint8_t RESERVED_4[3];
- __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
- uint8_t RESERVED_5[3];
- __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
- uint8_t RESERVED_6[3];
- __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
- uint8_t RESERVED_7[99];
- __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
- uint8_t RESERVED_8[3];
- __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
- uint8_t RESERVED_9[3];
- __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
- uint8_t RESERVED_10[3];
- __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
- uint8_t RESERVED_11[3];
- __I uint8_t STAT; /**< Status register, offset: 0x90 */
- uint8_t RESERVED_12[3];
- __IO uint8_t CTL; /**< Control register, offset: 0x94 */
- uint8_t RESERVED_13[3];
- __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
- uint8_t RESERVED_14[3];
- __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
- uint8_t RESERVED_15[3];
- __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
- uint8_t RESERVED_16[3];
- __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
- uint8_t RESERVED_17[3];
- __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
- uint8_t RESERVED_18[3];
- __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
- uint8_t RESERVED_19[3];
- __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
- uint8_t RESERVED_20[3];
- __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
- uint8_t RESERVED_21[11];
- struct { /* offset: 0xC0, array step: 0x4 */
- __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_0[3];
- } ENDPOINT[16];
- __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
- uint8_t RESERVED_22[3];
- __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
- uint8_t RESERVED_23[3];
- __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
- uint8_t RESERVED_24[3];
- __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/* PERID Bit Fields */
-#define USB_PERID_ID_MASK 0x3Fu
-#define USB_PERID_ID_SHIFT 0
-#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
-/* IDCOMP Bit Fields */
-#define USB_IDCOMP_NID_MASK 0x3Fu
-#define USB_IDCOMP_NID_SHIFT 0
-#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
-/* REV Bit Fields */
-#define USB_REV_REV_MASK 0xFFu
-#define USB_REV_REV_SHIFT 0
-#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
-/* ADDINFO Bit Fields */
-#define USB_ADDINFO_IEHOST_MASK 0x1u
-#define USB_ADDINFO_IEHOST_SHIFT 0
-#define USB_ADDINFO_IRQNUM_MASK 0xF8u
-#define USB_ADDINFO_IRQNUM_SHIFT 3
-#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
-/* OTGISTAT Bit Fields */
-#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
-#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
-#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
-#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
-#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
-#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
-#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
-#define USB_OTGISTAT_ONEMSEC_SHIFT 6
-#define USB_OTGISTAT_IDCHG_MASK 0x80u
-#define USB_OTGISTAT_IDCHG_SHIFT 7
-/* OTGICR Bit Fields */
-#define USB_OTGICR_AVBUSEN_MASK 0x1u
-#define USB_OTGICR_AVBUSEN_SHIFT 0
-#define USB_OTGICR_BSESSEN_MASK 0x4u
-#define USB_OTGICR_BSESSEN_SHIFT 2
-#define USB_OTGICR_SESSVLDEN_MASK 0x8u
-#define USB_OTGICR_SESSVLDEN_SHIFT 3
-#define USB_OTGICR_LINESTATEEN_MASK 0x20u
-#define USB_OTGICR_LINESTATEEN_SHIFT 5
-#define USB_OTGICR_ONEMSECEN_MASK 0x40u
-#define USB_OTGICR_ONEMSECEN_SHIFT 6
-#define USB_OTGICR_IDEN_MASK 0x80u
-#define USB_OTGICR_IDEN_SHIFT 7
-/* OTGSTAT Bit Fields */
-#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
-#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
-#define USB_OTGSTAT_BSESSEND_MASK 0x4u
-#define USB_OTGSTAT_BSESSEND_SHIFT 2
-#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
-#define USB_OTGSTAT_SESS_VLD_SHIFT 3
-#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
-#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
-#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
-#define USB_OTGSTAT_ID_MASK 0x80u
-#define USB_OTGSTAT_ID_SHIFT 7
-/* OTGCTL Bit Fields */
-#define USB_OTGCTL_OTGEN_MASK 0x4u
-#define USB_OTGCTL_OTGEN_SHIFT 2
-#define USB_OTGCTL_DMLOW_MASK 0x10u
-#define USB_OTGCTL_DMLOW_SHIFT 4
-#define USB_OTGCTL_DPLOW_MASK 0x20u
-#define USB_OTGCTL_DPLOW_SHIFT 5
-#define USB_OTGCTL_DPHIGH_MASK 0x80u
-#define USB_OTGCTL_DPHIGH_SHIFT 7
-/* ISTAT Bit Fields */
-#define USB_ISTAT_USBRST_MASK 0x1u
-#define USB_ISTAT_USBRST_SHIFT 0
-#define USB_ISTAT_ERROR_MASK 0x2u
-#define USB_ISTAT_ERROR_SHIFT 1
-#define USB_ISTAT_SOFTOK_MASK 0x4u
-#define USB_ISTAT_SOFTOK_SHIFT 2
-#define USB_ISTAT_TOKDNE_MASK 0x8u
-#define USB_ISTAT_TOKDNE_SHIFT 3
-#define USB_ISTAT_SLEEP_MASK 0x10u
-#define USB_ISTAT_SLEEP_SHIFT 4
-#define USB_ISTAT_RESUME_MASK 0x20u
-#define USB_ISTAT_RESUME_SHIFT 5
-#define USB_ISTAT_ATTACH_MASK 0x40u
-#define USB_ISTAT_ATTACH_SHIFT 6
-#define USB_ISTAT_STALL_MASK 0x80u
-#define USB_ISTAT_STALL_SHIFT 7
-/* INTEN Bit Fields */
-#define USB_INTEN_USBRSTEN_MASK 0x1u
-#define USB_INTEN_USBRSTEN_SHIFT 0
-#define USB_INTEN_ERROREN_MASK 0x2u
-#define USB_INTEN_ERROREN_SHIFT 1
-#define USB_INTEN_SOFTOKEN_MASK 0x4u
-#define USB_INTEN_SOFTOKEN_SHIFT 2
-#define USB_INTEN_TOKDNEEN_MASK 0x8u
-#define USB_INTEN_TOKDNEEN_SHIFT 3
-#define USB_INTEN_SLEEPEN_MASK 0x10u
-#define USB_INTEN_SLEEPEN_SHIFT 4
-#define USB_INTEN_RESUMEEN_MASK 0x20u
-#define USB_INTEN_RESUMEEN_SHIFT 5
-#define USB_INTEN_ATTACHEN_MASK 0x40u
-#define USB_INTEN_ATTACHEN_SHIFT 6
-#define USB_INTEN_STALLEN_MASK 0x80u
-#define USB_INTEN_STALLEN_SHIFT 7
-/* ERRSTAT Bit Fields */
-#define USB_ERRSTAT_PIDERR_MASK 0x1u
-#define USB_ERRSTAT_PIDERR_SHIFT 0
-#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
-#define USB_ERRSTAT_CRC5EOF_SHIFT 1
-#define USB_ERRSTAT_CRC16_MASK 0x4u
-#define USB_ERRSTAT_CRC16_SHIFT 2
-#define USB_ERRSTAT_DFN8_MASK 0x8u
-#define USB_ERRSTAT_DFN8_SHIFT 3
-#define USB_ERRSTAT_BTOERR_MASK 0x10u
-#define USB_ERRSTAT_BTOERR_SHIFT 4
-#define USB_ERRSTAT_DMAERR_MASK 0x20u
-#define USB_ERRSTAT_DMAERR_SHIFT 5
-#define USB_ERRSTAT_BTSERR_MASK 0x80u
-#define USB_ERRSTAT_BTSERR_SHIFT 7
-/* ERREN Bit Fields */
-#define USB_ERREN_PIDERREN_MASK 0x1u
-#define USB_ERREN_PIDERREN_SHIFT 0
-#define USB_ERREN_CRC5EOFEN_MASK 0x2u
-#define USB_ERREN_CRC5EOFEN_SHIFT 1
-#define USB_ERREN_CRC16EN_MASK 0x4u
-#define USB_ERREN_CRC16EN_SHIFT 2
-#define USB_ERREN_DFN8EN_MASK 0x8u
-#define USB_ERREN_DFN8EN_SHIFT 3
-#define USB_ERREN_BTOERREN_MASK 0x10u
-#define USB_ERREN_BTOERREN_SHIFT 4
-#define USB_ERREN_DMAERREN_MASK 0x20u
-#define USB_ERREN_DMAERREN_SHIFT 5
-#define USB_ERREN_BTSERREN_MASK 0x80u
-#define USB_ERREN_BTSERREN_SHIFT 7
-/* STAT Bit Fields */
-#define USB_STAT_ODD_MASK 0x4u
-#define USB_STAT_ODD_SHIFT 2
-#define USB_STAT_TX_MASK 0x8u
-#define USB_STAT_TX_SHIFT 3
-#define USB_STAT_ENDP_MASK 0xF0u
-#define USB_STAT_ENDP_SHIFT 4
-#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
-/* CTL Bit Fields */
-#define USB_CTL_USBENSOFEN_MASK 0x1u
-#define USB_CTL_USBENSOFEN_SHIFT 0
-#define USB_CTL_ODDRST_MASK 0x2u
-#define USB_CTL_ODDRST_SHIFT 1
-#define USB_CTL_RESUME_MASK 0x4u
-#define USB_CTL_RESUME_SHIFT 2
-#define USB_CTL_HOSTMODEEN_MASK 0x8u
-#define USB_CTL_HOSTMODEEN_SHIFT 3
-#define USB_CTL_RESET_MASK 0x10u
-#define USB_CTL_RESET_SHIFT 4
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
-#define USB_CTL_SE0_MASK 0x40u
-#define USB_CTL_SE0_SHIFT 6
-#define USB_CTL_JSTATE_MASK 0x80u
-#define USB_CTL_JSTATE_SHIFT 7
-/* ADDR Bit Fields */
-#define USB_ADDR_ADDR_MASK 0x7Fu
-#define USB_ADDR_ADDR_SHIFT 0
-#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK 0x80u
-#define USB_ADDR_LSEN_SHIFT 7
-/* BDTPAGE1 Bit Fields */
-#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
-#define USB_BDTPAGE1_BDTBA_SHIFT 1
-#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
-/* FRMNUML Bit Fields */
-#define USB_FRMNUML_FRM_MASK 0xFFu
-#define USB_FRMNUML_FRM_SHIFT 0
-#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
-/* FRMNUMH Bit Fields */
-#define USB_FRMNUMH_FRM_MASK 0x7u
-#define USB_FRMNUMH_FRM_SHIFT 0
-#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
-/* TOKEN Bit Fields */
-#define USB_TOKEN_TOKENENDPT_MASK 0xFu
-#define USB_TOKEN_TOKENENDPT_SHIFT 0
-#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK 0xF0u
-#define USB_TOKEN_TOKENPID_SHIFT 4
-#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
-/* SOFTHLD Bit Fields */
-#define USB_SOFTHLD_CNT_MASK 0xFFu
-#define USB_SOFTHLD_CNT_SHIFT 0
-#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
-/* BDTPAGE2 Bit Fields */
-#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE2_BDTBA_SHIFT 0
-#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
-/* BDTPAGE3 Bit Fields */
-#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
-#define USB_BDTPAGE3_BDTBA_SHIFT 0
-#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
-/* ENDPT Bit Fields */
-#define USB_ENDPT_EPHSHK_MASK 0x1u
-#define USB_ENDPT_EPHSHK_SHIFT 0
-#define USB_ENDPT_EPSTALL_MASK 0x2u
-#define USB_ENDPT_EPSTALL_SHIFT 1
-#define USB_ENDPT_EPTXEN_MASK 0x4u
-#define USB_ENDPT_EPTXEN_SHIFT 2
-#define USB_ENDPT_EPRXEN_MASK 0x8u
-#define USB_ENDPT_EPRXEN_SHIFT 3
-#define USB_ENDPT_EPCTLDIS_MASK 0x10u
-#define USB_ENDPT_EPCTLDIS_SHIFT 4
-#define USB_ENDPT_RETRYDIS_MASK 0x40u
-#define USB_ENDPT_RETRYDIS_SHIFT 6
-#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
-#define USB_ENDPT_HOSTWOHUB_SHIFT 7
-/* USBCTRL Bit Fields */
-#define USB_USBCTRL_PDE_MASK 0x40u
-#define USB_USBCTRL_PDE_SHIFT 6
-#define USB_USBCTRL_SUSP_MASK 0x80u
-#define USB_USBCTRL_SUSP_SHIFT 7
-/* OBSERVE Bit Fields */
-#define USB_OBSERVE_DMPD_MASK 0x10u
-#define USB_OBSERVE_DMPD_SHIFT 4
-#define USB_OBSERVE_DPPD_MASK 0x40u
-#define USB_OBSERVE_DPPD_SHIFT 6
-#define USB_OBSERVE_DPPU_MASK 0x80u
-#define USB_OBSERVE_DPPU_SHIFT 7
-/* CONTROL Bit Fields */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
-/* USBTRC0 Bit Fields */
-#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
-#define USB_USBTRC0_SYNC_DET_MASK 0x2u
-#define USB_USBTRC0_SYNC_DET_SHIFT 1
-#define USB_USBTRC0_USBRESMEN_MASK 0x20u
-#define USB_USBTRC0_USBRESMEN_SHIFT 5
-#define USB_USBTRC0_USBRESET_MASK 0x80u
-#define USB_USBTRC0_USBRESET_SHIFT 7
-
-/**
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40072000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASES { USB0 }
-
-/**
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__CWCC__)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/**
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Backward Compatibility
- ---------------------------------------------------------------------------- */
-
-/**
- * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
- * @{
- */
-
-/* No backward compatibility issues. */
-
-/**
- * @}
- */ /* end of group Backward_Compatibility_Symbols */
-
-
-#endif /* #if !defined(MKL25Z4_H_) */
-
-/* MKL25Z4.h, eof. */
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL25Z4
+**
+** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4.h
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief CMSIS Peripheral Access Layer for MKL25Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL25Z4
+ */
+
+#if !defined(MKL25Z4_H_)
+#define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ SPI1_IRQn = 11, /**< SPI1 interrupt */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ UART1_IRQn = 13, /**< UART1 status/error interrupt */
+ UART2_IRQn = 14, /**< UART2 status/error interrupt */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTD_IRQn = 31 /**< Port D interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL25Z4.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x40u
+#define CMP_MUXCR_PSTM_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
+ };
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* REQC_ARR Bit Fields */
+#define DMA_REQC_ARR_DMAC_MASK 0xFu
+#define DMA_REQC_ARR_DMAC_SHIFT 0
+#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
+#define DMA_REQC_ARR_CFSM_MASK 0x80u
+#define DMA_REQC_ARR_CFSM_SHIFT 7
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS_MASK 0x80u
+#define MCG_S_LOLS_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+#define SIM_SOPT5_UART1ODE_MASK 0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR_SHIFT 24
+#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
+ __I uint8_t S; /**< SPI status register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t D; /**< SPI data register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t M; /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPLPIE_MASK 0x40u
+#define SPI_C2_SPLPIE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK 0xFFu
+#define SPI_D_Bits_SHIFT 0
+#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK 0xFFu
+#define SPI_M_Bits_SHIFT 0
+#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1, TPM2 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK 0x1u
+#define UART_D_R0T0_SHIFT 0
+#define UART_D_R1T1_MASK 0x2u
+#define UART_D_R1T1_SHIFT 1
+#define UART_D_R2T2_MASK 0x4u
+#define UART_D_R2T2_SHIFT 2
+#define UART_D_R3T3_MASK 0x8u
+#define UART_D_R3T3_SHIFT 3
+#define UART_D_R4T4_MASK 0x10u
+#define UART_D_R4T4_SHIFT 4
+#define UART_D_R5T5_MASK 0x20u
+#define UART_D_R5T5_SHIFT 5
+#define UART_D_R6T6_MASK 0x40u
+#define UART_D_R6T6_SHIFT 6
+#define UART_D_R7T7_MASK 0x80u
+#define UART_D_R7T7_SHIFT 7
+/* C4 Bit Fields */
+#define UART_C4_LBKDDMAS_MASK 0x8u
+#define UART_C4_LBKDDMAS_SHIFT 3
+#define UART_C4_ILDMAS_MASK 0x10u
+#define UART_C4_ILDMAS_SHIFT 4
+#define UART_C4_RDMAS_MASK 0x20u
+#define UART_C4_RDMAS_SHIFT 5
+#define UART_C4_TCDMAS_MASK 0x40u
+#define UART_C4_TCDMAS_SHIFT 6
+#define UART_C4_TDMAS_MASK 0x80u
+#define UART_C4_TDMAS_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART1, UART2 }
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
+ * @{
+ */
+
+/** UARTLP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UARTLP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UARTLP_BDH_SBR_MASK 0x1Fu
+#define UARTLP_BDH_SBR_SHIFT 0
+#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
+#define UARTLP_BDH_SBNS_MASK 0x20u
+#define UARTLP_BDH_SBNS_SHIFT 5
+#define UARTLP_BDH_RXEDGIE_MASK 0x40u
+#define UARTLP_BDH_RXEDGIE_SHIFT 6
+#define UARTLP_BDH_LBKDIE_MASK 0x80u
+#define UARTLP_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UARTLP_BDL_SBR_MASK 0xFFu
+#define UARTLP_BDL_SBR_SHIFT 0
+#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UARTLP_C1_PT_MASK 0x1u
+#define UARTLP_C1_PT_SHIFT 0
+#define UARTLP_C1_PE_MASK 0x2u
+#define UARTLP_C1_PE_SHIFT 1
+#define UARTLP_C1_ILT_MASK 0x4u
+#define UARTLP_C1_ILT_SHIFT 2
+#define UARTLP_C1_WAKE_MASK 0x8u
+#define UARTLP_C1_WAKE_SHIFT 3
+#define UARTLP_C1_M_MASK 0x10u
+#define UARTLP_C1_M_SHIFT 4
+#define UARTLP_C1_RSRC_MASK 0x20u
+#define UARTLP_C1_RSRC_SHIFT 5
+#define UARTLP_C1_DOZEEN_MASK 0x40u
+#define UARTLP_C1_DOZEEN_SHIFT 6
+#define UARTLP_C1_LOOPS_MASK 0x80u
+#define UARTLP_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UARTLP_C2_SBK_MASK 0x1u
+#define UARTLP_C2_SBK_SHIFT 0
+#define UARTLP_C2_RWU_MASK 0x2u
+#define UARTLP_C2_RWU_SHIFT 1
+#define UARTLP_C2_RE_MASK 0x4u
+#define UARTLP_C2_RE_SHIFT 2
+#define UARTLP_C2_TE_MASK 0x8u
+#define UARTLP_C2_TE_SHIFT 3
+#define UARTLP_C2_ILIE_MASK 0x10u
+#define UARTLP_C2_ILIE_SHIFT 4
+#define UARTLP_C2_RIE_MASK 0x20u
+#define UARTLP_C2_RIE_SHIFT 5
+#define UARTLP_C2_TCIE_MASK 0x40u
+#define UARTLP_C2_TCIE_SHIFT 6
+#define UARTLP_C2_TIE_MASK 0x80u
+#define UARTLP_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UARTLP_S1_PF_MASK 0x1u
+#define UARTLP_S1_PF_SHIFT 0
+#define UARTLP_S1_FE_MASK 0x2u
+#define UARTLP_S1_FE_SHIFT 1
+#define UARTLP_S1_NF_MASK 0x4u
+#define UARTLP_S1_NF_SHIFT 2
+#define UARTLP_S1_OR_MASK 0x8u
+#define UARTLP_S1_OR_SHIFT 3
+#define UARTLP_S1_IDLE_MASK 0x10u
+#define UARTLP_S1_IDLE_SHIFT 4
+#define UARTLP_S1_RDRF_MASK 0x20u
+#define UARTLP_S1_RDRF_SHIFT 5
+#define UARTLP_S1_TC_MASK 0x40u
+#define UARTLP_S1_TC_SHIFT 6
+#define UARTLP_S1_TDRE_MASK 0x80u
+#define UARTLP_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UARTLP_S2_RAF_MASK 0x1u
+#define UARTLP_S2_RAF_SHIFT 0
+#define UARTLP_S2_LBKDE_MASK 0x2u
+#define UARTLP_S2_LBKDE_SHIFT 1
+#define UARTLP_S2_BRK13_MASK 0x4u
+#define UARTLP_S2_BRK13_SHIFT 2
+#define UARTLP_S2_RWUID_MASK 0x8u
+#define UARTLP_S2_RWUID_SHIFT 3
+#define UARTLP_S2_RXINV_MASK 0x10u
+#define UARTLP_S2_RXINV_SHIFT 4
+#define UARTLP_S2_MSBF_MASK 0x20u
+#define UARTLP_S2_MSBF_SHIFT 5
+#define UARTLP_S2_RXEDGIF_MASK 0x40u
+#define UARTLP_S2_RXEDGIF_SHIFT 6
+#define UARTLP_S2_LBKDIF_MASK 0x80u
+#define UARTLP_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UARTLP_C3_PEIE_MASK 0x1u
+#define UARTLP_C3_PEIE_SHIFT 0
+#define UARTLP_C3_FEIE_MASK 0x2u
+#define UARTLP_C3_FEIE_SHIFT 1
+#define UARTLP_C3_NEIE_MASK 0x4u
+#define UARTLP_C3_NEIE_SHIFT 2
+#define UARTLP_C3_ORIE_MASK 0x8u
+#define UARTLP_C3_ORIE_SHIFT 3
+#define UARTLP_C3_TXINV_MASK 0x10u
+#define UARTLP_C3_TXINV_SHIFT 4
+#define UARTLP_C3_TXDIR_MASK 0x20u
+#define UARTLP_C3_TXDIR_SHIFT 5
+#define UARTLP_C3_R9T8_MASK 0x40u
+#define UARTLP_C3_R9T8_SHIFT 6
+#define UARTLP_C3_R8T9_MASK 0x80u
+#define UARTLP_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UARTLP_D_R0T0_MASK 0x1u
+#define UARTLP_D_R0T0_SHIFT 0
+#define UARTLP_D_R1T1_MASK 0x2u
+#define UARTLP_D_R1T1_SHIFT 1
+#define UARTLP_D_R2T2_MASK 0x4u
+#define UARTLP_D_R2T2_SHIFT 2
+#define UARTLP_D_R3T3_MASK 0x8u
+#define UARTLP_D_R3T3_SHIFT 3
+#define UARTLP_D_R4T4_MASK 0x10u
+#define UARTLP_D_R4T4_SHIFT 4
+#define UARTLP_D_R5T5_MASK 0x20u
+#define UARTLP_D_R5T5_SHIFT 5
+#define UARTLP_D_R6T6_MASK 0x40u
+#define UARTLP_D_R6T6_SHIFT 6
+#define UARTLP_D_R7T7_MASK 0x80u
+#define UARTLP_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UARTLP_MA1_MA_MASK 0xFFu
+#define UARTLP_MA1_MA_SHIFT 0
+#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UARTLP_MA2_MA_MASK 0xFFu
+#define UARTLP_MA2_MA_SHIFT 0
+#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UARTLP_C4_OSR_MASK 0x1Fu
+#define UARTLP_C4_OSR_SHIFT 0
+#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
+#define UARTLP_C4_M10_MASK 0x20u
+#define UARTLP_C4_M10_SHIFT 5
+#define UARTLP_C4_MAEN2_MASK 0x40u
+#define UARTLP_C4_MAEN2_SHIFT 6
+#define UARTLP_C4_MAEN1_MASK 0x80u
+#define UARTLP_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UARTLP_C5_RESYNCDIS_MASK 0x1u
+#define UARTLP_C5_RESYNCDIS_SHIFT 0
+#define UARTLP_C5_BOTHEDGE_MASK 0x2u
+#define UARTLP_C5_BOTHEDGE_SHIFT 1
+#define UARTLP_C5_RDMAE_MASK 0x20u
+#define UARTLP_C5_RDMAE_SHIFT 5
+#define UARTLP_C5_TDMAE_MASK 0x80u
+#define UARTLP_C5_TDMAE_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UARTLP_Register_Masks */
+
+
+/* UARTLP - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UARTLP_Type *)UART0_BASE)
+/** Array initializer of UARTLP peripheral base pointers */
+#define UARTLP_BASES { UART0 }
+
+/**
+ * @}
+ */ /* end of group UARTLP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL25Z4_H_) */
+
+/* MKL25Z4.h, eof. */
--- a/TARGET_KL25Z/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,89 +1,89 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)UART0_BASE,
- UART_1 = (int)UART1_BASE,
- UART_2 = (int)UART2_BASE
-} UARTName;
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-typedef enum {
- I2C_0 = (int)I2C0_BASE,
- I2C_1 = (int)I2C1_BASE,
-} I2CName;
-
-#define TPM_SHIFT 8
-typedef enum {
- PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
- PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
- PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
- PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
- PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
- PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
-
- PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
- PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
-
- PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
- PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
-} PWMName;
-
-#define CHANNELS_A_SHIFT 5
-typedef enum {
- ADC0_SE0 = 0,
- ADC0_SE3 = 3,
- ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4),
- ADC0_SE4b = 4,
- ADC0_SE5b = 5,
- ADC0_SE6b = 6,
- ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7),
- ADC0_SE7b = 7,
- ADC0_SE8 = 8,
- ADC0_SE9 = 9,
- ADC0_SE11 = 11,
- ADC0_SE12 = 12,
- ADC0_SE13 = 13,
- ADC0_SE14 = 14,
- ADC0_SE15 = 15,
- ADC0_SE23 = 23
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-
-typedef enum {
- SPI_0 = (int)SPI0_BASE,
- SPI_1 = (int)SPI1_BASE,
-} SPIName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)UART0_BASE,
+ UART_1 = (int)UART1_BASE,
+ UART_2 = (int)UART2_BASE
+} UARTName;
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+typedef enum {
+ I2C_0 = (int)I2C0_BASE,
+ I2C_1 = (int)I2C1_BASE,
+} I2CName;
+
+#define TPM_SHIFT 8
+typedef enum {
+ PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
+ PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
+ PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
+ PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
+ PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
+ PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
+
+ PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
+ PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
+
+ PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
+ PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
+} PWMName;
+
+#define CHANNELS_A_SHIFT 5
+typedef enum {
+ ADC0_SE0 = 0,
+ ADC0_SE3 = 3,
+ ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4),
+ ADC0_SE4b = 4,
+ ADC0_SE5b = 5,
+ ADC0_SE6b = 6,
+ ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7),
+ ADC0_SE7b = 7,
+ ADC0_SE8 = 8,
+ ADC0_SE9 = 9,
+ ADC0_SE11 = 11,
+ ADC0_SE12 = 12,
+ ADC0_SE13 = 13,
+ ADC0_SE14 = 14,
+ ADC0_SE15 = 15,
+ ADC0_SE23 = 23
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+ SPI_0 = (int)SPI0_BASE,
+ SPI_1 = (int)SPI1_BASE,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL25Z/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,247 +1,247 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 12
-
-typedef enum {
- PTA0 = 0x0,
- PTA1 = 0x4,
- PTA2 = 0x8,
- PTA3 = 0xc,
- PTA4 = 0x10,
- PTA5 = 0x14,
- PTA6 = 0x18,
- PTA7 = 0x1c,
- PTA8 = 0x20,
- PTA9 = 0x24,
- PTA10 = 0x28,
- PTA11 = 0x2c,
- PTA12 = 0x30,
- PTA13 = 0x34,
- PTA14 = 0x38,
- PTA15 = 0x3c,
- PTA16 = 0x40,
- PTA17 = 0x44,
- PTA18 = 0x48,
- PTA19 = 0x4c,
- PTA20 = 0x50,
- PTA21 = 0x54,
- PTA22 = 0x58,
- PTA23 = 0x5c,
- PTA24 = 0x60,
- PTA25 = 0x64,
- PTA26 = 0x68,
- PTA27 = 0x6c,
- PTA28 = 0x70,
- PTA29 = 0x74,
- PTA30 = 0x78,
- PTA31 = 0x7c,
- PTB0 = 0x1000,
- PTB1 = 0x1004,
- PTB2 = 0x1008,
- PTB3 = 0x100c,
- PTB4 = 0x1010,
- PTB5 = 0x1014,
- PTB6 = 0x1018,
- PTB7 = 0x101c,
- PTB8 = 0x1020,
- PTB9 = 0x1024,
- PTB10 = 0x1028,
- PTB11 = 0x102c,
- PTB12 = 0x1030,
- PTB13 = 0x1034,
- PTB14 = 0x1038,
- PTB15 = 0x103c,
- PTB16 = 0x1040,
- PTB17 = 0x1044,
- PTB18 = 0x1048,
- PTB19 = 0x104c,
- PTB20 = 0x1050,
- PTB21 = 0x1054,
- PTB22 = 0x1058,
- PTB23 = 0x105c,
- PTB24 = 0x1060,
- PTB25 = 0x1064,
- PTB26 = 0x1068,
- PTB27 = 0x106c,
- PTB28 = 0x1070,
- PTB29 = 0x1074,
- PTB30 = 0x1078,
- PTB31 = 0x107c,
- PTC0 = 0x2000,
- PTC1 = 0x2004,
- PTC2 = 0x2008,
- PTC3 = 0x200c,
- PTC4 = 0x2010,
- PTC5 = 0x2014,
- PTC6 = 0x2018,
- PTC7 = 0x201c,
- PTC8 = 0x2020,
- PTC9 = 0x2024,
- PTC10 = 0x2028,
- PTC11 = 0x202c,
- PTC12 = 0x2030,
- PTC13 = 0x2034,
- PTC14 = 0x2038,
- PTC15 = 0x203c,
- PTC16 = 0x2040,
- PTC17 = 0x2044,
- PTC18 = 0x2048,
- PTC19 = 0x204c,
- PTC20 = 0x2050,
- PTC21 = 0x2054,
- PTC22 = 0x2058,
- PTC23 = 0x205c,
- PTC24 = 0x2060,
- PTC25 = 0x2064,
- PTC26 = 0x2068,
- PTC27 = 0x206c,
- PTC28 = 0x2070,
- PTC29 = 0x2074,
- PTC30 = 0x2078,
- PTC31 = 0x207c,
- PTD0 = 0x3000,
- PTD1 = 0x3004,
- PTD2 = 0x3008,
- PTD3 = 0x300c,
- PTD4 = 0x3010,
- PTD5 = 0x3014,
- PTD6 = 0x3018,
- PTD7 = 0x301c,
- PTD8 = 0x3020,
- PTD9 = 0x3024,
- PTD10 = 0x3028,
- PTD11 = 0x302c,
- PTD12 = 0x3030,
- PTD13 = 0x3034,
- PTD14 = 0x3038,
- PTD15 = 0x303c,
- PTD16 = 0x3040,
- PTD17 = 0x3044,
- PTD18 = 0x3048,
- PTD19 = 0x304c,
- PTD20 = 0x3050,
- PTD21 = 0x3054,
- PTD22 = 0x3058,
- PTD23 = 0x305c,
- PTD24 = 0x3060,
- PTD25 = 0x3064,
- PTD26 = 0x3068,
- PTD27 = 0x306c,
- PTD28 = 0x3070,
- PTD29 = 0x3074,
- PTD30 = 0x3078,
- PTD31 = 0x307c,
- PTE0 = 0x4000,
- PTE1 = 0x4004,
- PTE2 = 0x4008,
- PTE3 = 0x400c,
- PTE4 = 0x4010,
- PTE5 = 0x4014,
- PTE6 = 0x4018,
- PTE7 = 0x401c,
- PTE8 = 0x4020,
- PTE9 = 0x4024,
- PTE10 = 0x4028,
- PTE11 = 0x402c,
- PTE12 = 0x4030,
- PTE13 = 0x4034,
- PTE14 = 0x4038,
- PTE15 = 0x403c,
- PTE16 = 0x4040,
- PTE17 = 0x4044,
- PTE18 = 0x4048,
- PTE19 = 0x404c,
- PTE20 = 0x4050,
- PTE21 = 0x4054,
- PTE22 = 0x4058,
- PTE23 = 0x405c,
- PTE24 = 0x4060,
- PTE25 = 0x4064,
- PTE26 = 0x4068,
- PTE27 = 0x406c,
- PTE28 = 0x4070,
- PTE29 = 0x4074,
- PTE30 = 0x4078,
- PTE31 = 0x407c,
-
- LED_RED = PTB18,
- LED_GREEN = PTB19,
- LED_BLUE = PTD1,
-
- // mbed original LED naming
- LED1 = LED_BLUE,
- LED2 = LED_GREEN,
- LED3 = LED_RED,
- LED4 = LED_RED,
-
- // USB Pins
- USBTX = PTA2,
- USBRX = PTA1,
-
- // Arduino Headers
- D0 = PTA1,
- D1 = PTA2,
- D2 = PTD4,
- D3 = PTA12,
- D4 = PTA4,
- D5 = PTA5,
- D6 = PTC8,
- D7 = PTC9,
- D8 = PTA13,
- D9 = PTD5,
- D10 = PTD0,
- D11 = PTD2,
- D12 = PTD3,
- D13 = PTD1,
- D14 = PTE0,
- D15 = PTE1,
-
- A0 = PTB0,
- A1 = PTB1,
- A2 = PTB2,
- A3 = PTB3,
- A4 = PTC2,
- A5 = PTC1,
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-/* PullDown not available for KL25 */
-typedef enum {
- PullNone = 0,
- PullUp = 2,
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 12
+
+typedef enum {
+ PTA0 = 0x0,
+ PTA1 = 0x4,
+ PTA2 = 0x8,
+ PTA3 = 0xc,
+ PTA4 = 0x10,
+ PTA5 = 0x14,
+ PTA6 = 0x18,
+ PTA7 = 0x1c,
+ PTA8 = 0x20,
+ PTA9 = 0x24,
+ PTA10 = 0x28,
+ PTA11 = 0x2c,
+ PTA12 = 0x30,
+ PTA13 = 0x34,
+ PTA14 = 0x38,
+ PTA15 = 0x3c,
+ PTA16 = 0x40,
+ PTA17 = 0x44,
+ PTA18 = 0x48,
+ PTA19 = 0x4c,
+ PTA20 = 0x50,
+ PTA21 = 0x54,
+ PTA22 = 0x58,
+ PTA23 = 0x5c,
+ PTA24 = 0x60,
+ PTA25 = 0x64,
+ PTA26 = 0x68,
+ PTA27 = 0x6c,
+ PTA28 = 0x70,
+ PTA29 = 0x74,
+ PTA30 = 0x78,
+ PTA31 = 0x7c,
+ PTB0 = 0x1000,
+ PTB1 = 0x1004,
+ PTB2 = 0x1008,
+ PTB3 = 0x100c,
+ PTB4 = 0x1010,
+ PTB5 = 0x1014,
+ PTB6 = 0x1018,
+ PTB7 = 0x101c,
+ PTB8 = 0x1020,
+ PTB9 = 0x1024,
+ PTB10 = 0x1028,
+ PTB11 = 0x102c,
+ PTB12 = 0x1030,
+ PTB13 = 0x1034,
+ PTB14 = 0x1038,
+ PTB15 = 0x103c,
+ PTB16 = 0x1040,
+ PTB17 = 0x1044,
+ PTB18 = 0x1048,
+ PTB19 = 0x104c,
+ PTB20 = 0x1050,
+ PTB21 = 0x1054,
+ PTB22 = 0x1058,
+ PTB23 = 0x105c,
+ PTB24 = 0x1060,
+ PTB25 = 0x1064,
+ PTB26 = 0x1068,
+ PTB27 = 0x106c,
+ PTB28 = 0x1070,
+ PTB29 = 0x1074,
+ PTB30 = 0x1078,
+ PTB31 = 0x107c,
+ PTC0 = 0x2000,
+ PTC1 = 0x2004,
+ PTC2 = 0x2008,
+ PTC3 = 0x200c,
+ PTC4 = 0x2010,
+ PTC5 = 0x2014,
+ PTC6 = 0x2018,
+ PTC7 = 0x201c,
+ PTC8 = 0x2020,
+ PTC9 = 0x2024,
+ PTC10 = 0x2028,
+ PTC11 = 0x202c,
+ PTC12 = 0x2030,
+ PTC13 = 0x2034,
+ PTC14 = 0x2038,
+ PTC15 = 0x203c,
+ PTC16 = 0x2040,
+ PTC17 = 0x2044,
+ PTC18 = 0x2048,
+ PTC19 = 0x204c,
+ PTC20 = 0x2050,
+ PTC21 = 0x2054,
+ PTC22 = 0x2058,
+ PTC23 = 0x205c,
+ PTC24 = 0x2060,
+ PTC25 = 0x2064,
+ PTC26 = 0x2068,
+ PTC27 = 0x206c,
+ PTC28 = 0x2070,
+ PTC29 = 0x2074,
+ PTC30 = 0x2078,
+ PTC31 = 0x207c,
+ PTD0 = 0x3000,
+ PTD1 = 0x3004,
+ PTD2 = 0x3008,
+ PTD3 = 0x300c,
+ PTD4 = 0x3010,
+ PTD5 = 0x3014,
+ PTD6 = 0x3018,
+ PTD7 = 0x301c,
+ PTD8 = 0x3020,
+ PTD9 = 0x3024,
+ PTD10 = 0x3028,
+ PTD11 = 0x302c,
+ PTD12 = 0x3030,
+ PTD13 = 0x3034,
+ PTD14 = 0x3038,
+ PTD15 = 0x303c,
+ PTD16 = 0x3040,
+ PTD17 = 0x3044,
+ PTD18 = 0x3048,
+ PTD19 = 0x304c,
+ PTD20 = 0x3050,
+ PTD21 = 0x3054,
+ PTD22 = 0x3058,
+ PTD23 = 0x305c,
+ PTD24 = 0x3060,
+ PTD25 = 0x3064,
+ PTD26 = 0x3068,
+ PTD27 = 0x306c,
+ PTD28 = 0x3070,
+ PTD29 = 0x3074,
+ PTD30 = 0x3078,
+ PTD31 = 0x307c,
+ PTE0 = 0x4000,
+ PTE1 = 0x4004,
+ PTE2 = 0x4008,
+ PTE3 = 0x400c,
+ PTE4 = 0x4010,
+ PTE5 = 0x4014,
+ PTE6 = 0x4018,
+ PTE7 = 0x401c,
+ PTE8 = 0x4020,
+ PTE9 = 0x4024,
+ PTE10 = 0x4028,
+ PTE11 = 0x402c,
+ PTE12 = 0x4030,
+ PTE13 = 0x4034,
+ PTE14 = 0x4038,
+ PTE15 = 0x403c,
+ PTE16 = 0x4040,
+ PTE17 = 0x4044,
+ PTE18 = 0x4048,
+ PTE19 = 0x404c,
+ PTE20 = 0x4050,
+ PTE21 = 0x4054,
+ PTE22 = 0x4058,
+ PTE23 = 0x405c,
+ PTE24 = 0x4060,
+ PTE25 = 0x4064,
+ PTE26 = 0x4068,
+ PTE27 = 0x406c,
+ PTE28 = 0x4070,
+ PTE29 = 0x4074,
+ PTE30 = 0x4078,
+ PTE31 = 0x407c,
+
+ LED_RED = PTB18,
+ LED_GREEN = PTB19,
+ LED_BLUE = PTD1,
+
+ // mbed original LED naming
+ LED1 = LED_BLUE,
+ LED2 = LED_GREEN,
+ LED3 = LED_RED,
+ LED4 = LED_RED,
+
+ // USB Pins
+ USBTX = PTA2,
+ USBRX = PTA1,
+
+ // Arduino Headers
+ D0 = PTA1,
+ D1 = PTA2,
+ D2 = PTD4,
+ D3 = PTA12,
+ D4 = PTA4,
+ D5 = PTA5,
+ D6 = PTC8,
+ D7 = PTC9,
+ D8 = PTA13,
+ D9 = PTD5,
+ D10 = PTD0,
+ D11 = PTD2,
+ D12 = PTD3,
+ D13 = PTD1,
+ D14 = PTE0,
+ D15 = PTE1,
+
+ A0 = PTB0,
+ A1 = PTB1,
+ A2 = PTB2,
+ A3 = PTB3,
+ A4 = PTC2,
+ A5 = PTC1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+/* PullDown not available for KL25 */
+typedef enum {
+ PullNone = 0,
+ PullUp = 2,
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL25Z/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,34 +1,34 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PortA = 0,
+ PortB = 1,
+ PortC = 2,
+ PortD = 3,
+ PortE = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,14 +1,14 @@
-
-LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x20000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 0x4000 - 0xC0 = 0x3F40
- RW_IRAM1 0x1FFFF0C0 0x3F40 {
- .ANY (+RW +ZI)
- }
-}
-
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_KL25Z/TOOLCHAIN_ARM_STD/system_MKL25Z4.o has changed
--- a/TARGET_KL25Z/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_KL25Z/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "MKL25Z4.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MKL25Z4.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_KL25Z/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL25Z/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_KL25Z/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,58 +1,58 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 24 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 24 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- a/TARGET_KL25Z/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL25Z/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,75 +1,75 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_out;
- __I uint32_t *reg_in;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- __IO uint32_t *MOD;
- __IO uint32_t *CNT;
- __IO uint32_t *CnV;
-};
-
-struct serial_s {
- UARTLP_Type *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-struct i2c_s {
- I2C_Type *i2c;
-};
-
-struct spi_s {
- SPI_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MOD;
+ __IO uint32_t *CNT;
+ __IO uint32_t *CnV;
+};
+
+struct serial_s {
+ UARTLP_Type *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct i2c_s {
+ I2C_Type *i2c;
+};
+
+struct spi_s {
+ SPI_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_KL25Z/system_MKL25Z4.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_KL25Z/system_MKL25Z4.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,84 +1,84 @@
-/*
-** ###################################################################
-** Processor: MKL25Z128VLK4
-** Compilers: ARM Compiler
-** Freescale C/C++ for Embedded ARM
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-**
-** Reference manual: KL25RM, Rev.1, Jun 2012
-** Version: rev. 1.1, 2012-06-21
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
-**
-** http: www.freescale.com
-** mail: support@freescale.com
-**
-** Revisions:
-** - rev. 1.0 (2012-06-13)
-** Initial version.
-** - rev. 1.1 (2012-06-21)
-** Update according to reference manual rev. 1.
-**
-** ###################################################################
-*/
-
-/**
- * @file MKL25Z4
- * @version 1.1
- * @date 2012-06-21
- * @brief Device specific configuration file for MKL25Z4 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef SYSTEM_MKL25Z4_H_
-#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL25Z4_H_
+#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/LPC11xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,602 @@
+/****************************************************************************
+ * $Id:: LPC11xx.h 9198 2012-05-29 usb00175 $
+ * Project: NXP LPC11xx software example
+ *
+ * Description:
+ * CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * NXP LPC11xx Device Series
+
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+
+****************************************************************************/
+#ifndef __LPC11xx_H__
+#define __LPC11xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
+ This file defines all structures and symbols for LPC11xx:
+ - Registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
+ WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
+ WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
+ WAKEUP2_IRQn = 2,
+ WAKEUP3_IRQn = 3,
+ WAKEUP4_IRQn = 4,
+ WAKEUP5_IRQn = 5,
+ WAKEUP6_IRQn = 6,
+ WAKEUP7_IRQn = 7,
+ WAKEUP8_IRQn = 8,
+ WAKEUP9_IRQn = 9,
+ WAKEUP10_IRQn = 10,
+ WAKEUP11_IRQn = 11,
+ WAKEUP12_IRQn = 12,
+ CAN_IRQn = 13, /*!< CAN Interrupt */
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ Reserved0_IRQn = 22, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 23,
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
+ EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
+ EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
+ EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC11xx_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_LPC11xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __I uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
+ uint32_t RESERVED1[1];
+ __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
+ __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
+ uint32_t RESERVED6[12];
+
+ __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
+ __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
+ __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED9[5];
+
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
+ uint32_t RESERVED10[18];
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
+
+ uint32_t RESERVED13[7];
+ __IO uint32_t NMISRC; /*!< Offset: 0x174 NMI source selection register (R/W) */
+ uint32_t RESERVED14[34];
+
+ __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ __O uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
+ __I uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/) */
+ __IO uint32_t STARTAPRP1; /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
+ __O uint32_t STARTRSRP1CLR; /*!< Offset: 0x218 Start logic reset Register 0 ( /W). (LPC11UXX only) */
+ __IO uint32_t STARTSRP1; /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
+ uint32_t RESERVED17[4];
+
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED15[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_SYSCON */
+
+
+/*------------- Pin Connect Block (IOCON) --------------------------------*/
+/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
+ uint32_t RESERVED0[1];
+ __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
+ __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
+ __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
+ __IO uint32_t SSEL1_LOC; /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
+ __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
+
+ __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
+ __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
+ __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
+ __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
+ __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
+ __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
+ __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
+ __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
+
+ __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
+ __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
+ __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
+ __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
+ __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
+ __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
+ __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
+ __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
+
+ __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
+ __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
+ __IO uint32_t SWCLK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
+ __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
+ __IO uint32_t R_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
+ __IO uint32_t R_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
+ __IO uint32_t R_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
+
+ __IO uint32_t R_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
+ __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
+ __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
+ __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
+ __IO uint32_t SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
+ __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
+ __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
+ __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
+
+ __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
+ __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
+ __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
+ __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
+ __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
+ __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
+ __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
+ __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
+
+ __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
+ __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
+ __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
+ __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
+ __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
+ __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_IOCON */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC11xx_PMU */
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
+ struct {
+ uint32_t RESERVED0[4095];
+ __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
+ };
+ };
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
+ __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
+ __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
+ __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
+ __I uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
+ __I uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
+ __O uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (/W) */
+} LPC_GPIO_TypeDef;
+/*@}*/ /* end of group LPC11xx_GPIO */
+
+/*------------- Timer (TMR) --------------------------------------------------*/
+/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ union {
+ __IO uint32_t MR[4]; /*!< Offset: Match Register base */
+ struct{
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ };
+ };
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ uint32_t RESERVED1[2];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED2[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+ __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
+} LPC_TMR_TypeDef;
+/*@}*/ /* end of group LPC11xx_TMR */
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R) */
+} LPC_UART_TypeDef;
+/*@}*/ /* end of group LPC11xx_UART */
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __I uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
+ __I uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
+ __O uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
+} LPC_SSP_TypeDef;
+/*@}*/ /* end of group LPC11xx_SSP */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+/*@}*/ /* end of group LPC11xx_I2C */
+
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
+ uint32_t RESERVED0;
+ __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+ __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WDT_TypeDef;
+/*@}*/ /* end of group LPC11xx_WDT */
+
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+} LPC_ADC_TypeDef;
+/*@}*/ /* end of group LPC11xx_ADC */
+
+
+/*------------- CAN Controller (CAN) ----------------------------*/
+/** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CNTL; /* 0x000 */
+ __IO uint32_t STAT;
+ __IO uint32_t EC;
+ __IO uint32_t BT;
+ __IO uint32_t INT;
+ __IO uint32_t TEST;
+ __IO uint32_t BRPE;
+ uint32_t RESERVED0;
+ __IO uint32_t IF1_CMDREQ; /* 0x020 */
+ __IO uint32_t IF1_CMDMSK;
+ __IO uint32_t IF1_MSK1;
+ __IO uint32_t IF1_MSK2;
+ __IO uint32_t IF1_ARB1;
+ __IO uint32_t IF1_ARB2;
+ __IO uint32_t IF1_MCTRL;
+ __IO uint32_t IF1_DA1;
+ __IO uint32_t IF1_DA2;
+ __IO uint32_t IF1_DB1;
+ __IO uint32_t IF1_DB2;
+ uint32_t RESERVED1[13];
+ __IO uint32_t IF2_CMDREQ; /* 0x080 */
+ __IO uint32_t IF2_CMDMSK;
+ __IO uint32_t IF2_MSK1;
+ __IO uint32_t IF2_MSK2;
+ __IO uint32_t IF2_ARB1;
+ __IO uint32_t IF2_ARB2;
+ __IO uint32_t IF2_MCTRL;
+ __IO uint32_t IF2_DA1;
+ __IO uint32_t IF2_DA2;
+ __IO uint32_t IF2_DB1;
+ __IO uint32_t IF2_DB2;
+ uint32_t RESERVED2[21];
+ __I uint32_t TXREQ1; /* 0x100 */
+ __I uint32_t TXREQ2;
+ uint32_t RESERVED3[6];
+ __I uint32_t ND1; /* 0x120 */
+ __I uint32_t ND2;
+ uint32_t RESERVED4[6];
+ __I uint32_t IR1; /* 0x140 */
+ __I uint32_t IR2;
+ uint32_t RESERVED5[6];
+ __I uint32_t MSGV1; /* 0x160 */
+ __I uint32_t MSGV2;
+ uint32_t RESERVED6[6];
+ __IO uint32_t CLKDIV; /* 0x180 */
+} LPC_CAN_TypeDef;
+/*@}*/ /* end of group LPC11xx_CAN */
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_CAN_BASE (LPC_APB0_BASE + 0x50000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
+
+/* AHB peripherals */
+#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
+#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
+#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
+#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
+#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_CAN ((LPC_CAN_TypeDef *) LPC_CAN_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11xx_H__ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,233 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 12
+#define PIN_SHIFT 8
+
+typedef enum {
+ // LPC1114 Pin Names (PORT[15:12] + PIN[11:8] + IOCON offset[7:0])
+
+ P0_0 = (0 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x0c,
+ P0_1 = (0 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x10,
+ P0_2 = (0 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x1c,
+ P0_3 = (0 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x2c,
+ P0_4 = (0 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x30,
+ P0_5 = (0 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x34,
+ P0_6 = (0 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x4c,
+ P0_7 = (0 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x50,
+ P0_8 = (0 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x60,
+ P0_9 = (0 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x64,
+ P0_11 = (0 << PORT_SHIFT) | (11 << PIN_SHIFT) | 0x74,
+
+ P1_0 = (1 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x78,
+ P1_1 = (1 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x7c,
+ P1_2 = (1 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x80,
+ P1_4 = (1 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x94,
+ P1_5 = (1 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0xa0,
+ P1_6 = (1 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0xa4,
+ P1_7 = (1 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0xa8,
+ P1_8 = (1 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x14,
+ P1_9 = (1 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x38,
+ P1_10 = (1 << PORT_SHIFT) | (10 << PIN_SHIFT) | 0x6c,
+ P1_11 = (1 << PORT_SHIFT) | (11 << PIN_SHIFT) | 0x98,
+
+ P2_0 = (2 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x08,
+ P2_1 = (2 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x28,
+ P2_2 = (2 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x5c,
+ P2_3 = (2 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0x8c,
+ P2_4 = (2 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x40,
+ P2_5 = (2 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x44,
+ P2_6 = (2 << PORT_SHIFT) | (6 << PIN_SHIFT) | 0x00,
+ P2_7 = (2 << PORT_SHIFT) | (7 << PIN_SHIFT) | 0x20,
+ P2_8 = (2 << PORT_SHIFT) | (8 << PIN_SHIFT) | 0x24,
+ P2_9 = (2 << PORT_SHIFT) | (9 << PIN_SHIFT) | 0x54,
+ P2_10 = (2 << PORT_SHIFT) | (10 << PIN_SHIFT) | 0x58,
+ P2_11 = (2 << PORT_SHIFT) | (11 << PIN_SHIFT) | 0x70,
+
+ P3_0 = (3 << PORT_SHIFT) | (0 << PIN_SHIFT) | 0x84,
+ P3_1 = (3 << PORT_SHIFT) | (1 << PIN_SHIFT) | 0x88,
+ P3_2 = (3 << PORT_SHIFT) | (2 << PIN_SHIFT) | 0x9c,
+ P3_3 = (3 << PORT_SHIFT) | (3 << PIN_SHIFT) | 0xac,
+ P3_4 = (3 << PORT_SHIFT) | (4 << PIN_SHIFT) | 0x3c,
+ P3_5 = (3 << PORT_SHIFT) | (5 << PIN_SHIFT) | 0x48,
+
+ // mbed DIP Pin Names (CQ board)
+ p4 = P0_0,
+ p5 = P0_9,
+ p6 = P0_8,
+ p7 = P0_6,
+ p8 = P1_5,
+ p9 = P1_7,
+ p10 = P1_6,
+ p11 = P0_7,
+ p12 = P1_0,
+ p13 = P1_1,
+ p14 = P1_2,
+ p15 = P0_11,
+ p16 = P1_0,
+ p17 = P1_1,
+ p18 = P1_2,
+ p20 = P1_4,
+ p22 = P0_2,
+ p23 = P0_11,
+ p24 = P0_2,
+ p25 = P1_8,
+ p26 = P1_9,
+ p27 = P0_4,
+ p28 = P0_5,
+ p29 = P0_3,
+ p30 = P0_1,
+
+ // Other mbed Pin Names
+ LED1 = P1_5,
+ LED2 = P0_7,
+ LED3 = P1_5,
+ LED4 = P0_7,
+
+ USBTX = P1_7,
+ USBRX = P1_6,
+
+ // mbed DIP Pin Names (LPCXpresso LPC1114)
+ xp4 = P0_0,
+ xp5 = P0_9,
+ xp6 = P0_8,
+ xp7 = P2_11,
+ xp8 = P0_2,
+ xp9 = P1_7,
+ xp10 = P1_6,
+ xp11 = P0_7,
+ xp12 = P2_0,
+ xp13 = P2_1,
+ xp14 = P2_2,
+ xp15 = P0_11,
+ xp16 = P1_0,
+ xp17 = P1_1,
+ xp18 = P1_2,
+ xp20 = P1_4,
+ xp21 = P1_5,
+ xp22 = P1_8,
+ xp23 = P0_6,
+ xp25 = P3_0,
+ xp26 = P3_1,
+ xp27 = P3_2,
+
+ xp29 = P3_3,
+ xp30 = P2_10,
+ xp31 = P2_9,
+ xp32 = P2_8,
+ xp33 = P2_7,
+ xp34 = P2_6,
+ xp35 = P2_5,
+ xp36 = P2_4,
+ xp37 = P2_3,
+ xp38 = P1_11,
+ xp39 = P1_10,
+ xp40 = P1_9,
+ xp41 = P0_4,
+ xp42 = P0_5,
+ xp43 = P0_3,
+ xp44 = P0_1,
+
+ // Other mbed Pin Names
+ xLED1 = P0_7,
+
+ // DIP Package Names
+
+ dp1 = P0_8,
+ dp2 = P0_9,
+ dp4 = P0_11,
+ dp5 = P0_5,
+ dp6 = P0_6,
+ dp9 = P1_0,
+ dp10 = P1_1,
+ dp11 = P1_2,
+ dp13 = P1_4,
+ dp14 = P1_5,
+ dp15 = P1_6,
+ dp16 = P1_7,
+ dp17 = P1_8,
+ dp18 = P1_9,
+ dp23 = P0_0,
+ dp24 = P0_1,
+ dp25 = P0_2,
+ dp26 = P0_3,
+ dp27 = P0_4,
+ dp28 = P0_7,
+
+ dip1 = P0_8,
+ dip2 = P0_9,
+ dip4 = P0_11,
+ dip5 = P0_5,
+ dip6 = P0_6,
+ dip9 = P1_0,
+ dip10 = P1_1,
+ dip11 = P1_2,
+ dip13 = P1_4,
+ dip14 = P1_5,
+ dip15 = P1_6,
+ dip16 = P1_7,
+ dip17 = P1_8,
+ dip18 = P1_9,
+ dip23 = P0_0,
+ dip24 = P0_1,
+ dip25 = P0_2,
+ dip26 = P0_3,
+ dip27 = P0_4,
+ dip28 = P0_7,
+
+
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = WAKEUP0_IRQn,
+ CHANNEL1 = WAKEUP1_IRQn,
+ CHANNEL2 = WAKEUP2_IRQn,
+ CHANNEL3 = WAKEUP3_IRQn,
+ CHANNEL4 = WAKEUP4_IRQn,
+ CHANNEL5 = WAKEUP5_IRQn,
+ CHANNEL6 = WAKEUP6_IRQn,
+ CHANNEL7 = WAKEUP7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/LPC1114.sct Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0xF40
+ RW_IRAM1 0x100000C0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
+
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC1114/TOOLCHAIN_ARM_MICRO/system_LPC11xx.o has changed
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_LPC1114/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC11xx.h" +#include "cmsis_nvic.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cm0.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cm0plus.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cm3.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cm4.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include <stdint.h> /* standard types definitions */
+#include <core_cmInstr.h> /* Core Instruction Access */
+#include <core_cmFunc.h> /* Core Function Access */
+#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = ticks - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cm4_simd.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cmFunc.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/core_cmInstr.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_LPC1114/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -0,0 +1,59 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ __I uint32_t *reg_mask_read;
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_write;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ uint32_t pin_number = ((obj->pin & 0x0F00) >> 8);
+ if (value)
+ *obj->reg_write |= (1 << pin_number);
+ else
+ *obj->reg_write &= ~(1 << pin_number);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_mask_read) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+ PinName pin;
+ __I uint32_t *reg_mask_read;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_data;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC1114/system_LPC11xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -0,0 +1,64 @@
+/**************************************************************************//**
+ * @file system_LPC11xx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11xx/LPC11Cxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11xx_H
+#define __SYSTEM_LPC11xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11xx_H */
--- a/TARGET_LPC11U24/LPC11Uxx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/LPC11Uxx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,670 +1,670 @@
-
-/****************************************************************************************************//**
- * @file LPC11Uxx.h
- *
- *
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
- * default LPC11Uxx Device Series
- *
- * @version V0.1
- * @date 21. March 2011
- *
- * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
- *
- * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
- * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
- *
- *******************************************************************************************************/
-
-// ################################################################################
-// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
-// ################################################################################
-
-/** @addtogroup NXP
- * @{
- */
-
-/** @addtogroup LPC11Uxx
- * @{
- */
-
-#ifndef __LPC11UXX_H__
-#define __LPC11UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#if defined ( __CC_ARM )
- #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
-FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
- FLEX_INT1_IRQn = 1,
- FLEX_INT2_IRQn = 2,
- FLEX_INT3_IRQn = 3,
- FLEX_INT4_IRQn = 4,
- FLEX_INT5_IRQn = 5,
- FLEX_INT6_IRQn = 6,
- FLEX_INT7_IRQn = 7,
- GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
- GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
- Reserved0_IRQn = 10, /*!< Reserved Interrupt */
- Reserved1_IRQn = 11,
- Reserved2_IRQn = 12,
- Reserved3_IRQn = 13,
- SSP1_IRQn = 14, /*!< SSP1 Interrupt */
- I2C_IRQn = 15, /*!< I2C Interrupt */
- TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
- TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
- TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
- TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
- SSP0_IRQn = 20, /*!< SSP0 Interrupt */
- UART_IRQn = 21, /*!< UART Interrupt */
- USB_IRQn = 22, /*!< USB IRQ Interrupt */
- USB_FIQn = 23, /*!< USB FIQ Interrupt */
- ADC_IRQn = 24, /*!< A/D Converter Interrupt */
- WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
- BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
- FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
- Reserved4_IRQn = 28, /*!< Reserved Interrupt */
- Reserved5_IRQn = 29, /*!< Reserved Interrupt */
- USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
- Reserved6_IRQn = 31, /*!< Reserved Interrupt */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
-
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
-#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- I2C -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
- */
-
-typedef struct { /*!< (@ 0x40000000) I2C Structure */
- __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
- __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
- __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
- __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
- __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
- __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
- __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
- __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
- __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
- __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
- __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
- __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
-union{
- __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
- struct{
- __IO uint32_t MASK0;
- __IO uint32_t MASK1;
- __IO uint32_t MASK2;
- __IO uint32_t MASK3;
- };
- };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- WWDT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
- */
-
-typedef struct { /*!< (@ 0x40004000) WWDT Structure */
- __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
- __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
- __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
- __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
- __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
- __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
- __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USART -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
- */
-
-typedef struct { /*!< (@ 0x40008000) USART Structure */
-
- union {
- __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
- __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
- };
-
- union {
- __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
- __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- };
-
- union {
- __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
- __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
- __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
- __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
- __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
- __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
- __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
- __I uint32_t RESERVED1;
- __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
- __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
- __IO uint32_t SYNCCTRL;
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Timer -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
- */
-
-typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
- __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
- __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
- __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
- __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
- __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
- __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
- };
- };
-__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
- __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
-} LPC_CTxxBx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- ADC -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
- */
-
-typedef struct { /*!< (@ 0x4001C000) ADC Structure */
- __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
- __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
- __I uint32_t RESERVED0[1];
- __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
- union{
- __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
- struct{
- __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
- __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
- __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
- __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
- __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
- __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
- __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
- __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
- };
- };
- __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- PMU -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
- */
-
-typedef struct { /*!< (@ 0x40038000) PMU Structure */
- __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
- union{
- __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
- struct{
- __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
- __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
- __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
- __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
- };
- };
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- FLASHCTRL -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
- */
-
-typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
- __I uint32_t RESERVED0[4];
- __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
- __I uint32_t RESERVED1[3];
- __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
- __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
- __I uint32_t RESERVED2[1];
- __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
- __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
- __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
- __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
- __I uint32_t RESERVED3[1001];
- __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
- __I uint32_t RESERVED4[1];
- __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SSP0/1 -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
- */
-
-typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
- __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
- __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
- __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
- __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
- __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSPx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- IOCONFIG -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
- */
-
-typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
- __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
- __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
- __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
- __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
- __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
- __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
- __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
- __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
- __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
- __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
- __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
- __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
- __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
- __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
- __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
- __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
- __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
- __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
- __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
- __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
- __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
- __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
- __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
- __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
- __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
- __IO uint32_t PIO1_1;
- __IO uint32_t PIO1_2;
- __IO uint32_t PIO1_3;
- __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
- __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
- __IO uint32_t PIO1_6;
- __IO uint32_t PIO1_7;
- __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
- __IO uint32_t PIO1_9;
- __IO uint32_t PIO1_10;
- __IO uint32_t PIO1_11;
- __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
- __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
- __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
- __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
- __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
- __IO uint32_t PIO1_17;
- __IO uint32_t PIO1_18;
- __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
- __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
- __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
- __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
- __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
- __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
- __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
- __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
- __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
- __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
- __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
- __IO uint32_t PIO1_30;
- __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SYSCON -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
- */
-
-typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
- __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
- __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
- __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
- __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
- __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
- __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
- __I uint32_t RESERVED0[2];
- __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
- __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
- __I uint32_t RESERVED1[2];
- __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
- __I uint32_t RESERVED2[3];
- __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
- __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
- __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
- __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
- __I uint32_t RESERVED3[8];
- __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
- __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
- __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
- __I uint32_t RESERVED4[1];
- __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
- __I uint32_t RESERVED5[4];
- __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
- __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
- __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
- __I uint32_t RESERVED6[8];
- __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
- __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
- __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
- __I uint32_t RESERVED7[5];
- __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
- __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
- __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
- __I uint32_t RESERVED8[5];
- __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
- __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
- __I uint32_t RESERVED9[18];
- __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
- __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
- __I uint32_t RESERVED10[6];
- __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
- __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
- __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
- __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
- __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
- __I uint32_t RESERVED11[25];
- __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
- __I uint32_t RESERVED12[3];
- __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
- __I uint32_t RESERVED13[6];
- __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
- __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
- __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
- __I uint32_t RESERVED14[110];
- __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PIN_INT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
- */
-
-typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
- __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
- __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_GROUP_INT0/1 -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
- */
-
-typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
- __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
- __I uint32_t RESERVED1[6];
- __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INTx_Type;
-
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USB -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
- */
-
-typedef struct { /*!< (@ 0x40080000) USB Structure */
- __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
- __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
- __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
- __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
- __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
- __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
- __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
- __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
- __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
- __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
- __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
- __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
- __I uint32_t RESERVED0[1];
- __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PORT -----
-// ------------------------------------------------------------------------------------------------
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
- */
-
-typedef struct {
- union {
- struct {
- __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
- __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
- };
- __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
- };
- __I uint32_t RESERVED0[1008];
- union {
- struct {
- __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
- __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
- };
- __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
- };
- uint32_t RESERVED1[960];
- __IO uint32_t DIR[2]; /* 0x2000 */
- uint32_t RESERVED2[30];
- __IO uint32_t MASK[2]; /* 0x2080 */
- uint32_t RESERVED3[30];
- __IO uint32_t PIN[2]; /* 0x2100 */
- uint32_t RESERVED4[30];
- __IO uint32_t MPIN[2]; /* 0x2180 */
- uint32_t RESERVED5[30];
- __IO uint32_t SET[2]; /* 0x2200 */
- uint32_t RESERVED6[30];
- __O uint32_t CLR[2]; /* 0x2280 */
- uint32_t RESERVED7[30];
- __O uint32_t NOT[2]; /* 0x2300 */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM )
- #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral memory map -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE (0x40000000)
-#define LPC_WWDT_BASE (0x40004000)
-#define LPC_USART_BASE (0x40008000)
-#define LPC_CT16B0_BASE (0x4000C000)
-#define LPC_CT16B1_BASE (0x40010000)
-#define LPC_CT32B0_BASE (0x40014000)
-#define LPC_CT32B1_BASE (0x40018000)
-#define LPC_ADC_BASE (0x4001C000)
-#define LPC_PMU_BASE (0x40038000)
-#define LPC_FLASHCTRL_BASE (0x4003C000)
-#define LPC_SSP0_BASE (0x40040000)
-#define LPC_SSP1_BASE (0x40058000)
-#define LPC_IOCON_BASE (0x40044000)
-#define LPC_SYSCON_BASE (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
-#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
-#define LPC_USB_BASE (0x40080000)
-#define LPC_GPIO_BASE (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral declaration -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
-#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
-#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
-#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
-#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
-#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
-#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
-#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
-#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
-#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
-#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
-#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group LPC11Uxx */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif // __LPC11UXX_H__
+
+/****************************************************************************************************//**
+ * @file LPC11Uxx.h
+ *
+ *
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * default LPC11Uxx Device Series
+ *
+ * @version V0.1
+ * @date 21. March 2011
+ *
+ * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
+ *
+ * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
+ * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
+ *
+ *******************************************************************************************************/
+
+// ################################################################################
+// Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
+// ################################################################################
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC11Uxx
+ * @{
+ */
+
+#ifndef __LPC11UXX_H__
+#define __LPC11UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
+FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
+ FLEX_INT1_IRQn = 1,
+ FLEX_INT2_IRQn = 2,
+ FLEX_INT3_IRQn = 3,
+ FLEX_INT4_IRQn = 4,
+ FLEX_INT5_IRQn = 5,
+ FLEX_INT6_IRQn = 6,
+ FLEX_INT7_IRQn = 7,
+ GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
+ GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
+ Reserved0_IRQn = 10, /*!< Reserved Interrupt */
+ Reserved1_IRQn = 11,
+ Reserved2_IRQn = 12,
+ Reserved3_IRQn = 13,
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ USB_IRQn = 22, /*!< USB IRQ Interrupt */
+ USB_FIQn = 23, /*!< USB FIQ Interrupt */
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
+ Reserved4_IRQn = 28, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 29, /*!< Reserved Interrupt */
+ USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
+ Reserved6_IRQn = 31, /*!< Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
+
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
+ */
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
+ __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
+ __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
+ __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
+ __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
+union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
+ */
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
+ __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
+ */
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL;
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Timer -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
+ */
+
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
+} LPC_CTxxBx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
+ __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
+ __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
+ __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
+ __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
+ __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
+ __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
+ __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
+ */
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
+ */
+
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCONFIG -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
+ __IO uint32_t PIO1_1;
+ __IO uint32_t PIO1_2;
+ __IO uint32_t PIO1_3;
+ __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6;
+ __IO uint32_t PIO1_7;
+ __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
+ __IO uint32_t PIO1_9;
+ __IO uint32_t PIO1_10;
+ __IO uint32_t PIO1_11;
+ __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17;
+ __IO uint32_t PIO1_18;
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30;
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
+ */
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
+ __I uint32_t RESERVED3[8];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED4[1];
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED6[8];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED7[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED8[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED9[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED11[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0/1 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
+ */
+
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INTx_Type;
+
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
+ */
+
+typedef struct { /*!< (@ 0x40080000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /* 0x2000 */
+ uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /* 0x2080 */
+ uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /* 0x2100 */
+ uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /* 0x2180 */
+ uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /* 0x2200 */
+ uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /* 0x2280 */
+ uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /* 0x2300 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group LPC11Uxx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC11UXX_H__
--- a/TARGET_LPC11U24/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,71 +1,71 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_USART_BASE
-} UARTName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C_BASE
-} I2CName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- PWM_1 = 0,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6,
- PWM_7,
- PWM_8,
- PWM_9,
- PWM_10,
- PWM_11
-} PWMName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC11U24/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,165 +1,165 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC11U Pin Names
- P0_0 = 0,
- P0_1 = 1,
- P0_2 = 2,
- P0_3 = 3,
- P0_4 = 4,
- P0_5 = 5,
- P0_6 = 6,
- P0_7 = 7,
- P0_8 = 8,
- P0_9 = 9,
- P0_10 = 10,
- P0_11 = 11,
- P0_12 = 12,
- P0_13 = 13,
- P0_14 = 14,
- P0_15 = 15,
- P0_16 = 16,
- P0_17 = 17,
- P0_18 = 18,
- P0_19 = 19,
- P0_20 = 20,
- P0_21 = 21,
- P0_22 = 22,
- P0_23 = 23,
- P0_24 = 24,
- P0_25 = 25,
- P0_26 = 26,
- P0_27 = 27,
-
- P1_0 = 32,
- P1_1 = 33,
- P1_2 = 34,
- P1_3 = 35,
- P1_4 = 36,
- P1_5 = 37,
- P1_6 = 38,
- P1_7 = 39,
- P1_8 = 40,
- P1_9 = 41,
- P1_10 = 42,
- P1_11 = 43,
- P1_12 = 44,
- P1_13 = 45,
- P1_14 = 46,
- P1_15 = 47,
- P1_16 = 48,
- P1_17 = 49,
- P1_18 = 50,
- P1_19 = 51,
- P1_20 = 52,
- P1_21 = 53,
- P1_22 = 54,
- P1_23 = 55,
- P1_24 = 56,
- P1_25 = 57,
- P1_26 = 58,
- P1_27 = 59,
- P1_28 = 60,
- P1_29 = 61,
-
- P1_31 = 63,
-
- // mbed DIP Pin Names
- p5 = P0_9,
- p6 = P0_8,
- p7 = P1_29,
- p8 = P0_2,
- p9 = P1_27,
- p10 = P1_26,
- p11 = P1_22,
- p12 = P1_21,
- p13 = P1_20,
- p14 = P1_23,
- p15 = P0_11,
- p16 = P0_12,
- p17 = P0_13,
- p18 = P0_14,
- p19 = P0_16,
- p20 = P0_22,
- p21 = P0_7,
- p22 = P0_17,
- p23 = P1_17,
- p24 = P1_18,
- p25 = P1_24,
- p26 = P1_25,
- p27 = P0_4,
- p28 = P0_5,
- p29 = P1_5,
- p30 = P1_2,
-
- p33 = P0_3,
- p34 = P1_15,
- p35 = P0_20,
- p36 = P0_21,
-
- // Other mbed Pin Names
- LED1 = P1_8,
- LED2 = P1_9,
- LED3 = P1_10,
- LED4 = P1_11,
-
- USBTX = P0_19,
- USBRX = P0_18,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
- CHANNEL0 = FLEX_INT0_IRQn,
- CHANNEL1 = FLEX_INT1_IRQn,
- CHANNEL2 = FLEX_INT2_IRQn,
- CHANNEL3 = FLEX_INT3_IRQn,
- CHANNEL4 = FLEX_INT4_IRQn,
- CHANNEL5 = FLEX_INT5_IRQn,
- CHANNEL6 = FLEX_INT6_IRQn,
- CHANNEL7 = FLEX_INT7_IRQn
-} Channel;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- Repeater = 3,
- OpenDrain = 4
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC11U Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+ P0_24 = 24,
+ P0_25 = 25,
+ P0_26 = 26,
+ P0_27 = 27,
+
+ P1_0 = 32,
+ P1_1 = 33,
+ P1_2 = 34,
+ P1_3 = 35,
+ P1_4 = 36,
+ P1_5 = 37,
+ P1_6 = 38,
+ P1_7 = 39,
+ P1_8 = 40,
+ P1_9 = 41,
+ P1_10 = 42,
+ P1_11 = 43,
+ P1_12 = 44,
+ P1_13 = 45,
+ P1_14 = 46,
+ P1_15 = 47,
+ P1_16 = 48,
+ P1_17 = 49,
+ P1_18 = 50,
+ P1_19 = 51,
+ P1_20 = 52,
+ P1_21 = 53,
+ P1_22 = 54,
+ P1_23 = 55,
+ P1_24 = 56,
+ P1_25 = 57,
+ P1_26 = 58,
+ P1_27 = 59,
+ P1_28 = 60,
+ P1_29 = 61,
+
+ P1_31 = 63,
+
+ // mbed DIP Pin Names
+ p5 = P0_9,
+ p6 = P0_8,
+ p7 = P1_29,
+ p8 = P0_2,
+ p9 = P1_27,
+ p10 = P1_26,
+ p11 = P1_22,
+ p12 = P1_21,
+ p13 = P1_20,
+ p14 = P1_23,
+ p15 = P0_11,
+ p16 = P0_12,
+ p17 = P0_13,
+ p18 = P0_14,
+ p19 = P0_16,
+ p20 = P0_22,
+ p21 = P0_7,
+ p22 = P0_17,
+ p23 = P1_17,
+ p24 = P1_18,
+ p25 = P1_24,
+ p26 = P1_25,
+ p27 = P0_4,
+ p28 = P0_5,
+ p29 = P1_5,
+ p30 = P1_2,
+
+ p33 = P0_3,
+ p34 = P1_15,
+ p35 = P0_20,
+ p36 = P0_21,
+
+ // Other mbed Pin Names
+ LED1 = P1_8,
+ LED2 = P1_9,
+ LED3 = P1_10,
+ LED4 = P1_11,
+
+ USBTX = P0_19,
+ USBRX = P0_18,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ CHANNEL0 = FLEX_INT0_IRQn,
+ CHANNEL1 = FLEX_INT1_IRQn,
+ CHANNEL2 = FLEX_INT2_IRQn,
+ CHANNEL3 = FLEX_INT3_IRQn,
+ CHANNEL4 = FLEX_INT4_IRQn,
+ CHANNEL5 = FLEX_INT5_IRQn,
+ CHANNEL6 = FLEX_INT6_IRQn,
+ CHANNEL7 = FLEX_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC11U24/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,31 +1,31 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/LPC11U24.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/LPC11U24.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,17 +1,17 @@
-
-LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x8000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 8KB - 0xC0 = 0x1F40
- RW_IRAM1 0x100000C0 0x1F40 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (USBRAM)
- }
-}
-
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_MICRO/system_LPC11Uxx.o has changed
--- a/TARGET_LPC11U24/TOOLCHAIN_ARM_STD/LPC11U24.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/TOOLCHAIN_ARM_STD/LPC11U24.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,17 +1,17 @@
-
-LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x8000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 8KB - 0xC0 = 0x1F40
- RW_IRAM1 0x100000C0 0x1F40 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (USBRAM)
- }
-}
-
+
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (USBRAM)
+ }
+}
+
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/startup_LPC11xx.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC11U24/TOOLCHAIN_ARM_STD/system_LPC11Uxx.o has changed
--- a/TARGET_LPC11U24/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC11U24/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC11U24 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC11Uxx.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC11Uxx.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC11U24/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC11U24/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC11U24/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,59 +1,59 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- a/TARGET_LPC11U24/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC11U24/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,66 +1,66 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_mpin;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- PWMName pwm;
-};
-
-struct serial_s {
- LPC_USART_Type *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct i2c_s {
- LPC_I2C_Type *i2c;
-};
-
-struct spi_s {
- LPC_SSPx_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_mpin;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_USART_Type *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct i2c_s {
+ LPC_I2C_Type *i2c;
+};
+
+struct spi_s {
+ LPC_SSPx_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC11U24/power_api.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/power_api.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,82 +1,82 @@
-/****************************************************************************
- * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
- * Project: NXP LPC11Uxx software example
- *
- * Description:
- * Power API Header File for NXP LPC11Uxx Device Series
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-****************************************************************************/
-#ifndef __LPC11UXX_POWER_API_H__
-#define __LPC11UXX_POWER_API_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define PWRROMD_PRESENT
-
-typedef struct _PWRD {
- void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
- void (*set_power)(unsigned int cmd[], unsigned int resp[]);
-} PWRD;
-
-typedef struct _ROM {
-#ifdef USBROMD_PRESENT
- const USB * pUSBD;
-#else
- const unsigned p_usbd;
-#endif /* USBROMD_PRESENT */
- const unsigned p_clib;
- const unsigned p_cand;
-#ifdef PWRROMD_PRESENT
- const PWRD * pPWRD;
-#else
- const unsigned p_pwrd;
-#endif /* PWRROMD_PRESENT */
- const unsigned p_dev1;
- const unsigned p_dev2;
- const unsigned p_dev3;
- const unsigned p_dev4;
-} ROM;
-
-//PLL setup related definitions
-#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
-#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
-#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
-#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
-
-#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
-#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
-#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
-#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
-#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
-
-//power setup elated definitions
-#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
-#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
-#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
-#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
-
-#define PARAM_CMD_SUCCESS 0 //power setting successfully found
-#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
-#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
-
-#define MAX_CLOCK_KHZ_PARAM 50000
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC11UXX_POWER_API_H__ */
-
+/****************************************************************************
+ * $Id:: power_api.h 6249 2011-01-25 19:23:47Z usb01267 $
+ * Project: NXP LPC11Uxx software example
+ *
+ * Description:
+ * Power API Header File for NXP LPC11Uxx Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#ifndef __LPC11UXX_POWER_API_H__
+#define __LPC11UXX_POWER_API_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define PWRROMD_PRESENT
+
+typedef struct _PWRD {
+ void (*set_pll)(unsigned int cmd[], unsigned int resp[]);
+ void (*set_power)(unsigned int cmd[], unsigned int resp[]);
+} PWRD;
+
+typedef struct _ROM {
+#ifdef USBROMD_PRESENT
+ const USB * pUSBD;
+#else
+ const unsigned p_usbd;
+#endif /* USBROMD_PRESENT */
+ const unsigned p_clib;
+ const unsigned p_cand;
+#ifdef PWRROMD_PRESENT
+ const PWRD * pPWRD;
+#else
+ const unsigned p_pwrd;
+#endif /* PWRROMD_PRESENT */
+ const unsigned p_dev1;
+ const unsigned p_dev2;
+ const unsigned p_dev3;
+ const unsigned p_dev4;
+} ROM;
+
+//PLL setup related definitions
+#define CPU_FREQ_EQU 0 //main PLL freq must be equal to the specified
+#define CPU_FREQ_LTE 1 //main PLL freq must be less than or equal the specified
+#define CPU_FREQ_GTE 2 //main PLL freq must be greater than or equal the specified
+#define CPU_FREQ_APPROX 3 //main PLL freq must be as close as possible the specified
+
+#define PLL_CMD_SUCCESS 0 //PLL setup successfully found
+#define PLL_INVALID_FREQ 1 //specified freq out of range (either input or output)
+#define PLL_INVALID_MODE 2 //invalid mode (see above for valid) specified
+#define PLL_FREQ_NOT_FOUND 3 //specified freq not found under specified conditions
+#define PLL_NOT_LOCKED 4 //PLL not locked => no changes to the PLL setup
+
+//power setup elated definitions
+#define PARAM_DEFAULT 0 //default power settings (voltage regulator, flash interface)
+#define PARAM_CPU_PERFORMANCE 1 //setup for maximum CPU performance (higher current, more computation)
+#define PARAM_EFFICIENCY 2 //balanced setting (power vs CPU performance)
+#define PARAM_LOW_CURRENT 3 //lowest active current, lowest CPU performance
+
+#define PARAM_CMD_SUCCESS 0 //power setting successfully found
+#define PARAM_INVALID_FREQ 1 //specified freq out of range (=0 or > 50 MHz)
+#define PARAM_INVALID_MODE 2 //specified mode not valid (see above for valid)
+
+#define MAX_CLOCK_KHZ_PARAM 50000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11UXX_POWER_API_H__ */
+
--- a/TARGET_LPC11U24/system_LPC11Uxx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC11U24/system_LPC11Uxx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,64 +1,64 @@
-/**************************************************************************//**
- * @file system_LPC11Uxx.h
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
- * for the NXP LPC11Uxx Device Series
- * @version V1.10
- * @date 24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC11Uxx_H
-#define __SYSTEM_LPC11Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC11Uxx_H */
+/**************************************************************************//**
+ * @file system_LPC11Uxx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11Uxx_H
+#define __SYSTEM_LPC11Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11Uxx_H */
--- a/TARGET_LPC1347/LPC13Uxx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/LPC13Uxx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,776 +1,776 @@
-
-/****************************************************************************************************//**
- * @file LPC13Uxx.h
- *
- *
- *
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
- * default LPC13Uxx Device Series
- *
- * @version V0.1
- * @date 18. Jan 2012
- *
- * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
- *
- * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
- * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
- *
- *******************************************************************************************************/
-
-/** @addtogroup NXP
- * @{
- */
-
-/** @addtogroup LPC13Uxx
- * @{
- */
-
-#ifndef __LPC13UXX_H__
-#define __LPC13UXX_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#if defined ( __CC_ARM )
- #pragma anon_unions
-#endif
-
- /* Interrupt Number Definition */
-
-typedef enum {
-// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
- PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
- PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
- PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
- PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
- PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
- PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
- PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
- PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
- GINT0_IRQn = 8, /*!< 8 GINT0 */
- GINT1_IRQn = 9, /*!< 9 GINT1 */
- Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
- Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
- RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
- Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
- SSP1_IRQn = 14, /*!< 14 SSP1 */
- I2C_IRQn = 15, /*!< 15 I2C */
- CT16B0_IRQn = 16, /*!< 16 CT16B0 */
- CT16B1_IRQn = 17, /*!< 17 CT16B1 */
- CT32B0_IRQn = 18, /*!< 18 CT32B0 */
- CT32B1_IRQn = 19, /*!< 19 CT32B1 */
- SSP0_IRQn = 20, /*!< 20 SSP0 */
- USART_IRQn = 21, /*!< 21 USART */
- USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
- USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
- ADC_IRQn = 24, /*!< 24 ADC */
- WDT_IRQn = 25, /*!< 25 WDT */
- BOD_IRQn = 26, /*!< 26 BOD */
- FMC_IRQn = 27, /*!< 27 FMC */
- Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
- Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
- USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
- Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
- * @{
- */
-
-/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
-
-#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
-#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
-
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- I2C -----
-// ------------------------------------------------------------------------------------------------
-
-
-
-typedef struct { /*!< (@ 0x40000000) I2C Structure */
- __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
- __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
- __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
- __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
- __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
- __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
- union{
- __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
- struct{
- __IO uint32_t ADR1;
- __IO uint32_t ADR2;
- __IO uint32_t ADR3;
- };
- };
- __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
- union{
- __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
- struct{
- __IO uint32_t MASK0;
- __IO uint32_t MASK1;
- __IO uint32_t MASK2;
- __IO uint32_t MASK3;
- };
- };
-} LPC_I2C_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- WWDT -----
-// ------------------------------------------------------------------------------------------------
-
-
-typedef struct { /*!< (@ 0x40004000) WWDT Structure */
- __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
- __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
- __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
- __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
- __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
- __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
- __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
-} LPC_WWDT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USART -----
-// ------------------------------------------------------------------------------------------------
-
-
-typedef struct { /*!< (@ 0x40008000) USART Structure */
-
- union {
- __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
- __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
- };
-
- union {
- __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
- __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
- };
-
- union {
- __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
- __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
- };
- __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
- __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
- __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
- __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
- __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
- __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
- __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
- __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
- __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
- __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
- __I uint32_t RESERVED0[3];
- __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
- __I uint32_t RESERVED1;
- __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
- __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
- __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
- __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
- __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
-} LPC_USART_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- CT16B0 -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
- __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
- };
- };
- __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
- __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
-} LPC_CTxxBx_Type;
-
-typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
- __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
- };
- };
- __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
- __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
-} LPC_CT16B0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- CT16B1 -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
- __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
- };
- };
- __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
- __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
-} LPC_CT16B1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- CT32B0 -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
- __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
- };
- };
- __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
- __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
-} LPC_CT32B0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- CT32B1 -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
- __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
- __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
- __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
- __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
- __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
- __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
- union {
- __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
- struct{
- __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
- __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
- __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
- __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
- };
- };
- __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
- union{
- __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
- struct{
- __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
- __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
- __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
- __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
- };
- };
- __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
- __I uint32_t RESERVED0[12];
- __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
- __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
-} LPC_CT32B1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- ADC -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x4001C000) ADC Structure */
- __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
- __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
- __I uint32_t RESERVED0[1];
- __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
- union{
- __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
- struct{
- __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
- __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
- __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
- __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
- __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
- __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
- __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
- __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
- };
- };
- __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
-} LPC_ADC_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- PMU -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x40038000) PMU Structure */
- __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
- union{
- __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
- struct{
- __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
- __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
- __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
- __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
- };
- };
- __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
-} LPC_PMU_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- FLASHCTRL -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
- __I uint32_t RESERVED0[4];
- __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
- __I uint32_t RESERVED1[3];
- __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
- __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
- __I uint32_t RESERVED2[1];
- __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
- __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
- __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
- __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
- __I uint32_t RESERVED3[1001];
- __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
- __I uint32_t RESERVED4[1];
- __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
-} LPC_FLASHCTRL_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SSP -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
- __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
- __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
- __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
- __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
- __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
- __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
- __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
- __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
- __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
-} LPC_SSPx_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- IOCON -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x40044000) IOCON Structure */
- __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
- __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
- __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
- __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
- __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
- __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
- __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
- __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
- __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
- __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
- __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
- __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
- __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
- __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
- __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
- __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
- __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
- __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
- __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
- __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
- __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
- __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
- __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
- __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
- __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
- __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
- __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
- __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
- __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
- __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
- __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
- __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
- __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
- __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
- __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
- __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
- __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
- __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
- __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
- __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
- __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
- __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
- __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
- __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
- __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
- __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
- __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
- __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
- __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
- __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
- __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
- __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
- __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
- __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
- __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
- __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
-} LPC_IOCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- SYSCON -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
- __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
- __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
- __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
- __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
- __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
- __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
- __I uint32_t RESERVED0[2];
- __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
- __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
- __I uint32_t RESERVED1[2];
- __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
- __I uint32_t RESERVED2[3];
- __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
- __I uint32_t RESERVED3;
- __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
- __I uint32_t RESERVED4[9];
- __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
- __I uint32_t RESERVED5;
- __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
- __I uint32_t RESERVED6;
- __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
- __I uint32_t RESERVED7[4];
- __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
- __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
- __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
- __I uint32_t RESERVED8[3];
- __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
- __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
- __I uint32_t RESERVED9[3];
- __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
- __I uint32_t RESERVED10;
- __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
- __I uint32_t RESERVED11[5];
- __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
- __I uint32_t RESERVED12;
- __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
- __I uint32_t RESERVED13[5];
- __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
- __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
- __I uint32_t RESERVED14[18];
- __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
- __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
- __I uint32_t RESERVED15[6];
- __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
- __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
- __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
- __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
- __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
- __I uint32_t RESERVED16[25];
- __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
- __I uint32_t RESERVED17[3];
- __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
- __I uint32_t RESERVED18[6];
- __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
- __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
- __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
- __I uint32_t RESERVED19[111];
- __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
-} LPC_SYSCON_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PIN_INT -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
- __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
- __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
- __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
- __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
-} LPC_GPIO_PIN_INT_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_GROUP_INT0 -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
- __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
- __I uint32_t RESERVED1[6];
- __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INT0_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_GROUP_INT1 -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
- __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
- __I uint32_t RESERVED0[7];
- __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
- __I uint32_t RESERVED1[6];
- __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
-} LPC_GPIO_GROUP_INT1_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Repetitive Interrupt Timer (RIT) -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
- __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
- __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
- __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
- __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
- __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
- __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
- __I uint32_t RESERVED0[1];
- __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
-} LPC_RITIMER_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- USB -----
-// ------------------------------------------------------------------------------------------------
-typedef struct { /*!< (@ 0x40020000) USB Structure */
- __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
- __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
- __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
- __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
- __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
- __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
- __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
- __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
- __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
- __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
- __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
- __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
- __I uint32_t RESERVED0[1];
- __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
-} LPC_USB_Type;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PORT -----
-// ------------------------------------------------------------------------------------------------
-
-typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
- union {
- struct {
- __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
- __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
- };
- __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
- };
- __I uint32_t RESERVED0[1008];
- union {
- struct {
- __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
- __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
- };
- __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
- };
- __I uint32_t RESERVED1[960];
- __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
- __I uint32_t RESERVED2[30];
- __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
- __I uint32_t RESERVED3[30];
- __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
- __I uint32_t RESERVED4[30];
- __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
- __I uint32_t RESERVED5[30];
- __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
- __I uint32_t RESERVED6[30];
- __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
- __I uint32_t RESERVED7[30];
- __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
-} LPC_GPIO_Type;
-
-
-#if defined ( __CC_ARM )
- #pragma no_anon_unions
-#endif
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral memory map -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C_BASE (0x40000000)
-#define LPC_WWDT_BASE (0x40004000)
-#define LPC_USART_BASE (0x40008000)
-#define LPC_CT16B0_BASE (0x4000C000)
-#define LPC_CT16B1_BASE (0x40010000)
-#define LPC_CT32B0_BASE (0x40014000)
-#define LPC_CT32B1_BASE (0x40018000)
-#define LPC_ADC_BASE (0x4001C000)
-#define LPC_PMU_BASE (0x40038000)
-#define LPC_FLASHCTRL_BASE (0x4003C000)
-#define LPC_SSP0_BASE (0x40040000)
-#define LPC_IOCON_BASE (0x40044000)
-#define LPC_SYSCON_BASE (0x40048000)
-#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
-#define LPC_SSP1_BASE (0x40058000)
-#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
-#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
-#define LPC_RITIMER_BASE (0x40064000)
-#define LPC_USB_BASE (0x40080000)
-#define LPC_GPIO_BASE (0x50000000)
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- Peripheral declaration -----
-// ------------------------------------------------------------------------------------------------
-
-#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
-#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
-#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
-#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
-#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
-#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
-#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
-#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
-#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
-#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
-#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
-#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
-#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
-#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
-#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
-#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
-#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
-#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
-#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
-#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group (null) */
-/** @} */ /* End of group h1usf */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif // __LPC13UXX_H__
+
+/****************************************************************************************************//**
+ * @file LPC13Uxx.h
+ *
+ *
+ *
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * default LPC13Uxx Device Series
+ *
+ * @version V0.1
+ * @date 18. Jan 2012
+ *
+ * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
+ *
+ * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
+ * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
+ *
+ *******************************************************************************************************/
+
+/** @addtogroup NXP
+ * @{
+ */
+
+/** @addtogroup LPC13Uxx
+ * @{
+ */
+
+#ifndef __LPC13UXX_H__
+#define __LPC13UXX_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+ /* Interrupt Number Definition */
+
+typedef enum {
+// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+// ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
+ PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
+ PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
+ PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
+ PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
+ PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
+ PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
+ PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
+ PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
+ GINT0_IRQn = 8, /*!< 8 GINT0 */
+ GINT1_IRQn = 9, /*!< 9 GINT1 */
+ Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
+ Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
+ RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
+ Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
+ SSP1_IRQn = 14, /*!< 14 SSP1 */
+ I2C_IRQn = 15, /*!< 15 I2C */
+ CT16B0_IRQn = 16, /*!< 16 CT16B0 */
+ CT16B1_IRQn = 17, /*!< 17 CT16B1 */
+ CT32B0_IRQn = 18, /*!< 18 CT32B0 */
+ CT32B1_IRQn = 19, /*!< 19 CT32B1 */
+ SSP0_IRQn = 20, /*!< 20 SSP0 */
+ USART_IRQn = 21, /*!< 21 USART */
+ USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
+ USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
+ ADC_IRQn = 24, /*!< 24 ADC */
+ WDT_IRQn = 25, /*!< 25 WDT */
+ BOD_IRQn = 26, /*!< 26 BOD */
+ FMC_IRQn = 27, /*!< 27 FMC */
+ Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
+ Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
+ USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
+ Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
+
+#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
+#include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+
+typedef struct { /*!< (@ 0x40000000) I2C Structure */
+ __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
+ __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
+ __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
+ __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
+ __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
+ __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
+ union{
+ __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
+ struct{
+ __IO uint32_t ADR1;
+ __IO uint32_t ADR2;
+ __IO uint32_t ADR3;
+ };
+ };
+ __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
+ union{
+ __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
+ struct{
+ __IO uint32_t MASK0;
+ __IO uint32_t MASK1;
+ __IO uint32_t MASK2;
+ __IO uint32_t MASK3;
+ };
+ };
+} LPC_I2C_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- WWDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct { /*!< (@ 0x40004000) WWDT Structure */
+ __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+ __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
+ __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
+ __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+ __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
+ __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
+ __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
+} LPC_WWDT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USART -----
+// ------------------------------------------------------------------------------------------------
+
+
+typedef struct { /*!< (@ 0x40008000) USART Structure */
+
+ union {
+ __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
+ __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
+ };
+
+ union {
+ __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
+ __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
+ };
+
+ union {
+ __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
+ __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
+ };
+ __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
+ __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
+ __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
+ __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
+ __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
+ __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
+ __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
+ __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
+ __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
+ __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
+ __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
+ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
+ __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
+ __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
+} LPC_USART_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT16B0 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
+ __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CTxxBx_Type;
+
+typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT16B1 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
+} LPC_CT16B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT32B0 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- CT32B1 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
+ __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+ __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+ __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
+ __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
+ __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
+ __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
+ union {
+ __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+ struct{
+ __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
+ __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
+ __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
+ __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
+ };
+ };
+ __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+ union{
+ __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
+ struct{
+ __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
+ __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
+ __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
+ __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
+ };
+ };
+ __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
+ __I uint32_t RESERVED0[12];
+ __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+ __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
+} LPC_CT32B1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- ADC -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4001C000) ADC Structure */
+ __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
+ __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
+ union{
+ __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
+ struct{
+ __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
+ __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
+ __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
+ __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
+ __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
+ __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
+ __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
+ __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
+ };
+ };
+ __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
+} LPC_ADC_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PMU -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40038000) PMU Structure */
+ __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
+ union{
+ __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
+ struct{
+ __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
+ __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
+ __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
+ __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
+ };
+ };
+ __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
+} LPC_PMU_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- FLASHCTRL -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
+ __I uint32_t RESERVED2[1];
+ __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
+ __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
+ __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
+ __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
+ __I uint32_t RESERVED3[1001];
+ __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
+ __I uint32_t RESERVED4[1];
+ __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
+} LPC_FLASHCTRL_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SSP -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
+ __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
+ __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
+ __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
+ __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
+ __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
+ __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
+ __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
+ __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
+ __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
+} LPC_SSPx_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- IOCON -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40044000) IOCON Structure */
+ __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
+ __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
+ __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
+ __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
+ __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
+ __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
+ __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
+ __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
+ __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
+ __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
+ __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
+ __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
+ __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
+ __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
+ __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
+ __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
+ __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
+ __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
+ __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
+ __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
+ __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
+ __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
+ __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
+ __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
+ __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
+ __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
+ __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
+ __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
+ __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
+ __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
+ __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
+ __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
+ __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
+ __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
+ __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
+ __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
+ __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
+ __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
+ __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
+ __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
+ __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
+ __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
+ __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
+ __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
+ __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
+ __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
+} LPC_IOCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- SYSCON -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
+ __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
+ __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
+ __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
+ __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
+ __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
+ __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
+ __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
+ __I uint32_t RESERVED3;
+ __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
+ __I uint32_t RESERVED4[9];
+ __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
+ __I uint32_t RESERVED5;
+ __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
+ __I uint32_t RESERVED6;
+ __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
+ __I uint32_t RESERVED7[4];
+ __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
+ __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
+ __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
+ __I uint32_t RESERVED8[3];
+ __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
+ __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
+ __I uint32_t RESERVED9[3];
+ __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
+ __I uint32_t RESERVED10;
+ __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
+ __I uint32_t RESERVED11[5];
+ __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
+ __I uint32_t RESERVED12;
+ __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
+ __I uint32_t RESERVED13[5];
+ __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
+ __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
+ __I uint32_t RESERVED14[18];
+ __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
+ __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
+ __I uint32_t RESERVED15[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
+ __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
+ __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
+ __I uint32_t RESERVED16[25];
+ __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
+ __I uint32_t RESERVED17[3];
+ __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
+ __I uint32_t RESERVED18[6];
+ __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
+ __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
+ __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
+ __I uint32_t RESERVED19[111];
+ __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
+} LPC_SYSCON_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
+ __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
+ __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
+} LPC_GPIO_PIN_INT_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT0 -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT0_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_GROUP_INT1 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
+ __I uint32_t RESERVED0[7];
+ __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
+ __I uint32_t RESERVED1[6];
+ __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
+} LPC_GPIO_GROUP_INT1_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Repetitive Interrupt Timer (RIT) -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
+ __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
+ __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
+ __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
+ __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
+ __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
+ __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
+ __I uint32_t RESERVED0[1];
+ __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
+} LPC_RITIMER_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- USB -----
+// ------------------------------------------------------------------------------------------------
+typedef struct { /*!< (@ 0x40020000) USB Structure */
+ __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
+ __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
+ __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
+ __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
+ __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
+ __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
+ __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
+ __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
+ __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
+ __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
+ __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
+ __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
+ __I uint32_t RESERVED0[1];
+ __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
+} LPC_USB_Type;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
+ union {
+ struct {
+ __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
+ __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
+ };
+ __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED0[1008];
+ union {
+ struct {
+ __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
+ __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
+ };
+ __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
+ };
+ __I uint32_t RESERVED1[960];
+ __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
+ __I uint32_t RESERVED2[30];
+ __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
+ __I uint32_t RESERVED3[30];
+ __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
+ __I uint32_t RESERVED4[30];
+ __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
+ __I uint32_t RESERVED5[30];
+ __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
+ __I uint32_t RESERVED6[30];
+ __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
+ __I uint32_t RESERVED7[30];
+ __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
+} LPC_GPIO_Type;
+
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C_BASE (0x40000000)
+#define LPC_WWDT_BASE (0x40004000)
+#define LPC_USART_BASE (0x40008000)
+#define LPC_CT16B0_BASE (0x4000C000)
+#define LPC_CT16B1_BASE (0x40010000)
+#define LPC_CT32B0_BASE (0x40014000)
+#define LPC_CT32B1_BASE (0x40018000)
+#define LPC_ADC_BASE (0x4001C000)
+#define LPC_PMU_BASE (0x40038000)
+#define LPC_FLASHCTRL_BASE (0x4003C000)
+#define LPC_SSP0_BASE (0x40040000)
+#define LPC_IOCON_BASE (0x40044000)
+#define LPC_SYSCON_BASE (0x40048000)
+#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
+#define LPC_SSP1_BASE (0x40058000)
+#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
+#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
+#define LPC_RITIMER_BASE (0x40064000)
+#define LPC_USB_BASE (0x40080000)
+#define LPC_GPIO_BASE (0x50000000)
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+
+#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
+#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
+#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
+#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
+#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
+#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
+#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
+#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
+#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
+#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
+#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
+#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
+#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
+#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
+#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
+#define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
+#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
+#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group (null) */
+/** @} */ /* End of group h1usf */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __LPC13UXX_H__
--- a/TARGET_LPC1347/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,71 +1,71 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_USART_BASE
-} UARTName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C_BASE
-} I2CName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- PWM_1 = 0,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6,
- PWM_7,
- PWM_8,
- PWM_9,
- PWM_10,
- PWM_11
-} PWMName;
-
-#define STDIO_UART_TX UART_TX
-#define STDIO_UART_RX UART_RX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_USART_BASE
+} UARTName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C_BASE
+} I2CName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ PWM_1 = 0,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6,
+ PWM_7,
+ PWM_8,
+ PWM_9,
+ PWM_10,
+ PWM_11
+} PWMName;
+
+#define STDIO_UART_TX UART_TX
+#define STDIO_UART_RX UART_RX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1347/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,150 +1,150 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC1347 Pin Names
- P0_0 = 0,
- P0_1 = 1,
- P0_2 = 2,
- P0_3 = 3,
- P0_4 = 4,
- P0_5 = 5,
- P0_6 = 6,
- P0_7 = 7,
- P0_8 = 8,
- P0_9 = 9,
- P0_10 = 10,
- P0_11 = 11,
- P0_12 = 12,
- P0_13 = 13,
- P0_14 = 14,
- P0_15 = 15,
- P0_16 = 16,
- P0_17 = 17,
- P0_18 = 18,
- P0_19 = 19,
- P0_20 = 20,
- P0_21 = 21,
- P0_22 = 22,
- P0_23 = 23,
-
- P1_13 = 45,
- P1_14 = 46,
- P1_15 = 47,
- P1_16 = 48,
-
- P1_19 = 51,
- P1_20 = 52,
- P1_21 = 53,
- P1_22 = 54,
- P1_23 = 55,
- P1_24 = 56,
- P1_25 = 57,
- P1_26 = 58,
- P1_27 = 59,
- P1_28 = 60,
- P1_29 = 61,
-
- P1_31 = 63,
-
- // DIP Pin Names
- p1 = P0_0,
- p2 = P0_11,
- p3 = P0_12,
- p4 = P0_13,
- p5 = P0_14,
- p6 = P1_31,
- p8 = P0_16,
- p9 = P0_22,
- p10 = P0_23,
- p13 = P1_29,
- p14 = P1_21,
- p15 = P0_8,
- p16 = P0_9,
- p17 = P1_24,
- p18 = P0_4,
- p19 = P1_13,
- p20 = P1_14,
- p21 = P1_22,
- p22 = P0_17,
- p23 = P0_5,
- p24 = P0_21,
- p25 = P0_19,
- p26 = P0_18,
- p27 = P1_15,
- p28 = P1_16,
- p29 = P1_25,
- p30 = P1_19,
- p33 = P0_20,
- p34 = P0_2,
- p35 = P1_26,
- p36 = P1_27,
- p37 = P1_20,
- p38 = P1_23,
- p39 = P0_7,
- p40 = P1_28,
-
- UART_TX = P0_19,
- UART_RX = P0_18,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- LED1 = p21,
- LED2 = p21,
- LED3 = p21,
- LED4 = p21
-} PinName;
-
-typedef enum {
- CHANNEL0 = PIN_INT0_IRQn,
- CHANNEL1 = PIN_INT1_IRQn,
- CHANNEL2 = PIN_INT2_IRQn,
- CHANNEL3 = PIN_INT3_IRQn,
- CHANNEL4 = PIN_INT4_IRQn,
- CHANNEL5 = PIN_INT5_IRQn,
- CHANNEL6 = PIN_INT6_IRQn,
- CHANNEL7 = PIN_INT7_IRQn
-} Channel;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- Repeater = 3,
- OpenDrain = 4
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC1347 Pin Names
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+ P0_18 = 18,
+ P0_19 = 19,
+ P0_20 = 20,
+ P0_21 = 21,
+ P0_22 = 22,
+ P0_23 = 23,
+
+ P1_13 = 45,
+ P1_14 = 46,
+ P1_15 = 47,
+ P1_16 = 48,
+
+ P1_19 = 51,
+ P1_20 = 52,
+ P1_21 = 53,
+ P1_22 = 54,
+ P1_23 = 55,
+ P1_24 = 56,
+ P1_25 = 57,
+ P1_26 = 58,
+ P1_27 = 59,
+ P1_28 = 60,
+ P1_29 = 61,
+
+ P1_31 = 63,
+
+ // DIP Pin Names
+ p1 = P0_0,
+ p2 = P0_11,
+ p3 = P0_12,
+ p4 = P0_13,
+ p5 = P0_14,
+ p6 = P1_31,
+ p8 = P0_16,
+ p9 = P0_22,
+ p10 = P0_23,
+ p13 = P1_29,
+ p14 = P1_21,
+ p15 = P0_8,
+ p16 = P0_9,
+ p17 = P1_24,
+ p18 = P0_4,
+ p19 = P1_13,
+ p20 = P1_14,
+ p21 = P1_22,
+ p22 = P0_17,
+ p23 = P0_5,
+ p24 = P0_21,
+ p25 = P0_19,
+ p26 = P0_18,
+ p27 = P1_15,
+ p28 = P1_16,
+ p29 = P1_25,
+ p30 = P1_19,
+ p33 = P0_20,
+ p34 = P0_2,
+ p35 = P1_26,
+ p36 = P1_27,
+ p37 = P1_20,
+ p38 = P1_23,
+ p39 = P0_7,
+ p40 = P1_28,
+
+ UART_TX = P0_19,
+ UART_RX = P0_18,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ LED1 = p21,
+ LED2 = p21,
+ LED3 = p21,
+ LED4 = p21
+} PinName;
+
+typedef enum {
+ CHANNEL0 = PIN_INT0_IRQn,
+ CHANNEL1 = PIN_INT1_IRQn,
+ CHANNEL2 = PIN_INT2_IRQn,
+ CHANNEL3 = PIN_INT3_IRQn,
+ CHANNEL4 = PIN_INT4_IRQn,
+ CHANNEL5 = PIN_INT5_IRQn,
+ CHANNEL6 = PIN_INT6_IRQn,
+ CHANNEL7 = PIN_INT7_IRQn
+} Channel;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1347/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,31 +1,31 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC1347/TOOLCHAIN_ARM_STD/LPC1347.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/TOOLCHAIN_ARM_STD/LPC1347.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,19 +1,19 @@
-
-LR_IROM1 0x00000000 0x10000 { ; load region size_region
- ER_IROM1 0x00000000 0x10000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 8KB - 0xC0 = 0x1F40
- RW_IRAM1 0x100000C0 0x1F40 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20000000 0x800 { ; RW data
- .ANY (AHBSRAM0)
- }
- RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
- .ANY (AHBSRAM1)
- }
-}
+
+LR_IROM1 0x00000000 0x10000 { ; load region size_region
+ ER_IROM1 0x00000000 0x10000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0x1F40
+ RW_IRAM1 0x100000C0 0x1F40 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x800 { ; RW data
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20004000 0x800 { ; RW data, USB RAM
+ .ANY (AHBSRAM1)
+ }
+}
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/startup_LPC13xx.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC1347/TOOLCHAIN_ARM_STD/system_LPC13Uxx.o has changed
--- a/TARGET_LPC1347/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC1347/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC13XX specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC13Uxx.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC13XX specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC13Uxx.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC1347/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1347/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC1347/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,57 +1,57 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#include "objects.h" + +#endif
--- a/TARGET_LPC1347/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1347/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,70 +1,70 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_mpin;
- PortName port;
- uint32_t mask;
-};
-
-
-struct pwmout_s {
- PWMName pwm;
-};
-
-
-struct serial_s {
- LPC_USART_Type *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-
-struct i2c_s {
- LPC_I2C_Type *i2c;
-};
-
-
-struct spi_s {
- LPC_SSPx_Type *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_mpin;
+ PortName port;
+ uint32_t mask;
+};
+
+
+struct pwmout_s {
+ PWMName pwm;
+};
+
+
+struct serial_s {
+ LPC_USART_Type *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+
+struct i2c_s {
+ LPC_I2C_Type *i2c;
+};
+
+
+struct spi_s {
+ LPC_SSPx_Type *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1347/system_LPC13Uxx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1347/system_LPC13Uxx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,64 +1,64 @@
-/**************************************************************************//**
- * @file system_LPC13Uxx.h
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- * for the NXP LPC13Uxx Device Series
- * @version V1.10
- * @date 24. November 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC13Uxx_H
-#define __SYSTEM_LPC13Uxx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC13Uxx_H */
+/**************************************************************************//**
+ * @file system_LPC13Uxx.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC13Uxx Device Series
+ * @version V1.10
+ * @date 24. November 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC13Uxx_H
+#define __SYSTEM_LPC13Uxx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC13Uxx_H */
--- a/TARGET_LPC1768/LPC17xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/LPC17xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,1035 +1,1035 @@
-/**************************************************************************//**
- * @file LPC17xx.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
- * NXP LPC17xx Device Series
- * @version: V1.09
- * @date: 17. March 2010
-
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC17xx_H__
-#define __LPC17xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** LPC17xx Specific Interrupt Numbers *******************************************************/
- WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
- TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
- TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
- TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
- TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
- UART0_IRQn = 5, /*!< UART0 Interrupt */
- UART1_IRQn = 6, /*!< UART1 Interrupt */
- UART2_IRQn = 7, /*!< UART2 Interrupt */
- UART3_IRQn = 8, /*!< UART3 Interrupt */
- PWM1_IRQn = 9, /*!< PWM1 Interrupt */
- I2C0_IRQn = 10, /*!< I2C0 Interrupt */
- I2C1_IRQn = 11, /*!< I2C1 Interrupt */
- I2C2_IRQn = 12, /*!< I2C2 Interrupt */
- SPI_IRQn = 13, /*!< SPI Interrupt */
- SSP0_IRQn = 14, /*!< SSP0 Interrupt */
- SSP1_IRQn = 15, /*!< SSP1 Interrupt */
- PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
- RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
- EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
- EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
- EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
- EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
- ADC_IRQn = 22, /*!< A/D Converter Interrupt */
- BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
- USB_IRQn = 24, /*!< USB Interrupt */
- CAN_IRQn = 25, /*!< CAN Interrupt */
- DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
- I2S_IRQn = 27, /*!< I2S Interrupt */
- ENET_IRQn = 28, /*!< Ethernet Interrupt */
- RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
- MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
- QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
- PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
- USBActivity_IRQn = 33, /* USB Activity interrupt */
- CANActivity_IRQn = 34, /* CAN Activity interrupt */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
-#include "system_LPC17xx.h" /* System Header */
-
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
- __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
- uint32_t RESERVED0[31];
- __IO uint32_t PLL0CON; /* Clocking and Power Control */
- __IO uint32_t PLL0CFG;
- __I uint32_t PLL0STAT;
- __O uint32_t PLL0FEED;
- uint32_t RESERVED1[4];
- __IO uint32_t PLL1CON;
- __IO uint32_t PLL1CFG;
- __I uint32_t PLL1STAT;
- __O uint32_t PLL1FEED;
- uint32_t RESERVED2[4];
- __IO uint32_t PCON;
- __IO uint32_t PCONP;
- uint32_t RESERVED3[15];
- __IO uint32_t CCLKCFG;
- __IO uint32_t USBCLKCFG;
- __IO uint32_t CLKSRCSEL;
- __IO uint32_t CANSLEEPCLR;
- __IO uint32_t CANWAKEFLAGS;
- uint32_t RESERVED4[10];
- __IO uint32_t EXTINT; /* External Interrupts */
- uint32_t RESERVED5;
- __IO uint32_t EXTMODE;
- __IO uint32_t EXTPOLAR;
- uint32_t RESERVED6[12];
- __IO uint32_t RSID; /* Reset */
- uint32_t RESERVED7[7];
- __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
- __IO uint32_t IRCTRIM; /* Clock Dividers */
- __IO uint32_t PCLKSEL0;
- __IO uint32_t PCLKSEL1;
- uint32_t RESERVED8[4];
- __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
- __IO uint32_t DMAREQSEL;
- __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
- __IO uint32_t PINSEL0;
- __IO uint32_t PINSEL1;
- __IO uint32_t PINSEL2;
- __IO uint32_t PINSEL3;
- __IO uint32_t PINSEL4;
- __IO uint32_t PINSEL5;
- __IO uint32_t PINSEL6;
- __IO uint32_t PINSEL7;
- __IO uint32_t PINSEL8;
- __IO uint32_t PINSEL9;
- __IO uint32_t PINSEL10;
- uint32_t RESERVED0[5];
- __IO uint32_t PINMODE0;
- __IO uint32_t PINMODE1;
- __IO uint32_t PINMODE2;
- __IO uint32_t PINMODE3;
- __IO uint32_t PINMODE4;
- __IO uint32_t PINMODE5;
- __IO uint32_t PINMODE6;
- __IO uint32_t PINMODE7;
- __IO uint32_t PINMODE8;
- __IO uint32_t PINMODE9;
- __IO uint32_t PINMODE_OD0;
- __IO uint32_t PINMODE_OD1;
- __IO uint32_t PINMODE_OD2;
- __IO uint32_t PINMODE_OD3;
- __IO uint32_t PINMODE_OD4;
- __IO uint32_t I2CPADCFG;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
- union {
- __IO uint32_t FIODIR;
- struct {
- __IO uint16_t FIODIRL;
- __IO uint16_t FIODIRH;
- };
- struct {
- __IO uint8_t FIODIR0;
- __IO uint8_t FIODIR1;
- __IO uint8_t FIODIR2;
- __IO uint8_t FIODIR3;
- };
- };
- uint32_t RESERVED0[3];
- union {
- __IO uint32_t FIOMASK;
- struct {
- __IO uint16_t FIOMASKL;
- __IO uint16_t FIOMASKH;
- };
- struct {
- __IO uint8_t FIOMASK0;
- __IO uint8_t FIOMASK1;
- __IO uint8_t FIOMASK2;
- __IO uint8_t FIOMASK3;
- };
- };
- union {
- __IO uint32_t FIOPIN;
- struct {
- __IO uint16_t FIOPINL;
- __IO uint16_t FIOPINH;
- };
- struct {
- __IO uint8_t FIOPIN0;
- __IO uint8_t FIOPIN1;
- __IO uint8_t FIOPIN2;
- __IO uint8_t FIOPIN3;
- };
- };
- union {
- __IO uint32_t FIOSET;
- struct {
- __IO uint16_t FIOSETL;
- __IO uint16_t FIOSETH;
- };
- struct {
- __IO uint8_t FIOSET0;
- __IO uint8_t FIOSET1;
- __IO uint8_t FIOSET2;
- __IO uint8_t FIOSET3;
- };
- };
- union {
- __O uint32_t FIOCLR;
- struct {
- __O uint16_t FIOCLRL;
- __O uint16_t FIOCLRH;
- };
- struct {
- __O uint8_t FIOCLR0;
- __O uint8_t FIOCLR1;
- __O uint8_t FIOCLR2;
- __O uint8_t FIOCLR3;
- };
- };
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
- __I uint32_t IntStatus;
- __I uint32_t IO0IntStatR;
- __I uint32_t IO0IntStatF;
- __O uint32_t IO0IntClr;
- __IO uint32_t IO0IntEnR;
- __IO uint32_t IO0IntEnF;
- uint32_t RESERVED0[3];
- __I uint32_t IO2IntStatR;
- __I uint32_t IO2IntStatF;
- __O uint32_t IO2IntClr;
- __IO uint32_t IO2IntEnR;
- __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
- __IO uint32_t IR;
- __IO uint32_t TCR;
- __IO uint32_t TC;
- __IO uint32_t PR;
- __IO uint32_t PC;
- __IO uint32_t MCR;
- __IO uint32_t MR0;
- __IO uint32_t MR1;
- __IO uint32_t MR2;
- __IO uint32_t MR3;
- __IO uint32_t CCR;
- __I uint32_t CR0;
- __I uint32_t CR1;
- uint32_t RESERVED0[2];
- __IO uint32_t EMR;
- uint32_t RESERVED1[12];
- __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
- __IO uint32_t IR;
- __IO uint32_t TCR;
- __IO uint32_t TC;
- __IO uint32_t PR;
- __IO uint32_t PC;
- __IO uint32_t MCR;
- __IO uint32_t MR0;
- __IO uint32_t MR1;
- __IO uint32_t MR2;
- __IO uint32_t MR3;
- __IO uint32_t CCR;
- __I uint32_t CR0;
- __I uint32_t CR1;
- __I uint32_t CR2;
- __I uint32_t CR3;
- uint32_t RESERVED0;
- __IO uint32_t MR4;
- __IO uint32_t MR5;
- __IO uint32_t MR6;
- __IO uint32_t PCR;
- __IO uint32_t LER;
- uint32_t RESERVED1[7];
- __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[7];
- __I uint8_t LSR;
- uint8_t RESERVED2[7];
- __IO uint8_t SCR;
- uint8_t RESERVED3[3];
- __IO uint32_t ACR;
- __IO uint8_t ICR;
- uint8_t RESERVED4[3];
- __IO uint8_t FDR;
- uint8_t RESERVED5[7];
- __IO uint8_t TER;
- uint8_t RESERVED6[39];
- __IO uint32_t FIFOLVL;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[7];
- __I uint8_t LSR;
- uint8_t RESERVED2[7];
- __IO uint8_t SCR;
- uint8_t RESERVED3[3];
- __IO uint32_t ACR;
- __IO uint8_t ICR;
- uint8_t RESERVED4[3];
- __IO uint8_t FDR;
- uint8_t RESERVED5[7];
- __IO uint8_t TER;
- uint8_t RESERVED6[39];
- __IO uint32_t FIFOLVL;
-} LPC_UART0_TypeDef;
-
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[3];
- __IO uint8_t MCR;
- uint8_t RESERVED2[3];
- __I uint8_t LSR;
- uint8_t RESERVED3[3];
- __I uint8_t MSR;
- uint8_t RESERVED4[3];
- __IO uint8_t SCR;
- uint8_t RESERVED5[3];
- __IO uint32_t ACR;
- uint32_t RESERVED6;
- __IO uint32_t FDR;
- uint32_t RESERVED7;
- __IO uint8_t TER;
- uint8_t RESERVED8[27];
- __IO uint8_t RS485CTRL;
- uint8_t RESERVED9[3];
- __IO uint8_t ADRMATCH;
- uint8_t RESERVED10[3];
- __IO uint8_t RS485DLY;
- uint8_t RESERVED11[3];
- __IO uint32_t FIFOLVL;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
- __IO uint32_t SPCR;
- __I uint32_t SPSR;
- __IO uint32_t SPDR;
- __IO uint32_t SPCCR;
- uint32_t RESERVED0[3];
- __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
- __IO uint32_t CR0;
- __IO uint32_t CR1;
- __IO uint32_t DR;
- __I uint32_t SR;
- __IO uint32_t CPSR;
- __IO uint32_t IMSC;
- __IO uint32_t RIS;
- __IO uint32_t MIS;
- __IO uint32_t ICR;
- __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
- __IO uint32_t I2CONSET;
- __I uint32_t I2STAT;
- __IO uint32_t I2DAT;
- __IO uint32_t I2ADR0;
- __IO uint32_t I2SCLH;
- __IO uint32_t I2SCLL;
- __O uint32_t I2CONCLR;
- __IO uint32_t MMCTRL;
- __IO uint32_t I2ADR1;
- __IO uint32_t I2ADR2;
- __IO uint32_t I2ADR3;
- __I uint32_t I2DATA_BUFFER;
- __IO uint32_t I2MASK0;
- __IO uint32_t I2MASK1;
- __IO uint32_t I2MASK2;
- __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t I2SDAO;
- __IO uint32_t I2SDAI;
- __O uint32_t I2STXFIFO;
- __I uint32_t I2SRXFIFO;
- __I uint32_t I2SSTATE;
- __IO uint32_t I2SDMA1;
- __IO uint32_t I2SDMA2;
- __IO uint32_t I2SIRQ;
- __IO uint32_t I2STXRATE;
- __IO uint32_t I2SRXRATE;
- __IO uint32_t I2STXBITRATE;
- __IO uint32_t I2SRXBITRATE;
- __IO uint32_t I2STXMODE;
- __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
-typedef struct
-{
- __IO uint32_t RICOMPVAL;
- __IO uint32_t RIMASK;
- __IO uint8_t RICTRL;
- uint8_t RESERVED0[3];
- __IO uint32_t RICOUNTER;
-} LPC_RIT_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
- __IO uint8_t ILR;
- uint8_t RESERVED0[7];
- __IO uint8_t CCR;
- uint8_t RESERVED1[3];
- __IO uint8_t CIIR;
- uint8_t RESERVED2[3];
- __IO uint8_t AMR;
- uint8_t RESERVED3[3];
- __I uint32_t CTIME0;
- __I uint32_t CTIME1;
- __I uint32_t CTIME2;
- __IO uint8_t SEC;
- uint8_t RESERVED4[3];
- __IO uint8_t MIN;
- uint8_t RESERVED5[3];
- __IO uint8_t HOUR;
- uint8_t RESERVED6[3];
- __IO uint8_t DOM;
- uint8_t RESERVED7[3];
- __IO uint8_t DOW;
- uint8_t RESERVED8[3];
- __IO uint16_t DOY;
- uint16_t RESERVED9;
- __IO uint8_t MONTH;
- uint8_t RESERVED10[3];
- __IO uint16_t YEAR;
- uint16_t RESERVED11;
- __IO uint32_t CALIBRATION;
- __IO uint32_t GPREG0;
- __IO uint32_t GPREG1;
- __IO uint32_t GPREG2;
- __IO uint32_t GPREG3;
- __IO uint32_t GPREG4;
- __IO uint8_t RTC_AUXEN;
- uint8_t RESERVED12[3];
- __IO uint8_t RTC_AUX;
- uint8_t RESERVED13[3];
- __IO uint8_t ALSEC;
- uint8_t RESERVED14[3];
- __IO uint8_t ALMIN;
- uint8_t RESERVED15[3];
- __IO uint8_t ALHOUR;
- uint8_t RESERVED16[3];
- __IO uint8_t ALDOM;
- uint8_t RESERVED17[3];
- __IO uint8_t ALDOW;
- uint8_t RESERVED18[3];
- __IO uint16_t ALDOY;
- uint16_t RESERVED19;
- __IO uint8_t ALMON;
- uint8_t RESERVED20[3];
- __IO uint16_t ALYEAR;
- uint16_t RESERVED21;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
- __IO uint8_t WDMOD;
- uint8_t RESERVED0[3];
- __IO uint32_t WDTC;
- __O uint8_t WDFEED;
- uint8_t RESERVED1[3];
- __I uint32_t WDTV;
- __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t ADCR;
- __IO uint32_t ADGDR;
- uint32_t RESERVED0;
- __IO uint32_t ADINTEN;
- __I uint32_t ADDR0;
- __I uint32_t ADDR1;
- __I uint32_t ADDR2;
- __I uint32_t ADDR3;
- __I uint32_t ADDR4;
- __I uint32_t ADDR5;
- __I uint32_t ADDR6;
- __I uint32_t ADDR7;
- __I uint32_t ADSTAT;
- __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t DACR;
- __IO uint32_t DACCTRL;
- __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
- __I uint32_t MCCON;
- __O uint32_t MCCON_SET;
- __O uint32_t MCCON_CLR;
- __I uint32_t MCCAPCON;
- __O uint32_t MCCAPCON_SET;
- __O uint32_t MCCAPCON_CLR;
- __IO uint32_t MCTIM0;
- __IO uint32_t MCTIM1;
- __IO uint32_t MCTIM2;
- __IO uint32_t MCPER0;
- __IO uint32_t MCPER1;
- __IO uint32_t MCPER2;
- __IO uint32_t MCPW0;
- __IO uint32_t MCPW1;
- __IO uint32_t MCPW2;
- __IO uint32_t MCDEADTIME;
- __IO uint32_t MCCCP;
- __IO uint32_t MCCR0;
- __IO uint32_t MCCR1;
- __IO uint32_t MCCR2;
- __I uint32_t MCINTEN;
- __O uint32_t MCINTEN_SET;
- __O uint32_t MCINTEN_CLR;
- __I uint32_t MCCNTCON;
- __O uint32_t MCCNTCON_SET;
- __O uint32_t MCCNTCON_CLR;
- __I uint32_t MCINTFLAG;
- __O uint32_t MCINTFLAG_SET;
- __O uint32_t MCINTFLAG_CLR;
- __O uint32_t MCCAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
- __O uint32_t QEICON;
- __I uint32_t QEISTAT;
- __IO uint32_t QEICONF;
- __I uint32_t QEIPOS;
- __IO uint32_t QEIMAXPOS;
- __IO uint32_t CMPOS0;
- __IO uint32_t CMPOS1;
- __IO uint32_t CMPOS2;
- __I uint32_t INXCNT;
- __IO uint32_t INXCMP;
- __IO uint32_t QEILOAD;
- __I uint32_t QEITIME;
- __I uint32_t QEIVEL;
- __I uint32_t QEICAP;
- __IO uint32_t VELCOMP;
- __IO uint32_t FILTER;
- uint32_t RESERVED0[998];
- __O uint32_t QEIIEC;
- __O uint32_t QEIIES;
- __I uint32_t QEIINTSTAT;
- __I uint32_t QEIIE;
- __O uint32_t QEICLR;
- __O uint32_t QEISET;
-} LPC_QEI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
- __IO uint32_t mask[512]; /* ID Masks */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct /* Acceptance Filter Registers */
-{
- __IO uint32_t AFMR;
- __IO uint32_t SFF_sa;
- __IO uint32_t SFF_GRP_sa;
- __IO uint32_t EFF_sa;
- __IO uint32_t EFF_GRP_sa;
- __IO uint32_t ENDofTable;
- __I uint32_t LUTerrAd;
- __I uint32_t LUTerr;
- __IO uint32_t FCANIE;
- __IO uint32_t FCANIC0;
- __IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct /* Central Registers */
-{
- __I uint32_t CANTxSR;
- __I uint32_t CANRxSR;
- __I uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct /* Controller Registers */
-{
- __IO uint32_t MOD;
- __O uint32_t CMR;
- __IO uint32_t GSR;
- __I uint32_t ICR;
- __IO uint32_t IER;
- __IO uint32_t BTR;
- __IO uint32_t EWL;
- __I uint32_t SR;
- __IO uint32_t RFS;
- __IO uint32_t RID;
- __IO uint32_t RDA;
- __IO uint32_t RDB;
- __IO uint32_t TFI1;
- __IO uint32_t TID1;
- __IO uint32_t TDA1;
- __IO uint32_t TDB1;
- __IO uint32_t TFI2;
- __IO uint32_t TID2;
- __IO uint32_t TDA2;
- __IO uint32_t TDB2;
- __IO uint32_t TFI3;
- __IO uint32_t TID3;
- __IO uint32_t TDA3;
- __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct /* Common Registers */
-{
- __I uint32_t DMACIntStat;
- __I uint32_t DMACIntTCStat;
- __O uint32_t DMACIntTCClear;
- __I uint32_t DMACIntErrStat;
- __O uint32_t DMACIntErrClr;
- __I uint32_t DMACRawIntTCStat;
- __I uint32_t DMACRawIntErrStat;
- __I uint32_t DMACEnbldChns;
- __IO uint32_t DMACSoftBReq;
- __IO uint32_t DMACSoftSReq;
- __IO uint32_t DMACSoftLBReq;
- __IO uint32_t DMACSoftLSReq;
- __IO uint32_t DMACConfig;
- __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct /* Channel Registers */
-{
- __IO uint32_t DMACCSrcAddr;
- __IO uint32_t DMACCDestAddr;
- __IO uint32_t DMACCLLI;
- __IO uint32_t DMACCControl;
- __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
- __I uint32_t HcRevision; /* USB Host Registers */
- __IO uint32_t HcControl;
- __IO uint32_t HcCommandStatus;
- __IO uint32_t HcInterruptStatus;
- __IO uint32_t HcInterruptEnable;
- __IO uint32_t HcInterruptDisable;
- __IO uint32_t HcHCCA;
- __I uint32_t HcPeriodCurrentED;
- __IO uint32_t HcControlHeadED;
- __IO uint32_t HcControlCurrentED;
- __IO uint32_t HcBulkHeadED;
- __IO uint32_t HcBulkCurrentED;
- __I uint32_t HcDoneHead;
- __IO uint32_t HcFmInterval;
- __I uint32_t HcFmRemaining;
- __I uint32_t HcFmNumber;
- __IO uint32_t HcPeriodicStart;
- __IO uint32_t HcLSTreshold;
- __IO uint32_t HcRhDescriptorA;
- __IO uint32_t HcRhDescriptorB;
- __IO uint32_t HcRhStatus;
- __IO uint32_t HcRhPortStatus1;
- __IO uint32_t HcRhPortStatus2;
- uint32_t RESERVED0[40];
- __I uint32_t Module_ID;
-
- __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
- __IO uint32_t OTGIntEn;
- __O uint32_t OTGIntSet;
- __O uint32_t OTGIntClr;
- __IO uint32_t OTGStCtrl;
- __IO uint32_t OTGTmr;
- uint32_t RESERVED1[58];
-
- __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
- __IO uint32_t USBDevIntEn;
- __O uint32_t USBDevIntClr;
- __O uint32_t USBDevIntSet;
-
- __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
- __I uint32_t USBCmdData;
-
- __I uint32_t USBRxData; /* USB Device Transfer Registers */
- __O uint32_t USBTxData;
- __I uint32_t USBRxPLen;
- __O uint32_t USBTxPLen;
- __IO uint32_t USBCtrl;
- __O uint32_t USBDevIntPri;
-
- __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
- __IO uint32_t USBEpIntEn;
- __O uint32_t USBEpIntClr;
- __O uint32_t USBEpIntSet;
- __O uint32_t USBEpIntPri;
-
- __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
- __O uint32_t USBEpInd;
- __IO uint32_t USBMaxPSize;
-
- __I uint32_t USBDMARSt; /* USB Device DMA Registers */
- __O uint32_t USBDMARClr;
- __O uint32_t USBDMARSet;
- uint32_t RESERVED2[9];
- __IO uint32_t USBUDCAH;
- __I uint32_t USBEpDMASt;
- __O uint32_t USBEpDMAEn;
- __O uint32_t USBEpDMADis;
- __I uint32_t USBDMAIntSt;
- __IO uint32_t USBDMAIntEn;
- uint32_t RESERVED3[2];
- __I uint32_t USBEoTIntSt;
- __O uint32_t USBEoTIntClr;
- __O uint32_t USBEoTIntSet;
- __I uint32_t USBNDDRIntSt;
- __O uint32_t USBNDDRIntClr;
- __O uint32_t USBNDDRIntSet;
- __I uint32_t USBSysErrIntSt;
- __O uint32_t USBSysErrIntClr;
- __O uint32_t USBSysErrIntSet;
- uint32_t RESERVED4[15];
-
- union {
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */
- __O uint32_t I2C_TX;
- };
- __I uint32_t I2C_STS;
- __IO uint32_t I2C_CTL;
- __IO uint32_t I2C_CLKHI;
- __O uint32_t I2C_CLKLO;
- uint32_t RESERVED5[824];
-
- union {
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
- __IO uint32_t OTGClkCtrl;
- };
- union {
- __I uint32_t USBClkSt;
- __I uint32_t OTGClkSt;
- };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
- __IO uint32_t MAC1; /* MAC Registers */
- __IO uint32_t MAC2;
- __IO uint32_t IPGT;
- __IO uint32_t IPGR;
- __IO uint32_t CLRT;
- __IO uint32_t MAXF;
- __IO uint32_t SUPP;
- __IO uint32_t TEST;
- __IO uint32_t MCFG;
- __IO uint32_t MCMD;
- __IO uint32_t MADR;
- __O uint32_t MWTD;
- __I uint32_t MRDD;
- __I uint32_t MIND;
- uint32_t RESERVED0[2];
- __IO uint32_t SA0;
- __IO uint32_t SA1;
- __IO uint32_t SA2;
- uint32_t RESERVED1[45];
- __IO uint32_t Command; /* Control Registers */
- __I uint32_t Status;
- __IO uint32_t RxDescriptor;
- __IO uint32_t RxStatus;
- __IO uint32_t RxDescriptorNumber;
- __I uint32_t RxProduceIndex;
- __IO uint32_t RxConsumeIndex;
- __IO uint32_t TxDescriptor;
- __IO uint32_t TxStatus;
- __IO uint32_t TxDescriptorNumber;
- __IO uint32_t TxProduceIndex;
- __I uint32_t TxConsumeIndex;
- uint32_t RESERVED2[10];
- __I uint32_t TSV0;
- __I uint32_t TSV1;
- __I uint32_t RSV;
- uint32_t RESERVED3[3];
- __IO uint32_t FlowControlCounter;
- __I uint32_t FlowControlStatus;
- uint32_t RESERVED4[34];
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
- __IO uint32_t RxFilterWoLStatus;
- __IO uint32_t RxFilterWoLClear;
- uint32_t RESERVED5;
- __IO uint32_t HashFilterL;
- __IO uint32_t HashFilterH;
- uint32_t RESERVED6[882];
- __I uint32_t IntStatus; /* Module Control Registers */
- __IO uint32_t IntEnable;
- __O uint32_t IntClear;
- __O uint32_t IntSet;
- uint32_t RESERVED7;
- __IO uint32_t PowerDown;
- uint32_t RESERVED8;
- __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM )
-#pragma no_anon_unions
-#endif
-
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Base addresses */
-#define LPC_FLASH_BASE (0x00000000UL)
-#define LPC_RAM_BASE (0x10000000UL)
-#define LPC_GPIO_BASE (0x2009C000UL)
-#define LPC_APB0_BASE (0x40000000UL)
-#define LPC_APB1_BASE (0x40080000UL)
-#define LPC_AHB_BASE (0x50000000UL)
-#define LPC_CM3_BASE (0xE0000000UL)
-
-/* APB0 peripherals */
-#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
-#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
-#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals */
-#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
-#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
-#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
-#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
-#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals */
-#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
-#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
-#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
-#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
-#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
-#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
-#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
-#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
-#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
-#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
-#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
-
-/* GPIOs */
-#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
-#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
-#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
-#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
-#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
-
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
-#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
-#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
-#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
-#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
-#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
-#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
-#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
-#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
-#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
-#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
-#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
-#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
-#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
-#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
-#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
-#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
-#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
-#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
-#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
-#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
-#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
-#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
-#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
-#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
-#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
-#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
-#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
-#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
-#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
-#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
-#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
-#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
-#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
-#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
-#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
-#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
-#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
-#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
-
-#endif // __LPC17xx_H__
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 17. March 2010
+
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /* USB Activity interrupt */
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __IO uint32_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __IO uint32_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+#endif // __LPC17xx_H__
--- a/TARGET_LPC1768/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,80 +1,80 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_UART0_BASE,
- UART_1 = (int)LPC_UART1_BASE,
- UART_2 = (int)LPC_UART2_BASE,
- UART_3 = (int)LPC_UART3_BASE
-} UARTName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C0_BASE,
- I2C_1 = (int)LPC_I2C1_BASE,
- I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
- PWM_1 = 1,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)LPC_CAN1_BASE,
- CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = 1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1768/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,109 +1,109 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC Pin Names
- P0_0 = LPC_GPIO0_BASE,
- P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
- P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
- P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
- P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
- P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
-
- // mbed DIP Pin Names
- p5 = P0_9,
- p6 = P0_8,
- p7 = P0_7,
- p8 = P0_6,
- p9 = P0_0,
- p10 = P0_1,
- p11 = P0_18,
- p12 = P0_17,
- p13 = P0_15,
- p14 = P0_16,
- p15 = P0_23,
- p16 = P0_24,
- p17 = P0_25,
- p18 = P0_26,
- p19 = P1_30,
- p20 = P1_31,
- p21 = P2_5,
- p22 = P2_4,
- p23 = P2_3,
- p24 = P2_2,
- p25 = P2_1,
- p26 = P2_0,
- p27 = P0_11,
- p28 = P0_10,
- p29 = P0_5,
- p30 = P0_4,
-
- // Other mbed Pin Names
-#ifdef MCB1700
- LED1 = P1_28,
- LED2 = P1_29,
- LED3 = P1_31,
- LED4 = P2_2,
-#else
- LED1 = P1_18,
- LED2 = P1_20,
- LED3 = P1_21,
- LED4 = P1_23,
-#endif
- USBTX = P0_2,
- USBRX = P0_3,
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
- PullUp = 0,
- PullDown = 3,
- PullNone = 2,
- OpenDrain = 4
-} PinMode;
-
-// version of PINCON_TypeDef using register arrays
-typedef struct {
- __IO uint32_t PINSEL[11];
- uint32_t RESERVED0[5];
- __IO uint32_t PINMODE[10];
- __IO uint32_t PINMODE_OD[5];
-} PINCONARRAY_TypeDef;
-
-#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = LPC_GPIO0_BASE,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+
+ // mbed DIP Pin Names
+ p5 = P0_9,
+ p6 = P0_8,
+ p7 = P0_7,
+ p8 = P0_6,
+ p9 = P0_0,
+ p10 = P0_1,
+ p11 = P0_18,
+ p12 = P0_17,
+ p13 = P0_15,
+ p14 = P0_16,
+ p15 = P0_23,
+ p16 = P0_24,
+ p17 = P0_25,
+ p18 = P0_26,
+ p19 = P1_30,
+ p20 = P1_31,
+ p21 = P2_5,
+ p22 = P2_4,
+ p23 = P2_3,
+ p24 = P2_2,
+ p25 = P2_1,
+ p26 = P2_0,
+ p27 = P0_11,
+ p28 = P0_10,
+ p29 = P0_5,
+ p30 = P0_4,
+
+ // Other mbed Pin Names
+#ifdef MCB1700
+ LED1 = P1_28,
+ LED2 = P1_29,
+ LED3 = P1_31,
+ LED4 = P2_2,
+#else
+ LED1 = P1_18,
+ LED2 = P1_20,
+ LED3 = P1_21,
+ LED4 = P1_23,
+#endif
+ USBTX = P0_2,
+ USBRX = P0_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ OpenDrain = 4
+} PinMode;
+
+// version of PINCON_TypeDef using register arrays
+typedef struct {
+ __IO uint32_t PINSEL[11];
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE[10];
+ __IO uint32_t PINMODE_OD[5];
+} PINCONARRAY_TypeDef;
+
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1768/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,34 +1,34 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1,
- Port2 = 2,
- Port3 = 3,
- Port4 = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC1768/TOOLCHAIN_ARM_STD/LPC1768.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/TOOLCHAIN_ARM_STD/LPC1768.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,22 +1,22 @@
-
-LR_IROM1 0x00000000 0x80000 { ; load region size_region
- ER_IROM1 0x00000000 0x80000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
- ; 32KB - 0xC8 = 0x7F38
- RW_IRAM1 0x100000C8 0x7F38 {
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
- .ANY (AHBSRAM0)
- }
- RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
- .ANY (AHBSRAM1)
- }
- RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
- .ANY (CANRAM)
- }
-}
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ ; 32KB - 0xC8 = 0x7F38
+ RW_IRAM1 0x100000C8 0x7F38 {
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+}
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/startup_LPC17xx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_ARM_STD/system_LPC17xx.o has changed
--- a/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld Mon Aug 19 13:34:54 2013 +0300
@@ -1,149 +1,172 @@
-/* Linker script for mbed LPC1768 */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
- RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
-
- USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
- ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE (__fini_array_end = .);
-
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
-
- } > RAM
-
- .bss :
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM
-
- .heap :
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy :
- {
- *(.stack)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
+
+ USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ Image$$RW_IRAM1$$Base = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ Image$$RW_IRAM1$$ZI$$Limit = . ;
+ } > RAM
+
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Code can explicitly ask for data to be
+ placed in these higher RAM banks where
+ they will be left uninitialized.
+ */
+ .AHBSRAM0 (NOLOAD):
+ {
+ Image$$RW_IRAM2$$Base = . ;
+ *(AHBSRAM0)
+ Image$$RW_IRAM2$$ZI$$Limit = .;
+ } > USB_RAM
+
+ .AHBSRAM1 (NOLOAD):
+ {
+ Image$$RW_IRAM3$$Base = . ;
+ *(AHBSRAM1)
+ Image$$RW_IRAM3$$ZI$$Limit = .;
+ } > ETH_RAM
+}
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a has changed
--- a/TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld Mon Aug 19 13:34:54 2013 +0300
@@ -1,153 +1,153 @@
-/* mbed - LPC1768 linker script
- * Based linker script generated by Code Red Technologies Red Suite 4.1
- */
-GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
-
-MEMORY
-{
- /* Define each memory region */
- MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
- RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
- RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
-
-}
- /* Define a symbol for the top of each memory region */
- __top_MFlash512 = 0x0 + 0x80000;
- __top_RamLoc32 = 0x10000000 + 0x8000;
- __top_RamAHB32 = 0x2007c000 + 0x8000;
-
-ENTRY(ResetISR)
-
-SECTIONS
-{
-
- /* MAIN TEXT SECTION */
- .text : ALIGN(4)
- {
- FILL(0xff)
- KEEP(*(.isr_vector))
-
- /* Global Section Table */
- . = ALIGN(4) ;
- __section_table_start = .;
- __data_section_table = .;
- LONG(LOADADDR(.data));
- LONG( ADDR(.data)) ;
- LONG( SIZEOF(.data));
- LONG(LOADADDR(.data_RAM2));
- LONG( ADDR(.data_RAM2)) ;
- LONG( SIZEOF(.data_RAM2));
- __data_section_table_end = .;
- __bss_section_table = .;
- LONG( ADDR(.bss));
- LONG( SIZEOF(.bss));
- LONG( ADDR(.bss_RAM2));
- LONG( SIZEOF(.bss_RAM2));
- __bss_section_table_end = .;
- __section_table_end = . ;
- /* End of Global Section Table */
-
-
- *(.after_vectors*)
-
- *(.text*)
- *(.rodata .rodata.*)
- . = ALIGN(4);
-
- /* C++ constructors etc */
- . = ALIGN(4);
- KEEP(*(.init))
-
- . = ALIGN(4);
- __preinit_array_start = .;
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-
- . = ALIGN(4);
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-
- KEEP(*(.fini));
-
- . = ALIGN(0x4);
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*crtend.o(.ctors))
-
- . = ALIGN(0x4);
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*crtend.o(.dtors))
- /* End C++ */
- } > MFlash512
-
- /*
- * for exception handling/unwind - some Newlib functions (in common
- * with C++ and STDC++) use this.
- */
- .ARM.extab : ALIGN(4)
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > MFlash512
- __exidx_start = .;
-
- .ARM.exidx : ALIGN(4)
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > MFlash512
- __exidx_end = .;
-
- _etext = .;
-
-
- .data_RAM2 : ALIGN(4)
- {
- FILL(0xff)
- *(.data.$RAM2*)
- *(.data.$RamAHB32*)
- . = ALIGN(4) ;
- } > RamAHB32 AT>MFlash512
-
- /* MAIN DATA SECTION */
-
- .uninit_RESERVED : ALIGN(4)
- {
- KEEP(*(.bss.$RESERVED*))
- } > RamLoc32
-
- .data : ALIGN(4)
- {
- FILL(0xff)
- _data = .;
- *(vtable)
- *(.data*)
- . = ALIGN(4) ;
- _edata = .;
- } > RamLoc32 AT>MFlash512
-
-
- .bss_RAM2 : ALIGN(4)
- {
- *(.bss.$RAM2*)
- *(.bss.$RamAHB32*)
- . = ALIGN(4) ;
- } > RamAHB32
-
- /* MAIN BSS SECTION */
- .bss : ALIGN(4)
- {
- _bss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4) ;
- _ebss = .;
- PROVIDE(end = .);
- } > RamLoc32
-
- PROVIDE(_pvHeapStart = .);
- PROVIDE(_vStackTop = __top_RamLoc32 - 0);
-}
+/* mbed - LPC1768 linker script
+ * Based linker script generated by Code Red Technologies Red Suite 4.1
+ */
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+ /* Define each memory region */
+ MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+ RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
+ RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+
+}
+ /* Define a symbol for the top of each memory region */
+ __top_MFlash512 = 0x0 + 0x80000;
+ __top_RamLoc32 = 0x10000000 + 0x8000;
+ __top_RamAHB32 = 0x2007c000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+ /* MAIN TEXT SECTION */
+ .text : ALIGN(4)
+ {
+ FILL(0xff)
+ KEEP(*(.isr_vector))
+
+ /* Global Section Table */
+ . = ALIGN(4) ;
+ __section_table_start = .;
+ __data_section_table = .;
+ LONG(LOADADDR(.data));
+ LONG( ADDR(.data)) ;
+ LONG( SIZEOF(.data));
+ LONG(LOADADDR(.data_RAM2));
+ LONG( ADDR(.data_RAM2)) ;
+ LONG( SIZEOF(.data_RAM2));
+ __data_section_table_end = .;
+ __bss_section_table = .;
+ LONG( ADDR(.bss));
+ LONG( SIZEOF(.bss));
+ LONG( ADDR(.bss_RAM2));
+ LONG( SIZEOF(.bss_RAM2));
+ __bss_section_table_end = .;
+ __section_table_end = . ;
+ /* End of Global Section Table */
+
+
+ *(.after_vectors*)
+
+ *(.text*)
+ *(.rodata .rodata.*)
+ . = ALIGN(4);
+
+ /* C++ constructors etc */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ KEEP(*(.fini));
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ /* End C++ */
+ } > MFlash512
+
+ /*
+ * for exception handling/unwind - some Newlib functions (in common
+ * with C++ and STDC++) use this.
+ */
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > MFlash512
+ __exidx_start = .;
+
+ .ARM.exidx : ALIGN(4)
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > MFlash512
+ __exidx_end = .;
+
+ _etext = .;
+
+
+ .data_RAM2 : ALIGN(4)
+ {
+ FILL(0xff)
+ *(.data.$RAM2*)
+ *(.data.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32 AT>MFlash512
+
+ /* MAIN DATA SECTION */
+
+ .uninit_RESERVED : ALIGN(4)
+ {
+ KEEP(*(.bss.$RESERVED*))
+ } > RamLoc32
+
+ .data : ALIGN(4)
+ {
+ FILL(0xff)
+ _data = .;
+ *(vtable)
+ *(.data*)
+ . = ALIGN(4) ;
+ _edata = .;
+ } > RamLoc32 AT>MFlash512
+
+
+ .bss_RAM2 : ALIGN(4)
+ {
+ *(.bss.$RAM2*)
+ *(.bss.$RamAHB32*)
+ . = ALIGN(4) ;
+ } > RamAHB32
+
+ /* MAIN BSS SECTION */
+ .bss : ALIGN(4)
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4) ;
+ _ebss = .;
+ PROVIDE(end = .);
+ } > RamLoc32
+
+ PROVIDE(_pvHeapStart = .);
+ PROVIDE(_vStackTop = __top_RamLoc32 - 0);
+}
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CR/libmbed.a has changed
--- a/TARGET_LPC1768/TOOLCHAIN_GCC_CS/LPC1768.ld Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/TOOLCHAIN_GCC_CS/LPC1768.ld Mon Aug 19 13:34:54 2013 +0300
@@ -1,212 +1,212 @@
-/* Linker script for mbed LPC1768
- *
- * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
- * BugURL:https://support.codesourcery.com/GNUToolchain/
- *
- * Copyright 2007 CodeSourcery.
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply. */
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-ENTRY(__cs3_reset_cortex_m)
-SEARCH_DIR(.)
-
-/*
-ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
-ram LENGTH: 32KB - 0xC8 = 0x7F38
-*/
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
-
- ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
-
- ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
- ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
-}
-
-/* These force the linker to search for particular symbols from
- * the start of the link process and thus ensure the user's
- * overrides are picked up
- */
-EXTERN(__cs3_reset_cortex_m)
-EXTERN(__cs3_interrupt_vector_cortex_m)
-EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
-
-PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
-PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
-PROVIDE(__cs3_heap_start = _end);
-PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
-
-SECTIONS
-{
- .text :
- {
- CREATE_OBJECT_SYMBOLS
- __cs3_region_start_rom = .;
- *(.cs3.region-head.rom)
- __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
- *(.cs3.interrupt_vector)
- /* Make sure we pulled in an interrupt vector. */
- ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
- *(.rom)
- *(.rom.b)
-
- __cs3_reset = __cs3_reset_cortex_m;
- *(.cs3.reset)
- /* Make sure we pulled in some reset code. */
- ASSERT (. != __cs3_reset, "No reset code");
-
- *(.text .text.* .gnu.linkonce.t.*)
- *(.plt)
- *(.gnu.warning)
- *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
-
- *(.rodata .rodata.* .gnu.linkonce.r.*)
-
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- *(.gcc_except_table)
- *(.eh_frame_hdr)
- *(.eh_frame)
-
- . = ALIGN(4);
- KEEP(*(.init))
-
- . = ALIGN(4);
- __preinit_array_start = .;
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-
- . = ALIGN(4);
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-
- . = ALIGN(0x4);
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*crtend.o(.ctors))
-
- . = ALIGN(4);
- KEEP(*(.fini))
-
- . = ALIGN(4);
- __fini_array_start = .;
- KEEP (*(.fini_array))
- KEEP (*(SORT(.fini_array.*)))
- __fini_array_end = .;
-
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*crtend.o(.dtors))
-
- . = ALIGN(4);
- __cs3_regions = .;
- LONG (0)
- LONG (__cs3_region_init_ram)
- LONG (__cs3_region_start_ram)
- LONG (__cs3_region_init_size_ram)
- LONG (__cs3_region_zero_size_ram)
- }
-
- /* .ARM.exidx is sorted, so has to go in its own output section. */
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } >rom
- __exidx_end = .;
- .text.align :
- {
- . = ALIGN(8);
- _etext = .;
- } >rom
- __cs3_region_size_rom = LENGTH(rom);
- __cs3_region_num = 1;
-
- .data :
- {
- __cs3_region_start_ram = .;
- *(.cs3.region-head.ram)
- KEEP(*(.jcr))
- *(.got.plt) *(.got)
- *(.shdata)
- *(.data .data.* .gnu.linkonce.d.*)
- *(.ram)
- . = ALIGN (8);
- _edata = .;
- } >ram AT>rom
- .bss :
- {
- *(.shbss)
- *(.bss .bss.* .gnu.linkonce.b.*)
- *(COMMON)
- *(.ram.b)
- . = ALIGN (8);
- _end = .;
- __end = .;
- } >ram AT>rom
- /* This used for USB RAM section */
- .usb_ram (NOLOAD):
- {
- *.o (USB_RAM)
- } > ram2
- .heap (NOLOAD) :
- {
- *(.heap)
- } >ram
- .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
- {
- *(.stack)
- _estack = .;
- PROVIDE(estack = .);
- } >ram
-
- __cs3_region_init_ram = LOADADDR (.data);
- __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
- __cs3_region_zero_size_ram = _end - _edata;
- __cs3_region_size_ram = LENGTH(ram);
- __cs3_region_num = 1;
-
- .stab 0 (NOLOAD) : { *(.stab) }
- .stabstr 0 (NOLOAD) : { *(.stabstr) }
- /* DWARF debug sections.
- * Symbols in the DWARF debugging sections are relative to the beginning
- * of the section so we begin them at 0. */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-
- .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
- .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
- /DISCARD/ : { *(.note.GNU-stack) }
-}
+/* Linker script for mbed LPC1768
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(__cs3_reset_cortex_m)
+SEARCH_DIR(.)
+
+/*
+ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
+ram LENGTH: 32KB - 0xC8 = 0x7F38
+*/
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+
+ ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38
+
+ ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+ ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ /* This used for USB RAM section */
+ .usb_ram (NOLOAD):
+ {
+ *.o (USB_RAM)
+ } > ram2
+ .heap (NOLOAD) :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
+ {
+ *(.stack)
+ _estack = .;
+ PROVIDE(estack = .);
+ } >ram
+
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
Binary file TARGET_LPC1768/TOOLCHAIN_GCC_CS/libmbed.a has changed
--- a/TARGET_LPC1768/TOOLCHAIN_IAR/LPC17xx.icf Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/TOOLCHAIN_IAR/LPC17xx.icf Mon Aug 19 13:34:54 2013 +0300
@@ -1,40 +1,40 @@
-/* [ROM] */
-define symbol __intvec_start__ = 0x00000000;
-define symbol __region_ROM_start__ = 0x00000000;
-define symbol __CRP_start__ = 0x000002FC;
-define symbol __CRP_end__ = 0x000002FF;
-define symbol __region_ROM_end__ = 0x0007FFFF;
-
-/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8*/
-define symbol __NVIC_start__ = 0x10000000;
-define symbol __NVIC_end__ = 0x100000C7;
-define symbol __region_RAM_start__ = 0x100000C8;
-define symbol __region_RAM_end__ = 0x1000FFDF;
-define symbol _AHB_RAM_start__ = 0x2007C000;
-define symbol _AHB_RAM_end__ = 0x20083FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
-define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
-
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__ = 0x800;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__intvec_start__ { section .intvec };
-place at address mem:0x2FC { section CRPKEY };
-place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
-place in AHB_RAM_region { section USB_RAM };
-place in CRP_region { section .crp };
+/* [ROM] */
+define symbol __intvec_start__ = 0x00000000;
+define symbol __region_ROM_start__ = 0x00000000;
+define symbol __CRP_start__ = 0x000002FC;
+define symbol __CRP_end__ = 0x000002FF;
+define symbol __region_ROM_end__ = 0x0007FFFF;
+
+/* [RAM] Vector table dynamic copy: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8*/
+define symbol __NVIC_start__ = 0x10000000;
+define symbol __NVIC_end__ = 0x100000C7;
+define symbol __region_RAM_start__ = 0x100000C8;
+define symbol __region_RAM_end__ = 0x1000FFDF;
+define symbol _AHB_RAM_start__ = 0x2007C000;
+define symbol _AHB_RAM_end__ = 0x20083FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
+define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
+
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__ = 0x800;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { section .intvec };
+place at address mem:0x2FC { section CRPKEY };
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
+place in AHB_RAM_region { section USB_RAM };
+place in CRP_region { section .crp };
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/cmsis_nvic.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/mbed.a has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/retarget.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/startup_LPC17xx.o has changed
Binary file TARGET_LPC1768/TOOLCHAIN_IAR/system_LPC17xx.o has changed
--- a/TARGET_LPC1768/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC1768/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC1768 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC17xx.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC17xx.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC1768/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_NUM_VECTORS (16 + 33)
-#define NVIC_USER_IRQ_OFFSET 16
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 33)
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1768/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC1768/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,59 +1,59 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 1 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 1 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 1 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 1 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- a/TARGET_LPC1768/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1768/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,79 +1,79 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_out;
- __I uint32_t *reg_in;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- __IO uint32_t *MR;
- PWMName pwm;
-};
-
-struct serial_s {
- LPC_UART_TypeDef *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-struct can_s {
- LPC_CAN_TypeDef *dev;
- int index;
-};
-
-struct i2c_s {
- LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
- LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MR;
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+ int index;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC1768/system_LPC17xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC1768/system_LPC17xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,60 +1,60 @@
-/******************************************************************************
- * @file: system_LPC17xx.h
- * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- * for the NXP LPC17xx Device Series
- * @version: V1.02
- * @date: 27. July 2009
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC17xx_H
-#define __SYSTEM_LPC17xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC17xx_H */
+/******************************************************************************
+ * @file: system_LPC17xx.h
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version: V1.02
+ * @date: 27. July 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC17xx_H */
--- a/TARGET_LPC2368/LPC23xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/LPC23xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,864 +1,864 @@
-/* mbed Microcontroller Library - LPC23xx CMSIS-like structs
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
- */
-
-#ifndef __LPC23xx_H
-#define __LPC23xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/****** LPC23xx Specific Interrupt Numbers *******************************************************/
- WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
-
- TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
- TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
- UART0_IRQn = 6, /*!< UART0 Interrupt */
- UART1_IRQn = 7, /*!< UART1 Interrupt */
- PWM1_IRQn = 8, /*!< PWM1 Interrupt */
- I2C0_IRQn = 9, /*!< I2C0 Interrupt */
- SPI_IRQn = 10, /*!< SPI Interrupt */
- SSP0_IRQn = 10, /*!< SSP0 Interrupt */
- SSP1_IRQn = 11, /*!< SSP1 Interrupt */
- PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
- RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
- EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
- EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
- EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
- EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
- ADC_IRQn = 18, /*!< A/D Converter Interrupt */
- I2C1_IRQn = 19, /*!< I2C1 Interrupt */
- BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
- ENET_IRQn = 21, /*!< Ethernet Interrupt */
- USB_IRQn = 22, /*!< USB Interrupt */
- CAN_IRQn = 23, /*!< CAN Interrupt */
- MIC_IRQn = 24, /*!< Multimedia Interface Controler */
- DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
- TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
- TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
- UART2_IRQn = 28, /*!< UART2 Interrupt */
- UART3_IRQn = 29, /*!< UART3 Interrupt */
- I2C2_IRQn = 30, /*!< I2C2 Interrupt */
- I2S_IRQn = 31, /*!< I2S Interrupt */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the ARM7 Processor and Core Peripherals */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-
-#include <core_arm7.h>
-#include "system_LPC23xx.h" /* System Header */
-
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-#if defined ( __CC_ARM )
- #pragma anon_unions
-#endif
-
-/*------------- Vector Interupt Controler (VIC) ------------------------------*/
-typedef struct
-{
- __I uint32_t IRQStatus;
- __I uint32_t FIQStatus;
- __I uint32_t RawIntr;
- __IO uint32_t IntSelect;
- __IO uint32_t IntEnable;
- __O uint32_t IntEnClr;
- __IO uint32_t SoftInt;
- __O uint32_t SoftIntClr;
- __IO uint32_t Protection;
- __IO uint32_t SWPriorityMask;
- __IO uint32_t RESERVED0[54];
- __IO uint32_t VectAddr[32];
- __IO uint32_t RESERVED1[32];
- __IO uint32_t VectPriority[32];
- __IO uint32_t RESERVED2[800];
- __IO uint32_t Address;
-} LPC_VIC_TypeDef;
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
- __IO uint32_t MAMCR;
- __IO uint32_t MAMTIM;
- uint32_t RESERVED0[14];
- __IO uint32_t MEMMAP;
- uint32_t RESERVED1[15];
- __IO uint32_t PLL0CON; /* Clocking and Power Control */
- __IO uint32_t PLL0CFG;
- __I uint32_t PLL0STAT;
- __O uint32_t PLL0FEED;
- uint32_t RESERVED2[12];
- __IO uint32_t PCON;
- __IO uint32_t PCONP;
- uint32_t RESERVED3[15];
- __IO uint32_t CCLKCFG;
- __IO uint32_t USBCLKCFG;
- __IO uint32_t CLKSRCSEL;
- uint32_t RESERVED4[12];
- __IO uint32_t EXTINT; /* External Interrupts */
- __IO uint32_t INTWAKE;
- __IO uint32_t EXTMODE;
- __IO uint32_t EXTPOLAR;
- uint32_t RESERVED6[12];
- __IO uint32_t RSID; /* Reset */
- __IO uint32_t CSPR;
- __IO uint32_t AHBCFG1;
- __IO uint32_t AHBCFG2;
- uint32_t RESERVED7[4];
- __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
- __IO uint32_t IRCTRIM; /* Clock Dividers */
- __IO uint32_t PCLKSEL0;
- __IO uint32_t PCLKSEL1;
- uint32_t RESERVED8[4];
- __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
- uint32_t RESERVED9;
-// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
- __IO uint32_t PINSEL0;
- __IO uint32_t PINSEL1;
- __IO uint32_t PINSEL2;
- __IO uint32_t PINSEL3;
- __IO uint32_t PINSEL4;
- __IO uint32_t PINSEL5;
- __IO uint32_t PINSEL6;
- __IO uint32_t PINSEL7;
- __IO uint32_t PINSEL8;
- __IO uint32_t PINSEL9;
- __IO uint32_t PINSEL10;
- uint32_t RESERVED0[5];
- __IO uint32_t PINMODE0;
- __IO uint32_t PINMODE1;
- __IO uint32_t PINMODE2;
- __IO uint32_t PINMODE3;
- __IO uint32_t PINMODE4;
- __IO uint32_t PINMODE5;
- __IO uint32_t PINMODE6;
- __IO uint32_t PINMODE7;
- __IO uint32_t PINMODE8;
- __IO uint32_t PINMODE9;
- __IO uint32_t PINMODE_OD0;
- __IO uint32_t PINMODE_OD1;
- __IO uint32_t PINMODE_OD2;
- __IO uint32_t PINMODE_OD3;
- __IO uint32_t PINMODE_OD4;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
- __IO uint32_t FIODIR;
- uint32_t RESERVED0[3];
- __IO uint32_t FIOMASK;
- __IO uint32_t FIOPIN;
- __IO uint32_t FIOSET;
- __O uint32_t FIOCLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
- __I uint32_t IntStatus;
- __I uint32_t IO0IntStatR;
- __I uint32_t IO0IntStatF;
- __O uint32_t IO0IntClr;
- __IO uint32_t IO0IntEnR;
- __IO uint32_t IO0IntEnF;
- uint32_t RESERVED0[3];
- __I uint32_t IO2IntStatR;
- __I uint32_t IO2IntStatF;
- __O uint32_t IO2IntClr;
- __IO uint32_t IO2IntEnR;
- __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
- __IO uint32_t IR;
- __IO uint32_t TCR;
- __IO uint32_t TC;
- __IO uint32_t PR;
- __IO uint32_t PC;
- __IO uint32_t MCR;
- __IO uint32_t MR0;
- __IO uint32_t MR1;
- __IO uint32_t MR2;
- __IO uint32_t MR3;
- __IO uint32_t CCR;
- __I uint32_t CR0;
- __I uint32_t CR1;
- uint32_t RESERVED0[2];
- __IO uint32_t EMR;
- uint32_t RESERVED1[12];
- __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
- __IO uint32_t IR;
- __IO uint32_t TCR;
- __IO uint32_t TC;
- __IO uint32_t PR;
- __IO uint32_t PC;
- __IO uint32_t MCR;
- __IO uint32_t MR0;
- __IO uint32_t MR1;
- __IO uint32_t MR2;
- __IO uint32_t MR3;
- __IO uint32_t CCR;
- __I uint32_t CR0;
- __I uint32_t CR1;
- __I uint32_t CR2;
- __I uint32_t CR3;
- uint32_t RESERVED0;
- __IO uint32_t MR4;
- __IO uint32_t MR5;
- __IO uint32_t MR6;
- __IO uint32_t PCR;
- __IO uint32_t LER;
- uint32_t RESERVED1[7];
- __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[7];
- __IO uint8_t LSR;
- uint8_t RESERVED2[7];
- __IO uint8_t SCR;
- uint8_t RESERVED3[3];
- __IO uint32_t ACR;
- __IO uint8_t ICR;
- uint8_t RESERVED4[3];
- __IO uint8_t FDR;
- uint8_t RESERVED5[7];
- __IO uint8_t TER;
- uint8_t RESERVED6[27];
- __IO uint8_t RS485CTRL;
- uint8_t RESERVED7[3];
- __IO uint8_t ADRMATCH;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[3];
- __IO uint8_t MCR;
- uint8_t RESERVED2[3];
- __IO uint8_t LSR;
- uint8_t RESERVED3[3];
- __IO uint8_t MSR;
- uint8_t RESERVED4[3];
- __IO uint8_t SCR;
- uint8_t RESERVED5[3];
- __IO uint32_t ACR;
- uint32_t RESERVED6;
- __IO uint32_t FDR;
- uint32_t RESERVED7;
- __IO uint8_t TER;
- uint8_t RESERVED8[27];
- __IO uint8_t RS485CTRL;
- uint8_t RESERVED9[3];
- __IO uint8_t ADRMATCH;
- uint8_t RESERVED10[3];
- __IO uint8_t RS485DLY;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
- __IO uint32_t SPCR;
- __I uint32_t SPSR;
- __IO uint32_t SPDR;
- __IO uint32_t SPCCR;
- uint32_t RESERVED0[3];
- __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
- __IO uint32_t CR0;
- __IO uint32_t CR1;
- __IO uint32_t DR;
- __I uint32_t SR;
- __IO uint32_t CPSR;
- __IO uint32_t IMSC;
- __IO uint32_t RIS;
- __IO uint32_t MIS;
- __IO uint32_t ICR;
- __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
- __IO uint32_t I2CONSET;
- __I uint32_t I2STAT;
- __IO uint32_t I2DAT;
- __IO uint32_t I2ADR0;
- __IO uint32_t I2SCLH;
- __IO uint32_t I2SCLL;
- __O uint32_t I2CONCLR;
- __IO uint32_t MMCTRL;
- __IO uint32_t I2ADR1;
- __IO uint32_t I2ADR2;
- __IO uint32_t I2ADR3;
- __I uint32_t I2DATA_BUFFER;
- __IO uint32_t I2MASK0;
- __IO uint32_t I2MASK1;
- __IO uint32_t I2MASK2;
- __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t I2SDAO;
- __I uint32_t I2SDAI;
- __O uint32_t I2STXFIFO;
- __I uint32_t I2SRXFIFO;
- __I uint32_t I2SSTATE;
- __IO uint32_t I2SDMA1;
- __IO uint32_t I2SDMA2;
- __IO uint32_t I2SIRQ;
- __IO uint32_t I2STXRATE;
- __IO uint32_t I2SRXRATE;
- __IO uint32_t I2STXBITRATE;
- __IO uint32_t I2SRXBITRATE;
- __IO uint32_t I2STXMODE;
- __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
- __IO uint8_t ILR;
- uint8_t RESERVED0[3];
- __IO uint8_t CTC;
- uint8_t RESERVED1[3];
- __IO uint8_t CCR;
- uint8_t RESERVED2[3];
- __IO uint8_t CIIR;
- uint8_t RESERVED3[3];
- __IO uint8_t AMR;
- uint8_t RESERVED4[3];
- __I uint32_t CTIME0;
- __I uint32_t CTIME1;
- __I uint32_t CTIME2;
- __IO uint8_t SEC;
- uint8_t RESERVED5[3];
- __IO uint8_t MIN;
- uint8_t RESERVED6[3];
- __IO uint8_t HOUR;
- uint8_t RESERVED7[3];
- __IO uint8_t DOM;
- uint8_t RESERVED8[3];
- __IO uint8_t DOW;
- uint8_t RESERVED9[3];
- __IO uint16_t DOY;
- uint16_t RESERVED10;
- __IO uint8_t MONTH;
- uint8_t RESERVED11[3];
- __IO uint16_t YEAR;
- uint16_t RESERVED12;
- __IO uint32_t CALIBRATION;
- __IO uint32_t GPREG0;
- __IO uint32_t GPREG1;
- __IO uint32_t GPREG2;
- __IO uint32_t GPREG3;
- __IO uint32_t GPREG4;
- __IO uint8_t WAKEUPDIS;
- uint8_t RESERVED13[3];
- __IO uint8_t PWRCTRL;
- uint8_t RESERVED14[3];
- __IO uint8_t ALSEC;
- uint8_t RESERVED15[3];
- __IO uint8_t ALMIN;
- uint8_t RESERVED16[3];
- __IO uint8_t ALHOUR;
- uint8_t RESERVED17[3];
- __IO uint8_t ALDOM;
- uint8_t RESERVED18[3];
- __IO uint8_t ALDOW;
- uint8_t RESERVED19[3];
- __IO uint16_t ALDOY;
- uint16_t RESERVED20;
- __IO uint8_t ALMON;
- uint8_t RESERVED21[3];
- __IO uint16_t ALYEAR;
- uint16_t RESERVED22;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
- __IO uint8_t WDMOD;
- uint8_t RESERVED0[3];
- __IO uint32_t WDTC;
- __O uint8_t WDFEED;
- uint8_t RESERVED1[3];
- __I uint32_t WDTV;
- __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t ADCR;
- __IO uint32_t ADGDR;
- uint32_t RESERVED0;
- __IO uint32_t ADINTEN;
- __I uint32_t ADDR0;
- __I uint32_t ADDR1;
- __I uint32_t ADDR2;
- __I uint32_t ADDR3;
- __I uint32_t ADDR4;
- __I uint32_t ADDR5;
- __I uint32_t ADDR6;
- __I uint32_t ADDR7;
- __I uint32_t ADSTAT;
- __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t DACR;
- __IO uint32_t DACCTRL;
- __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Multimedia Card Interface (MCI) ------------------------------*/
-typedef struct
-{
- __IO uint32_t MCIPower; /* Power control */
- __IO uint32_t MCIClock; /* Clock control */
- __IO uint32_t MCIArgument;
- __IO uint32_t MMCCommand;
- __I uint32_t MCIRespCmd;
- __I uint32_t MCIResponse0;
- __I uint32_t MCIResponse1;
- __I uint32_t MCIResponse2;
- __I uint32_t MCIResponse3;
- __IO uint32_t MCIDataTimer;
- __IO uint32_t MCIDataLength;
- __IO uint32_t MCIDataCtrl;
- __I uint32_t MCIDataCnt;
-} LPC_MCI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
- __IO uint32_t mask[512]; /* ID Masks */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct /* Acceptance Filter Registers */
-{
- __IO uint32_t AFMR;
- __IO uint32_t SFF_sa;
- __IO uint32_t SFF_GRP_sa;
- __IO uint32_t EFF_sa;
- __IO uint32_t EFF_GRP_sa;
- __IO uint32_t ENDofTable;
- __I uint32_t LUTerrAd;
- __I uint32_t LUTerr;
-} LPC_CANAF_TypeDef;
-
-typedef struct /* Central Registers */
-{
- __I uint32_t CANTxSR;
- __I uint32_t CANRxSR;
- __I uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct /* Controller Registers */
-{
- __IO uint32_t MOD;
- __O uint32_t CMR;
- __IO uint32_t GSR;
- __I uint32_t ICR;
- __IO uint32_t IER;
- __IO uint32_t BTR;
- __IO uint32_t EWL;
- __I uint32_t SR;
- __IO uint32_t RFS;
- __IO uint32_t RID;
- __IO uint32_t RDA;
- __IO uint32_t RDB;
- __IO uint32_t TFI1;
- __IO uint32_t TID1;
- __IO uint32_t TDA1;
- __IO uint32_t TDB1;
- __IO uint32_t TFI2;
- __IO uint32_t TID2;
- __IO uint32_t TDA2;
- __IO uint32_t TDB2;
- __IO uint32_t TFI3;
- __IO uint32_t TID3;
- __IO uint32_t TDA3;
- __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct /* Common Registers */
-{
- __I uint32_t DMACIntStat;
- __I uint32_t DMACIntTCStat;
- __O uint32_t DMACIntTCClear;
- __I uint32_t DMACIntErrStat;
- __O uint32_t DMACIntErrClr;
- __I uint32_t DMACRawIntTCStat;
- __I uint32_t DMACRawIntErrStat;
- __I uint32_t DMACEnbldChns;
- __IO uint32_t DMACSoftBReq;
- __IO uint32_t DMACSoftSReq;
- __IO uint32_t DMACSoftLBReq;
- __IO uint32_t DMACSoftLSReq;
- __IO uint32_t DMACConfig;
- __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct /* Channel Registers */
-{
- __IO uint32_t DMACCSrcAddr;
- __IO uint32_t DMACCDestAddr;
- __IO uint32_t DMACCLLI;
- __IO uint32_t DMACCControl;
- __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
- __I uint32_t HcRevision; /* USB Host Registers */
- __IO uint32_t HcControl;
- __IO uint32_t HcCommandStatus;
- __IO uint32_t HcInterruptStatus;
- __IO uint32_t HcInterruptEnable;
- __IO uint32_t HcInterruptDisable;
- __IO uint32_t HcHCCA;
- __I uint32_t HcPeriodCurrentED;
- __IO uint32_t HcControlHeadED;
- __IO uint32_t HcControlCurrentED;
- __IO uint32_t HcBulkHeadED;
- __IO uint32_t HcBulkCurrentED;
- __I uint32_t HcDoneHead;
- __IO uint32_t HcFmInterval;
- __I uint32_t HcFmRemaining;
- __I uint32_t HcFmNumber;
- __IO uint32_t HcPeriodicStart;
- __IO uint32_t HcLSTreshold;
- __IO uint32_t HcRhDescriptorA;
- __IO uint32_t HcRhDescriptorB;
- __IO uint32_t HcRhStatus;
- __IO uint32_t HcRhPortStatus1;
- __IO uint32_t HcRhPortStatus2;
- uint32_t RESERVED0[40];
- __I uint32_t Module_ID;
-
- __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
- __IO uint32_t OTGIntEn;
- __O uint32_t OTGIntSet;
- __O uint32_t OTGIntClr;
- __IO uint32_t OTGStCtrl;
- __IO uint32_t OTGTmr;
- uint32_t RESERVED1[58];
-
- __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
- __IO uint32_t USBDevIntEn;
- __O uint32_t USBDevIntClr;
- __O uint32_t USBDevIntSet;
-
- __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
- __I uint32_t USBCmdData;
-
- __I uint32_t USBRxData; /* USB Device Transfer Registers */
- __O uint32_t USBTxData;
- __I uint32_t USBRxPLen;
- __O uint32_t USBTxPLen;
- __IO uint32_t USBCtrl;
- __O uint32_t USBDevIntPri;
-
- __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
- __IO uint32_t USBEpIntEn;
- __O uint32_t USBEpIntClr;
- __O uint32_t USBEpIntSet;
- __O uint32_t USBEpIntPri;
-
- __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
- __O uint32_t USBEpInd;
- __IO uint32_t USBMaxPSize;
-
- __I uint32_t USBDMARSt; /* USB Device DMA Registers */
- __O uint32_t USBDMARClr;
- __O uint32_t USBDMARSet;
- uint32_t RESERVED2[9];
- __IO uint32_t USBUDCAH;
- __I uint32_t USBEpDMASt;
- __O uint32_t USBEpDMAEn;
- __O uint32_t USBEpDMADis;
- __I uint32_t USBDMAIntSt;
- __IO uint32_t USBDMAIntEn;
- uint32_t RESERVED3[2];
- __I uint32_t USBEoTIntSt;
- __O uint32_t USBEoTIntClr;
- __O uint32_t USBEoTIntSet;
- __I uint32_t USBNDDRIntSt;
- __O uint32_t USBNDDRIntClr;
- __O uint32_t USBNDDRIntSet;
- __I uint32_t USBSysErrIntSt;
- __O uint32_t USBSysErrIntClr;
- __O uint32_t USBSysErrIntSet;
- uint32_t RESERVED4[15];
-
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */
- __O uint32_t I2C_WO;
- __I uint32_t I2C_STS;
- __IO uint32_t I2C_CTL;
- __IO uint32_t I2C_CLKHI;
- __O uint32_t I2C_CLKLO;
- uint32_t RESERVED5[823];
-
- union {
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
- __IO uint32_t OTGClkCtrl;
- };
- union {
- __I uint32_t USBClkSt;
- __I uint32_t OTGClkSt;
- };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
- __IO uint32_t MAC1; /* MAC Registers */
- __IO uint32_t MAC2;
- __IO uint32_t IPGT;
- __IO uint32_t IPGR;
- __IO uint32_t CLRT;
- __IO uint32_t MAXF;
- __IO uint32_t SUPP;
- __IO uint32_t TEST;
- __IO uint32_t MCFG;
- __IO uint32_t MCMD;
- __IO uint32_t MADR;
- __O uint32_t MWTD;
- __I uint32_t MRDD;
- __I uint32_t MIND;
- uint32_t RESERVED0[2];
- __IO uint32_t SA0;
- __IO uint32_t SA1;
- __IO uint32_t SA2;
- uint32_t RESERVED1[45];
- __IO uint32_t Command; /* Control Registers */
- __I uint32_t Status;
- __IO uint32_t RxDescriptor;
- __IO uint32_t RxStatus;
- __IO uint32_t RxDescriptorNumber;
- __I uint32_t RxProduceIndex;
- __IO uint32_t RxConsumeIndex;
- __IO uint32_t TxDescriptor;
- __IO uint32_t TxStatus;
- __IO uint32_t TxDescriptorNumber;
- __IO uint32_t TxProduceIndex;
- __I uint32_t TxConsumeIndex;
- uint32_t RESERVED2[10];
- __I uint32_t TSV0;
- __I uint32_t TSV1;
- __I uint32_t RSV;
- uint32_t RESERVED3[3];
- __IO uint32_t FlowControlCounter;
- __I uint32_t FlowControlStatus;
- uint32_t RESERVED4[34];
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
- __IO uint32_t RxFilterWoLStatus;
- __IO uint32_t RxFilterWoLClear;
- uint32_t RESERVED5;
- __IO uint32_t HashFilterL;
- __IO uint32_t HashFilterH;
- uint32_t RESERVED6[882];
- __I uint32_t IntStatus; /* Module Control Registers */
- __IO uint32_t IntEnable;
- __O uint32_t IntClear;
- __O uint32_t IntSet;
- uint32_t RESERVED7;
- __IO uint32_t PowerDown;
- uint32_t RESERVED8;
- __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM )
- #pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Base addresses */
-
-/* AHB Peripheral # 0 */
-
-/*
-#define FLASH_BASE (0x00000000UL)
-#define RAM_BASE (0x10000000UL)
-#define GPIO_BASE (0x2009C000UL)
-#define APB0_BASE (0x40000000UL)
-#define APB1_BASE (0x40080000UL)
-#define AHB_BASE (0x50000000UL)
-#define CM3_BASE (0xE0000000UL)
-*/
-
-// TODO - #define VIC_BASE_ADDR 0xFFFFF000
-
-#define LPC_WDT_BASE (0xE0000000)
-#define LPC_TIM0_BASE (0xE0004000)
-#define LPC_TIM1_BASE (0xE0008000)
-#define LPC_UART0_BASE (0xE000C000)
-#define LPC_UART1_BASE (0xE0010000)
-#define LPC_PWM1_BASE (0xE0018000)
-#define LPC_I2C0_BASE (0xE001C000)
-#define LPC_SPI_BASE (0xE0020000)
-#define LPC_RTC_BASE (0xE0024000)
-#define LPC_GPIOINT_BASE (0xE0028080)
-#define LPC_PINCON_BASE (0xE002C000)
-#define LPC_SSP1_BASE (0xE0030000)
-#define LPC_ADC_BASE (0xE0034000)
-#define LPC_CANAF_RAM_BASE (0xE0038000)
-#define LPC_CANAF_BASE (0xE003C000)
-#define LPC_CANCR_BASE (0xE0040000)
-#define LPC_CAN1_BASE (0xE0044000)
-#define LPC_CAN2_BASE (0xE0048000)
-#define LPC_I2C1_BASE (0xE005C000)
-#define LPC_SSP0_BASE (0xE0068000)
-#define LPC_DAC_BASE (0xE006C000)
-#define LPC_TIM2_BASE (0xE0070000)
-#define LPC_TIM3_BASE (0xE0074000)
-#define LPC_UART2_BASE (0xE0078000)
-#define LPC_UART3_BASE (0xE007C000)
-#define LPC_I2C2_BASE (0xE0080000)
-#define LPC_I2S_BASE (0xE0088000)
-#define LPC_MCI_BASE (0xE008C000)
-#define LPC_SC_BASE (0xE01FC000)
-#define LPC_EMAC_BASE (0xFFE00000)
-#define LPC_GPDMA_BASE (0xFFE04000)
-#define LPC_GPDMACH0_BASE (0xFFE04100)
-#define LPC_GPDMACH1_BASE (0xFFE04120)
-#define LPC_USB_BASE (0xFFE0C000)
-#define LPC_VIC_BASE (0xFFFFF000)
-
-/* GPIOs */
-#define LPC_GPIO0_BASE (0x3FFFC000)
-#define LPC_GPIO1_BASE (0x3FFFC020)
-#define LPC_GPIO2_BASE (0x3FFFC040)
-#define LPC_GPIO3_BASE (0x3FFFC060)
-#define LPC_GPIO4_BASE (0x3FFFC080)
-
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
-#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
-#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
-#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
-#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
-#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
-#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
-#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
-#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
-#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
-#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
-#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
-#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
-#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
-#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
-#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
-#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
-#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
-#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
-#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
-#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
-#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
-#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
-#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
-#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
-#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
-#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
-#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
-#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
-#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
-#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
-#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
-#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
-#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
-#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
-#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
-#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
-#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
-#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif // __LPC23xx_H
-
+/* mbed Microcontroller Library - LPC23xx CMSIS-like structs
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
+ */
+
+#ifndef __LPC23xx_H
+#define __LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** LPC23xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+
+ TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
+ UART0_IRQn = 6, /*!< UART0 Interrupt */
+ UART1_IRQn = 7, /*!< UART1 Interrupt */
+ PWM1_IRQn = 8, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 9, /*!< I2C0 Interrupt */
+ SPI_IRQn = 10, /*!< SPI Interrupt */
+ SSP0_IRQn = 10, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 11, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 18, /*!< A/D Converter Interrupt */
+ I2C1_IRQn = 19, /*!< I2C1 Interrupt */
+ BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
+ ENET_IRQn = 21, /*!< Ethernet Interrupt */
+ USB_IRQn = 22, /*!< USB Interrupt */
+ CAN_IRQn = 23, /*!< CAN Interrupt */
+ MIC_IRQn = 24, /*!< Multimedia Interface Controler */
+ DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
+ TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
+ UART2_IRQn = 28, /*!< UART2 Interrupt */
+ UART3_IRQn = 29, /*!< UART3 Interrupt */
+ I2C2_IRQn = 30, /*!< I2C2 Interrupt */
+ I2S_IRQn = 31, /*!< I2S Interrupt */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the ARM7 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include <core_arm7.h>
+#include "system_LPC23xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+#if defined ( __CC_ARM )
+ #pragma anon_unions
+#endif
+
+/*------------- Vector Interupt Controler (VIC) ------------------------------*/
+typedef struct
+{
+ __I uint32_t IRQStatus;
+ __I uint32_t FIQStatus;
+ __I uint32_t RawIntr;
+ __IO uint32_t IntSelect;
+ __IO uint32_t IntEnable;
+ __O uint32_t IntEnClr;
+ __IO uint32_t SoftInt;
+ __O uint32_t SoftIntClr;
+ __IO uint32_t Protection;
+ __IO uint32_t SWPriorityMask;
+ __IO uint32_t RESERVED0[54];
+ __IO uint32_t VectAddr[32];
+ __IO uint32_t RESERVED1[32];
+ __IO uint32_t VectPriority[32];
+ __IO uint32_t RESERVED2[800];
+ __IO uint32_t Address;
+} LPC_VIC_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t MAMCR;
+ __IO uint32_t MAMTIM;
+ uint32_t RESERVED0[14];
+ __IO uint32_t MEMMAP;
+ uint32_t RESERVED1[15];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED2[12];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ uint32_t RESERVED4[12];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ __IO uint32_t INTWAKE;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ __IO uint32_t CSPR;
+ __IO uint32_t AHBCFG1;
+ __IO uint32_t AHBCFG2;
+ uint32_t RESERVED7[4];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ uint32_t RESERVED9;
+// __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t FIODIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t FIOMASK;
+ __IO uint32_t FIOPIN;
+ __IO uint32_t FIOSET;
+ __O uint32_t FIOCLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __IO uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED7[3];
+ __IO uint8_t ADRMATCH;
+} LPC_UART_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __IO uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __I uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[3];
+ __IO uint8_t CTC;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CCR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED3[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED4[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED5[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED6[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED8[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED9[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED10;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED11[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED12;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t WAKEUPDIS;
+ uint8_t RESERVED13[3];
+ __IO uint8_t PWRCTRL;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED18[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED19[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED20;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED21[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED22;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Multimedia Card Interface (MCI) ------------------------------*/
+typedef struct
+{
+ __IO uint32_t MCIPower; /* Power control */
+ __IO uint32_t MCIClock; /* Clock control */
+ __IO uint32_t MCIArgument;
+ __IO uint32_t MMCCommand;
+ __I uint32_t MCIRespCmd;
+ __I uint32_t MCIResponse0;
+ __I uint32_t MCIResponse1;
+ __I uint32_t MCIResponse2;
+ __I uint32_t MCIResponse3;
+ __IO uint32_t MCIDataTimer;
+ __IO uint32_t MCIDataLength;
+ __IO uint32_t MCIDataCtrl;
+ __I uint32_t MCIDataCnt;
+} LPC_MCI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_WO;
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[823];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+#if defined ( __CC_ARM )
+ #pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+
+/* AHB Peripheral # 0 */
+
+/*
+#define FLASH_BASE (0x00000000UL)
+#define RAM_BASE (0x10000000UL)
+#define GPIO_BASE (0x2009C000UL)
+#define APB0_BASE (0x40000000UL)
+#define APB1_BASE (0x40080000UL)
+#define AHB_BASE (0x50000000UL)
+#define CM3_BASE (0xE0000000UL)
+*/
+
+// TODO - #define VIC_BASE_ADDR 0xFFFFF000
+
+#define LPC_WDT_BASE (0xE0000000)
+#define LPC_TIM0_BASE (0xE0004000)
+#define LPC_TIM1_BASE (0xE0008000)
+#define LPC_UART0_BASE (0xE000C000)
+#define LPC_UART1_BASE (0xE0010000)
+#define LPC_PWM1_BASE (0xE0018000)
+#define LPC_I2C0_BASE (0xE001C000)
+#define LPC_SPI_BASE (0xE0020000)
+#define LPC_RTC_BASE (0xE0024000)
+#define LPC_GPIOINT_BASE (0xE0028080)
+#define LPC_PINCON_BASE (0xE002C000)
+#define LPC_SSP1_BASE (0xE0030000)
+#define LPC_ADC_BASE (0xE0034000)
+#define LPC_CANAF_RAM_BASE (0xE0038000)
+#define LPC_CANAF_BASE (0xE003C000)
+#define LPC_CANCR_BASE (0xE0040000)
+#define LPC_CAN1_BASE (0xE0044000)
+#define LPC_CAN2_BASE (0xE0048000)
+#define LPC_I2C1_BASE (0xE005C000)
+#define LPC_SSP0_BASE (0xE0068000)
+#define LPC_DAC_BASE (0xE006C000)
+#define LPC_TIM2_BASE (0xE0070000)
+#define LPC_TIM3_BASE (0xE0074000)
+#define LPC_UART2_BASE (0xE0078000)
+#define LPC_UART3_BASE (0xE007C000)
+#define LPC_I2C2_BASE (0xE0080000)
+#define LPC_I2S_BASE (0xE0088000)
+#define LPC_MCI_BASE (0xE008C000)
+#define LPC_SC_BASE (0xE01FC000)
+#define LPC_EMAC_BASE (0xFFE00000)
+#define LPC_GPDMA_BASE (0xFFE04000)
+#define LPC_GPDMACH0_BASE (0xFFE04100)
+#define LPC_GPDMACH1_BASE (0xFFE04120)
+#define LPC_USB_BASE (0xFFE0C000)
+#define LPC_VIC_BASE (0xFFFFF000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (0x3FFFC000)
+#define LPC_GPIO1_BASE (0x3FFFC020)
+#define LPC_GPIO2_BASE (0x3FFFC040)
+#define LPC_GPIO3_BASE (0x3FFFC060)
+#define LPC_GPIO4_BASE (0x3FFFC080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
+#define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
+#define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
+#define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
+#define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
+#define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
+#define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
+#define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
+#define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
+#define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
+#define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
+#define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
+#define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
+#define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
+#define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
+#define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
+#define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
+#define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
+#define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
+#define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
+#define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
+#define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
+#define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
+#define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
+#define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
+#define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
+#define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
+#define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
+#define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
+#define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
+#define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
+#define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
+#define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
+#define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
+#define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
+#define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
+#define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
+#define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif // __LPC23xx_H
+
--- a/TARGET_LPC2368/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,80 +1,80 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_UART0_BASE,
- UART_1 = (int)LPC_UART1_BASE,
- UART_2 = (int)LPC_UART2_BASE,
- UART_3 = (int)LPC_UART3_BASE
-} UARTName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C0_BASE,
- I2C_1 = (int)LPC_I2C1_BASE,
- I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
- PWM_1 = 1,
- PWM_2,
- PWM_3,
- PWM_4,
- PWM_5,
- PWM_6
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)LPC_CAN1_BASE,
- CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = 1,
+ PWM_2,
+ PWM_3,
+ PWM_4,
+ PWM_5,
+ PWM_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,103 +1,103 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-#define PORT_SHIFT 5
-
-typedef enum {
- // LPC Pin Names
- P0_0 = LPC_GPIO0_BASE,
- P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
- P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
- P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
- P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
- P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
-
- // mbed DIP Pin Names
- p5 = P0_9,
- p6 = P0_8,
- p7 = P0_7,
- p8 = P0_6,
- p9 = P0_0,
- p10 = P0_1,
- p11 = P0_18,
- p12 = P0_17,
- p13 = P0_15,
- p14 = P0_16,
- p15 = P0_23,
- p16 = P0_24,
- p17 = P0_25,
- p18 = P0_26,
- p19 = P1_30,
- p20 = P1_31,
- p21 = P2_5,
- p22 = P2_4,
- p23 = P2_3,
- p24 = P2_2,
- p25 = P2_1,
- p26 = P2_0,
- p27 = P0_11,
- p28 = P0_10,
- p29 = P0_5,
- p30 = P0_4,
-
- // Other mbed Pin Names
- LED1 = P1_18,
- LED2 = P1_20,
- LED3 = P1_21,
- LED4 = P1_23,
-
- USBTX = P0_2,
- USBRX = P0_3,
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
- PullUp = 0,
- PullDown = 3,
- PullNone = 2,
- OpenDrain = 4
-} PinMode;
-
-// version of PINCON_TypeDef using register arrays
-typedef struct {
- __IO uint32_t PINSEL[11];
- uint32_t RESERVED0[5];
- __IO uint32_t PINMODE[10];
-} PINCONARRAY_TypeDef;
-
-#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 5
+
+typedef enum {
+ // LPC Pin Names
+ P0_0 = LPC_GPIO0_BASE,
+ P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
+ P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
+ P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
+ P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
+ P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
+
+ // mbed DIP Pin Names
+ p5 = P0_9,
+ p6 = P0_8,
+ p7 = P0_7,
+ p8 = P0_6,
+ p9 = P0_0,
+ p10 = P0_1,
+ p11 = P0_18,
+ p12 = P0_17,
+ p13 = P0_15,
+ p14 = P0_16,
+ p15 = P0_23,
+ p16 = P0_24,
+ p17 = P0_25,
+ p18 = P0_26,
+ p19 = P1_30,
+ p20 = P1_31,
+ p21 = P2_5,
+ p22 = P2_4,
+ p23 = P2_3,
+ p24 = P2_2,
+ p25 = P2_1,
+ p26 = P2_0,
+ p27 = P0_11,
+ p28 = P0_10,
+ p29 = P0_5,
+ p30 = P0_4,
+
+ // Other mbed Pin Names
+ LED1 = P1_18,
+ LED2 = P1_20,
+ LED3 = P1_21,
+ LED4 = P1_23,
+
+ USBTX = P0_2,
+ USBRX = P0_3,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullUp = 0,
+ PullDown = 3,
+ PullNone = 2,
+ OpenDrain = 4
+} PinMode;
+
+// version of PINCON_TypeDef using register arrays
+typedef struct {
+ __IO uint32_t PINSEL[11];
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE[10];
+} PINCONARRAY_TypeDef;
+
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,34 +1,34 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1,
- Port2 = 2,
- Port3 = 3,
- Port4 = 4
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC2368/TOOLCHAIN_ARM_STD/LPC2368.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/TOOLCHAIN_ARM_STD/LPC2368.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,24 +1,24 @@
-
-LR_IROM1 0x00000000 0x80000 { ; load region size_region
- ER_IROM1 0x00000000 0x80000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x40000120 0x7EE0 { ; RW data, inc space for realmonitor
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x7FD00000 0x2000 { ; RW data, USB RAM
- .ANY (AHBSRAM0)
- }
- RW_IRAM3 0x7FE00000 0x4000 { ; RW data, ETH RAM
- .ANY (AHBSRAM1)
- }
- RW_IRAM4 0xE0038000 0x0800 { ; RW data, CAN RAM
- .ANY (CANRAM)
- }
- RW_IRAM5 0xE0084000 0x0800 { ; RW data, RTC RAM
- .ANY (RTCRAM)
- }
-}
-
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x40000120 0x7EE0 { ; RW data, inc space for realmonitor
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x7FD00000 0x2000 { ; RW data, USB RAM
+ .ANY (AHBSRAM0)
+ }
+ RW_IRAM3 0x7FE00000 0x4000 { ; RW data, ETH RAM
+ .ANY (AHBSRAM1)
+ }
+ RW_IRAM4 0xE0038000 0x0800 { ; RW data, CAN RAM
+ .ANY (CANRAM)
+ }
+ RW_IRAM5 0xE0084000 0x0800 { ; RW data, RTC RAM
+ .ANY (RTCRAM)
+ }
+}
+
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/core_arm7.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/system_LPC23xx.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_functions.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_realmonitor.o has changed
Binary file TARGET_LPC2368/TOOLCHAIN_ARM_STD/vector_table.o has changed
--- a/TARGET_LPC2368/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC2368/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC2368 specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC23xx.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC2368 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC23xx.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC2368/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS 32
-#define NVIC_USER_IRQ_OFFSET 0
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS 32
+#define NVIC_USER_IRQ_OFFSET 0
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/core_arm7.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/core_arm7.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,276 +1,276 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- * based on core_cm3.h, V1.20
- */
-
-#ifndef __ARM7_CORE_H__
-#define __ARM7_CORE_H__
-
-#include "vector_defns.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-/**
- * Lint configuration \n
- * ----------------------- \n
- *
- * The following Lint messages will be suppressed and not shown: \n
- * \n
- * --- Error 10: --- \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';' \n
- * \n
- * --- Error 530: --- \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
- * \n
- * --- Error 550: --- \n
- * __regBasePri = (basePri & 0x1ff); \n
- * } \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
- * \n
- * --- Error 754: --- \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
- * \n
- * --- Error 750: --- \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
- * \n
- * --- Error 528: --- \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
- * \n
- * --- Error 751: --- \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
- * \n
- * \n
- * Note: To re-enable a Message, insert a space before 'lint' * \n
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-#include <stdint.h> /* Include standard types */
-
-#if defined ( __CC_ARM )
-/**
- * @brief Return the Main Stack Pointer (current ARM7 stack)
- *
- * @param none
- * @return uint32_t Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-#endif
-
-
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-typedef struct
-{
- uint32_t IRQStatus;
- uint32_t FIQStatus;
- uint32_t RawIntr;
- uint32_t IntSelect;
- uint32_t IntEnable;
- uint32_t IntEnClr;
- uint32_t SoftInt;
- uint32_t SoftIntClr;
- uint32_t Protection;
- uint32_t SWPriorityMask;
- uint32_t RESERVED0[54];
- uint32_t VectAddr[32];
- uint32_t RESERVED1[32];
- uint32_t VectPriority[32];
- uint32_t RESERVED2[800];
- uint32_t Address;
-} NVIC_TypeDef;
-
-#define NVIC_BASE (0xFFFFF000)
-#define NVIC (( NVIC_TypeDef *) NVIC_BASE)
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-#define __I volatile /*!< defines 'read only' permissions */
-#else
-#define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-//#define __WFI __wfi
-//#define __WFE __wfe
-//#define __SEV __sev
-//#define __ISB() __isb(0)
-//#define __DSB() __dsb(0)
-//#define __DMB() __dmb(0)
-//#define __REV __rev
-//#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
- LPC_VIC->IntEnClr = 0xffffffff
-
-#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-static __INLINE void __enable_irq() {
- unsigned long temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
- "bic %0, %0, #0x80\n"
- "msr cpsr_c, %0"
- : "=r" (temp)
- :
- : "memory");
-}
-
-static __INLINE void __disable_irq() {
- unsigned long old,temp;
- __asm__ __volatile__("mrs %0, cpsr\n"
- "orr %1, %0, #0xc0\n"
- "msr cpsr_c, %1"
- : "=r" (old), "=r" (temp)
- :
- : "memory");
- // return (old & 0x80) == 0;
-}
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn_Type IRQn specifies the interrupt number
- * @return none
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->IntEnable = 1 << (uint32_t)IRQn;
-}
-
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn_Type IRQn is the positive number of the external interrupt
- * @return none
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->IntEnClr = 1 << (uint32_t)IRQn;
-}
-
-static __INLINE uint32_t __get_IPSR(void)
-{
- unsigned i;
-
- for(i = 0; i < 32; i ++)
- if(NVIC->Address == NVIC->VectAddr[i])
- return i;
- return 1; // 1 is an invalid entry in the interrupt table on LPC2368
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARM7_CORE_H__ */
-
-/*lint -restore */
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on core_cm3.h, V1.20
+ */
+
+#ifndef __ARM7_CORE_H__
+#define __ARM7_CORE_H__
+
+#include "vector_defns.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+#include <stdint.h> /* Include standard types */
+
+#if defined ( __CC_ARM )
+/**
+ * @brief Return the Main Stack Pointer (current ARM7 stack)
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+#endif
+
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+typedef struct
+{
+ uint32_t IRQStatus;
+ uint32_t FIQStatus;
+ uint32_t RawIntr;
+ uint32_t IntSelect;
+ uint32_t IntEnable;
+ uint32_t IntEnClr;
+ uint32_t SoftInt;
+ uint32_t SoftIntClr;
+ uint32_t Protection;
+ uint32_t SWPriorityMask;
+ uint32_t RESERVED0[54];
+ uint32_t VectAddr[32];
+ uint32_t RESERVED1[32];
+ uint32_t VectPriority[32];
+ uint32_t RESERVED2[800];
+ uint32_t Address;
+} NVIC_TypeDef;
+
+#define NVIC_BASE (0xFFFFF000)
+#define NVIC (( NVIC_TypeDef *) NVIC_BASE)
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define __I volatile /*!< defines 'read only' permissions */
+#else
+#define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+//#define __WFI __wfi
+//#define __WFE __wfe
+//#define __SEV __sev
+//#define __ISB() __isb(0)
+//#define __DSB() __dsb(0)
+//#define __DMB() __dmb(0)
+//#define __REV __rev
+//#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+#define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
+ LPC_VIC->IntEnClr = 0xffffffff
+
+#define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+static __INLINE void __enable_irq() {
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "bic %0, %0, #0x80\n"
+ "msr cpsr_c, %0"
+ : "=r" (temp)
+ :
+ : "memory");
+}
+
+static __INLINE void __disable_irq() {
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+ "orr %1, %0, #0xc0\n"
+ "msr cpsr_c, %1"
+ : "=r" (old), "=r" (temp)
+ :
+ : "memory");
+ // return (old & 0x80) == 0;
+}
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnable = 1 << (uint32_t)IRQn;
+}
+
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->IntEnClr = 1 << (uint32_t)IRQn;
+}
+
+static __INLINE uint32_t __get_IPSR(void)
+{
+ unsigned i;
+
+ for(i = 0; i < 32; i ++)
+ if(NVIC->Address == NVIC->VectAddr[i])
+ return i;
+ return 1; // 1 is an invalid entry in the interrupt table on LPC2368
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM7_CORE_H__ */
+
+/*lint -restore */
--- a/TARGET_LPC2368/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC2368/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,59 +1,59 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 1 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 1 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 1 - -#define DEVICE_RTC 1 - -#define DEVICE_ETHERNET 1 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 1 -#define DEVICE_LOCALFILESYSTEM 1 -#define DEVICE_ID_LENGTH 32 -#define DEVICE_MAC_OFFSET 20 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 1 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 1 + +#define DEVICE_RTC 1 + +#define DEVICE_ETHERNET 1 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 1 +#define DEVICE_LOCALFILESYSTEM 1 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_PATTERN 1 + +#include "objects.h" + +#endif
--- a/TARGET_LPC2368/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,78 +1,78 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t port;
- uint32_t pin;
- uint32_t ch;
-};
-
-struct port_s {
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_out;
- __I uint32_t *reg_in;
- PortName port;
- uint32_t mask;
-};
-
-struct pwmout_s {
- __IO uint32_t *MR;
- PWMName pwm;
-};
-
-struct serial_s {
- LPC_UART_TypeDef *uart;
- int index;
-};
-
-struct analogin_s {
- ADCName adc;
-};
-
-struct dac_s {
- DACName dac;
-};
-
-struct can_s {
- LPC_CAN_TypeDef *dev;
-};
-
-struct i2c_s {
- LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
- LPC_SSP_TypeDef *spi;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t port;
+ uint32_t pin;
+ uint32_t ch;
+};
+
+struct port_s {
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_out;
+ __I uint32_t *reg_in;
+ PortName port;
+ uint32_t mask;
+};
+
+struct pwmout_s {
+ __IO uint32_t *MR;
+ PWMName pwm;
+};
+
+struct serial_s {
+ LPC_UART_TypeDef *uart;
+ int index;
+};
+
+struct analogin_s {
+ ADCName adc;
+};
+
+struct dac_s {
+ DACName dac;
+};
+
+struct can_s {
+ LPC_CAN_TypeDef *dev;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SSP_TypeDef *spi;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/system_LPC23xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC2368/system_LPC23xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,44 +1,44 @@
-/* mbed Microcontroller Library
- * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
- *
- * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
- * based on cmsis system_LPC17xx.h
- */
-
-#ifndef __SYSTEM_LPC23xx_H
-#define __SYSTEM_LPC23xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
+ *
+ * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
+ * based on cmsis system_LPC17xx.h
+ */
+
+#ifndef __SYSTEM_LPC23xx_H
+#define __SYSTEM_LPC23xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC2368/vector_defns.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC2368/vector_defns.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,77 +1,77 @@ -/* mbed Microcontroller Library - Vectors - * Copyright (c) 2006-2009 ARM Limited. All rights reserved. - */ - -#ifndef MBED_VECTOR_DEFNS_H -#define MBED_VECTOR_DEFNS_H - -// Assember Macros -#ifdef __ARMCC_VERSION -#define EXPORT(x) EXPORT x -#define WEAK_EXPORT(x) EXPORT x [WEAK] -#define IMPORT(x) IMPORT x -#define LABEL(x) x -#else -#define EXPORT(x) .global x -#define WEAK_EXPORT(x) .weak x -#define IMPORT(x) .global x -#define LABEL(x) x: -#endif - -// RealMonitor -// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker - -// RealMonitor entry points -#define rm_init_entry 0x7fffff91 -#define rm_undef_handler 0x7fffffa0 -#define rm_prefetchabort_handler 0x7fffffb0 -#define rm_dataabort_handler 0x7fffffc0 -#define rm_irqhandler2 0x7fffffe0 -//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 -#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 - -// Unofficial RealMonitor entry points and variables -#define RM_MSG_SWI 0x00940000 -#define StateP 0x40000040 - -// VIC register addresses -#define VIC_Base 0xfffff000 -#define VICAddress_Offset 0xf00 -#define VICVectAddr0_Offset 0x100 -#define VICVectAddr2_Offset 0x108 -#define VICVectAddr3_Offset 0x10c -#define VICVectAddr31_Offset 0x17c -#define VICIntEnClr_Offset 0x014 -#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) -#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) -#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) - -// ARM Mode bits and Interrupt flags in PSRs -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F -#define I_Bit 0x80 // when I bit is set, IRQ is disabled -#define F_Bit 0x40 // when F bit is set, FIQ is disabled - -// MCU RAM -#define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base -#define LPC2368_RAM_SIZE 0x8000 // 32KB - -// ISR Stack Allocation -#define UND_stack_size 0x00000040 -#define SVC_stack_size 0x00000040 -#define ABT_stack_size 0x00000040 -#define FIQ_stack_size 0x00000000 -#define IRQ_stack_size 0x00000040 - -#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) - -// Full Descending Stack, so top-most stack points to just above the top of RAM -#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE) -#define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size) - -#endif +/* mbed Microcontroller Library - Vectors + * Copyright (c) 2006-2009 ARM Limited. All rights reserved. + */ + +#ifndef MBED_VECTOR_DEFNS_H +#define MBED_VECTOR_DEFNS_H + +// Assember Macros +#ifdef __ARMCC_VERSION +#define EXPORT(x) EXPORT x +#define WEAK_EXPORT(x) EXPORT x [WEAK] +#define IMPORT(x) IMPORT x +#define LABEL(x) x +#else +#define EXPORT(x) .global x +#define WEAK_EXPORT(x) .weak x +#define IMPORT(x) .global x +#define LABEL(x) x: +#endif + +// RealMonitor +// Requires RAM (0x40000040-0x4000011F) to be allocated by the linker + +// RealMonitor entry points +#define rm_init_entry 0x7fffff91 +#define rm_undef_handler 0x7fffffa0 +#define rm_prefetchabort_handler 0x7fffffb0 +#define rm_dataabort_handler 0x7fffffc0 +#define rm_irqhandler2 0x7fffffe0 +//#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 +#define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 + +// Unofficial RealMonitor entry points and variables +#define RM_MSG_SWI 0x00940000 +#define StateP 0x40000040 + +// VIC register addresses +#define VIC_Base 0xfffff000 +#define VICAddress_Offset 0xf00 +#define VICVectAddr0_Offset 0x100 +#define VICVectAddr2_Offset 0x108 +#define VICVectAddr3_Offset 0x10c +#define VICVectAddr31_Offset 0x17c +#define VICIntEnClr_Offset 0x014 +#define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) + +// ARM Mode bits and Interrupt flags in PSRs +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F +#define I_Bit 0x80 // when I bit is set, IRQ is disabled +#define F_Bit 0x40 // when F bit is set, FIQ is disabled + +// MCU RAM +#define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base +#define LPC2368_RAM_SIZE 0x8000 // 32KB + +// ISR Stack Allocation +#define UND_stack_size 0x00000040 +#define SVC_stack_size 0x00000040 +#define ABT_stack_size 0x00000040 +#define FIQ_stack_size 0x00000000 +#define IRQ_stack_size 0x00000040 + +#define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) + +// Full Descending Stack, so top-most stack points to just above the top of RAM +#define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE) +#define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size) + +#endif
--- a/TARGET_LPC4088/LPC407x_8x_177x_8x.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/LPC407x_8x_177x_8x.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,1521 +1,1521 @@
-/****************************************************************************************************//**
-* $Id$ LPC407x_8x_177x_8x.h 2012-04-25
-*//**
- * @file LPC407x_8x_177x_8x.h
- *
- * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
- * NXP LPC407x_8x_177x_8x.
- * @version V0.7
- * @date 20. June 2012
- * @author NXP MCU SW Application Team
-*
-* Copyright(C) 2012, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers. This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __LPC407x_8x_177x_8x_H__
-#define __LPC407x_8x_177x_8x_H__
-
-#define CORE_M4
-
-// ##################
-// Code Red - excluded extern "C" as unrequired
-// ##################
-#if 0
-#ifdef __cplusplus
-extern "C" {
-#endif
-#endif
-
-
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum IRQn
-{
-/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
- WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
- TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
- TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
- TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
- TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
- UART0_IRQn = 5, /*!< UART0 Interrupt */
- UART1_IRQn = 6, /*!< UART1 Interrupt */
- UART2_IRQn = 7, /*!< UART2 Interrupt */
- UART3_IRQn = 8, /*!< UART3 Interrupt */
- PWM1_IRQn = 9, /*!< PWM1 Interrupt */
- I2C0_IRQn = 10, /*!< I2C0 Interrupt */
- I2C1_IRQn = 11, /*!< I2C1 Interrupt */
- I2C2_IRQn = 12, /*!< I2C2 Interrupt */
- Reserved0_IRQn = 13, /*!< Reserved */
- SSP0_IRQn = 14, /*!< SSP0 Interrupt */
- SSP1_IRQn = 15, /*!< SSP1 Interrupt */
- PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
- RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
- EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
- EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
- EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
- EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
- ADC_IRQn = 22, /*!< A/D Converter Interrupt */
- BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
- USB_IRQn = 24, /*!< USB Interrupt */
- CAN_IRQn = 25, /*!< CAN Interrupt */
- DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
- I2S_IRQn = 27, /*!< I2S Interrupt */
- ENET_IRQn = 28, /*!< Ethernet Interrupt */
- MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
- MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
- QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
- PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
- USBActivity_IRQn = 33, /*!< USB Activity interrupt */
- CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
- UART4_IRQn = 35, /*!< UART4 Interrupt */
- SSP2_IRQn = 36, /*!< SSP2 Interrupt */
- LCD_IRQn = 37, /*!< LCD Interrupt */
- GPIO_IRQn = 38, /*!< GPIO Interrupt */
- PWM0_IRQn = 39, /*!< 39 PWM0 */
- EEPROM_IRQn = 40, /*!< 40 EEPROM */
- CMP0_IRQn = 41, /*!< 41 CMP0 */
- CMP1_IRQn = 42 /*!< 42 CMP1 */
-} IRQn_Type;
-
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-#ifdef CORE_M4
-/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
-#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-
-
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-#else
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
-
-#endif
-
-#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
-
-
-
-
-
-
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct /* Common Registers */
-{
- __I uint32_t IntStat;
- __I uint32_t IntTCStat;
- __O uint32_t IntTCClear;
- __I uint32_t IntErrStat;
- __O uint32_t IntErrClr;
- __I uint32_t RawIntTCStat;
- __I uint32_t RawIntErrStat;
- __I uint32_t EnbldChns;
- __IO uint32_t SoftBReq;
- __IO uint32_t SoftSReq;
- __IO uint32_t SoftLBReq;
- __IO uint32_t SoftLSReq;
- __IO uint32_t Config;
- __IO uint32_t Sync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct /* Channel Registers */
-{
- __IO uint32_t CSrcAddr;
- __IO uint32_t CDestAddr;
- __IO uint32_t CLLI;
- __IO uint32_t CControl;
- __IO uint32_t CConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
- __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
- uint32_t RESERVED0[31];
- __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
- __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
- __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
- __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
- uint32_t RESERVED1[4];
- __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
- __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
- __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
- __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
- uint32_t RESERVED2[4];
- __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
- __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
- __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
- uint32_t RESERVED3[13];
- __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
- __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
- __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
- __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
- __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
- __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
- uint32_t RESERVED4[10];
- __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
- uint32_t RESERVED5[1];
- __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
- __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
- uint32_t RESERVED6[12];
- __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
- uint32_t RESERVED7[7];
- __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
- __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
- __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
- uint32_t RESERVED8;
- __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
- __IO uint32_t SPIFICLKSEL;
- __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
- uint32_t RESERVED10[1];
- __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
- __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
- __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
- __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
- __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
- uint32_t RESERVED11[2];
- __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
- __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
- } LPC_SC_TypeDef;
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
- __IO uint32_t MAC1; /* MAC Registers */
- __IO uint32_t MAC2;
- __IO uint32_t IPGT;
- __IO uint32_t IPGR;
- __IO uint32_t CLRT;
- __IO uint32_t MAXF;
- __IO uint32_t SUPP;
- __IO uint32_t TEST;
- __IO uint32_t MCFG;
- __IO uint32_t MCMD;
- __IO uint32_t MADR;
- __O uint32_t MWTD;
- __I uint32_t MRDD;
- __I uint32_t MIND;
- uint32_t RESERVED0[2];
- __IO uint32_t SA0;
- __IO uint32_t SA1;
- __IO uint32_t SA2;
- uint32_t RESERVED1[45];
- __IO uint32_t Command; /* Control Registers */
- __I uint32_t Status;
- __IO uint32_t RxDescriptor;
- __IO uint32_t RxStatus;
- __IO uint32_t RxDescriptorNumber;
- __I uint32_t RxProduceIndex;
- __IO uint32_t RxConsumeIndex;
- __IO uint32_t TxDescriptor;
- __IO uint32_t TxStatus;
- __IO uint32_t TxDescriptorNumber;
- __IO uint32_t TxProduceIndex;
- __I uint32_t TxConsumeIndex;
- uint32_t RESERVED2[10];
- __I uint32_t TSV0;
- __I uint32_t TSV1;
- __I uint32_t RSV;
- uint32_t RESERVED3[3];
- __IO uint32_t FlowControlCounter;
- __I uint32_t FlowControlStatus;
- uint32_t RESERVED4[34];
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
- __I uint32_t RxFilterWoLStatus;
- __O uint32_t RxFilterWoLClear;
- uint32_t RESERVED5;
- __IO uint32_t HashFilterL;
- __IO uint32_t HashFilterH;
- uint32_t RESERVED6[882];
- __I uint32_t IntStatus; /* Module Control Registers */
- __IO uint32_t IntEnable;
- __O uint32_t IntClear;
- __O uint32_t IntSet;
- uint32_t RESERVED7;
- __IO uint32_t PowerDown;
- uint32_t RESERVED8;
- __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-/*------------- LCD controller (LCD) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t TIMH; /* LCD Registers */
- __IO uint32_t TIMV;
- __IO uint32_t POL;
- __IO uint32_t LE;
- __IO uint32_t UPBASE;
- __IO uint32_t LPBASE;
- __IO uint32_t CTRL;
- __IO uint32_t INTMSK;
- __I uint32_t INTRAW;
- __I uint32_t INTSTAT;
- __O uint32_t INTCLR;
- __I uint32_t UPCURR;
- __I uint32_t LPCURR;
- uint32_t RESERVED0[115];
- __IO uint32_t PAL[128];
- uint32_t RESERVED1[256];
- __IO uint32_t CRSR_IMG[256];
- __IO uint32_t CRSR_CTRL;
- __IO uint32_t CRSR_CFG;
- __IO uint32_t CRSR_PAL0;
- __IO uint32_t CRSR_PAL1;
- __IO uint32_t CRSR_XY;
- __IO uint32_t CRSR_CLIP;
- uint32_t RESERVED2[2];
- __IO uint32_t CRSR_INTMSK;
- __O uint32_t CRSR_INTCLR;
- __I uint32_t CRSR_INTRAW;
- __I uint32_t CRSR_INTSTAT;
-} LPC_LCD_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
- __I uint32_t Revision; /* USB Host Registers */
- __IO uint32_t Control;
- __IO uint32_t CommandStatus;
- __IO uint32_t InterruptStatus;
- __IO uint32_t InterruptEnable;
- __IO uint32_t InterruptDisable;
- __IO uint32_t HCCA;
- __I uint32_t PeriodCurrentED;
- __IO uint32_t ControlHeadED;
- __IO uint32_t ControlCurrentED;
- __IO uint32_t BulkHeadED;
- __IO uint32_t BulkCurrentED;
- __I uint32_t DoneHead;
- __IO uint32_t FmInterval;
- __I uint32_t FmRemaining;
- __I uint32_t FmNumber;
- __IO uint32_t PeriodicStart;
- __IO uint32_t LSTreshold;
- __IO uint32_t RhDescriptorA;
- __IO uint32_t RhDescriptorB;
- __IO uint32_t RhStatus;
- __IO uint32_t RhPortStatus1;
- __IO uint32_t RhPortStatus2;
- uint32_t RESERVED0[40];
- __I uint32_t Module_ID;
-
- __I uint32_t IntSt; /* USB On-The-Go Registers */
- __IO uint32_t IntEn;
- __O uint32_t IntSet;
- __O uint32_t IntClr;
- __IO uint32_t StCtrl;
- __IO uint32_t Tmr;
- uint32_t RESERVED1[58];
-
- __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
- __IO uint32_t DevIntEn;
- __O uint32_t DevIntClr;
- __O uint32_t DevIntSet;
-
- __O uint32_t CmdCode; /* USB Device SIE Command Registers */
- __I uint32_t CmdData;
-
- __I uint32_t RxData; /* USB Device Transfer Registers */
- __O uint32_t TxData;
- __I uint32_t RxPLen;
- __O uint32_t TxPLen;
- __IO uint32_t Ctrl;
- __O uint32_t DevIntPri;
-
- __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
- __IO uint32_t EpIntEn;
- __O uint32_t EpIntClr;
- __O uint32_t EpIntSet;
- __O uint32_t EpIntPri;
-
- __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
- __O uint32_t EpInd;
- __IO uint32_t MaxPSize;
-
- __I uint32_t DMARSt; /* USB Device DMA Registers */
- __O uint32_t DMARClr;
- __O uint32_t DMARSet;
- uint32_t RESERVED2[9];
- __IO uint32_t UDCAH;
- __I uint32_t EpDMASt;
- __O uint32_t EpDMAEn;
- __O uint32_t EpDMADis;
- __I uint32_t DMAIntSt;
- __IO uint32_t DMAIntEn;
- uint32_t RESERVED3[2];
- __I uint32_t EoTIntSt;
- __O uint32_t EoTIntClr;
- __O uint32_t EoTIntSet;
- __I uint32_t NDDRIntSt;
- __O uint32_t NDDRIntClr;
- __O uint32_t NDDRIntSet;
- __I uint32_t SysErrIntSt;
- __O uint32_t SysErrIntClr;
- __O uint32_t SysErrIntSet;
- uint32_t RESERVED4[15];
-
- union {
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */
- __O uint32_t I2C_TX;
- };
- __IO uint32_t I2C_STS;
- __IO uint32_t I2C_CTL;
- __IO uint32_t I2C_CLKHI;
- __O uint32_t I2C_CLKLO;
- uint32_t RESERVED5[824];
-
- union {
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
- __IO uint32_t OTGClkCtrl;
- };
- union {
- __I uint32_t USBClkSt;
- __I uint32_t OTGClkSt;
- };
-} LPC_USB_TypeDef;
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t MODE;
- __IO uint32_t SEED;
- union {
- __I uint32_t SUM;
- struct {
- __O uint32_t DATA;
- } WR_DATA_DWORD;
-
- struct {
- __O uint16_t DATA;
- uint16_t RESERVED;
- }WR_DATA_WORD;
-
- struct {
- __O uint8_t DATA;
- uint8_t RESERVED[3];
- }WR_DATA_BYTE;
- };
-} LPC_CRC_TypeDef;
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
- __IO uint32_t DIR;
- uint32_t RESERVED0[3];
- __IO uint32_t MASK;
- __IO uint32_t PIN;
- __IO uint32_t SET;
- __O uint32_t CLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
- __I uint32_t IntStatus;
- __I uint32_t IO0IntStatR;
- __I uint32_t IO0IntStatF;
- __O uint32_t IO0IntClr;
- __IO uint32_t IO0IntEnR;
- __IO uint32_t IO0IntEnF;
- uint32_t RESERVED0[3];
- __I uint32_t IO2IntStatR;
- __I uint32_t IO2IntStatF;
- __O uint32_t IO2IntClr;
- __IO uint32_t IO2IntEnR;
- __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- External Memory Controller (EMC) -----------------------------*/
-typedef struct
-{
- __IO uint32_t Control;
- __I uint32_t Status;
- __IO uint32_t Config;
- uint32_t RESERVED0[5];
- __IO uint32_t DynamicControl;
- __IO uint32_t DynamicRefresh;
- __IO uint32_t DynamicReadConfig;
- uint32_t RESERVED1[1];
- __IO uint32_t DynamicRP;
- __IO uint32_t DynamicRAS;
- __IO uint32_t DynamicSREX;
- __IO uint32_t DynamicAPR;
- __IO uint32_t DynamicDAL;
- __IO uint32_t DynamicWR;
- __IO uint32_t DynamicRC;
- __IO uint32_t DynamicRFC;
- __IO uint32_t DynamicXSR;
- __IO uint32_t DynamicRRD;
- __IO uint32_t DynamicMRD;
- uint32_t RESERVED2[9];
- __IO uint32_t StaticExtendedWait;
- uint32_t RESERVED3[31];
- __IO uint32_t DynamicConfig0;
- __IO uint32_t DynamicRasCas0;
- uint32_t RESERVED4[6];
- __IO uint32_t DynamicConfig1;
- __IO uint32_t DynamicRasCas1;
- uint32_t RESERVED5[6];
- __IO uint32_t DynamicConfig2;
- __IO uint32_t DynamicRasCas2;
- uint32_t RESERVED6[6];
- __IO uint32_t DynamicConfig3;
- __IO uint32_t DynamicRasCas3;
- uint32_t RESERVED7[38];
- __IO uint32_t StaticConfig0;
- __IO uint32_t StaticWaitWen0;
- __IO uint32_t StaticWaitOen0;
- __IO uint32_t StaticWaitRd0;
- __IO uint32_t StaticWaitPage0;
- __IO uint32_t StaticWaitWr0;
- __IO uint32_t StaticWaitTurn0;
- uint32_t RESERVED8[1];
- __IO uint32_t StaticConfig1;
- __IO uint32_t StaticWaitWen1;
- __IO uint32_t StaticWaitOen1;
- __IO uint32_t StaticWaitRd1;
- __IO uint32_t StaticWaitPage1;
- __IO uint32_t StaticWaitWr1;
- __IO uint32_t StaticWaitTurn1;
- uint32_t RESERVED9[1];
- __IO uint32_t StaticConfig2;
- __IO uint32_t StaticWaitWen2;
- __IO uint32_t StaticWaitOen2;
- __IO uint32_t StaticWaitRd2;
- __IO uint32_t StaticWaitPage2;
- __IO uint32_t StaticWaitWr2;
- __IO uint32_t StaticWaitTurn2;
- uint32_t RESERVED10[1];
- __IO uint32_t StaticConfig3;
- __IO uint32_t StaticWaitWen3;
- __IO uint32_t StaticWaitOen3;
- __IO uint32_t StaticWaitRd3;
- __IO uint32_t StaticWaitPage3;
- __IO uint32_t StaticWaitWr3;
- __IO uint32_t StaticWaitTurn3;
-} LPC_EMC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
- __IO uint8_t MOD;
- uint8_t RESERVED0[3];
- __IO uint32_t TC;
- __O uint8_t FEED;
- uint8_t RESERVED1[3];
- __I uint32_t TV;
- uint32_t RESERVED2;
- __IO uint32_t WARNINT;
- __IO uint32_t WINDOW;
-} LPC_WDT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
- __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
- __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
- __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
- __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
- __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
- __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
- __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
- __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
- __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
- __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
- __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
- __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
- __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
- uint32_t RESERVED0[2];
- __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
- uint32_t RESERVED1[12];
- __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
-} LPC_TIM_TypeDef;
-
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
- __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
- __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
- __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
- __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
- __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
- __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
- __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
- __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
- __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
- __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
- __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
- __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
- __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
- __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
- __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
- uint32_t RESERVED0;
- __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
- __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
- __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
- __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
- __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
- uint32_t RESERVED1[7];
- __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
-/* There are three types of UARTs on the chip:
-(1) UART0,UART2, and UART3 are the standard UART.
-(2) UART1 is the standard with modem capability.
-(3) USART(UART4) is the sync/async UART with smart card capability.
-More details can be found on the Users Manual. */
-
-#if 0
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[7];
- __I uint8_t LSR;
- uint8_t RESERVED2[7];
- __IO uint8_t SCR;
- uint8_t RESERVED3[3];
- __IO uint32_t ACR;
- __IO uint8_t ICR;
- uint8_t RESERVED4[3];
- __IO uint8_t FDR;
- uint8_t RESERVED5[7];
- __IO uint8_t TER;
- uint8_t RESERVED6[39];
- __I uint8_t FIFOLVL;
-} LPC_UART_TypeDef;
-#else
-typedef struct
-{
- union
- {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union
- {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union
- {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[7];//Reserved
- __I uint8_t LSR;
- uint8_t RESERVED2[7];//Reserved
- __IO uint8_t SCR;
- uint8_t RESERVED3[3];//Reserved
- __IO uint32_t ACR;
- __IO uint8_t ICR;
- uint8_t RESERVED4[3];//Reserved
- __IO uint8_t FDR;
- uint8_t RESERVED5[7];//Reserved
- __IO uint8_t TER;
- uint8_t RESERVED8[27];//Reserved
- __IO uint8_t RS485CTRL;
- uint8_t RESERVED9[3];//Reserved
- __IO uint8_t ADRMATCH;
- uint8_t RESERVED10[3];//Reserved
- __IO uint8_t RS485DLY;
- uint8_t RESERVED11[3];//Reserved
- __I uint8_t FIFOLVL;
-}LPC_UART_TypeDef;
-#endif
-
-
-typedef struct
-{
- union {
- __I uint8_t RBR;
- __O uint8_t THR;
- __IO uint8_t DLL;
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint8_t FCR;
- };
- __IO uint8_t LCR;
- uint8_t RESERVED1[3];
- __IO uint8_t MCR;
- uint8_t RESERVED2[3];
- __I uint8_t LSR;
- uint8_t RESERVED3[3];
- __I uint8_t MSR;
- uint8_t RESERVED4[3];
- __IO uint8_t SCR;
- uint8_t RESERVED5[3];
- __IO uint32_t ACR;
- uint32_t RESERVED6;
- __IO uint32_t FDR;
- uint32_t RESERVED7;
- __IO uint8_t TER;
- uint8_t RESERVED8[27];
- __IO uint8_t RS485CTRL;
- uint8_t RESERVED9[3];
- __IO uint8_t ADRMATCH;
- uint8_t RESERVED10[3];
- __IO uint8_t RS485DLY;
- uint8_t RESERVED11[3];
- __I uint8_t FIFOLVL;
-} LPC_UART1_TypeDef;
-
-typedef struct
-{
- union {
- __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
- __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
- __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
- };
- union {
- __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
- __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
- };
- union {
- __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
- __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
- };
- __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
- __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
- __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
- __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
- __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
- __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
- __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
- __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
- __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
- __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
- __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
- uint32_t RESERVED0[2];
- __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
- uint32_t RESERVED1;
- __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
- __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
- __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
- __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
- __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
- __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
- uint32_t RESERVED2[989];
- __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
- __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
- __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
- __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
- __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
- __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
- __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
- uint32_t RESERVED3[3];
- __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
-} LPC_UART4_TypeDef;
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
- __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
- __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
- __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
- __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
- __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
- __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
- __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
- __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
- __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
- __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
- __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
- __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
- __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
- __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
- __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
- __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
- __IO uint8_t ILR;
- uint8_t RESERVED0[7];
- __IO uint8_t CCR;
- uint8_t RESERVED1[3];
- __IO uint8_t CIIR;
- uint8_t RESERVED2[3];
- __IO uint8_t AMR;
- uint8_t RESERVED3[3];
- __I uint32_t CTIME0;
- __I uint32_t CTIME1;
- __I uint32_t CTIME2;
- __IO uint8_t SEC;
- uint8_t RESERVED4[3];
- __IO uint8_t MIN;
- uint8_t RESERVED5[3];
- __IO uint8_t HOUR;
- uint8_t RESERVED6[3];
- __IO uint8_t DOM;
- uint8_t RESERVED7[3];
- __IO uint8_t DOW;
- uint8_t RESERVED8[3];
- __IO uint16_t DOY;
- uint16_t RESERVED9;
- __IO uint8_t MONTH;
- uint8_t RESERVED10[3];
- __IO uint16_t YEAR;
- uint16_t RESERVED11;
- __IO uint32_t CALIBRATION;
- __IO uint32_t GPREG0;
- __IO uint32_t GPREG1;
- __IO uint32_t GPREG2;
- __IO uint32_t GPREG3;
- __IO uint32_t GPREG4;
- __IO uint8_t RTC_AUXEN;
- uint8_t RESERVED12[3];
- __IO uint8_t RTC_AUX;
- uint8_t RESERVED13[3];
- __IO uint8_t ALSEC;
- uint8_t RESERVED14[3];
- __IO uint8_t ALMIN;
- uint8_t RESERVED15[3];
- __IO uint8_t ALHOUR;
- uint8_t RESERVED16[3];
- __IO uint8_t ALDOM;
- uint8_t RESERVED17[3];
- __IO uint8_t ALDOW;
- uint8_t RESERVED18[3];
- __IO uint16_t ALDOY;
- uint16_t RESERVED19;
- __IO uint8_t ALMON;
- uint8_t RESERVED20[3];
- __IO uint16_t ALYEAR;
- uint16_t RESERVED21;
- __IO uint32_t ERSTATUS;
- __IO uint32_t ERCONTROL;
- __IO uint32_t ERCOUNTERS;
- uint32_t RESERVED22;
- __IO uint32_t ERFIRSTSTAMP0;
- __IO uint32_t ERFIRSTSTAMP1;
- __IO uint32_t ERFIRSTSTAMP2;
- uint32_t RESERVED23;
- __IO uint32_t ERLASTSTAMP0;
- __IO uint32_t ERLASTSTAMP1;
- __IO uint32_t ERLASTSTAMP2;
-} LPC_RTC_TypeDef;
-
-
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
- __IO uint32_t P0_0; /* 0x000 */
- __IO uint32_t P0_1;
- __IO uint32_t P0_2;
- __IO uint32_t P0_3;
- __IO uint32_t P0_4;
- __IO uint32_t P0_5;
- __IO uint32_t P0_6;
- __IO uint32_t P0_7;
-
- __IO uint32_t P0_8; /* 0x020 */
- __IO uint32_t P0_9;
- __IO uint32_t P0_10;
- __IO uint32_t P0_11;
- __IO uint32_t P0_12;
- __IO uint32_t P0_13;
- __IO uint32_t P0_14;
- __IO uint32_t P0_15;
-
- __IO uint32_t P0_16; /* 0x040 */
- __IO uint32_t P0_17;
- __IO uint32_t P0_18;
- __IO uint32_t P0_19;
- __IO uint32_t P0_20;
- __IO uint32_t P0_21;
- __IO uint32_t P0_22;
- __IO uint32_t P0_23;
-
- __IO uint32_t P0_24; /* 0x060 */
- __IO uint32_t P0_25;
- __IO uint32_t P0_26;
- __IO uint32_t P0_27;
- __IO uint32_t P0_28;
- __IO uint32_t P0_29;
- __IO uint32_t P0_30;
- __IO uint32_t P0_31;
-
- __IO uint32_t P1_0; /* 0x080 */
- __IO uint32_t P1_1;
- __IO uint32_t P1_2;
- __IO uint32_t P1_3;
- __IO uint32_t P1_4;
- __IO uint32_t P1_5;
- __IO uint32_t P1_6;
- __IO uint32_t P1_7;
-
- __IO uint32_t P1_8; /* 0x0A0 */
- __IO uint32_t P1_9;
- __IO uint32_t P1_10;
- __IO uint32_t P1_11;
- __IO uint32_t P1_12;
- __IO uint32_t P1_13;
- __IO uint32_t P1_14;
- __IO uint32_t P1_15;
-
- __IO uint32_t P1_16; /* 0x0C0 */
- __IO uint32_t P1_17;
- __IO uint32_t P1_18;
- __IO uint32_t P1_19;
- __IO uint32_t P1_20;
- __IO uint32_t P1_21;
- __IO uint32_t P1_22;
- __IO uint32_t P1_23;
-
- __IO uint32_t P1_24; /* 0x0E0 */
- __IO uint32_t P1_25;
- __IO uint32_t P1_26;
- __IO uint32_t P1_27;
- __IO uint32_t P1_28;
- __IO uint32_t P1_29;
- __IO uint32_t P1_30;
- __IO uint32_t P1_31;
-
- __IO uint32_t P2_0; /* 0x100 */
- __IO uint32_t P2_1;
- __IO uint32_t P2_2;
- __IO uint32_t P2_3;
- __IO uint32_t P2_4;
- __IO uint32_t P2_5;
- __IO uint32_t P2_6;
- __IO uint32_t P2_7;
-
- __IO uint32_t P2_8; /* 0x120 */
- __IO uint32_t P2_9;
- __IO uint32_t P2_10;
- __IO uint32_t P2_11;
- __IO uint32_t P2_12;
- __IO uint32_t P2_13;
- __IO uint32_t P2_14;
- __IO uint32_t P2_15;
-
- __IO uint32_t P2_16; /* 0x140 */
- __IO uint32_t P2_17;
- __IO uint32_t P2_18;
- __IO uint32_t P2_19;
- __IO uint32_t P2_20;
- __IO uint32_t P2_21;
- __IO uint32_t P2_22;
- __IO uint32_t P2_23;
-
- __IO uint32_t P2_24; /* 0x160 */
- __IO uint32_t P2_25;
- __IO uint32_t P2_26;
- __IO uint32_t P2_27;
- __IO uint32_t P2_28;
- __IO uint32_t P2_29;
- __IO uint32_t P2_30;
- __IO uint32_t P2_31;
-
- __IO uint32_t P3_0; /* 0x180 */
- __IO uint32_t P3_1;
- __IO uint32_t P3_2;
- __IO uint32_t P3_3;
- __IO uint32_t P3_4;
- __IO uint32_t P3_5;
- __IO uint32_t P3_6;
- __IO uint32_t P3_7;
-
- __IO uint32_t P3_8; /* 0x1A0 */
- __IO uint32_t P3_9;
- __IO uint32_t P3_10;
- __IO uint32_t P3_11;
- __IO uint32_t P3_12;
- __IO uint32_t P3_13;
- __IO uint32_t P3_14;
- __IO uint32_t P3_15;
-
- __IO uint32_t P3_16; /* 0x1C0 */
- __IO uint32_t P3_17;
- __IO uint32_t P3_18;
- __IO uint32_t P3_19;
- __IO uint32_t P3_20;
- __IO uint32_t P3_21;
- __IO uint32_t P3_22;
- __IO uint32_t P3_23;
-
- __IO uint32_t P3_24; /* 0x1E0 */
- __IO uint32_t P3_25;
- __IO uint32_t P3_26;
- __IO uint32_t P3_27;
- __IO uint32_t P3_28;
- __IO uint32_t P3_29;
- __IO uint32_t P3_30;
- __IO uint32_t P3_31;
-
- __IO uint32_t P4_0; /* 0x200 */
- __IO uint32_t P4_1;
- __IO uint32_t P4_2;
- __IO uint32_t P4_3;
- __IO uint32_t P4_4;
- __IO uint32_t P4_5;
- __IO uint32_t P4_6;
- __IO uint32_t P4_7;
-
- __IO uint32_t P4_8; /* 0x220 */
- __IO uint32_t P4_9;
- __IO uint32_t P4_10;
- __IO uint32_t P4_11;
- __IO uint32_t P4_12;
- __IO uint32_t P4_13;
- __IO uint32_t P4_14;
- __IO uint32_t P4_15;
-
- __IO uint32_t P4_16; /* 0x240 */
- __IO uint32_t P4_17;
- __IO uint32_t P4_18;
- __IO uint32_t P4_19;
- __IO uint32_t P4_20;
- __IO uint32_t P4_21;
- __IO uint32_t P4_22;
- __IO uint32_t P4_23;
-
- __IO uint32_t P4_24; /* 0x260 */
- __IO uint32_t P4_25;
- __IO uint32_t P4_26;
- __IO uint32_t P4_27;
- __IO uint32_t P4_28;
- __IO uint32_t P4_29;
- __IO uint32_t P4_30;
- __IO uint32_t P4_31;
-
- __IO uint32_t P5_0; /* 0x280 */
- __IO uint32_t P5_1;
- __IO uint32_t P5_2;
- __IO uint32_t P5_3;
- __IO uint32_t P5_4; /* 0x290 */
-} LPC_IOCON_TypeDef;
-
-
-
-
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
- __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
- __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
- __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
- __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
- __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
- __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
- __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
- __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
- __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
- __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
- __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
- uint32_t RESERVED0;
- __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
- __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
- __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
- __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
- __IO uint32_t mask[512]; /* ID Masks */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct /* Acceptance Filter Registers */
-{
- ///Offset: 0x00000000 - Acceptance Filter Register
- __IO uint32_t AFMR;
-
- ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
- __IO uint32_t SFF_sa;
-
- ///Offset: 0x00000008 - Standard Frame Group Start Address Register
- __IO uint32_t SFF_GRP_sa;
-
- ///Offset: 0x0000000C - Extended Frame Start Address Register
- __IO uint32_t EFF_sa;
-
- ///Offset: 0x00000010 - Extended Frame Group Start Address Register
- __IO uint32_t EFF_GRP_sa;
-
- ///Offset: 0x00000014 - End of AF Tables register
- __IO uint32_t ENDofTable;
-
- ///Offset: 0x00000018 - LUT Error Address register
- __I uint32_t LUTerrAd;
-
- ///Offset: 0x0000001C - LUT Error Register
- __I uint32_t LUTerr;
-
- ///Offset: 0x00000020 - CAN Central Transmit Status Register
- __IO uint32_t FCANIE;
-
- ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
- __IO uint32_t FCANIC0;
-
- ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
- __IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct /* Central Registers */
-{
- __I uint32_t TxSR;
- __I uint32_t RxSR;
- __I uint32_t MSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct /* Controller Registers */
-{
- ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
- __IO uint32_t MOD;
-
- ///Offset: 0x00000004 - Command bits that affect the state
- __O uint32_t CMR;
-
- ///Offset: 0x00000008 - Global Controller Status and Error Counters
- __IO uint32_t GSR;
-
- ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
- __I uint32_t ICR;
-
- ///Offset: 0x00000010 - Interrupt Enable Register
- __IO uint32_t IER;
-
- ///Offset: 0x00000014 - Bus Timing Register
- __IO uint32_t BTR;
-
- ///Offset: 0x00000018 - Error Warning Limit
- __IO uint32_t EWL;
-
- ///Offset: 0x0000001C - Status Register
- __I uint32_t SR;
-
- ///Offset: 0x00000020 - Receive frame status
- __IO uint32_t RFS;
-
- ///Offset: 0x00000024 - Received Identifier
- __IO uint32_t RID;
-
- ///Offset: 0x00000028 - Received data bytes 1-4
- __IO uint32_t RDA;
-
- ///Offset: 0x0000002C - Received data bytes 5-8
- __IO uint32_t RDB;
-
- ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
- __IO uint32_t TFI1;
-
- ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
- __IO uint32_t TID1;
-
- ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
- __IO uint32_t TDA1;
-
- ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
- __IO uint32_t TDB1;
-
- ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
- __IO uint32_t TFI2;
-
- ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
- __IO uint32_t TID2;
-
- ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
- __IO uint32_t TDA2;
-
- ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
- __IO uint32_t TDB2;
-
- ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
- __IO uint32_t TFI3;
-
- ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
- __IO uint32_t TID3;
-
- ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
- __IO uint32_t TDA3;
-
- ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
- __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CTRL;
- __IO uint32_t CNTVAL;
-} LPC_DAC_TypeDef;
-
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t DAO;
- __IO uint32_t DAI;
- __O uint32_t TXFIFO;
- __I uint32_t RXFIFO;
- __I uint32_t STATE;
- __IO uint32_t DMA1;
- __IO uint32_t DMA2;
- __IO uint32_t IRQ;
- __IO uint32_t TXRATE;
- __IO uint32_t RXRATE;
- __IO uint32_t TXBITRATE;
- __IO uint32_t RXBITRATE;
- __IO uint32_t TXMODE;
- __IO uint32_t RXMODE;
-} LPC_I2S_TypeDef;
-
-
-
-
-
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
- __I uint32_t CON;
- __O uint32_t CON_SET;
- __O uint32_t CON_CLR;
- __I uint32_t CAPCON;
- __O uint32_t CAPCON_SET;
- __O uint32_t CAPCON_CLR;
- __IO uint32_t TC0;
- __IO uint32_t TC1;
- __IO uint32_t TC2;
- __IO uint32_t LIM0;
- __IO uint32_t LIM1;
- __IO uint32_t LIM2;
- __IO uint32_t MAT0;
- __IO uint32_t MAT1;
- __IO uint32_t MAT2;
- __IO uint32_t DT;
- __IO uint32_t CP;
- __IO uint32_t CAP0;
- __IO uint32_t CAP1;
- __IO uint32_t CAP2;
- __I uint32_t INTEN;
- __O uint32_t INTEN_SET;
- __O uint32_t INTEN_CLR;
- __I uint32_t CNTCON;
- __O uint32_t CNTCON_SET;
- __O uint32_t CNTCON_CLR;
- __I uint32_t INTF;
- __O uint32_t INTF_SET;
- __O uint32_t INTF_CLR;
- __O uint32_t CAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
- __O uint32_t CON;
- __I uint32_t STAT;
- __IO uint32_t CONF;
- __I uint32_t POS;
- __IO uint32_t MAXPOS;
- __IO uint32_t CMPOS0;
- __IO uint32_t CMPOS1;
- __IO uint32_t CMPOS2;
- __I uint32_t INXCNT;
- __IO uint32_t INXCMP0;
- __IO uint32_t LOAD;
- __I uint32_t TIME;
- __I uint32_t VEL;
- __I uint32_t CAP;
- __IO uint32_t VELCOMP;
- __IO uint32_t FILTERPHA;
- __IO uint32_t FILTERPHB;
- __IO uint32_t FILTERINX;
- __IO uint32_t WINDOW;
- __IO uint32_t INXCMP1;
- __IO uint32_t INXCMP2;
- uint32_t RESERVED0[993];
- __O uint32_t IEC;
- __O uint32_t IES;
- __I uint32_t INTSTAT;
- __I uint32_t IE;
- __O uint32_t CLR;
- __O uint32_t SET;
-} LPC_QEI_TypeDef;
-
-/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
-typedef struct
-{
- __IO uint32_t POWER;
- __IO uint32_t CLOCK;
- __IO uint32_t ARGUMENT;
- __IO uint32_t COMMAND;
- __I uint32_t RESP_CMD;
- __I uint32_t RESP0;
- __I uint32_t RESP1;
- __I uint32_t RESP2;
- __I uint32_t RESP3;
- __IO uint32_t DATATMR;
- __IO uint32_t DATALEN;
- __IO uint32_t DATACTRL;
- __I uint32_t DATACNT;
- __I uint32_t STATUS;
- __O uint32_t CLEAR;
- __IO uint32_t MASK0;
- uint32_t RESERVED0[2];
- __I uint32_t FIFOCNT;
- uint32_t RESERVED1[13];
- __IO uint32_t FIFO[16];
-} LPC_MCI_TypeDef;
-
-
-
-
-
-
-
-
-
-
-/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
-typedef struct
-{
- __IO uint32_t CMD; /* 0x0080 */
- __IO uint32_t ADDR;
- __IO uint32_t WDATA;
- __IO uint32_t RDATA;
- __IO uint32_t WSTATE; /* 0x0090 */
- __IO uint32_t CLKDIV;
- __IO uint32_t PWRDWN; /* 0x0098 */
- uint32_t RESERVED0[975];
- __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
- __IO uint32_t INT_SET_ENABLE;
- __IO uint32_t INT_STATUS; /* 0x0FE0 */
- __IO uint32_t INT_ENABLE;
- __IO uint32_t INT_CLR_STATUS;
- __IO uint32_t INT_SET_STATUS;
-} LPC_EEPROM_TypeDef;
-
-
-/*------------- COMPARATOR ----------------------------------------------------*/
-
-typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
- __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
- __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
- __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
-} LPC_COMPARATOR_Type;
-
-
-#if defined ( __CC_ARM )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Base addresses */
-#define LPC_FLASH_BASE (0x00000000UL)
-#define LPC_RAM_BASE (0x10000000UL)
-#define LPC_PERI_RAM_BASE (0x20000000UL)
-#define LPC_APB0_BASE (0x40000000UL)
-#define LPC_APB1_BASE (0x40080000UL)
-#define LPC_AHBRAM1_BASE (0x20004000UL)
-#define LPC_AHB_BASE (0x20080000UL)
-#define LPC_CM3_BASE (0xE0000000UL)
-
-/* APB0 peripherals */
-#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
-#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
-#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
-#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals */
-#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
-#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
-#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
-#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
-#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
-#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
-#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals */
-#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
-#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
-#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
-#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
-#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
-#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
-#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
-#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
-#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
-#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
-#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
-#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
-#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
-#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
-#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
-#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
-#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
-#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
-#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
-#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
-
-#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
-
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
-#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
-#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
-#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
-#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
-#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
-#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
-#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
-#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
-#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
-#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
-#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
-#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
-#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
-#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
-#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
-#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
-#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
-#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
-#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
-#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
-#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
-#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
-#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
-#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
-#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
-#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
-#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
-#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
-#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
-#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
-#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
-#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
-#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
-#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
-#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
-#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
-#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
-#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
-#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
-#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
-#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
-#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
-#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
-#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
-#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
-#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
-
-
-
-#endif // __LPC407x_8x_177x_8x_H__
+/****************************************************************************************************//**
+* $Id$ LPC407x_8x_177x_8x.h 2012-04-25
+*//**
+ * @file LPC407x_8x_177x_8x.h
+ *
+ * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
+ * NXP LPC407x_8x_177x_8x.
+ * @version V0.7
+ * @date 20. June 2012
+ * @author NXP MCU SW Application Team
+*
+* Copyright(C) 2012, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __LPC407x_8x_177x_8x_H__
+#define __LPC407x_8x_177x_8x_H__
+
+#define CORE_M4
+
+// ##################
+// Code Red - excluded extern "C" as unrequired
+// ##################
+#if 0
+#ifdef __cplusplus
+extern "C" {
+#endif
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ Reserved0_IRQn = 13, /*!< Reserved */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /*!< USB Activity interrupt */
+ CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
+ UART4_IRQn = 35, /*!< UART4 Interrupt */
+ SSP2_IRQn = 36, /*!< SSP2 Interrupt */
+ LCD_IRQn = 37, /*!< LCD Interrupt */
+ GPIO_IRQn = 38, /*!< GPIO Interrupt */
+ PWM0_IRQn = 39, /*!< 39 PWM0 */
+ EEPROM_IRQn = 40, /*!< 40 EEPROM */
+ CMP0_IRQn = 41, /*!< 41 CMP0 */
+ CMP1_IRQn = 42 /*!< 42 CMP1 */
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+#ifdef CORE_M4
+/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
+#define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#else
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+
+#endif
+
+#include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+typedef struct /* Common Registers */
+{
+ __I uint32_t IntStat;
+ __I uint32_t IntTCStat;
+ __O uint32_t IntTCClear;
+ __I uint32_t IntErrStat;
+ __O uint32_t IntErrClr;
+ __I uint32_t RawIntTCStat;
+ __I uint32_t RawIntErrStat;
+ __I uint32_t EnbldChns;
+ __IO uint32_t SoftBReq;
+ __IO uint32_t SoftSReq;
+ __IO uint32_t SoftLBReq;
+ __IO uint32_t SoftLSReq;
+ __IO uint32_t Config;
+ __IO uint32_t Sync;
+} LPC_GPDMA_TypeDef;
+
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t CSrcAddr;
+ __IO uint32_t CDestAddr;
+ __IO uint32_t CLLI;
+ __IO uint32_t CControl;
+ __IO uint32_t CConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- System Control (SC) ------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
+ __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
+ __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
+ __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
+ __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
+ __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
+ __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
+ __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
+ __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
+ uint32_t RESERVED3[13];
+ __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
+ __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
+ __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
+ __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
+ __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
+ __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
+ uint32_t RESERVED5[1];
+ __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
+ __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
+ __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
+ __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
+ uint32_t RESERVED8;
+ __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
+ __IO uint32_t SPIFICLKSEL;
+ __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
+ uint32_t RESERVED10[1];
+ __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
+ __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
+ __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
+ __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
+ __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
+ uint32_t RESERVED11[2];
+ __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
+ __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
+ } LPC_SC_TypeDef;
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __I uint32_t RxFilterWoLStatus;
+ __O uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+/*------------- LCD controller (LCD) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t TIMH; /* LCD Registers */
+ __IO uint32_t TIMV;
+ __IO uint32_t POL;
+ __IO uint32_t LE;
+ __IO uint32_t UPBASE;
+ __IO uint32_t LPBASE;
+ __IO uint32_t CTRL;
+ __IO uint32_t INTMSK;
+ __I uint32_t INTRAW;
+ __I uint32_t INTSTAT;
+ __O uint32_t INTCLR;
+ __I uint32_t UPCURR;
+ __I uint32_t LPCURR;
+ uint32_t RESERVED0[115];
+ __IO uint32_t PAL[128];
+ uint32_t RESERVED1[256];
+ __IO uint32_t CRSR_IMG[256];
+ __IO uint32_t CRSR_CTRL;
+ __IO uint32_t CRSR_CFG;
+ __IO uint32_t CRSR_PAL0;
+ __IO uint32_t CRSR_PAL1;
+ __IO uint32_t CRSR_XY;
+ __IO uint32_t CRSR_CLIP;
+ uint32_t RESERVED2[2];
+ __IO uint32_t CRSR_INTMSK;
+ __O uint32_t CRSR_INTCLR;
+ __I uint32_t CRSR_INTRAW;
+ __I uint32_t CRSR_INTSTAT;
+} LPC_LCD_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+typedef struct
+{
+ __I uint32_t Revision; /* USB Host Registers */
+ __IO uint32_t Control;
+ __IO uint32_t CommandStatus;
+ __IO uint32_t InterruptStatus;
+ __IO uint32_t InterruptEnable;
+ __IO uint32_t InterruptDisable;
+ __IO uint32_t HCCA;
+ __I uint32_t PeriodCurrentED;
+ __IO uint32_t ControlHeadED;
+ __IO uint32_t ControlCurrentED;
+ __IO uint32_t BulkHeadED;
+ __IO uint32_t BulkCurrentED;
+ __I uint32_t DoneHead;
+ __IO uint32_t FmInterval;
+ __I uint32_t FmRemaining;
+ __I uint32_t FmNumber;
+ __IO uint32_t PeriodicStart;
+ __IO uint32_t LSTreshold;
+ __IO uint32_t RhDescriptorA;
+ __IO uint32_t RhDescriptorB;
+ __IO uint32_t RhStatus;
+ __IO uint32_t RhPortStatus1;
+ __IO uint32_t RhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t IntSt; /* USB On-The-Go Registers */
+ __IO uint32_t IntEn;
+ __O uint32_t IntSet;
+ __O uint32_t IntClr;
+ __IO uint32_t StCtrl;
+ __IO uint32_t Tmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t DevIntEn;
+ __O uint32_t DevIntClr;
+ __O uint32_t DevIntSet;
+
+ __O uint32_t CmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t CmdData;
+
+ __I uint32_t RxData; /* USB Device Transfer Registers */
+ __O uint32_t TxData;
+ __I uint32_t RxPLen;
+ __O uint32_t TxPLen;
+ __IO uint32_t Ctrl;
+ __O uint32_t DevIntPri;
+
+ __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t EpIntEn;
+ __O uint32_t EpIntClr;
+ __O uint32_t EpIntSet;
+ __O uint32_t EpIntPri;
+
+ __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t EpInd;
+ __IO uint32_t MaxPSize;
+
+ __I uint32_t DMARSt; /* USB Device DMA Registers */
+ __O uint32_t DMARClr;
+ __O uint32_t DMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t UDCAH;
+ __I uint32_t EpDMASt;
+ __O uint32_t EpDMAEn;
+ __O uint32_t EpDMADis;
+ __I uint32_t DMAIntSt;
+ __IO uint32_t DMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t EoTIntSt;
+ __O uint32_t EoTIntClr;
+ __O uint32_t EoTIntSet;
+ __I uint32_t NDDRIntSt;
+ __O uint32_t NDDRIntClr;
+ __O uint32_t NDDRIntSet;
+ __I uint32_t SysErrIntSt;
+ __O uint32_t SysErrIntClr;
+ __O uint32_t SysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __IO uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ struct {
+ __O uint32_t DATA;
+ } WR_DATA_DWORD;
+
+ struct {
+ __O uint16_t DATA;
+ uint16_t RESERVED;
+ }WR_DATA_WORD;
+
+ struct {
+ __O uint8_t DATA;
+ uint8_t RESERVED[3];
+ }WR_DATA_BYTE;
+ };
+} LPC_CRC_TypeDef;
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+typedef struct
+{
+ __IO uint32_t DIR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t MASK;
+ __IO uint32_t PIN;
+ __IO uint32_t SET;
+ __O uint32_t CLR;
+} LPC_GPIO_TypeDef;
+
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- External Memory Controller (EMC) -----------------------------*/
+typedef struct
+{
+ __IO uint32_t Control;
+ __I uint32_t Status;
+ __IO uint32_t Config;
+ uint32_t RESERVED0[5];
+ __IO uint32_t DynamicControl;
+ __IO uint32_t DynamicRefresh;
+ __IO uint32_t DynamicReadConfig;
+ uint32_t RESERVED1[1];
+ __IO uint32_t DynamicRP;
+ __IO uint32_t DynamicRAS;
+ __IO uint32_t DynamicSREX;
+ __IO uint32_t DynamicAPR;
+ __IO uint32_t DynamicDAL;
+ __IO uint32_t DynamicWR;
+ __IO uint32_t DynamicRC;
+ __IO uint32_t DynamicRFC;
+ __IO uint32_t DynamicXSR;
+ __IO uint32_t DynamicRRD;
+ __IO uint32_t DynamicMRD;
+ uint32_t RESERVED2[9];
+ __IO uint32_t StaticExtendedWait;
+ uint32_t RESERVED3[31];
+ __IO uint32_t DynamicConfig0;
+ __IO uint32_t DynamicRasCas0;
+ uint32_t RESERVED4[6];
+ __IO uint32_t DynamicConfig1;
+ __IO uint32_t DynamicRasCas1;
+ uint32_t RESERVED5[6];
+ __IO uint32_t DynamicConfig2;
+ __IO uint32_t DynamicRasCas2;
+ uint32_t RESERVED6[6];
+ __IO uint32_t DynamicConfig3;
+ __IO uint32_t DynamicRasCas3;
+ uint32_t RESERVED7[38];
+ __IO uint32_t StaticConfig0;
+ __IO uint32_t StaticWaitWen0;
+ __IO uint32_t StaticWaitOen0;
+ __IO uint32_t StaticWaitRd0;
+ __IO uint32_t StaticWaitPage0;
+ __IO uint32_t StaticWaitWr0;
+ __IO uint32_t StaticWaitTurn0;
+ uint32_t RESERVED8[1];
+ __IO uint32_t StaticConfig1;
+ __IO uint32_t StaticWaitWen1;
+ __IO uint32_t StaticWaitOen1;
+ __IO uint32_t StaticWaitRd1;
+ __IO uint32_t StaticWaitPage1;
+ __IO uint32_t StaticWaitWr1;
+ __IO uint32_t StaticWaitTurn1;
+ uint32_t RESERVED9[1];
+ __IO uint32_t StaticConfig2;
+ __IO uint32_t StaticWaitWen2;
+ __IO uint32_t StaticWaitOen2;
+ __IO uint32_t StaticWaitRd2;
+ __IO uint32_t StaticWaitPage2;
+ __IO uint32_t StaticWaitWr2;
+ __IO uint32_t StaticWaitTurn2;
+ uint32_t RESERVED10[1];
+ __IO uint32_t StaticConfig3;
+ __IO uint32_t StaticWaitWen3;
+ __IO uint32_t StaticWaitOen3;
+ __IO uint32_t StaticWaitRd3;
+ __IO uint32_t StaticWaitPage3;
+ __IO uint32_t StaticWaitWr3;
+ __IO uint32_t StaticWaitTurn3;
+} LPC_EMC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t MOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t TC;
+ __O uint8_t FEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t TV;
+ uint32_t RESERVED2;
+ __IO uint32_t WARNINT;
+ __IO uint32_t WINDOW;
+} LPC_WDT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+} LPC_TIM_TypeDef;
+
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
+ __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
+ __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
+ uint32_t RESERVED0;
+ __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
+ __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
+ __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
+ __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
+ __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
+/* There are three types of UARTs on the chip:
+(1) UART0,UART2, and UART3 are the standard UART.
+(2) UART1 is the standard with modem capability.
+(3) USART(UART4) is the sync/async UART with smart card capability.
+More details can be found on the Users Manual. */
+
+#if 0
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL;
+} LPC_UART_TypeDef;
+#else
+typedef struct
+{
+ union
+ {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union
+ {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union
+ {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];//Reserved
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];//Reserved
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];//Reserved
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];//Reserved
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];//Reserved
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];//Reserved
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];//Reserved
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];//Reserved
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];//Reserved
+ __I uint8_t FIFOLVL;
+}LPC_UART_TypeDef;
+#endif
+
+
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __I uint8_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
+ __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
+ __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
+ uint32_t RESERVED0[2];
+ __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
+ __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[989];
+ __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
+ __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
+ __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
+ __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
+ __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
+ __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
+ __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
+ uint32_t RESERVED3[3];
+ __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
+} LPC_UART4_TypeDef;
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+ __IO uint32_t ERSTATUS;
+ __IO uint32_t ERCONTROL;
+ __IO uint32_t ERCOUNTERS;
+ uint32_t RESERVED22;
+ __IO uint32_t ERFIRSTSTAMP0;
+ __IO uint32_t ERFIRSTSTAMP1;
+ __IO uint32_t ERFIRSTSTAMP2;
+ uint32_t RESERVED23;
+ __IO uint32_t ERLASTSTAMP0;
+ __IO uint32_t ERLASTSTAMP1;
+ __IO uint32_t ERLASTSTAMP2;
+} LPC_RTC_TypeDef;
+
+
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t P0_0; /* 0x000 */
+ __IO uint32_t P0_1;
+ __IO uint32_t P0_2;
+ __IO uint32_t P0_3;
+ __IO uint32_t P0_4;
+ __IO uint32_t P0_5;
+ __IO uint32_t P0_6;
+ __IO uint32_t P0_7;
+
+ __IO uint32_t P0_8; /* 0x020 */
+ __IO uint32_t P0_9;
+ __IO uint32_t P0_10;
+ __IO uint32_t P0_11;
+ __IO uint32_t P0_12;
+ __IO uint32_t P0_13;
+ __IO uint32_t P0_14;
+ __IO uint32_t P0_15;
+
+ __IO uint32_t P0_16; /* 0x040 */
+ __IO uint32_t P0_17;
+ __IO uint32_t P0_18;
+ __IO uint32_t P0_19;
+ __IO uint32_t P0_20;
+ __IO uint32_t P0_21;
+ __IO uint32_t P0_22;
+ __IO uint32_t P0_23;
+
+ __IO uint32_t P0_24; /* 0x060 */
+ __IO uint32_t P0_25;
+ __IO uint32_t P0_26;
+ __IO uint32_t P0_27;
+ __IO uint32_t P0_28;
+ __IO uint32_t P0_29;
+ __IO uint32_t P0_30;
+ __IO uint32_t P0_31;
+
+ __IO uint32_t P1_0; /* 0x080 */
+ __IO uint32_t P1_1;
+ __IO uint32_t P1_2;
+ __IO uint32_t P1_3;
+ __IO uint32_t P1_4;
+ __IO uint32_t P1_5;
+ __IO uint32_t P1_6;
+ __IO uint32_t P1_7;
+
+ __IO uint32_t P1_8; /* 0x0A0 */
+ __IO uint32_t P1_9;
+ __IO uint32_t P1_10;
+ __IO uint32_t P1_11;
+ __IO uint32_t P1_12;
+ __IO uint32_t P1_13;
+ __IO uint32_t P1_14;
+ __IO uint32_t P1_15;
+
+ __IO uint32_t P1_16; /* 0x0C0 */
+ __IO uint32_t P1_17;
+ __IO uint32_t P1_18;
+ __IO uint32_t P1_19;
+ __IO uint32_t P1_20;
+ __IO uint32_t P1_21;
+ __IO uint32_t P1_22;
+ __IO uint32_t P1_23;
+
+ __IO uint32_t P1_24; /* 0x0E0 */
+ __IO uint32_t P1_25;
+ __IO uint32_t P1_26;
+ __IO uint32_t P1_27;
+ __IO uint32_t P1_28;
+ __IO uint32_t P1_29;
+ __IO uint32_t P1_30;
+ __IO uint32_t P1_31;
+
+ __IO uint32_t P2_0; /* 0x100 */
+ __IO uint32_t P2_1;
+ __IO uint32_t P2_2;
+ __IO uint32_t P2_3;
+ __IO uint32_t P2_4;
+ __IO uint32_t P2_5;
+ __IO uint32_t P2_6;
+ __IO uint32_t P2_7;
+
+ __IO uint32_t P2_8; /* 0x120 */
+ __IO uint32_t P2_9;
+ __IO uint32_t P2_10;
+ __IO uint32_t P2_11;
+ __IO uint32_t P2_12;
+ __IO uint32_t P2_13;
+ __IO uint32_t P2_14;
+ __IO uint32_t P2_15;
+
+ __IO uint32_t P2_16; /* 0x140 */
+ __IO uint32_t P2_17;
+ __IO uint32_t P2_18;
+ __IO uint32_t P2_19;
+ __IO uint32_t P2_20;
+ __IO uint32_t P2_21;
+ __IO uint32_t P2_22;
+ __IO uint32_t P2_23;
+
+ __IO uint32_t P2_24; /* 0x160 */
+ __IO uint32_t P2_25;
+ __IO uint32_t P2_26;
+ __IO uint32_t P2_27;
+ __IO uint32_t P2_28;
+ __IO uint32_t P2_29;
+ __IO uint32_t P2_30;
+ __IO uint32_t P2_31;
+
+ __IO uint32_t P3_0; /* 0x180 */
+ __IO uint32_t P3_1;
+ __IO uint32_t P3_2;
+ __IO uint32_t P3_3;
+ __IO uint32_t P3_4;
+ __IO uint32_t P3_5;
+ __IO uint32_t P3_6;
+ __IO uint32_t P3_7;
+
+ __IO uint32_t P3_8; /* 0x1A0 */
+ __IO uint32_t P3_9;
+ __IO uint32_t P3_10;
+ __IO uint32_t P3_11;
+ __IO uint32_t P3_12;
+ __IO uint32_t P3_13;
+ __IO uint32_t P3_14;
+ __IO uint32_t P3_15;
+
+ __IO uint32_t P3_16; /* 0x1C0 */
+ __IO uint32_t P3_17;
+ __IO uint32_t P3_18;
+ __IO uint32_t P3_19;
+ __IO uint32_t P3_20;
+ __IO uint32_t P3_21;
+ __IO uint32_t P3_22;
+ __IO uint32_t P3_23;
+
+ __IO uint32_t P3_24; /* 0x1E0 */
+ __IO uint32_t P3_25;
+ __IO uint32_t P3_26;
+ __IO uint32_t P3_27;
+ __IO uint32_t P3_28;
+ __IO uint32_t P3_29;
+ __IO uint32_t P3_30;
+ __IO uint32_t P3_31;
+
+ __IO uint32_t P4_0; /* 0x200 */
+ __IO uint32_t P4_1;
+ __IO uint32_t P4_2;
+ __IO uint32_t P4_3;
+ __IO uint32_t P4_4;
+ __IO uint32_t P4_5;
+ __IO uint32_t P4_6;
+ __IO uint32_t P4_7;
+
+ __IO uint32_t P4_8; /* 0x220 */
+ __IO uint32_t P4_9;
+ __IO uint32_t P4_10;
+ __IO uint32_t P4_11;
+ __IO uint32_t P4_12;
+ __IO uint32_t P4_13;
+ __IO uint32_t P4_14;
+ __IO uint32_t P4_15;
+
+ __IO uint32_t P4_16; /* 0x240 */
+ __IO uint32_t P4_17;
+ __IO uint32_t P4_18;
+ __IO uint32_t P4_19;
+ __IO uint32_t P4_20;
+ __IO uint32_t P4_21;
+ __IO uint32_t P4_22;
+ __IO uint32_t P4_23;
+
+ __IO uint32_t P4_24; /* 0x260 */
+ __IO uint32_t P4_25;
+ __IO uint32_t P4_26;
+ __IO uint32_t P4_27;
+ __IO uint32_t P4_28;
+ __IO uint32_t P4_29;
+ __IO uint32_t P4_30;
+ __IO uint32_t P4_31;
+
+ __IO uint32_t P5_0; /* 0x280 */
+ __IO uint32_t P5_1;
+ __IO uint32_t P5_2;
+ __IO uint32_t P5_3;
+ __IO uint32_t P5_4; /* 0x290 */
+} LPC_IOCON_TypeDef;
+
+
+
+
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
+ __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+typedef struct /* Acceptance Filter Registers */
+{
+ ///Offset: 0x00000000 - Acceptance Filter Register
+ __IO uint32_t AFMR;
+
+ ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
+ __IO uint32_t SFF_sa;
+
+ ///Offset: 0x00000008 - Standard Frame Group Start Address Register
+ __IO uint32_t SFF_GRP_sa;
+
+ ///Offset: 0x0000000C - Extended Frame Start Address Register
+ __IO uint32_t EFF_sa;
+
+ ///Offset: 0x00000010 - Extended Frame Group Start Address Register
+ __IO uint32_t EFF_GRP_sa;
+
+ ///Offset: 0x00000014 - End of AF Tables register
+ __IO uint32_t ENDofTable;
+
+ ///Offset: 0x00000018 - LUT Error Address register
+ __I uint32_t LUTerrAd;
+
+ ///Offset: 0x0000001C - LUT Error Register
+ __I uint32_t LUTerr;
+
+ ///Offset: 0x00000020 - CAN Central Transmit Status Register
+ __IO uint32_t FCANIE;
+
+ ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
+ __IO uint32_t FCANIC0;
+
+ ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+typedef struct /* Central Registers */
+{
+ __I uint32_t TxSR;
+ __I uint32_t RxSR;
+ __I uint32_t MSR;
+} LPC_CANCR_TypeDef;
+
+typedef struct /* Controller Registers */
+{
+ ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
+ __IO uint32_t MOD;
+
+ ///Offset: 0x00000004 - Command bits that affect the state
+ __O uint32_t CMR;
+
+ ///Offset: 0x00000008 - Global Controller Status and Error Counters
+ __IO uint32_t GSR;
+
+ ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
+ __I uint32_t ICR;
+
+ ///Offset: 0x00000010 - Interrupt Enable Register
+ __IO uint32_t IER;
+
+ ///Offset: 0x00000014 - Bus Timing Register
+ __IO uint32_t BTR;
+
+ ///Offset: 0x00000018 - Error Warning Limit
+ __IO uint32_t EWL;
+
+ ///Offset: 0x0000001C - Status Register
+ __I uint32_t SR;
+
+ ///Offset: 0x00000020 - Receive frame status
+ __IO uint32_t RFS;
+
+ ///Offset: 0x00000024 - Received Identifier
+ __IO uint32_t RID;
+
+ ///Offset: 0x00000028 - Received data bytes 1-4
+ __IO uint32_t RDA;
+
+ ///Offset: 0x0000002C - Received data bytes 5-8
+ __IO uint32_t RDB;
+
+ ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
+ __IO uint32_t TFI1;
+
+ ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
+ __IO uint32_t TID1;
+
+ ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
+ __IO uint32_t TDA1;
+
+ ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
+ __IO uint32_t TDB1;
+
+ ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
+ __IO uint32_t TFI2;
+
+ ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
+ __IO uint32_t TID2;
+
+ ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
+ __IO uint32_t TDA2;
+
+ ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
+ __IO uint32_t TDB2;
+
+ ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
+ __IO uint32_t TFI3;
+
+ ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
+ __IO uint32_t TID3;
+
+ ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
+ __IO uint32_t TDA3;
+
+ ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CTRL;
+ __IO uint32_t CNTVAL;
+} LPC_DAC_TypeDef;
+
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+typedef struct
+{
+ __IO uint32_t DAO;
+ __IO uint32_t DAI;
+ __O uint32_t TXFIFO;
+ __I uint32_t RXFIFO;
+ __I uint32_t STATE;
+ __IO uint32_t DMA1;
+ __IO uint32_t DMA2;
+ __IO uint32_t IRQ;
+ __IO uint32_t TXRATE;
+ __IO uint32_t RXRATE;
+ __IO uint32_t TXBITRATE;
+ __IO uint32_t RXBITRATE;
+ __IO uint32_t TXMODE;
+ __IO uint32_t RXMODE;
+} LPC_I2S_TypeDef;
+
+
+
+
+
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+typedef struct
+{
+ __I uint32_t CON;
+ __O uint32_t CON_SET;
+ __O uint32_t CON_CLR;
+ __I uint32_t CAPCON;
+ __O uint32_t CAPCON_SET;
+ __O uint32_t CAPCON_CLR;
+ __IO uint32_t TC0;
+ __IO uint32_t TC1;
+ __IO uint32_t TC2;
+ __IO uint32_t LIM0;
+ __IO uint32_t LIM1;
+ __IO uint32_t LIM2;
+ __IO uint32_t MAT0;
+ __IO uint32_t MAT1;
+ __IO uint32_t MAT2;
+ __IO uint32_t DT;
+ __IO uint32_t CP;
+ __IO uint32_t CAP0;
+ __IO uint32_t CAP1;
+ __IO uint32_t CAP2;
+ __I uint32_t INTEN;
+ __O uint32_t INTEN_SET;
+ __O uint32_t INTEN_CLR;
+ __I uint32_t CNTCON;
+ __O uint32_t CNTCON_SET;
+ __O uint32_t CNTCON_CLR;
+ __I uint32_t INTF;
+ __O uint32_t INTF_SET;
+ __O uint32_t INTF_CLR;
+ __O uint32_t CAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+typedef struct
+{
+ __O uint32_t CON;
+ __I uint32_t STAT;
+ __IO uint32_t CONF;
+ __I uint32_t POS;
+ __IO uint32_t MAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP0;
+ __IO uint32_t LOAD;
+ __I uint32_t TIME;
+ __I uint32_t VEL;
+ __I uint32_t CAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTERPHA;
+ __IO uint32_t FILTERPHB;
+ __IO uint32_t FILTERINX;
+ __IO uint32_t WINDOW;
+ __IO uint32_t INXCMP1;
+ __IO uint32_t INXCMP2;
+ uint32_t RESERVED0[993];
+ __O uint32_t IEC;
+ __O uint32_t IES;
+ __I uint32_t INTSTAT;
+ __I uint32_t IE;
+ __O uint32_t CLR;
+ __O uint32_t SET;
+} LPC_QEI_TypeDef;
+
+/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLOCK;
+ __IO uint32_t ARGUMENT;
+ __IO uint32_t COMMAND;
+ __I uint32_t RESP_CMD;
+ __I uint32_t RESP0;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __IO uint32_t DATATMR;
+ __IO uint32_t DATALEN;
+ __IO uint32_t DATACTRL;
+ __I uint32_t DATACNT;
+ __I uint32_t STATUS;
+ __O uint32_t CLEAR;
+ __IO uint32_t MASK0;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO[16];
+} LPC_MCI_TypeDef;
+
+
+
+
+
+
+
+
+
+
+/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
+typedef struct
+{
+ __IO uint32_t CMD; /* 0x0080 */
+ __IO uint32_t ADDR;
+ __IO uint32_t WDATA;
+ __IO uint32_t RDATA;
+ __IO uint32_t WSTATE; /* 0x0090 */
+ __IO uint32_t CLKDIV;
+ __IO uint32_t PWRDWN; /* 0x0098 */
+ uint32_t RESERVED0[975];
+ __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
+ __IO uint32_t INT_SET_ENABLE;
+ __IO uint32_t INT_STATUS; /* 0x0FE0 */
+ __IO uint32_t INT_ENABLE;
+ __IO uint32_t INT_CLR_STATUS;
+ __IO uint32_t INT_SET_STATUS;
+} LPC_EEPROM_TypeDef;
+
+
+/*------------- COMPARATOR ----------------------------------------------------*/
+
+typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
+ __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
+ __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
+} LPC_COMPARATOR_Type;
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_PERI_RAM_BASE (0x20000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHBRAM1_BASE (0x20004000UL)
+#define LPC_AHB_BASE (0x20080000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
+#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
+#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
+#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
+
+#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
+#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
+#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
+
+
+
+#endif // __LPC407x_8x_177x_8x_H__
--- a/TARGET_LPC4088/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,88 +1,88 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- UART_0 = (int)LPC_UART0_BASE,
- UART_1 = (int)LPC_UART1_BASE,
- UART_2 = (int)LPC_UART2_BASE,
- UART_3 = (int)LPC_UART3_BASE,
- UART_4 = (int)LPC_UART4_BASE
-} UARTName;
-
-typedef enum {
- ADC0_0 = 0,
- ADC0_1,
- ADC0_2,
- ADC0_3,
- ADC0_4,
- ADC0_5,
- ADC0_6,
- ADC0_7
-} ADCName;
-
-typedef enum {
- DAC_0 = 0
-} DACName;
-
-typedef enum {
- SPI_0 = (int)LPC_SSP0_BASE,
- SPI_1 = (int)LPC_SSP1_BASE,
- SPI_2 = (int)LPC_SSP2_BASE
-} SPIName;
-
-typedef enum {
- I2C_0 = (int)LPC_I2C0_BASE,
- I2C_1 = (int)LPC_I2C1_BASE,
- I2C_2 = (int)LPC_I2C2_BASE
-} I2CName;
-
-typedef enum {
- PWM0_1 = 1,
- PWM0_2,
- PWM0_3,
- PWM0_4,
- PWM0_5,
- PWM0_6,
- PWM1_1,
- PWM1_2,
- PWM1_3,
- PWM1_4,
- PWM1_5,
- PWM1_6
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)LPC_CAN1_BASE,
- CAN_2 = (int)LPC_CAN2_BASE
-} CANName;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-#define STDIO_UART UART_0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ UART_0 = (int)LPC_UART0_BASE,
+ UART_1 = (int)LPC_UART1_BASE,
+ UART_2 = (int)LPC_UART2_BASE,
+ UART_3 = (int)LPC_UART3_BASE,
+ UART_4 = (int)LPC_UART4_BASE
+} UARTName;
+
+typedef enum {
+ ADC0_0 = 0,
+ ADC0_1,
+ ADC0_2,
+ ADC0_3,
+ ADC0_4,
+ ADC0_5,
+ ADC0_6,
+ ADC0_7
+} ADCName;
+
+typedef enum {
+ DAC_0 = 0
+} DACName;
+
+typedef enum {
+ SPI_0 = (int)LPC_SSP0_BASE,
+ SPI_1 = (int)LPC_SSP1_BASE,
+ SPI_2 = (int)LPC_SSP2_BASE
+} SPIName;
+
+typedef enum {
+ I2C_0 = (int)LPC_I2C0_BASE,
+ I2C_1 = (int)LPC_I2C1_BASE,
+ I2C_2 = (int)LPC_I2C2_BASE
+} I2CName;
+
+typedef enum {
+ PWM0_1 = 1,
+ PWM0_2,
+ PWM0_3,
+ PWM0_4,
+ PWM0_5,
+ PWM0_6,
+ PWM1_1,
+ PWM1_2,
+ PWM1_3,
+ PWM1_4,
+ PWM1_5,
+ PWM1_6
+} PWMName;
+
+typedef enum {
+ CAN_1 = (int)LPC_CAN1_BASE,
+ CAN_2 = (int)LPC_CAN2_BASE
+} CANName;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+#define STDIO_UART UART_0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC4088/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,35 +1,35 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
- Port1 = 1,
- Port2 = 2,
- Port3 = 3,
- Port4 = 4,
- Port5 = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+ Port1 = 1,
+ Port2 = 2,
+ Port3 = 3,
+ Port4 = 4,
+ Port5 = 5
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC4088/TOOLCHAIN_ARM_STD/LPC407X_8X.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/TOOLCHAIN_ARM_STD/LPC407X_8X.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,18 +1,18 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x00000000 0x00080000 { ; load region size_region
- ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
- .ANY (+RW +ZI)
- }
- RW_IRAM2 0x20000000 0x00008000 {
- .ANY (AHBSRAM1)
- }
-}
-
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x100000E8 0x0000FF18 { ; RW data
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM2 0x20000000 0x00008000 {
+ .ANY (AHBSRAM1)
+ }
+}
+
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/cmsis_nvic.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/mbed.ar has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/retarget.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/startup_LPC407x_8x_177x_8x.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/sys.o has changed
Binary file TARGET_LPC4088/TOOLCHAIN_ARM_STD/system_LPC407x_8x_177x_8x.o has changed
--- a/TARGET_LPC4088/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC4088/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC407x_8x specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC407x_8x_177x_8x.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC407x_8x specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC407x_8x_177x_8x.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC4088/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 41) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC4088/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC4088/system_LPC407x_8x_177x_8x.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC4088/system_LPC407x_8x_177x_8x.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,89 +1,89 @@
-/**********************************************************************
-* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
-*//**
-* @file system_LPC407x_8x_177x_8x.h
-* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-* for the NXP LPC Device Series
-* @version 1.0
-* @date 02. June. 2011
-* @author NXP MCU SW Application Team
-*
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers. This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
-#define __SYSTEM_LPC407x_8x_177x_8x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
-extern uint32_t EMCClock; /*!< EMC Clock */
-extern uint32_t USBClock; /*!< USB Frequency */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL (12000000UL) /* Oscillator frequency */
-#define OSC_CLK ( XTAL) /* Main oscillator frequency */
-#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
-#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
-#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
-
-
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */
+/**********************************************************************
+* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
+*//**
+* @file system_LPC407x_8x_177x_8x.h
+* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+* for the NXP LPC Device Series
+* @version 1.0
+* @date 02. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
+#define __SYSTEM_LPC407x_8x_177x_8x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
+extern uint32_t EMCClock; /*!< EMC Clock */
+extern uint32_t USBClock; /*!< USB Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
+#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
+#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
+
+
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */
--- a/TARGET_LPC812/LPC8xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/LPC8xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,687 +1,687 @@
-/****************************************************************************
- * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
- * Project: NXP LPC8xx software example
- *
- * Description:
- * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
- * NXP LPC800 Device Series
- *
- ****************************************************************************
- * Software that is described herein is for illustrative purposes only
- * which provides customers with programming information regarding the
- * products. This software is supplied "AS IS" without any warranties.
- * NXP Semiconductors assumes no responsibility or liability for the
- * use of the software, conveys no license or title under any patent,
- * copyright, or mask work right to the product. NXP Semiconductors
- * reserves the right to make changes in the software without
- * notification. NXP Semiconductors also make no representation or
- * warranty that such application will be suitable for the specified
- * use without further testing or modification.
-
- * Permission to use, copy, modify, and distribute this software and its
- * documentation is hereby granted, under NXP Semiconductors'
- * relevant copyright in the software, without fee, provided that it
- * is used in conjunction with NXP Semiconductors microcontrollers. This
- * copyright, permission, and disclaimer notice must appear in all copies of
- * this code.
-****************************************************************************/
-#ifndef __LPC8xx_H__
-#define __LPC8xx_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
- This file defines all structures and symbols for LPC8xx:
- - Registers and bitfields
- - peripheral base address
- - PIO definitions
- @{
-*/
-
-
-/******************************************************************************/
-/* Processor and Core Peripherals */
-/******************************************************************************/
-/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
- Configuration of the Cortex-M0+ Processor and Core Peripherals
- @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-typedef enum IRQn
-{
-/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-
-/****** LPC8xx Specific Interrupt Numbers ********************************************************/
- SPI0_IRQn = 0, /*!< SPI0 */
- SPI1_IRQn = 1, /*!< SPI1 */
- Reserved0_IRQn = 2, /*!< Reserved Interrupt */
- UART0_IRQn = 3, /*!< USART0 */
- UART1_IRQn = 4, /*!< USART1 */
- UART2_IRQn = 5, /*!< USART2 */
- Reserved1_IRQn = 6, /*!< Reserved Interrupt */
- Reserved2_IRQn = 7, /*!< Reserved Interrupt */
- I2C_IRQn = 8, /*!< I2C */
- SCT_IRQn = 9, /*!< SCT */
- MRT_IRQn = 10, /*!< MRT */
- CMP_IRQn = 11, /*!< CMP */
- WDT_IRQn = 12, /*!< WDT */
- BOD_IRQn = 13, /*!< BOD */
- Reserved3_IRQn = 14, /*!< Reserved Interrupt */
- WKT_IRQn = 15, /*!< WKT Interrupt */
- Reserved4_IRQn = 16, /*!< Reserved Interrupt */
- Reserved5_IRQn = 17, /*!< Reserved Interrupt */
- Reserved6_IRQn = 18, /*!< Reserved Interrupt */
- Reserved7_IRQn = 19, /*!< Reserved Interrupt */
- Reserved8_IRQn = 20, /*!< Reserved Interrupt */
- Reserved9_IRQn = 21, /*!< Reserved Interrupt */
- Reserved10_IRQn = 22, /*!< Reserved Interrupt */
- Reserved11_IRQn = 23, /*!< Reserved Interrupt */
- PININT0_IRQn = 24, /*!< External Interrupt 0 */
- PININT1_IRQn = 25, /*!< External Interrupt 1 */
- PININT2_IRQn = 26, /*!< External Interrupt 2 */
- PININT3_IRQn = 27, /*!< External Interrupt 3 */
- PININT4_IRQn = 28, /*!< External Interrupt 4 */
- PININT5_IRQn = 29, /*!< External Interrupt 5 */
- PININT6_IRQn = 30, /*!< External Interrupt 6 */
- PININT7_IRQn = 31, /*!< External Interrupt 7 */
-} IRQn_Type;
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/*@}*/ /* end of group LPC8xx_CMSIS */
-
-
-#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
-#include "system_LPC8xx.h" /* System Header */
-
-
-/******************************************************************************/
-/* Device Specific Peripheral Registers structures */
-/******************************************************************************/
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
- @{
-*/
-typedef struct
-{
- __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
- __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
- __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
- __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
- uint32_t RESERVED0[4];
-
- __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
- __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
- uint32_t RESERVED1[2];
- __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
- uint32_t RESERVED2[3];
- __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
- __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
- uint32_t RESERVED3[10];
-
- __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
- __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
- __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
- uint32_t RESERVED4[1];
-
- __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
- uint32_t RESERVED5[4];
- __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
- uint32_t RESERVED6[18];
-
- __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
- __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
- __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
- uint32_t RESERVED7;
- __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
- __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
- uint32_t RESERVED8[1];
- __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
- __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
- uint32_t RESERVED9[12];
- __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
- __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
- __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
- uint32_t RESERVED10[6];
- __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
- __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
- __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
- uint32_t RESERVED11[27];
- __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
- uint32_t RESERVED12[3];
- __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
- uint32_t RESERVED13[6];
- __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
- __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
- __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
- uint32_t RESERVED14[110];
- __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
-} LPC_SYSCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_SYSCON */
-
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
- */
-
-typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
- __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
- __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
- __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
- __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
- __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
- __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
- __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
- __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
- __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
- __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
- __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
- __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
- __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
- __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
- __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
- __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
- __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
- __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
- __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
-} LPC_IOCON_TypeDef;
-/*@}*/ /* end of group LPC8xx_IOCON */
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
- */
-typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
- __I uint32_t RESERVED0[4];
- __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
- __I uint32_t RESERVED1[3];
- __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
- __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
- __I uint32_t RESERVED2;
- __I uint32_t FMSW0;
-} LPC_FLASHCTRL_TypeDef;
-/*@}*/ /* end of group LPC8xx_FLASHCTRL */
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
- @{
-*/
-typedef struct
-{
- __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
- __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
- __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
- __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
- __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
- __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
-} LPC_PMU_TypeDef;
-/*@}*/ /* end of group LPC8xx_PMU */
-
-
-/*------------- Switch Matrix Port --------------------------*/
-/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
- @{
-*/
-typedef struct
-{
- union {
- __IO uint32_t PINASSIGN[9];
- struct {
- __IO uint32_t PINASSIGN0;
- __IO uint32_t PINASSIGN1;
- __IO uint32_t PINASSIGN2;
- __IO uint32_t PINASSIGN3;
- __IO uint32_t PINASSIGN4;
- __IO uint32_t PINASSIGN5;
- __IO uint32_t PINASSIGN6;
- __IO uint32_t PINASSIGN7;
- __IO uint32_t PINASSIGN8;
- };
- };
- __I uint32_t RESERVED0[103];
- __IO uint32_t PINENABLE0;
-} LPC_SWM_TypeDef;
-/*@}*/ /* end of group LPC8xx_SWM */
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- GPIO_PORT -----
-// ------------------------------------------------------------------------------------------------
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
- */
-
-typedef struct {
- __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
- __I uint16_t RESERVED0[2039];
- __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
- uint32_t RESERVED1[1006];
- __IO uint32_t DIR0; /* 0x2000 */
- uint32_t RESERVED2[31];
- __IO uint32_t MASK0; /* 0x2080 */
- uint32_t RESERVED3[31];
- __IO uint32_t PIN0; /* 0x2100 */
- uint32_t RESERVED4[31];
- __IO uint32_t MPIN0; /* 0x2180 */
- uint32_t RESERVED5[31];
- __IO uint32_t SET0; /* 0x2200 */
- uint32_t RESERVED6[31];
- __O uint32_t CLR0; /* 0x2280 */
- uint32_t RESERVED7[31];
- __O uint32_t NOT0; /* 0x2300 */
-
-} LPC_GPIO_PORT_TypeDef;
-
-
-// ------------------------------------------------------------------------------------------------
-// ----- PIN_INT -----
-// ------------------------------------------------------------------------------------------------
-
-/**
- * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
- */
-
-typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
- __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
- __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
- __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
- __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
- __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
- __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
- __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
- __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
- __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
- __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
- __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
- __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
-} LPC_PIN_INT_TypeDef;
-
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-/** @addtogroup LPC8xx_CRC
- @{
-*/
-typedef struct
-{
- __IO uint32_t MODE;
- __IO uint32_t SEED;
- union {
- __I uint32_t SUM;
- __O uint32_t WR_DATA_DWORD;
- __O uint16_t WR_DATA_WORD;
- uint16_t RESERVED_WORD;
- __O uint8_t WR_DATA_BYTE;
- uint8_t RESERVED_BYTE[3];
- };
-} LPC_CRC_TypeDef;
-/*@}*/ /* end of group LPC8xx_CRC */
-
-/*------------- Comparator (CMP) --------------------------------------------------*/
-/** @addtogroup LPC8xx_CMP LPC8xx Comparator
- @{
-*/
-typedef struct { /*!< (@ 0x40024000) CMP Structure */
- __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
- __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
-} LPC_CMP_TypeDef;
-/*@}*/ /* end of group LPC8xx_CMP */
-
-
-/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
-/** @addtogroup LPC8xx_WKT
- @{
-*/
-typedef struct { /*!< (@ 0x40028000) WKT Structure */
- __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
- uint32_t Reserved[2];
- __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
-} LPC_WKT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WKT */
-
-
-/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
-typedef struct {
-__IO uint32_t INTVAL;
-__IO uint32_t TIMER;
-__IO uint32_t CTRL;
-__IO uint32_t STAT;
-} MRT_Channel_cfg_Type;
-
-typedef struct {
- MRT_Channel_cfg_Type Channel[4];
- uint32_t Reserved0[1];
- __IO uint32_t IDLE_CH;
- __IO uint32_t IRQ_FLAG;
-} LPC_MRT_TypeDef;
-
-
-/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
-/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
- @{
-*/
-/**
- * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
- */
-typedef struct
-{
- __IO uint32_t CFG; /* 0x00 */
- __IO uint32_t CTRL;
- __IO uint32_t STAT;
- __IO uint32_t INTENSET;
- __O uint32_t INTENCLR; /* 0x10 */
- __I uint32_t RXDATA;
- __I uint32_t RXDATA_STAT;
- __IO uint32_t TXDATA;
- __IO uint32_t BRG; /* 0x20 */
- __IO uint32_t INTSTAT;
-} LPC_USART_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_USART */
-
-
-/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
-/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
- @{
-*/
-typedef struct
-{
- __IO uint32_t CFG; /* 0x00 */
- __IO uint32_t DLY;
- __IO uint32_t STAT;
- __IO uint32_t INTENSET;
- __O uint32_t INTENCLR; /* 0x10 */
- __I uint32_t RXDAT;
- __IO uint32_t TXDATCTL;
- __IO uint32_t TXDAT;
- __IO uint32_t TXCTRL; /* 0x20 */
- __IO uint32_t DIV;
- __I uint32_t INTSTAT;
-} LPC_SPI_TypeDef;
-/*@}*/ /* end of group LPC8xx_SPI */
-
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-/** @addtogroup LPC8xx_I2C I2C-Bus Interface
- @{
-*/
-typedef struct
-{
- __IO uint32_t CFG; /* 0x00 */
- __IO uint32_t STAT;
- __IO uint32_t INTENSET;
- __O uint32_t INTENCLR;
- __IO uint32_t TIMEOUT; /* 0x10 */
- __IO uint32_t DIV;
- __IO uint32_t INTSTAT;
- uint32_t Reserved0[1];
- __IO uint32_t MSTCTL; /* 0x20 */
- __IO uint32_t MSTTIME;
- __IO uint32_t MSTDAT;
- uint32_t Reserved1[5];
- __IO uint32_t SLVCTL; /* 0x40 */
- __IO uint32_t SLVDAT;
- __IO uint32_t SLVADR0;
- __IO uint32_t SLVADR1;
- __IO uint32_t SLVADR2; /* 0x50 */
- __IO uint32_t SLVADR3;
- __IO uint32_t SLVQUAL0;
- uint32_t Reserved2[9];
- __I uint32_t MONRXDAT; /* 0x80 */
-} LPC_I2C_TypeDef;
-
-/*@}*/ /* end of group LPC8xx_I2C */
-
-/**
- * @brief State Configurable Timer (SCT) (SCT)
- */
-
-/**
- * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
- */
-
-#define CONFIG_SCT_nEV (6) /* Number of events */
-#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
-#define CONFIG_SCT_nOU (4) /* Number of outputs */
-
-typedef struct
-{
- __IO uint32_t CONFIG; /* 0x000 Configuration Register */
- union {
- __IO uint32_t CTRL_U; /* 0x004 Control Register */
- struct {
- __IO uint16_t CTRL_L; /* 0x004 low control register */
- __IO uint16_t CTRL_H; /* 0x006 high control register */
- };
- };
- __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
- __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
- __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
- __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
- __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
- __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
- __IO uint16_t START_L; /* 0x014 start register for counter L */
- __IO uint16_t START_H; /* 0x016 start register for counter H */
- uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
- union {
- __IO uint32_t COUNT_U; /* 0x040 counter register */
- struct {
- __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
- __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
- };
- };
- __IO uint16_t STATE_L; /* 0x044 state register for counter L */
- __IO uint16_t STATE_H; /* 0x046 state register for counter H */
- __I uint32_t INPUT; /* 0x048 input register */
- __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
- __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
- __IO uint32_t OUTPUT; /* 0x050 output register */
- __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
- __IO uint32_t RES; /* 0x058 conflict resolution register */
- uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
- __IO uint32_t EVEN; /* 0x0F0 event enable register */
- __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
- __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
- __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
-
- union {
- __IO union { /* 0x100-... Match / Capture value */
- uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTMATCH[i].L Access to L value */
- uint16_t H; /* SCTMATCH[i].H Access to H value */
- };
- } MATCH[CONFIG_SCT_nRG];
- __I union {
- uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTCAP[i].L Access to H value */
- uint16_t H; /* SCTCAP[i].H Access to H value */
- };
- } CAP[CONFIG_SCT_nRG];
- };
-
-
- uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
-
- union {
- __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
- __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
- };
- uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
- union {
- __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
- __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
- };
-
- uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
-
-
- union {
- __IO union { /* 0x200-... Match Reload / Capture Control value */
- uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTMATCHREL[i].L Access to L value */
- uint16_t H; /* SCTMATCHREL[i].H Access to H value */
- };
- } MATCHREL[CONFIG_SCT_nRG];
- __IO union {
- uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
- struct {
- uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
- uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
- };
- } CAPCTRL[CONFIG_SCT_nRG];
- };
-
- uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
-
- union {
- __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
- __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
- };
- uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
- union {
- __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
- __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
- };
- uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
-
- __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
- uint32_t STATE; /* Event State Register */
- uint32_t CTRL; /* Event Control Register */
- } EVENT[CONFIG_SCT_nEV];
-
- uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
-
- __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
- uint32_t SET; /* Output n Set Register */
- uint32_t CLR; /* Output n Clear Register */
- } OUT[CONFIG_SCT_nOU];
-
- uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
-
- __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
-
-} LPC_SCT_TypeDef;
-/*@}*/ /* end of group LPC8xx_SCT */
-
-
-/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
-/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
- @{
-*/
-typedef struct
-{
- __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
- __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
- __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
- __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
- uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
- __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
- __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
-} LPC_WWDT_TypeDef;
-/*@}*/ /* end of group LPC8xx_WDT */
-
-
-#if defined ( __CC_ARM )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Base addresses */
-#define LPC_FLASH_BASE (0x00000000UL)
-#define LPC_RAM_BASE (0x10000000UL)
-#define LPC_ROM_BASE (0x1FFF0000UL)
-#define LPC_APB0_BASE (0x40000000UL)
-#define LPC_AHB_BASE (0x50000000UL)
-
-/* APB0 peripherals */
-#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
-#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
-#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
-#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
-#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
-#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
-
-#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
-#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
-#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
-#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
-#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
-#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
-
-/* AHB peripherals */
-#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
-#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
-
-#define LPC_GPIO_PORT_BASE (0xA0000000)
-#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
-#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
-
-
-#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
-#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
-#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
-#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
-
-#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
-#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
-#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
-#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
-#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
-#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
-#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
-#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
-
-#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
-#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
-
-#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
-#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC8xx_H__ */
+/****************************************************************************
+ * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
+ * Project: NXP LPC8xx software example
+ *
+ * Description:
+ * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
+ * NXP LPC800 Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors'
+ * relevant copyright in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+****************************************************************************/
+#ifndef __LPC8xx_H__
+#define __LPC8xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
+ This file defines all structures and symbols for LPC8xx:
+ - Registers and bitfields
+ - peripheral base address
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
+ Configuration of the Cortex-M0+ Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC8xx Specific Interrupt Numbers ********************************************************/
+ SPI0_IRQn = 0, /*!< SPI0 */
+ SPI1_IRQn = 1, /*!< SPI1 */
+ Reserved0_IRQn = 2, /*!< Reserved Interrupt */
+ UART0_IRQn = 3, /*!< USART0 */
+ UART1_IRQn = 4, /*!< USART1 */
+ UART2_IRQn = 5, /*!< USART2 */
+ Reserved1_IRQn = 6, /*!< Reserved Interrupt */
+ Reserved2_IRQn = 7, /*!< Reserved Interrupt */
+ I2C_IRQn = 8, /*!< I2C */
+ SCT_IRQn = 9, /*!< SCT */
+ MRT_IRQn = 10, /*!< MRT */
+ CMP_IRQn = 11, /*!< CMP */
+ WDT_IRQn = 12, /*!< WDT */
+ BOD_IRQn = 13, /*!< BOD */
+ Reserved3_IRQn = 14, /*!< Reserved Interrupt */
+ WKT_IRQn = 15, /*!< WKT Interrupt */
+ Reserved4_IRQn = 16, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 17, /*!< Reserved Interrupt */
+ Reserved6_IRQn = 18, /*!< Reserved Interrupt */
+ Reserved7_IRQn = 19, /*!< Reserved Interrupt */
+ Reserved8_IRQn = 20, /*!< Reserved Interrupt */
+ Reserved9_IRQn = 21, /*!< Reserved Interrupt */
+ Reserved10_IRQn = 22, /*!< Reserved Interrupt */
+ Reserved11_IRQn = 23, /*!< Reserved Interrupt */
+ PININT0_IRQn = 24, /*!< External Interrupt 0 */
+ PININT1_IRQn = 25, /*!< External Interrupt 1 */
+ PININT2_IRQn = 26, /*!< External Interrupt 2 */
+ PININT3_IRQn = 27, /*!< External Interrupt 3 */
+ PININT4_IRQn = 28, /*!< External Interrupt 4 */
+ PININT5_IRQn = 29, /*!< External Interrupt 5 */
+ PININT6_IRQn = 30, /*!< External Interrupt 6 */
+ PININT7_IRQn = 31, /*!< External Interrupt 7 */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC8xx_CMSIS */
+
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_LPC8xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
+ uint32_t RESERVED6[18];
+
+ __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
+ __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
+ uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ uint32_t RESERVED11[27];
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_SYSCON */
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
+ __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_IOCON */
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0;
+} LPC_FLASHCTRL_TypeDef;
+/*@}*/ /* end of group LPC8xx_FLASHCTRL */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC8xx_PMU */
+
+
+/*------------- Switch Matrix Port --------------------------*/
+/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t PINASSIGN[9];
+ struct {
+ __IO uint32_t PINASSIGN0;
+ __IO uint32_t PINASSIGN1;
+ __IO uint32_t PINASSIGN2;
+ __IO uint32_t PINASSIGN3;
+ __IO uint32_t PINASSIGN4;
+ __IO uint32_t PINASSIGN5;
+ __IO uint32_t PINASSIGN6;
+ __IO uint32_t PINASSIGN7;
+ __IO uint32_t PINASSIGN8;
+ };
+ };
+ __I uint32_t RESERVED0[103];
+ __IO uint32_t PINENABLE0;
+} LPC_SWM_TypeDef;
+/*@}*/ /* end of group LPC8xx_SWM */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
+ __I uint16_t RESERVED0[2039];
+ __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ uint32_t RESERVED1[1006];
+ __IO uint32_t DIR0; /* 0x2000 */
+ uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /* 0x2080 */
+ uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /* 0x2100 */
+ uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /* 0x2180 */
+ uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /* 0x2200 */
+ uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /* 0x2280 */
+ uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /* 0x2300 */
+
+} LPC_GPIO_PORT_TypeDef;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
+} LPC_PIN_INT_TypeDef;
+
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+/** @addtogroup LPC8xx_CRC
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ __O uint32_t WR_DATA_DWORD;
+ __O uint16_t WR_DATA_WORD;
+ uint16_t RESERVED_WORD;
+ __O uint8_t WR_DATA_BYTE;
+ uint8_t RESERVED_BYTE[3];
+ };
+} LPC_CRC_TypeDef;
+/*@}*/ /* end of group LPC8xx_CRC */
+
+/*------------- Comparator (CMP) --------------------------------------------------*/
+/** @addtogroup LPC8xx_CMP LPC8xx Comparator
+ @{
+*/
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_TypeDef;
+/*@}*/ /* end of group LPC8xx_CMP */
+
+
+/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
+/** @addtogroup LPC8xx_WKT
+ @{
+*/
+typedef struct { /*!< (@ 0x40028000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
+ uint32_t Reserved[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
+} LPC_WKT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WKT */
+
+
+/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
+typedef struct {
+__IO uint32_t INTVAL;
+__IO uint32_t TIMER;
+__IO uint32_t CTRL;
+__IO uint32_t STAT;
+} MRT_Channel_cfg_Type;
+
+typedef struct {
+ MRT_Channel_cfg_Type Channel[4];
+ uint32_t Reserved0[1];
+ __IO uint32_t IDLE_CH;
+ __IO uint32_t IRQ_FLAG;
+} LPC_MRT_TypeDef;
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
+/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+/**
+ * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
+ */
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t CTRL;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDATA;
+ __I uint32_t RXDATA_STAT;
+ __IO uint32_t TXDATA;
+ __IO uint32_t BRG; /* 0x20 */
+ __IO uint32_t INTSTAT;
+} LPC_USART_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_USART */
+
+
+/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
+/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t DLY;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDAT;
+ __IO uint32_t TXDATCTL;
+ __IO uint32_t TXDAT;
+ __IO uint32_t TXCTRL; /* 0x20 */
+ __IO uint32_t DIV;
+ __I uint32_t INTSTAT;
+} LPC_SPI_TypeDef;
+/*@}*/ /* end of group LPC8xx_SPI */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC8xx_I2C I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR;
+ __IO uint32_t TIMEOUT; /* 0x10 */
+ __IO uint32_t DIV;
+ __IO uint32_t INTSTAT;
+ uint32_t Reserved0[1];
+ __IO uint32_t MSTCTL; /* 0x20 */
+ __IO uint32_t MSTTIME;
+ __IO uint32_t MSTDAT;
+ uint32_t Reserved1[5];
+ __IO uint32_t SLVCTL; /* 0x40 */
+ __IO uint32_t SLVDAT;
+ __IO uint32_t SLVADR0;
+ __IO uint32_t SLVADR1;
+ __IO uint32_t SLVADR2; /* 0x50 */
+ __IO uint32_t SLVADR3;
+ __IO uint32_t SLVQUAL0;
+ uint32_t Reserved2[9];
+ __I uint32_t MONRXDAT; /* 0x80 */
+} LPC_I2C_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_I2C */
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
+ */
+
+#define CONFIG_SCT_nEV (6) /* Number of events */
+#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (4) /* Number of outputs */
+
+typedef struct
+{
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* 0x004 low control register */
+ __IO uint16_t CTRL_H; /* 0x006 high control register */
+ };
+ };
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
+ __IO uint16_t START_L; /* 0x014 start register for counter L */
+ __IO uint16_t START_H; /* 0x016 start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* 0x040 counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
+ };
+ };
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */
+ __I uint32_t INPUT; /* 0x048 input register */
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* 0x050 output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
+ __IO uint32_t RES; /* 0x058 conflict resolution register */
+ uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
+
+ union {
+ __IO union { /* 0x100-... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+ } MATCH[CONFIG_SCT_nRG];
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to H value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+ } CAP[CONFIG_SCT_nRG];
+ };
+
+
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+
+
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+ } MATCHREL[CONFIG_SCT_nRG];
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+ } CAPCTRL[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+
+} LPC_SCT_TypeDef;
+/*@}*/ /* end of group LPC8xx_SCT */
+
+
+/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
+/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
+ uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
+ __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+ __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WWDT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WDT */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_ROM_BASE (0x1FFF0000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
+
+#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
+#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
+#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
+#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
+#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
+#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
+
+/* AHB peripherals */
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
+
+#define LPC_GPIO_PORT_BASE (0xA0000000)
+#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
+#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
+
+
+#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
+#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
+
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
+#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
+#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
+#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
+#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
+
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
+
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
+#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC8xx_H__ */
--- a/TARGET_LPC812/PeripheralNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/PeripheralNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC812/PinNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/PinNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,106 +1,106 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
- P0_0 = 0,
- P0_1 = 1,
- P0_2 = 2,
- P0_3 = 3,
- P0_4 = 4,
- P0_5 = 5,
- P0_6 = 6,
- P0_7 = 7,
- P0_8 = 8,
- P0_9 = 9,
- P0_10 = 10,
- P0_11 = 11,
- P0_12 = 12,
- P0_13 = 13,
- P0_14 = 14,
- P0_15 = 15,
- P0_16 = 16,
- P0_17 = 17,
-
- D0 = P0_0,
- D1 = P0_4,
- D2 = P0_6,
- D3 = P0_8,
- D4 = P0_9,
-
- D7 = P0_7,
- D8 = P0_17,
- D9 = P0_16,
- D10 = P0_13,
- D11 = P0_14,
- D12 = P0_15,
- D13 = P0_12,
-
- A4 = P0_10,
- A5 = P0_11,
-
- // LPC800-MAX board
- LED_RED = P0_7,
- LED_GREEN = P0_17,
- LED_BLUE = P0_16,
-
- // mbed original LED naming
- LED1 = LED_BLUE,
- LED2 = LED_GREEN,
- LED3 = LED_RED,
- LED4 = LED_RED,
-
- // Serial to USB pins
- USBTX = P0_6,
- USBRX = P0_1,
-
- // Not connected
- NC = (int)0xFFFFFFFF,
-} PinName;
-
-typedef enum {
- PullUp = 2,
- PullDown = 1,
- PullNone = 0,
- Repeater = 3,
- OpenDrain = 4
-} PinMode;
-
-#define STDIO_UART_TX USBTX
-#define STDIO_UART_RX USBRX
-
-typedef struct {
- unsigned char n;
- unsigned char offset;
-} SWM_Map;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+ P0_6 = 6,
+ P0_7 = 7,
+ P0_8 = 8,
+ P0_9 = 9,
+ P0_10 = 10,
+ P0_11 = 11,
+ P0_12 = 12,
+ P0_13 = 13,
+ P0_14 = 14,
+ P0_15 = 15,
+ P0_16 = 16,
+ P0_17 = 17,
+
+ D0 = P0_0,
+ D1 = P0_4,
+ D2 = P0_6,
+ D3 = P0_8,
+ D4 = P0_9,
+
+ D7 = P0_7,
+ D8 = P0_17,
+ D9 = P0_16,
+ D10 = P0_13,
+ D11 = P0_14,
+ D12 = P0_15,
+ D13 = P0_12,
+
+ A4 = P0_10,
+ A5 = P0_11,
+
+ // LPC800-MAX board
+ LED_RED = P0_7,
+ LED_GREEN = P0_17,
+ LED_BLUE = P0_16,
+
+ // mbed original LED naming
+ LED1 = LED_BLUE,
+ LED2 = LED_GREEN,
+ LED3 = LED_RED,
+ LED4 = LED_RED,
+
+ // Serial to USB pins
+ USBTX = P0_6,
+ USBRX = P0_1,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4
+} PinMode;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+
+typedef struct {
+ unsigned char n;
+ unsigned char offset;
+} SWM_Map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC812/PortNames.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/PortNames.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- Port0 = 0,
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- a/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC812.sct Mon Aug 19 13:34:54 2013 +0300
@@ -1,14 +1,14 @@
-
-LR_IROM1 0x00000000 0x4000 { ; load region size_region (32k)
- ER_IROM1 0x00000000 0x4000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
- ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
- ; 8KB - 0xC0 = 0xF40
- RW_IRAM1 0x100000C0 0xF40 {
- .ANY (+RW +ZI)
- }
-}
-
+
+LR_IROM1 0x00000000 0x4000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x4000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 8KB - 0xC0 = 0xF40
+ RW_IRAM1 0x100000C0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
+
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/cmsis_nvic.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/mbed.ar has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/retarget.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/sys.o has changed
Binary file TARGET_LPC812/TOOLCHAIN_ARM_MICRO/system_LPC8xx.o has changed
--- a/TARGET_LPC812/cmsis.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC812/cmsis.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,13 +1,13 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC8xx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC8xx.h" -#include "cmsis_nvic.h" - -#endif +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC8xx specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "LPC8xx.h" +#include "cmsis_nvic.h" + +#endif
--- a/TARGET_LPC812/cmsis_nvic.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/cmsis_nvic.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,26 +1,26 @@
-/* mbed Microcontroller Library - cmsis_nvic
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC812/device.h Mon Aug 12 13:17:46 2013 +0300 +++ b/TARGET_LPC812/device.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,57 +1,57 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 0 -#define DEVICE_PORTOUT 0 -#define DEVICE_PORTINOUT 0 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 0 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 0 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 0 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 0 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 1 - -#define DEVICE_ERROR_RED 1 - -#include "objects.h" - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 0 +#define DEVICE_PORTOUT 0 +#define DEVICE_PORTINOUT 0 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 0 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 0 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 0 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 1 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif
--- a/TARGET_LPC812/gpio_object.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/gpio_object.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,48 +1,48 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-
- __IO uint32_t *reg_dir;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value) {
- if (value)
- *obj->reg_set = obj->mask;
- else
- *obj->reg_clr = obj->mask;
-}
-
-static inline int gpio_read(gpio_t *obj) {
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC812/objects.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/objects.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,52 +1,52 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- uint32_t ch;
-};
-
-struct serial_s {
- LPC_USART_TypeDef *uart;
- unsigned char index;
-};
-
-struct i2c_s {
- LPC_I2C_TypeDef *i2c;
-};
-
-struct spi_s {
- LPC_SPI_TypeDef *spi;
- unsigned char spi_n;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+ uint32_t ch;
+};
+
+struct serial_s {
+ LPC_USART_TypeDef *uart;
+ unsigned char index;
+};
+
+struct i2c_s {
+ LPC_I2C_TypeDef *i2c;
+};
+
+struct spi_s {
+ LPC_SPI_TypeDef *spi;
+ unsigned char spi_n;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/TARGET_LPC812/system_LPC8xx.h Mon Aug 12 13:17:46 2013 +0300
+++ b/TARGET_LPC812/system_LPC8xx.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,62 +1,62 @@
-/******************************************************************************
- * @file: system_LPC8xx.h
- * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
- * for the NXP LPC8xx Device Series
- * @version: V1.0
- * @date: 16. Aug. 2012
- *----------------------------------------------------------------------------
- *
- * Copyright (C) 2012 ARM Limited. All rights reserved.
- *
- * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC8xx_H
-#define __SYSTEM_LPC8xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC8xx_H */
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
--- a/Ticker.h Mon Aug 12 13:17:46 2013 +0300
+++ b/Ticker.h Mon Aug 19 13:34:54 2013 +0300
@@ -104,7 +104,7 @@
*/
template<typename T>
pFunctionPointer_t attach(T* tptr, void (T::*mptr)(void), float t) {
- return attach_us(tptr, mptr, t * 1000000.0f);
+ return attach_us(tptr, mptr, t * 1000000.0f);
}
/** Add a function to be called by the Ticker at the end of the call chain
@@ -142,6 +142,7 @@
* The function object created for 'fptr'
*/
pFunctionPointer_t attach_us(void (*fptr)(void), unsigned int t) {
+ _chain.clear();
pFunctionPointer_t pf = _chain.add(fptr);
setup(t);
return pf;
@@ -158,7 +159,8 @@
*/
template<typename T>
pFunctionPointer_t attach_us(T* tptr, void (T::*mptr)(void), unsigned int t) {
- pFunctionPointer_t pf = _chain.add(mptr, tptr);
+ _chain.clear();
+ pFunctionPointer_t pf = _chain.add(tptr, mptr);
setup(t);
return pf;
}
--- a/can_api.h Mon Aug 12 13:17:46 2013 +0300
+++ b/can_api.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,79 +1,79 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- IRQ_RX,
- IRQ_TX,
- IRQ_ERROR,
- IRQ_OVERRUN,
- IRQ_WAKEUP,
- IRQ_PASSIVE,
- IRQ_ARB,
- IRQ_BUS,
- IRQ_READY
-} CanIrqType;
-
-
-typedef enum {
- MODE_RESET,
- MODE_NORMAL,
- MODE_SILENT,
- MODE_TEST_GLOBAL,
- MODE_TEST_LOCAL,
- MODE_TEST_SILENT
-} CanMode;
-
-typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
-
-typedef struct can_s can_t;
-
-void can_init (can_t *obj, PinName rd, PinName td);
-void can_free (can_t *obj);
-int can_frequency(can_t *obj, int hz);
-
-void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
-void can_irq_free (can_t *obj);
-void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
-
-int can_write (can_t *obj, CAN_Message, int cc);
-int can_read (can_t *obj, CAN_Message *msg);
-int can_mode (can_t *obj, CanMode mode);
-void can_reset (can_t *obj);
-unsigned char can_rderror (can_t *obj);
-unsigned char can_tderror (can_t *obj);
-void can_monitor (can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif // MBED_CAN_API_H
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_LOCAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void can_init (can_t *obj, PinName rd, PinName td);
+void can_free (can_t *obj);
+int can_frequency(can_t *obj, int hz);
+
+void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free (can_t *obj);
+void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int can_write (can_t *obj, CAN_Message, int cc);
+int can_read (can_t *obj, CAN_Message *msg);
+int can_mode (can_t *obj, CanMode mode);
+void can_reset (can_t *obj);
+unsigned char can_rderror (can_t *obj);
+unsigned char can_tderror (can_t *obj);
+void can_monitor (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // MBED_CAN_API_H
+
+#endif
--- a/gpio_api.h Mon Aug 12 13:17:46 2013 +0300
+++ b/gpio_api.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,44 +1,44 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set the given pin as GPIO
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-
-/* GPIO object */
-void gpio_init (gpio_t *obj, PinName pin, PinDirection direction);
-
-void gpio_mode (gpio_t *obj, PinMode mode);
-void gpio_dir (gpio_t *obj, PinDirection direction);
-
-void gpio_write(gpio_t *obj, int value);
-int gpio_read (gpio_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* GPIO object */
+void gpio_init (gpio_t *obj, PinName pin, PinDirection direction);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int gpio_read (gpio_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/i2c_api.h Mon Aug 12 13:17:46 2013 +0300
+++ b/i2c_api.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,58 +1,58 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-
-#if DEVICE_I2C
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct i2c_s i2c_t;
-
-enum {
- I2C_ERROR_NO_SLAVE = -1,
- I2C_ERROR_BUS_BUSY = -2
-};
-
-void i2c_init (i2c_t *obj, PinName sda, PinName scl);
-void i2c_frequency (i2c_t *obj, int hz);
-int i2c_start (i2c_t *obj);
-int i2c_stop (i2c_t *obj);
-int i2c_read (i2c_t *obj, int address, char *data, int length, int stop);
-int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop);
-void i2c_reset (i2c_t *obj);
-int i2c_byte_read (i2c_t *obj, int last);
-int i2c_byte_write (i2c_t *obj, int data);
-
-#if DEVICE_I2CSLAVE
-void i2c_slave_mode (i2c_t *obj, int enable_slave);
-int i2c_slave_receive(i2c_t *obj);
-int i2c_slave_read (i2c_t *obj, char *data, int length);
-int i2c_slave_write (i2c_t *obj, const char *data, int length);
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+
+#if DEVICE_I2C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct i2c_s i2c_t;
+
+enum {
+ I2C_ERROR_NO_SLAVE = -1,
+ I2C_ERROR_BUS_BUSY = -2
+};
+
+void i2c_init (i2c_t *obj, PinName sda, PinName scl);
+void i2c_frequency (i2c_t *obj, int hz);
+int i2c_start (i2c_t *obj);
+int i2c_stop (i2c_t *obj);
+int i2c_read (i2c_t *obj, int address, char *data, int length, int stop);
+int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop);
+void i2c_reset (i2c_t *obj);
+int i2c_byte_read (i2c_t *obj, int last);
+int i2c_byte_write (i2c_t *obj, int data);
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode (i2c_t *obj, int enable_slave);
+int i2c_slave_receive(i2c_t *obj);
+int i2c_slave_read (i2c_t *obj, char *data, int length);
+int i2c_slave_write (i2c_t *obj, const char *data, int length);
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
--- a/mbed_interface.h Mon Aug 12 13:17:46 2013 +0300
+++ b/mbed_interface.h Mon Aug 19 13:34:54 2013 +0300
@@ -18,6 +18,19 @@
#include "device.h"
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
#ifdef __cplusplus
extern "C" {
#endif
--- a/pinmap.h Mon Aug 12 13:17:46 2013 +0300
+++ b/pinmap.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,42 +1,42 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINMAP_H
-#define MBED_PINMAP_H
-
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- int peripheral;
- int function;
-} PinMap;
-
-void pin_function(PinName pin, int function);
-void pin_mode (PinName pin, PinMode mode);
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_merge (uint32_t a, uint32_t b);
-void pinmap_pinout (PinName pin, const PinMap *map);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ int peripheral;
+ int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_merge (uint32_t a, uint32_t b);
+void pinmap_pinout (PinName pin, const PinMap *map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/serial_api.h Mon Aug 12 13:17:46 2013 +0300
+++ b/serial_api.h Mon Aug 19 13:34:54 2013 +0300
@@ -1,69 +1,69 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-
-#if DEVICE_SERIAL
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ParityNone = 0,
- ParityOdd = 1,
- ParityEven = 2,
- ParityForced1 = 3,
- ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
- RxIrq,
- TxIrq
-} SerialIrq;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-typedef struct serial_s serial_t;
-
-void serial_init (serial_t *obj, PinName tx, PinName rx);
-void serial_free (serial_t *obj);
-void serial_baud (serial_t *obj, int baudrate);
-void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable);
-
-int serial_getc (serial_t *obj);
-void serial_putc (serial_t *obj, int c);
-int serial_readable (serial_t *obj);
-int serial_writable (serial_t *obj);
-void serial_clear (serial_t *obj);
-
-void serial_break_set (serial_t *obj);
-void serial_break_clear(serial_t *obj);
-
-void serial_pinout_tx(PinName tx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+
+#if DEVICE_SERIAL
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ParityNone = 0,
+ ParityOdd = 1,
+ ParityEven = 2,
+ ParityForced1 = 3,
+ ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+ RxIrq,
+ TxIrq
+} SerialIrq;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+typedef struct serial_s serial_t;
+
+void serial_init (serial_t *obj, PinName tx, PinName rx);
+void serial_free (serial_t *obj);
+void serial_baud (serial_t *obj, int baudrate);
+void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable);
+
+int serial_getc (serial_t *obj);
+void serial_putc (serial_t *obj, int c);
+int serial_readable (serial_t *obj);
+int serial_writable (serial_t *obj);
+void serial_clear (serial_t *obj);
+
+void serial_break_set (serial_t *obj);
+void serial_break_clear(serial_t *obj);
+
+void serial_pinout_tx(PinName tx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
--- a/toolchain.h Mon Aug 12 13:17:46 2013 +0300 +++ b/toolchain.h Mon Aug 19 13:34:54 2013 +0300 @@ -1,35 +1,35 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_TOOLCHAIN_H -#define MBED_TOOLCHAIN_H - -#if defined(TOOLCHAIN_ARM) -#include <rt_sys.h> -#endif - -#ifndef FILEHANDLE -typedef int FILEHANDLE; -#endif - -#if defined (__ICCARM__) -# define WEAK __weak -# define PACKED __packed -#else -# define WEAK __attribute__((weak)) -# define PACKED __attribute__((packed)) -#endif - -#endif +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TOOLCHAIN_H +#define MBED_TOOLCHAIN_H + +#if defined(TOOLCHAIN_ARM) +#include <rt_sys.h> +#endif + +#ifndef FILEHANDLE +typedef int FILEHANDLE; +#endif + +#if defined (__ICCARM__) +# define WEAK __weak +# define PACKED __packed +#else +# define WEAK __attribute__((weak)) +# define PACKED __attribute__((packed)) +#endif + +#endif